| /art/compiler/utils/arm/ |
| H A D | assembler_arm.cc | 399 CHECK_EQ(R0, method_reg.AsArm().AsCoreRegister());
405 Register reg = callee_save_regs.at(i).AsArm().AsCoreRegister();
421 Register reg = entry_spills.at(i).AsArm().AsCoreRegister();
433 Register reg = callee_save_regs.at(i).AsArm().AsCoreRegister();
461 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
478 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
484 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
491 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
492 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, in_off.Int32Value());
493 StoreToOffset(kStoreWord, scratch.AsCoreRegister(), S
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| H A D | managed_register_arm.cc | 79 os << "Core: " << static_cast<int>(AsCoreRegister());
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| H A D | managed_register_arm.h | 87 Register AsCoreRegister() const { function in class:art::arm::ArmManagedRegister
127 return FromRegId(AllocIdLow()).AsCoreRegister();
133 return FromRegId(AllocIdHigh()).AsCoreRegister();
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| H A D | managed_register_arm_test.cc | 37 EXPECT_EQ(R0, reg.AsCoreRegister());
46 EXPECT_EQ(R1, reg.AsCoreRegister());
55 EXPECT_EQ(R8, reg.AsCoreRegister());
64 EXPECT_EQ(R15, reg.AsCoreRegister());
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| H A D | assembler_arm32.cc | 1471 CHECK_EQ(mscratch.AsArm().AsCoreRegister(), R12);
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| H A D | assembler_thumb2.cc | 2521 CHECK_EQ(mscratch.AsArm().AsCoreRegister(), R12);
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| /art/compiler/utils/arm64/ |
| H A D | assembler_arm64.cc | 53 ___ Mov(reg_x(tr.AsArm64().AsCoreRegister()), reg_x(ETR));
131 StoreToOffset(src.AsCoreRegister(), SP, offs.Int32Value());
150 StoreToOffset(src.AsCoreRegister(), SP, offs.Int32Value());
157 LoadImmediate(scratch.AsCoreRegister(), imm);
166 LoadImmediate(scratch.AsCoreRegister(), imm);
167 StoreToOffset(scratch.AsCoreRegister(), ETR, offs.Int32Value());
175 AddConstant(scratch.AsCoreRegister(), SP, fr_offs.Int32Value());
176 StoreToOffset(scratch.AsCoreRegister(), ETR, tr_offs.Int32Value());
190 StoreToOffset(source.AsCoreRegister(), SP, dest_off.Int32Value());
191 LoadFromOffset(scratch.AsCoreRegister(), S
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| H A D | managed_register_arm64.cc | 59 no = static_cast<int>(AsCoreRegister());
98 os << "XCore: " << static_cast<int>(AsCoreRegister());
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| H A D | managed_register_arm64.h | 58 Register AsCoreRegister() const { function in class:art::arm64::Arm64ManagedRegister
82 return static_cast<WRegister>(AsCoreRegister());
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| H A D | managed_register_arm64_test.cc | 41 EXPECT_EQ(X0, reg.AsCoreRegister());
51 EXPECT_EQ(X1, reg.AsCoreRegister());
61 EXPECT_EQ(X7, reg.AsCoreRegister());
71 EXPECT_EQ(X15, reg.AsCoreRegister());
81 EXPECT_EQ(X19, reg.AsCoreRegister());
91 EXPECT_EQ(IP0, reg.AsCoreRegister());
101 EXPECT_EQ(SP, reg.AsCoreRegister());
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| /art/compiler/utils/mips/ |
| H A D | assembler_mips.cc | 464 LoadFromOffset(kLoadWord, dst.AsCoreRegister(), src_register, src_offset);
554 Register reg = callee_save_regs.at(i).AsMips().AsCoreRegister();
559 StoreToOffset(kStoreWord, method_reg.AsMips().AsCoreRegister(), SP, 0);
563 Register reg = entry_spills.at(i).AsMips().AsCoreRegister();
575 Register reg = callee_save_regs.at(i).AsMips().AsCoreRegister();
604 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
621 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
627 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
634 LoadImmediate(scratch.AsCoreRegister(), imm);
635 StoreToOffset(kStoreWord, scratch.AsCoreRegister(), S
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| H A D | managed_register_mips.h | 89 Register AsCoreRegister() const { function in class:art::mips::MipsManagedRegister
119 return FromRegId(AllocIdLow()).AsCoreRegister();
125 return FromRegId(AllocIdHigh()).AsCoreRegister();
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| H A D | managed_register_mips.cc | 80 os << "Core: " << static_cast<int>(AsCoreRegister());
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| /art/compiler/optimizing/ |
| H A D | code_generator_arm.cc | 374 __ Mov(destination.AsArm().AsCoreRegister(), source.AsArm().AsCoreRegister());
376 __ ldr(destination.AsArm().AsCoreRegister(), Address(SP, source.GetStackIndex()));
381 __ str(source.AsArm().AsCoreRegister(), Address(SP, destination.GetStackIndex()));
464 __ LoadImmediate(location.AsArm().AsCoreRegister(), value);
565 __ cmp(if_instr->GetLocations()->InAt(0).AsArm().AsCoreRegister(),
573 __ cmp(locations->InAt(0).AsArm().AsCoreRegister(),
574 ShifterOperand(locations->InAt(1).AsArm().AsCoreRegister()));
580 __ cmp(locations->InAt(0).AsArm().AsCoreRegister(), ShifterOperand(value));
584 __ cmp(locations->InAt(0).AsArm().AsCoreRegister(), ShifterOperan
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