Searched refs:IP (Results 1 - 6 of 6) sorted by relevance
/art/compiler/optimizing/ |
H A D | code_generator_arm.cc | 247 blocked_registers[IP] = true; 274 __ LoadFromOffset(kLoadWord, IP, TR, Thread::StackEndOffset<kArmWordSize>().Int32Value()); 275 __ cmp(SP, ShifterOperand(IP)); 278 __ AddConstant(IP, SP, -static_cast<int32_t>(GetStackOverflowReservedBytes(kArm))); 279 __ ldr(IP, Address(IP, 0)); 383 __ ldr(IP, Address(SP, source.GetStackIndex())); 384 __ str(IP, Address(SP, destination.GetStackIndex())); 447 __ ldr(IP, Address(SP, source.GetStackIndex())); 448 __ str(IP, Addres [all...] |
/art/compiler/utils/arm/ |
H A D | assembler_arm32.cc | 1261 CHECK(rn != IP); 1263 mvn(IP, shifter_op, cond); 1264 add(rd, rn, ShifterOperand(IP), cond); 1266 mvn(IP, shifter_op, cond); 1267 sub(rd, rn, ShifterOperand(IP), cond); 1269 movw(IP, Low16Bits(value), cond); 1272 movt(IP, value_high, cond); 1274 add(rd, rn, ShifterOperand(IP), cond); 1288 CHECK(rn != IP); 1290 mvn(IP, shifter_o [all...] |
H A D | assembler_thumb2.cc | 2312 CHECK(rn != IP); 2314 mvn(IP, shifter_op, cond); 2315 add(rd, rn, ShifterOperand(IP), cond); 2317 mvn(IP, shifter_op, cond); 2318 sub(rd, rn, ShifterOperand(IP), cond); 2320 movw(IP, Low16Bits(value), cond); 2323 movt(IP, value_high, cond); 2325 add(rd, rn, ShifterOperand(IP), cond); 2339 CHECK(rn != IP); 2341 mvn(IP, shifter_o [all...] |
/art/runtime/arch/arm/ |
H A D | registers_arm.h | 45 IP = 12, enumerator in enum:art::arm::Register
|
/art/compiler/jni/quick/arm/ |
H A D | calling_convention_arm.cc | 27 return ArmManagedRegister::FromCoreRegister(IP); // R12 31 return ArmManagedRegister::FromCoreRegister(IP); // R12
|
/art/compiler/trampolines/ |
H A D | trampoline_compiler.cc | 40 __ LoadFromOffset(kLoadWord, IP, R0, JNIEnvExt::SelfOffset().Int32Value()); 41 __ LoadFromOffset(kLoadWord, PC, IP, offset.Int32Value());
|
Completed in 289 milliseconds