Searched refs:IP (Results 1 - 6 of 6) sorted by relevance

/art/compiler/optimizing/
H A Dcode_generator_arm.cc247 blocked_registers[IP] = true;
274 __ LoadFromOffset(kLoadWord, IP, TR, Thread::StackEndOffset<kArmWordSize>().Int32Value());
275 __ cmp(SP, ShifterOperand(IP));
278 __ AddConstant(IP, SP, -static_cast<int32_t>(GetStackOverflowReservedBytes(kArm)));
279 __ ldr(IP, Address(IP, 0));
383 __ ldr(IP, Address(SP, source.GetStackIndex()));
384 __ str(IP, Address(SP, destination.GetStackIndex()));
447 __ ldr(IP, Address(SP, source.GetStackIndex()));
448 __ str(IP, Addres
[all...]
/art/compiler/utils/arm/
H A Dassembler_arm32.cc1261 CHECK(rn != IP);
1263 mvn(IP, shifter_op, cond);
1264 add(rd, rn, ShifterOperand(IP), cond);
1266 mvn(IP, shifter_op, cond);
1267 sub(rd, rn, ShifterOperand(IP), cond);
1269 movw(IP, Low16Bits(value), cond);
1272 movt(IP, value_high, cond);
1274 add(rd, rn, ShifterOperand(IP), cond);
1288 CHECK(rn != IP);
1290 mvn(IP, shifter_o
[all...]
H A Dassembler_thumb2.cc2312 CHECK(rn != IP);
2314 mvn(IP, shifter_op, cond);
2315 add(rd, rn, ShifterOperand(IP), cond);
2317 mvn(IP, shifter_op, cond);
2318 sub(rd, rn, ShifterOperand(IP), cond);
2320 movw(IP, Low16Bits(value), cond);
2323 movt(IP, value_high, cond);
2325 add(rd, rn, ShifterOperand(IP), cond);
2339 CHECK(rn != IP);
2341 mvn(IP, shifter_o
[all...]
/art/runtime/arch/arm/
H A Dregisters_arm.h45 IP = 12, enumerator in enum:art::arm::Register
/art/compiler/jni/quick/arm/
H A Dcalling_convention_arm.cc27 return ArmManagedRegister::FromCoreRegister(IP); // R12
31 return ArmManagedRegister::FromCoreRegister(IP); // R12
/art/compiler/trampolines/
H A Dtrampoline_compiler.cc40 __ LoadFromOffset(kLoadWord, IP, R0, JNIEnvExt::SelfOffset().Int32Value());
41 __ LoadFromOffset(kLoadWord, PC, IP, offset.Int32Value());

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