Searched refs:TR (Results 1 - 11 of 11) sorted by relevance

/art/runtime/arch/arm/
H A Dregisters_arm.h43 TR = 9, // thread register enumerator in enum:art::arm::Register
H A Dcontext_arm.cc113 DCHECK_EQ(reinterpret_cast<uintptr_t>(Thread::Current()), gprs[TR]);
/art/compiler/utils/arm/
H A Dassembler_arm.cc541 StoreToOffset(kStoreWord, scratch.AsCoreRegister(), TR, dest.Int32Value());
569 return EmitLoad(this, m_dst, TR, src.Int32Value(), size);
575 LoadFromOffset(kLoadWord, dst.AsCoreRegister(), TR, offs.Int32Value());
584 TR, thr_offs.Int32Value());
597 TR, thr_offs.Int32Value());
607 TR, thr_offs.Int32Value());
611 StoreToOffset(kStoreWord, SP, TR, thr_offs.Int32Value());
804 mov(tr.AsArm().AsCoreRegister(), ShifterOperand(TR));
809 StoreToOffset(kStoreWord, TR, SP, offset.Int32Value(), AL);
817 TR, Threa
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/art/runtime/arch/arm64/
H A Dregisters_arm64.h59 TR = 18, // ART Thread Register - Managed Runtime (Caller Saved Reg) enumerator in enum:art::arm64::Register
H A Dcontext_arm64.cc159 DCHECK_EQ(reinterpret_cast<uintptr_t>(Thread::Current()), gprs[TR]);
/art/compiler/dex/quick/x86/
H A Dx86_lir.h389 // TR - Thread Register - opcode fs:[disp], reg - where fs: is equal to Thread::Current()
408 opcode ## 8MR, opcode ## 8AR, opcode ## 8TR, \
411 opcode ## 16MR, opcode ## 16AR, opcode ## 16TR, \
415 opcode ## 32MR, opcode ## 32AR, opcode ## 32TR, \
419 opcode ## 64MR, opcode ## 64AR, opcode ## 64TR, \
667 kMemReg, kArrayReg, kThreadReg, // MR, AR and TR instruction kinds.
H A Dassemble_x86.cc39 { kX86 ## opname ## 8TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8TR", "fs:[!0d],!1r" }, \
51 { kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16TR", "fs:[!0d],!1r" }, \
67 { kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32TR", "fs:[!0d],!1r" }, \
83 { kX86 ## opname ## 64TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64TR", "fs:[!0d],!1r" }, \
/art/compiler/trampolines/
H A Dtrampoline_compiler.cc80 __ JumpTo(Arm64ManagedRegister::FromCoreRegister(TR), Offset(offset.Int32Value()),
/art/compiler/optimizing/
H A Dcode_generator_arm.cc69 __ ldr(LR, Address(TR, offset));
85 __ LoadFromOffset(kLoadWord, PC, TR,
107 __ ldr(LR, Address(TR, offset));
244 blocked_registers[TR] = true;
274 __ LoadFromOffset(kLoadWord, IP, TR, Thread::StackEndOffset<kArmWordSize>().Int32Value());
1003 __ ldr(LR, Address(TR, offset));
1409 __ ldr(LR, Address(TR, offset));
1478 __ LoadFromOffset(kLoadWord, card, TR, Thread::CardTableOffset<kArmWordSize>().Int32Value());
/art/compiler/utils/arm64/
H A Dassembler_arm64.cc627 // Move ETR(Callee saved) back to TR(Caller saved) reg. We use ETR on calls
628 // to external functions that might trash TR. We do not need the original
630 ___ Mov(reg_x(TR), reg_x(ETR));
681 // Move TR(Caller saved) to ETR(Callee saved). The original (ETR)X21 has been saved on stack.
682 // This way we make sure that TR is not trashed by native code.
683 ___ Mov(reg_x(ETR), reg_x(TR));
720 // We move ETR(aapcs64 callee saved) back to TR(aapcs64 caller saved) which might have
722 ___ Mov(reg_x(TR), reg_x(ETR));
H A Dmanaged_register_arm64_test.cc649 EXPECT_TRUE(vixl::x18.Is(Arm64Assembler::reg_x(TR)));

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