/art/runtime/arch/arm/ |
H A D | registers_arm.h | 43 TR = 9, // thread register enumerator in enum:art::arm::Register
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H A D | context_arm.cc | 113 DCHECK_EQ(reinterpret_cast<uintptr_t>(Thread::Current()), gprs[TR]);
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/art/compiler/utils/arm/ |
H A D | assembler_arm.cc | 541 StoreToOffset(kStoreWord, scratch.AsCoreRegister(), TR, dest.Int32Value()); 569 return EmitLoad(this, m_dst, TR, src.Int32Value(), size); 575 LoadFromOffset(kLoadWord, dst.AsCoreRegister(), TR, offs.Int32Value()); 584 TR, thr_offs.Int32Value()); 597 TR, thr_offs.Int32Value()); 607 TR, thr_offs.Int32Value()); 611 StoreToOffset(kStoreWord, SP, TR, thr_offs.Int32Value()); 804 mov(tr.AsArm().AsCoreRegister(), ShifterOperand(TR)); 809 StoreToOffset(kStoreWord, TR, SP, offset.Int32Value(), AL); 817 TR, Threa [all...] |
/art/runtime/arch/arm64/ |
H A D | registers_arm64.h | 59 TR = 18, // ART Thread Register - Managed Runtime (Caller Saved Reg) enumerator in enum:art::arm64::Register
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H A D | context_arm64.cc | 159 DCHECK_EQ(reinterpret_cast<uintptr_t>(Thread::Current()), gprs[TR]);
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/art/compiler/dex/quick/x86/ |
H A D | x86_lir.h | 389 // TR - Thread Register - opcode fs:[disp], reg - where fs: is equal to Thread::Current() 408 opcode ## 8MR, opcode ## 8AR, opcode ## 8TR, \ 411 opcode ## 16MR, opcode ## 16AR, opcode ## 16TR, \ 415 opcode ## 32MR, opcode ## 32AR, opcode ## 32TR, \ 419 opcode ## 64MR, opcode ## 64AR, opcode ## 64TR, \ 667 kMemReg, kArrayReg, kThreadReg, // MR, AR and TR instruction kinds.
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H A D | assemble_x86.cc | 39 { kX86 ## opname ## 8TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8TR", "fs:[!0d],!1r" }, \ 51 { kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16TR", "fs:[!0d],!1r" }, \ 67 { kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32TR", "fs:[!0d],!1r" }, \ 83 { kX86 ## opname ## 64TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64TR", "fs:[!0d],!1r" }, \
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/art/compiler/trampolines/ |
H A D | trampoline_compiler.cc | 80 __ JumpTo(Arm64ManagedRegister::FromCoreRegister(TR), Offset(offset.Int32Value()),
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/art/compiler/optimizing/ |
H A D | code_generator_arm.cc | 69 __ ldr(LR, Address(TR, offset)); 85 __ LoadFromOffset(kLoadWord, PC, TR, 107 __ ldr(LR, Address(TR, offset)); 244 blocked_registers[TR] = true; 274 __ LoadFromOffset(kLoadWord, IP, TR, Thread::StackEndOffset<kArmWordSize>().Int32Value()); 1003 __ ldr(LR, Address(TR, offset)); 1409 __ ldr(LR, Address(TR, offset)); 1478 __ LoadFromOffset(kLoadWord, card, TR, Thread::CardTableOffset<kArmWordSize>().Int32Value());
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/art/compiler/utils/arm64/ |
H A D | assembler_arm64.cc | 627 // Move ETR(Callee saved) back to TR(Caller saved) reg. We use ETR on calls 628 // to external functions that might trash TR. We do not need the original 630 ___ Mov(reg_x(TR), reg_x(ETR)); 681 // Move TR(Caller saved) to ETR(Callee saved). The original (ETR)X21 has been saved on stack. 682 // This way we make sure that TR is not trashed by native code. 683 ___ Mov(reg_x(ETR), reg_x(TR)); 720 // We move ETR(aapcs64 callee saved) back to TR(aapcs64 caller saved) which might have 722 ___ Mov(reg_x(TR), reg_x(ETR));
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H A D | managed_register_arm64_test.cc | 649 EXPECT_TRUE(vixl::x18.Is(Arm64Assembler::reg_x(TR)));
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