/art/compiler/dex/ |
H A D | reg_location.h | 44 unsigned wide:1; member in struct:art::RegLocation
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H A D | vreg_analysis.cc | 84 if (is_wide && !reg_location_[index].wide) { 85 reg_location_[index].wide = true; 93 if (!reg_location_[index].wide) { 94 reg_location_[index].wide = true; 150 reg_location_[defs[0]].wide = true; 151 reg_location_[defs[1]].wide = true; 169 reg_location_[uses[next]].wide = true; 170 reg_location_[uses[next + 1]].wide = true; 176 type_mismatch |= reg_location_[uses[next]].wide; 188 reg_location_[uses[next]].wide [all...] |
H A D | mir_graph.h | 289 bool GetConstant(int64_t* ptr_value, bool* wide) const; 783 DCHECK(!res.wide); 789 DCHECK(!res.wide); 795 DCHECK(res.wide); 801 DCHECK(res.wide); 874 * @param wide Whether we should allocate a wide temporary. 877 CompilerTemp* GetNewCompilerTemp(CompilerTempType ct_type, bool wide);
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H A D | mir_graph.cc | 354 bool wide = false; local 357 wide = true; 365 wide = true; 373 wide = true; 390 if (dest == monitor_reg || (wide && dest + 1 == monitor_reg)) { 1290 // For invokes-style formats, treat wide regs as a pair of singles. 1302 if (!show_singles && (reg_location_ != NULL) && reg_location_[i].wide) { 1317 case Instruction::k51l: // Add one wide immediate. 1370 if (!singles_only && reg_location_[ssa_reg].wide) { 1449 * high-word loc for wide argument [all...] |
H A D | mir_optimization.cc | 248 CompilerTemp* MIRGraph::GetNewCompilerTemp(CompilerTempType ct_type, bool wide) { argument 252 if (available_temps <= 0 || (available_temps <= 1 && wide)) { 263 DCHECK_EQ(wide, false); 278 if (wide) { 300 reg_location_[ssa_reg_high].wide = true; 312 reg_location_[ssa_reg_low].wide = wide;
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H A D | local_value_numbering.cc | 1026 // Try to find out if this is merging wide regs. 1029 // This is the high part of a wide reg. Ignore the Phi. 1032 bool wide = false; local 1035 wide = true; 1053 value_name = wide ? lvn->GetOperandValueWide(s_reg) : lvn->GetOperandValue(s_reg); 1067 if (!wide && gvn_->NullCheckedInAllPredecessors(merge_names_)) { 1072 if (wide) { 1481 // 1 wide result, treat as unique each time, use result s_reg - will be unique. 1584 // res = op + 1 wide operand 1597 // wide re [all...] |
/art/compiler/dex/quick/mips/ |
H A D | fp_mips.cc | 106 DCHECK(rl_src1.wide); 108 DCHECK(rl_src2.wide); 110 DCHECK(rl_dest.wide); 111 DCHECK(rl_result.wide); 154 if (rl_src.wide) { 161 if (rl_dest.wide) { 170 bool wide = true; local 176 wide = false; 180 wide = false; 194 if (wide) { [all...] |
/art/compiler/dex/quick/arm64/ |
H A D | utility_arm64.cc | 226 // 2. If the value is two bits wide, it can be encoded. 567 ArmOpcode wide = (r_dest_src1.Is64Bit()) ? WIDE(0) : UNWIDE(0); local 593 return NewLIR2(kA64Rev2rr | wide, r_dest_src1.GetReg(), r_src2.GetReg()); 597 NewLIR2(kA64Rev162rr | wide, r_dest_src1.GetReg(), r_src2.GetReg()); 599 return NewLIR4(kA64Sbfm4rrdd | wide, r_dest_src1.GetReg(), r_dest_src1.GetReg(), 0, 15); 605 return NewLIR4(kA64Sbfm4rrdd | wide, r_dest_src1.GetReg(), r_src2.GetReg(), 0, 7); 609 return NewLIR4(kA64Sbfm4rrdd | wide, r_dest_src1.GetReg(), r_src2.GetReg(), 0, 15); 614 return NewLIR4(kA64Ubfm4rrdd | wide, r_dest_src1.GetReg(), r_src2.GetReg(), 0, 15); 622 return NewLIR2(opcode | wide, r_dest_src1.GetReg(), r_src2.GetReg()); 626 return NewLIR3(opcode | wide, r_dest_src 636 ArmOpcode wide = (r_dest_src1.Is64Bit()) ? WIDE(0) : UNWIDE(0); local 817 ArmOpcode wide = (is_wide) ? WIDE(0) : UNWIDE(0); local 940 ArmOpcode wide = (r_dest_src1.Is64Bit()) ? WIDE(0) : UNWIDE(0); local [all...] |
H A D | fp_arm64.cc | 109 DCHECK(rl_src1.wide); 111 DCHECK(rl_src2.wide); 113 DCHECK(rl_dest.wide); 114 DCHECK(rl_result.wide); 185 if (rl_src.wide) { 194 if (rl_dest.wide) { 422 ArmOpcode wide = (is_double) ? FWIDE(0) : FUNWIDE(0); local 430 NewLIR2(kA64Fmov2fI | wide, r_imm_point5.GetReg(), encoded_imm); 431 NewLIR3(kA64Fadd3fff | wide, r_tmp.GetReg(), rl_src.reg.GetReg(), r_imm_point5.GetReg()); 440 ArmOpcode wide local [all...] |
H A D | target_arm64.cc | 839 arg_locs[in_position].wide, 843 if (arg_locs[in_position].wide) { 865 if (loc->wide) { 878 if (loc->wide || loc->ref) { 956 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(start_vreg + i), reg, t_loc->wide ? k64 : k32, 967 t_loc->wide ? k64 : k32, kNotVolatile); 971 if (t_loc->wide) { 1059 if (loc.wide) { 1130 if (rl_arg.wide) { 1160 if (rl_arg.wide) { [all...] |
H A D | int_arm64.cc | 206 bool is_wide = rl_dest.ref || rl_dest.wide; 266 ArmOpcode wide = reg.Is64Bit() ? WIDE(0) : UNWIDE(0); local 267 branch = NewLIR2(opcode | wide, reg.GetReg(), 0); 272 ArmOpcode wide = reg.Is64Bit() ? WIDE(0) : UNWIDE(0); local 273 branch = NewLIR2(opcode | wide, reg.GetReg(), 0); 523 const bool is_64bit = rl_dest.wide; 628 ArmOpcode wide; local 631 wide = WIDE(0); 634 wide = UNWIDE(0); 637 NewLIR4(kA64Msub4rrrr | wide, rl_resul 752 ArmOpcode wide = UNWIDE(0); local 1689 ArmOpcode wide = (size == k64) ? WIDE(0) : UNWIDE(0); local [all...] |
/art/compiler/dex/quick/ |
H A D | mir_to_lir.cc | 55 void Mir2Lir::LockArg(int in_position, bool wide) { argument 57 RegStorage reg_arg_high = wide ? GetArgMappingToPhysicalReg(in_position + 1) : 69 RegStorage Mir2Lir::LoadArg(int in_position, RegisterClass reg_class, bool wide) { argument 93 wide ? AllocTypedTempWide(false, reg_class) : AllocTypedTemp(false, reg_class); 94 LoadBaseDisp(TargetPtrReg(kSp), offset, new_reg, wide ? k64 : k32, kNotVolatile); 99 if (wide) { 114 RegStorage reg_arg_high = wide ? GetArgMappingToPhysicalReg(in_position + 1) : 117 // If the VR is wide and there is no register for high part, we need to load it. 118 if (wide && !reg_arg_high.Valid()) { 125 // Assume that no ABI allows splitting a wide f 236 bool wide = (data.op_variant == InlineMethodAnalyser::IGetVariant(Instruction::IGET_WIDE)); local 280 bool wide = (data.op_variant == InlineMethodAnalyser::IPutVariant(Instruction::IPUT_WIDE)); local 305 bool wide = (data.is_wide != 0u); local 1274 CheckRegStorageImpl(RegStorage rs, WidenessCheck wide, RefCheck ref, FPCheck fp, bool fail, bool report) const argument [all...] |
H A D | gen_loadstore.cc | 186 DCHECK(!rl_dest.wide); 187 DCHECK(!rl_src.wide); 232 DCHECK(rl_src.wide); 270 DCHECK(rl_dest.wide); 271 DCHECK(rl_src.wide); 347 DCHECK(rl_dest.wide); 348 DCHECK(rl_src.wide); 389 DCHECK(!loc.wide); 406 DCHECK(loc.wide);
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H A D | ralloc_util.cc | 132 // Existence of core64 registers implies wide references. 362 // If it's wide, split it up. 364 // If the pair was associated with a wide value, unmark the partner as well. 486 RegStorage Mir2Lir::AllocLiveReg(int s_reg, int reg_class, bool wide) { argument 493 reg = FindLiveReg(wide ? reg_pool_->dp_regs_ : reg_pool_->sp_regs_, s_reg); 497 reg = FindLiveReg(wide || reg_class == kRefReg ? reg_pool_->core64_regs_ : 504 if (wide && !reg.IsFloat() && !cu_->target64) { 515 if (reg.Valid() && (wide != GetRegInfo(reg)->IsWide())) { 539 if (wide) { 564 DCHECK(rl_keep.wide); 1280 bool wide = fp_regs[i].s_reg & STARTING_WIDE_SREG; local 1319 bool wide = curr->wide || (cu_->target64 && curr->ref); local [all...] |
H A D | gen_invoke.cc | 123 if (arg0.wide == 0) { 144 if (arg1.wide == 0) { 158 DCHECK(!arg0.wide); 233 if (arg0.wide == 0) { 239 if (arg1.wide == 0) { 246 if (arg0.wide == 0) { 248 if (arg1.wide == 0) { 263 if (arg1.wide == 0) { 334 DCHECK_EQ(static_cast<unsigned int>(arg1.wide), 0U); // The static_cast works around an 337 if (arg2.wide [all...] |
H A D | mir_to_lir-inl.h | 271 inline void Mir2Lir::CheckRegStorage(RegStorage rs, WidenessCheck wide, RefCheck ref, FPCheck fp) argument 274 CheckRegStorageImpl(rs, wide, ref, fp, kFailOnSizeError, kReportSizeError);
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H A D | mir_to_lir.h | 269 * is wide. Similarly, a 32-bit register containing half of a 64-bit Dalvik value 276 * NOTE 3: In the case of a 64-bit register holding a Dalvik wide value, wide_value 281 * other fields have meaning. [perhaps not true, wide should work for promoted regs?] 316 * because it is wide), its aliases s2 and s3 will show as live, but will have 324 * 1. Treat them all as 128-bits wide, but denote how much data used via bytes field. 383 // If not wide, reset partner to self. 426 bool wide_value_; // Holds a Dalvik wide value (either itself, or part of a pair). 718 // Handle bookkeeping to convert a wide RegLocation to a narrow RegLocation. No code generated. 758 RegStorage AllocLiveReg(int s_reg, int reg_class, bool wide); 792 * @brief Used to prepare a register location to receive a wide valu 1504 LoadStoreOpSize(bool wide, bool ref) argument [all...] |
H A D | codegen_util.cc | 58 if (rl_src.wide) { 59 // For wide registers, check whether we're the high partner. In that case we need to switch 372 /* Search the existing constants in the literal pool for an exact wide match */ 1205 DCHECK(rl_src.wide); 1206 DCHECK(rl_dest.wide); 1307 loc.wide = false;
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/art/compiler/dex/quick/arm/ |
H A D | fp_arm.cc | 106 DCHECK(rl_src1.wide); 108 DCHECK(rl_src2.wide); 110 DCHECK(rl_dest.wide); 111 DCHECK(rl_result.wide); 196 if (rl_src.wide) { 203 if (rl_dest.wide) {
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H A D | int_arm.cc | 1305 if (rl_dest.wide) { 1329 if (rl_dest.wide || rl_dest.fp || constant_index) { 1354 if (rl_dest.wide) { 1431 if (rl_src.wide || rl_src.fp || constant_index) { 1432 if (rl_src.wide) {
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/art/compiler/dex/quick/x86/ |
H A D | call_x86.cc | 87 if (rl_method.wide) { 161 if (rl_method.wide) {
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H A D | fp_x86.cc | 77 DCHECK(rl_dest.wide); 79 DCHECK(rl_src1.wide); 81 DCHECK(rl_src2.wide); 328 if (rl_src.wide) { 335 if (rl_dest.wide) {
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H A D | target_x86.cc | 936 << (loc.wide ? " w" : " ") 1812 if (rl_method.wide) { 2320 if (rl_src.wide == 0) { 2326 // If opsize is 8 bits wide then double value and use 16 bit shuffle instead. 2412 arg_locs[in_position].wide, arg_locs[in_position].ref); 2416 if (arg_locs[in_position].wide) { 2522 StoreBaseDisp(rs_rX86_SP, SRegOffset(start_vreg + i), reg, t_loc->wide ? k64 : k32, 2533 t_loc->wide ? k64 : k32, kNotVolatile); 2537 if (t_loc->wide) { 2609 info->args[last_mapped_in].wide [all...] |
H A D | utility_x86.cc | 395 bool is64Bit = rl_dest.wide != 0; 580 if (rl_method.wide) {
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/art/compiler/dex/portable/ |
H A D | mir_to_gbc.cc | 103 if (loc.wide) { 224 if (loc.wide) { 252 if (loc.wide) { 450 ::llvm::Value* res = GenArithOp(op, rl_dest.wide, src1, src2); 458 ::llvm::Value* res = GenArithOp(op, rl_dest.wide, src1, src2); 481 i += info->args[i].wide ? 2 : 1; 494 if (info->result.wide) { 642 DCHECK_EQ(rl_src1.wide, rl_src2.wide); 1564 * representing wide value [all...] |