Searched refs:CFC1 (Results 1 - 9 of 9) sorted by relevance

/external/chromium_org/v8/src/mips/
H A Dconstants-mips.h447 CFC1 = ((0 << 3) + 2) << 21,
H A Dsimulator-mips.cc1890 case CFC1:
2181 case CFC1:
H A Dassembler-mips.cc2036 GenInstrRegister(COP1, CFC1, rt, fs);
/external/chromium_org/v8/src/mips64/
H A Dconstants-mips64.h459 CFC1 = ((0 << 3) + 2) << 21,
H A Dsimulator-mips64.cc1957 case CFC1:
2317 case CFC1:
H A Dassembler-mips64.cc2262 GenInstrRegister(COP1, CFC1, rt, fs);
/external/pcre/dist/sljit/
H A DsljitNativeMIPS_common.c115 #define CFC1 (HI(17) | (2 << 21)) macro
1397 FAIL_IF(push_inst(compiler, CFC1 | TA(EQUAL_FLAG) | DA(FCSR_REG), EQUAL_FLAG));
1404 FAIL_IF(push_inst(compiler, CFC1 | TA(ULESS_FLAG) | DA(FCSR_REG), ULESS_FLAG));
1408 FAIL_IF(push_inst(compiler, CFC1 | TA(UGREATER_FLAG) | DA(FCSR_REG), UGREATER_FLAG));
2095 FAIL_IF(push_inst(compiler, CFC1 | TA(sugg_dst_ar) | DA(FCSR_REG), sugg_dst_ar));
/external/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp96 Opc = Mips::CFC1;
/external/valgrind/main/none/tests/mips64/
H A Dfpu_control_word.stdout.exp1 --- CTC1, CFC1 ---

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