/external/llvm/include/llvm/MC/ |
H A D | MCInstrItineraries.h | 195 /// index DefIdx can be bypassed when it's read by an instruction of 197 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, argument 201 if ((FirstDefIdx + DefIdx) >= LastDefIdx) 203 if (Forwardings[FirstDefIdx + DefIdx] == 0) 211 return Forwardings[FirstDefIdx + DefIdx] == 218 int getOperandLatency(unsigned DefClass, unsigned DefIdx, argument 223 int DefCycle = getOperandCycle(DefClass, DefIdx); 233 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
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H A D | MCSubtargetInfo.h | 103 unsigned DefIdx) const { 104 assert(DefIdx < SC->NumWriteLatencyEntries && 105 "MachineModel does not specify a WriteResource for DefIdx"); 107 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
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/external/llvm/lib/CodeGen/ |
H A D | TargetSchedule.cpp | 129 unsigned DefIdx = 0; local 133 ++DefIdx; 135 return DefIdx; 189 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); local 190 if (DefIdx < SCDesc->NumWriteLatencyEntries) { 193 STI->getWriteLatencyEntry(SCDesc, DefIdx); 209 // If DefIdx does not exist in the model (e.g. implicit defs), then return 217 ss << "DefIdx " << DefIdx << " exceeds machine model writes for " 241 for (unsigned DefIdx [all...] |
H A D | PeepholeOptimizer.cpp | 166 unsigned DefIdx; member in class:__anon25783::ValueTracker 205 /// at the operand index \p DefIdx. 212 ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg, argument 215 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg), 217 assert(Def->getOperand(DefIdx).isDef() && 218 Def->getOperand(DefIdx).isReg() && 221 Reg = Def->getOperand(DefIdx).getReg(); 462 unsigned SrcIdx, DefIdx; local 465 SrcIdx, DefIdx) ! 486 getCopyOrBitcastDefUseIdx(const MachineInstr &Copy, unsigned &DefIdx, unsigned &SrcIdx) argument 532 unsigned DefIdx, SrcIdx; local [all...] |
H A D | LiveRangeEdit.cpp | 128 SlotIndex DefIdx; 130 DefIdx = LIS.getInstructionIndex(RM.OrigMI); 132 DefIdx = RM.ParentVNI->def; 133 RM.OrigMI = LIS.getInstructionFromIndex(DefIdx); 142 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
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H A D | TargetInstrInfo.cpp | 702 SDNode *DefNode, unsigned DefIdx, 712 return ItinData->getOperandCycle(DefClass, DefIdx); 714 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 778 unsigned DefIdx) const { 783 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 791 const MachineInstr *DefMI, unsigned DefIdx, 795 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 824 /// to call getOperandLatency(). For most subtargets, we don't need DefIdx or 828 const MachineInstr *DefMI, unsigned DefIdx, 839 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseM 701 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const argument 790 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 827 computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument [all...] |
H A D | LiveRangeCalc.cpp | 90 unsigned DefIdx; local 94 } else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) { 97 if (MI->getOperand(DefIdx).isEarlyClobber())
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H A D | MachineVerifier.cpp | 888 unsigned DefIdx; local 890 MI->isRegTiedToDefOperand(MONum, &DefIdx) && 891 Reg != MI->getOperand(DefIdx).getReg()) 1084 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI); local 1085 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber()); 1088 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) { 1090 if (VNI->def != DefIdx) { 1093 << DefIdx << " in " << LI << '\n'; 1097 *OS << DefIdx << " i [all...] |
H A D | MachineInstr.cpp | 720 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); local 721 if (DefIdx != -1) 722 tieOperands(DefIdx, OpNo); 983 unsigned DefIdx; local 984 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) 985 OpIdx = DefIdx; 1165 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other. 1177 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { argument 1178 MachineOperand &DefMO = getOperand(DefIdx); 1180 assert(DefMO.isDef() && "DefIdx mus [all...] |
H A D | RegisterCoalescer.cpp | 597 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); local 598 assert(DefIdx != -1); 600 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) 699 SlotIndex DefIdx = UseIdx.getRegSlot(); local 700 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx); 703 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI); 704 assert(DVNI->def == DefIdx);
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H A D | InlineSpiller.cpp | 908 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewVReg, RM, local 910 (void)DefIdx; 911 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t' 912 << *LIS.getInstructionFromIndex(DefIdx));
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H A D | RegAllocFast.cpp | 736 unsigned DefIdx = 0; local 737 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue; 739 << DefIdx << ".\n"); local
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H A D | MachineLICM.cpp | 201 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx, 1011 unsigned DefIdx, unsigned Reg) const { 1028 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, &UseMI, i)) 1010 HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx, unsigned Reg) const argument
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGSDNodes.h | 136 unsigned DefIdx; member in class:llvm::ScheduleDAGSDNodes::RegDefIter 154 return DefIdx-1;
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H A D | ScheduleDAGSDNodes.cpp | 554 DefIdx = 0; 560 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) { 568 for (;DefIdx < NodeNumDefs; ++DefIdx) { 569 if (!Node->hasAnyUseOfValue(DefIdx)) 571 ValueType = Node->getSimpleValueType(DefIdx); 572 ++DefIdx; 634 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); 638 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
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H A D | InstrEmitter.cpp | 990 unsigned DefIdx = GroupIdx[DefGroup] + 1; 993 MIB->tieOperands(DefIdx + j, UseIdx + j);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.h | 216 const MachineInstr *DefMI, unsigned DefIdx, 220 SDNode *DefNode, unsigned DefIdx, 248 unsigned DefIdx, unsigned DefAlign) const; 252 unsigned DefIdx, unsigned DefAlign) const; 263 unsigned DefIdx, unsigned DefAlign, 278 const MachineInstr *DefMI, unsigned DefIdx, 283 unsigned DefIdx) const override;
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H A D | ARMBaseInstrInfo.cpp | 3008 unsigned DefIdx, unsigned DefAlign) const { 3009 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 3012 return ItinData->getOperandCycle(DefClass, DefIdx); 3049 unsigned DefIdx, unsigned DefAlign) const { 3050 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 3053 return ItinData->getOperandCycle(DefClass, DefIdx); 3152 unsigned DefIdx, unsigned DefAlign, 3158 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) 3159 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 3168 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 3005 getVLDMDefCycle(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const argument 3046 getLDMDefCycle(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const argument 3150 getOperandLatency(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID, unsigned UseIdx, unsigned UseAlign) const argument 3261 getBundledDefMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &DefIdx, unsigned &Dist) argument 3497 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 3588 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const argument 3891 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | TargetSchedule.h | 174 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
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H A D | MachineInstr.h | 924 /// tieOperands - Add a tie between the register operands at DefIdx and 930 void tieOperands(unsigned DefIdx, unsigned UseIdx);
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/external/llvm/lib/MC/MCDisassembler/ |
H A D | Disassembler.cpp | 225 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; 226 DefIdx != DefEnd; ++DefIdx) { 229 DefIdx);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.h | 99 const MachineInstr *DefMI, unsigned DefIdx, 103 SDNode *DefNode, unsigned DefIdx, 105 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
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H A D | PPCInstrInfo.cpp | 109 const MachineInstr *DefMI, unsigned DefIdx, 112 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, 115 const MachineOperand &DefMO = DefMI->getOperand(DefIdx); 108 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
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/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 838 SDNode *DefNode, unsigned DefIdx, 850 const MachineInstr *DefMI, unsigned DefIdx, 857 const MachineInstr *DefMI, unsigned DefIdx, 892 const MachineInstr *DefMI, unsigned DefIdx, 901 const MachineInstr *DefMI, unsigned DefIdx) const; 890 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 419 const MachineInstr *DefMI, unsigned DefIdx,
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