/external/javassist/src/main/javassist/bytecode/ |
H A D | Opcode.java | 102 int FNEG = 118; field in interface:Opcode
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/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 481 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 485 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator in enum:llvm::ISD::NodeType
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/external/mockito/cglib-and-asm/src/org/mockito/asm/ |
H A D | Opcodes.java | 257 int FNEG = 118; // -
field in interface:Opcodes
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H A D | Frame.java | 363 // 0, //FNEG, // -
833 case Opcodes.FNEG:
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/external/mockito/cglib-and-asm/src/org/mockito/asm/tree/analysis/ |
H A D | BasicInterpreter.java | 149 case FNEG:
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H A D | BasicVerifier.java | 122 case FNEG:
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H A D | Frame.java | 450 case Opcodes.FNEG:
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/external/jarjar/lib/ |
H A D | asm-4.0.jar | META-INF/MANIFEST.MF org/objectweb/asm/AnnotationVisitor.class " package org.objectweb.asm public ... |
/external/owasp/sanitizer/tools/findbugs/lib/ |
H A D | asm-3.3.jar | META-INF/MANIFEST.MF org/objectweb/asm/AnnotationVisitor.class " package org.objectweb.asm public ... |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeFloatTypes.cpp | 85 case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break; 361 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 830 case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break; 875 DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo), 1039 Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo); 1040 Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi);
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H A D | DAGCombiner.cpp | 453 if (Op.getOpcode() == ISD::FNEG) return 2; 515 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 1255 case ISD::FNEG: return visitFNEG(N); 6254 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || 6263 if (N0.getOpcode() == ISD::FNEG) 6518 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) 6523 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) 6699 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6700 return DAG.getNode(ISD::FNEG, dl, VT, N1); 6739 DAG.getNode(ISD::FNEG, d [all...] |
H A D | SelectionDAGDumper.cpp | 143 case ISD::FNEG: return "fneg";
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H A D | LegalizeVectorOps.cpp | 68 /// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if 274 case ISD::FNEG: 654 case ISD::FNEG:
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | R600ISelLowering.cpp | 493 DAG.getNode(ISD::FNEG, DL, VT, Cond));
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H A D | AMDILISelLowering.cpp | 539 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FLTTY, fq);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1174 setOperationAction(ISD::FNEG, MVT::f32, Legal); 1175 setOperationAction(ISD::FNEG, MVT::f64, Expand); 1285 setOperationAction(ISD::FNEG, MVT::f32, Expand); 1286 setOperationAction(ISD::FNEG, MVT::f64, Expand);
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | R600ISelLowering.cpp | 493 DAG.getNode(ISD::FNEG, DL, VT, Cond));
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H A D | AMDILISelLowering.cpp | 539 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FLTTY, fq);
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1507 setOperationAction(ISD::FNEG, MVT::f64, Custom); 1601 setOperationAction(ISD::FNEG, MVT::f128, Legal); 1604 setOperationAction(ISD::FNEG, MVT::f128, Custom); 1623 setOperationAction(ISD::FNEG, MVT::f128, Custom); 2519 assert(opcode == ISD::FNEG || opcode == ISD::FABS); 2638 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) 2822 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
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/external/chromium_org/v8/src/arm64/ |
H A D | disasm-arm64.cc | 993 FORMAT(FNEG, "fneg");
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H A D | constants-arm64.h | 1062 FNEG = FNEG_s, enumerator in enum:v8::internal::FPDataProcessing1SourceOp
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/external/javassist/src/main/javassist/bytecode/analysis/ |
H A D | Executor.java | 374 case FNEG:
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/external/vixl/src/a64/ |
H A D | disasm-a64.cc | 1000 FORMAT(FNEG, "fneg");
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H A D | constants-a64.h | 944 FNEG = FNEG_s, enumerator in enum:vixl::FPDataProcessing1SourceOp
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/external/pcre/dist/sljit/ |
H A D | sljitNativeARM_64.c | 91 #define FNEG 0x1e614000 macro 1674 FAIL_IF(push_inst(compiler, (FNEG ^ inv_bits) | VD(dst_r) | VN(src)));
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