/external/chromium_org/third_party/mesa/src/src/mesa/sparc/ |
H A D | sparc_matrix.h | 35 #define M0 %f16 macro 53 ldd [BASE + ( 0 * 0x4)], M0; \ 59 ldd [BASE + ( 0 * 0x4)], M0; \ 63 ld [BASE + ( 0 * 0x4)], M0; \ 67 ldd [BASE + ( 0 * 0x4)], M0; \ 73 ld [BASE + ( 0 * 0x4)], M0; \ 78 ld [BASE + ( 0 * 0x4)], M0; \ 82 ldd [BASE + ( 0 * 0x4)], M0; \ 90 ld [BASE + ( 0 * 0x4)], M0; \ 95 ldd [BASE + ( 0 * 0x4)], M0; \ [all...] |
H A D | norm.S | 60 fmuls %f0, M0, %f3 ! FGM Group 104 fmuls M0, %f15, M0 125 fmuls %f0, M0, %f3 ! FGM Group 199 fmuls %f0, M0, %f3 ! FGM Group 231 fmuls M0, %f15, M0 246 fmuls %f0, M0, %f3 ! FGM Group 291 fmuls M0, %f15, M0 [all...] |
H A D | xform.S | 82 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0 86 fmuls %f8, M0, %f9 ! FGM Group f1 available 115 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0 197 fmuls %f0, M0, %f1 ! FGM Group 199 fmuls %f8, M0, %f9 ! FGM Group 218 fmuls %f0, M0, %f1 251 fmuls %f0, M0, %f1 ! FGM Group 252 fmuls %f4, M0, %f5 ! FGM Group 268 fmuls %f0, M0, %f1 299 fmuls %f0, M0, [all...] |
/external/mesa3d/src/mesa/sparc/ |
H A D | sparc_matrix.h | 35 #define M0 %f16 macro 53 ldd [BASE + ( 0 * 0x4)], M0; \ 59 ldd [BASE + ( 0 * 0x4)], M0; \ 63 ld [BASE + ( 0 * 0x4)], M0; \ 67 ldd [BASE + ( 0 * 0x4)], M0; \ 73 ld [BASE + ( 0 * 0x4)], M0; \ 78 ld [BASE + ( 0 * 0x4)], M0; \ 82 ldd [BASE + ( 0 * 0x4)], M0; \ 90 ld [BASE + ( 0 * 0x4)], M0; \ 95 ldd [BASE + ( 0 * 0x4)], M0; \ [all...] |
H A D | norm.S | 60 fmuls %f0, M0, %f3 ! FGM Group 104 fmuls M0, %f15, M0 125 fmuls %f0, M0, %f3 ! FGM Group 199 fmuls %f0, M0, %f3 ! FGM Group 231 fmuls M0, %f15, M0 246 fmuls %f0, M0, %f3 ! FGM Group 291 fmuls M0, %f15, M0 [all...] |
H A D | xform.S | 82 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0 86 fmuls %f8, M0, %f9 ! FGM Group f1 available 115 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0 197 fmuls %f0, M0, %f1 ! FGM Group 199 fmuls %f8, M0, %f9 ! FGM Group 218 fmuls %f0, M0, %f1 251 fmuls %f0, M0, %f1 ! FGM Group 252 fmuls %f4, M0, %f5 ! FGM Group 268 fmuls %f0, M0, %f1 299 fmuls %f0, M0, [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | SIRegisterInfo.cpp | 36 case AMDGPU::M0: return 124;
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H A D | SIISelLowering.cpp | 153 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass); local 161 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0) 168 .addReg(M0); 176 .addReg(M0); 189 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass); local 191 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0) 198 .addReg(M0);
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H A D | SIGenRegisterInfo.pl | 95 def M0 : SIReg <"M0">; 143 (add (sequence "SGPR%u", 0, $SGPR_MAX_IDX), SREG_LIT_0, M0) 174 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | SIRegisterInfo.cpp | 36 case AMDGPU::M0: return 124;
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H A D | SIISelLowering.cpp | 153 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass); local 161 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0) 168 .addReg(M0); 176 .addReg(M0); 189 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass); local 191 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0) 198 .addReg(M0);
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H A D | SIGenRegisterInfo.pl | 95 def M0 : SIReg <"M0">; 143 (add (sequence "SGPR%u", 0, $SGPR_MAX_IDX), SREG_LIT_0, M0) 174 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
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/external/llvm/unittests/Support/ |
H A D | CommandLineTest.cpp | 51 explicit StackOption(const M0t &M0) : Base(M0) {} argument 55 StackOption(const M0t &M0, const M1t &M1) : Base(M0, M1) {} argument 59 StackOption(const M0t &M0, const M1t &M1, const M2t &M2) : Base(M0, M1, M2) {} argument 63 StackOption(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3) argument 64 : Base(M0, M1, M2, M3) {}
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/external/llvm/include/llvm/Support/ |
H A D | CommandLine.h | 1210 explicit opt(const M0t &M0) : Option(Optional, NotHidden) { argument 1211 apply(M0, this); 1217 opt(const M0t &M0, const M1t &M1) : Option(Optional, NotHidden) { argument 1218 apply(M0, this); apply(M1, this); 1224 opt(const M0t &M0, const M1t &M1, argument 1226 apply(M0, this); apply(M1, this); apply(M2, this); 1231 opt(const M0t &M0, const M1t &M1, const M2t &M2, argument 1233 apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this); 1238 opt(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3, argument 1240 apply(M0, thi 1247 opt(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3, const M4t &M4, const M5t &M5) argument 1256 opt(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3, const M4t &M4, const M5t &M5, const M6t &M6) argument 1266 opt(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3, const M4t &M4, const M5t &M5, const M6t &M6, const M7t &M7) argument 1379 list(const M0t &M0) argument 1385 list(const M0t &M0, const M1t &M1) argument 1391 list(const M0t &M0, const M1t &M1, const M2t &M2) argument 1398 list(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3) argument 1405 list(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3, const M4t &M4) argument 1414 list(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3, const M4t &M4, const M5t &M5) argument 1423 list(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3, const M4t &M4, const M5t &M5, const M6t &M6) argument 1433 list(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3, const M4t &M4, const M5t &M5, const M6t &M6, const M7t &M7) argument [all...] |
/external/openssl/crypto/md5/asm/ |
H A D | md5-ia64.S | 35 // {in,out}4 Block Value 0 M0 125 #define M0 in4 define 310 // loading into M12 here produces the M0 value, M13 -> M1, etc. 441 // Passed the first 4 words (M0 - M3) and initial (A, B, C, D) values, 542 G(A, B, C, D, M0) \ 543 COMPUTE(A, B, 5, M0, RotateM0) \ 552 H(A, B, C, D, M0) \ 553 COMPUTE(A, B, 4, M0, RotateM0) \ 562 I(A, B, C, D, M0) \ 563 COMPUTE(A, B, 6, M0, RotateM [all...] |
/external/llvm/lib/Target/R600/ |
H A D | SILowerControlFlow.cpp | 329 AMDGPU::M0).addImm(0xffffffff); 342 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) 359 // Move index from VCC into M0 360 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) 363 // Compare the just read M0 value to all possible Idx values 365 .addReg(AMDGPU::M0) 414 .addReg(AMDGPU::M0, RegState::Implicit) 436 .addReg(AMDGPU::M0, RegState::Implicit) 538 // Initialize M0 to a value that won't cause LDS access to be discarded
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H A D | AMDGPUAsmPrinter.cpp | 251 case AMDGPU::M0:
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/external/llvm/unittests/Analysis/ |
H A D | ScalarEvolutionTest.cpp | 64 const SCEVMulExpr *M0 = cast<SCEVMulExpr>(P0); local 68 EXPECT_EQ(cast<SCEVConstant>(M0->getOperand(0))->getValue()->getZExtValue(), 76 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0); 85 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0);
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/external/chromium_org/third_party/boringssl/src/crypto/poly1305/ |
H A D | poly1305_vec.c | 289 xmmi M0, M1, M2, M3, M4; local 352 M0 = _mm_and_si128(MMASK, T5); 360 T5 = _mm_mul_epu32(M0, p->R20.v); 361 T6 = _mm_mul_epu32(M0, p->R21.v); 380 T5 = _mm_mul_epu32(M0, p->R22.v); 381 T6 = _mm_mul_epu32(M0, p->R23.v); 400 T5 = _mm_mul_epu32(M0, p->R24.v); 416 M0 = _mm_and_si128(MMASK, T5); 423 T0 = _mm_add_epi64(T0, M0); 478 xmmi M0, M local [all...] |
/external/opencv/cvaux/src/ |
H A D | cvbgfg_codebook.cpp | 238 uchar m0, m1, m2, M0, M1, M2; local 256 m0 = model->modMin[0]; M0 = model->modMax[0]; 272 int h0 = p0 - M0, h1 = p1 - M1, h2 = p2 - M2;
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/external/chromium_org/third_party/boringssl/src/crypto/bn/asm/ |
H A D | armv4-mont.pl | 249 my ($Bi,$Ni,$M0)=map("d$_",(28..31)); 273 vld1.32 {${M0}[0]}, [$n0,:32] 287 vmul.u32 $Ni,$temp,$M0 341 vmul.u32 $Ni,$temp,$M0 466 vmul.u32 $Ni,$temp,$M0
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/external/openssl/crypto/bn/asm/ |
H A D | armv4-mont.pl | 253 my ($Bi,$Ni,$M0)=map("d$_",(28..31)); 277 vld1.32 {${M0}[0]}, [$n0,:32] 291 vmul.u32 $Ni,$temp,$M0 345 vmul.u32 $Ni,$temp,$M0 470 vmul.u32 $Ni,$temp,$M0
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 295 case AMDGPU::M0: return 124;
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/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 295 case AMDGPU::M0: return 124;
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/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineMulDivRem.cpp | 495 Value *M0 = isNormalFp(cast<Constant>(M1)) ? local 498 if (M0 && M1) { 500 std::swap(M0, M1); 503 ? BinaryOperator::CreateFAdd(M0, M1) 504 : BinaryOperator::CreateFSub(M0, M1);
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