/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 157 EVT NewVT = N->getValueType(0).getVectorElementType(); local 159 NewVT, N->getOperand(0)); 173 EVT NewVT = N->getValueType(0).getVectorElementType(); local 175 return DAG.getConvertRndSat(NewVT, SDLoc(N), 176 Op0, DAG.getValueType(NewVT), 190 EVT NewVT = N->getValueType(0).getVectorElementType(); local 193 NewVT, Op, N->getOperand(1)); 1066 EVT NewVT = Inputs[0].getValueType(); local 1067 unsigned NewElts = NewVT.getVectorNumElements(); 1124 EVT EltVT = NewVT 2534 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts); local 2747 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); local 2953 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT); local [all...] |
H A D | LegalizeTypesGeneric.cpp | 215 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); local 228 NewVT, 2*OldElts), 235 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); 239 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); 375 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); local 397 NewVT, NewElts.size()),
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H A D | LegalizeVectorOps.cpp | 419 EVT NewVT; local 422 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext()); 423 assert(NewVT.isSimple() && "Promoting to a non-simple vector type!"); 424 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) { 428 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) { 435 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
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H A D | DAGCombiner.cpp | 2239 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); local 2240 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2241 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2242 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2243 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2244 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2275 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); local 2276 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2277 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2278 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N 2357 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); local 2387 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); local 8805 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); local [all...] |
H A D | SelectionDAG.cpp | 3830 EVT NewVT = VT; local 3835 NewVT = (VT.getSizeInBits() > 64) ? MVT::i64 : MVT::i32; 3836 if (TLI.isOperationLegalOrCustom(ISD::STORE, NewVT) && 3837 TLI.isSafeMemOpType(NewVT.getSimpleVT())) 3839 else if (NewVT == MVT::i64 && 3843 NewVT = MVT::f64; 3850 NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1); 3851 if (NewVT == MVT::i8) 3853 } while (!TLI.isSafeMemOpType(NewVT [all...] |
H A D | LegalizeDAG.cpp | 3337 EVT NewVT = 3340 assert(NewVT.bitsEq(VT)); 3343 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); 3344 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); 3348 NewVT.getVectorNumElements()/VT.getVectorNumElements(); 3364 VT = NewVT;
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/external/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 893 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); local 894 if (!TLI->isTypeLegal(NewVT)) 895 NewVT = EltTy; 896 IntermediateVT = NewVT; 898 unsigned NewVTSize = NewVT.getSizeInBits(); 904 MVT DestVT = TLI->getRegisterType(NewVT); 906 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1246 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); local 1247 if (!isTypeLegal(NewVT)) 1248 NewVT [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineCalls.cpp | 916 VectorType *NewVT = cast<VectorType>(II->getType()); local 919 CV0 = ConstantExpr::getIntegerCast(CV0, NewVT, /*isSigned=*/!Zext); 920 CV1 = ConstantExpr::getIntegerCast(CV1, NewVT, /*isSigned=*/!Zext);
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 6206 EVT NewVT = V0_LO.getValueType(); local 6208 SDValue LO = DAG.getUNDEF(NewVT); 6209 SDValue HI = DAG.getUNDEF(NewVT); 6214 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI); 6216 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI); 6221 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO); 6225 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI); 7963 MVT NewVT = 7966 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 7967 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V [all...] |
/external/llvm/lib/Target/R600/ |
H A D | R600ISelLowering.cpp | 1543 EVT NewVT = MVT::v4i32; local 1546 NewVT = VT; 1549 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT,
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 5711 EVT NewVT = getExtensionTo64Bits(OrigTy); 5713 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
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