Searched refs:Outs (Results 1 - 25 of 41) sorted by relevance

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/external/llvm/lib/CodeGen/
H A DCallingConvLower.cpp86 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
89 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
90 MVT VT = Outs[i].VT;
91 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
100 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
103 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
104 MVT VT = Outs[i].VT;
105 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
118 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
120 unsigned NumOps = Outs
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonCallingConvLower.cpp94 Hexagon_CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
116 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
117 EVT VT = Outs[i].VT;
118 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
132 &Outs,
136 unsigned NumOps = Outs.size();
147 EVT ArgVT = Outs[i].VT;
148 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
131 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, Hexagon_CCAssignFn Fn, int NonVarArgsParams, unsigned SretValueSize) argument
H A DHexagonCallingConvLower.h83 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
88 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DHexagonISelLowering.h90 SmallVectorImpl<ISD::OutputArg> &Outs,
133 const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DHexagonISelLowering.cpp317 const SmallVectorImpl<ISD::OutputArg> &Outs,
329 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
399 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local
408 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
435 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
437 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
446 Outs, OutVals, Ins, DAG);
475 ISD::ArgFlagsTy Flags = Outs[
315 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument
1665 IsEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
[all...]
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h129 const SmallVectorImpl<ISD::OutputArg> &Outs,
161 const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DMSP430ISelLowering.cpp267 const SmallVectorImpl<ISD::OutputArg> &Outs) {
268 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
352 const SmallVectorImpl<ISD::OutputArg> &Outs) {
353 State.AnalyzeReturn(Outs, RetCC_MSP430);
396 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local
414 Outs, OutVals, Ins, dl, DAG, InVals);
524 const SmallVectorImpl<ISD::OutputArg> &Outs,
532 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
540 AnalyzeReturnValues(CCInfo, RVLocs, Outs);
266 AnalyzeVarArgs(CCState &State, const SmallVectorImpl<ISD::OutputArg> &Outs) argument
351 AnalyzeRetResult(CCState &State, const SmallVectorImpl<ISD::OutputArg> &Outs) argument
522 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument
575 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.h123 const SmallVectorImpl<ISD::OutputArg> &Outs,
128 const SmallVectorImpl<ISD::OutputArg> &Outs,
133 const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DSparcISelLowering.cpp173 const SmallVectorImpl<ISD::OutputArg> &Outs,
177 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
178 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
184 const SmallVectorImpl<ISD::OutputArg> &Outs,
197 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
246 const SmallVectorImpl<ISD::OutputArg> &Outs,
257 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
687 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local
703 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc3
171 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, SelectionDAG &DAG) const argument
182 LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, SelectionDAG &DAG) const argument
244 LowerReturn_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, SelectionDAG &DAG) const argument
1006 fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs, ArrayRef<ISD::OutputArg> Outs) argument
[all...]
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h139 const SmallVectorImpl<ISD::OutputArg> &Outs,
206 const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DXCoreISelLowering.cpp1036 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local
1056 Outs, OutVals, Ins, dl, DAG, InVals);
1113 const SmallVectorImpl<ISD::OutputArg> &Outs,
1128 CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
1443 const SmallVectorImpl<ISD::OutputArg> &Outs,
1447 if (!CCInfo.CheckReturn(Outs, RetCC_XCore))
1457 const SmallVectorImpl<ISD::OutputArg> &Outs,
1477 CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
1110 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1441 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument
1455 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h599 const SmallVectorImpl<ISD::OutputArg> &Outs,
605 const SmallVectorImpl<ISD::OutputArg> &Outs,
641 const SmallVectorImpl<ISD::OutputArg> &Outs,
650 const SmallVectorImpl<ISD::OutputArg> &Outs,
658 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h357 const SmallVectorImpl<ISD::OutputArg> &Outs,
376 const SmallVectorImpl<ISD::OutputArg> &Outs,
380 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUISelLowering.h52 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.h360 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
372 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
542 const SmallVectorImpl<ISD::OutputArg> &Outs,
547 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUISelLowering.h52 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h269 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
280 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp75 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
494 const SmallVectorImpl<ISD::OutputArg> &Outs,
551 if (Outs[OIdx].Flags.isByVal() == false) {
563 // update the index for Outs
571 assert((getValueType(Ty) == Outs[OIdx].VT ||
572 (getValueType(Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
592 unsigned align = Outs[OIdx].Flags.getByValAlign();
655 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local
680 // Args.size() and Outs
493 getPrototype(Type *retTy, const ArgListTy &Args, const SmallVectorImpl<ISD::OutputArg> &Outs, unsigned retAlignment, const ImmutableCallSite *CS) const argument
1934 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument
[all...]
H A DNVPTXISelLowering.h232 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp67 SmallVector<ISD::OutputArg, 4> Outs; local
68 GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
71 Outs, Fn->getContext());
/external/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp109 SmallVectorImpl<MachineInstr*> &Outs);
361 SmallVectorImpl<MachineInstr*> &Outs) {
395 Outs.push_back(MI);
360 elideCopiesAndPHIs(MachineInstr *MI, SmallVectorImpl<MachineInstr*> &Outs) argument
H A DARMISelLowering.h544 const SmallVectorImpl<ISD::OutputArg> &Outs,
551 const SmallVectorImpl<ISD::OutputArg> &Outs,
557 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.h859 const SmallVectorImpl<ISD::OutputArg> &Outs,
931 const SmallVectorImpl<ISD::OutputArg> &Outs,
944 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.h127 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h243 const SmallVectorImpl<ISD::OutputArg> &Outs,

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