Searched refs:ROR (Results 1 - 25 of 57) sorted by relevance

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/external/chromium_org/third_party/boringssl/linux-arm/crypto/sha/
H A Dsha1-armv4-large.S32 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
38 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
57 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
63 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
82 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
88 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
107 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
113 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
132 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
138 add r3,r3,r4,ror#27 @ E+=ROR(
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/external/chromium_org/v8/test/mjsunit/compiler/
H A Drotate.js47 function ROR(x, sa) { function
67 assertEquals(1 << ((2 % 32)), ROR(1, 30));
68 assertEquals(1 << ((2 % 32)), ROR(1, 30));
69 %OptimizeFunctionOnNextCall(ROR);
70 assertEquals(1 << ((2 % 32)), ROR(1, 30));
/external/openssl/crypto/sha/asm/
H A Dsha512-ppc.pl76 $ROR="rotrdi";
88 $ROR="rotrwi";
127 $ROR $a0,$e,$Sigma1[0]
128 $ROR $a1,$e,$Sigma1[1]
133 $ROR $a1,$a1,`$Sigma1[2]-$Sigma1[1]`
140 $ROR $a0,$a,$Sigma0[0]
141 $ROR $a1,$a,$Sigma0[1]
145 $ROR $a1,$a1,`$Sigma0[2]-$Sigma0[1]`
161 $ROR $a0,@X[($i+1)%16],$sigma0[0]
162 $ROR
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H A Dsha1-armv4-large.S40 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
46 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
65 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
71 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
90 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
96 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
115 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
121 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
140 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
146 add r3,r3,r4,ror#27 @ E+=ROR(
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H A Dsha1-thumb.pl50 add $t2,$e @ E+=ROR(A,27)
60 orr $c,$b @ C=ROR(B,2)
/external/chromium_org/v8/test/cctest/
H A Dtest-disasm-arm.cc157 COMPARE(sbc(r7, r1, Operand(ip, ROR, 1), LeaveCC, hi),
159 COMPARE(sbc(r7, r9, Operand(ip, ROR, 4)),
163 COMPARE(sbc(r7, ip, Operand(ip, ROR, 31), SetCC, hi),
184 COMPARE(teq(r7, Operand(r5, ROR, r0), lt),
186 COMPARE(teq(r7, Operand(r6, ROR, lr)),
190 COMPARE(teq(r7, Operand(r8, ROR, r1)),
204 COMPARE(cmn(r1, Operand(r6, ROR, 1)),
413 COMPARE(uxtb(r9, Operand(r10, ROR, 0)),
415 COMPARE(uxtb(r3, Operand(r4, ROR, 8)),
417 COMPARE(uxtab(r3, r4, Operand(r5, ROR,
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H A Dtest-disasm-arm64.cc704 COMPARE(and_(w12, w13, Operand(w14, ROR, 4)), "and w12, w13, w14, ror #4");
710 COMPARE(bic(w27, w28, Operand(w29, ROR, 8)), "bic w27, w28, w29, ror #8");
716 COMPARE(orr(w12, w13, Operand(w14, ROR, 12)), "orr w12, w13, w14, ror #12");
722 COMPARE(orn(w27, w28, Operand(w29, ROR, 16)), "orn w27, w28, w29, ror #16");
728 COMPARE(eor(w12, w13, Operand(w14, ROR, 20)), "eor w12, w13, w14, ror #20");
734 COMPARE(eon(w27, w28, Operand(w29, ROR, 24)), "eon w27, w28, w29, ror #24");
740 COMPARE(ands(w12, w13, Operand(w14, ROR, 4)), "ands w12, w13, w14, ror #4");
746 COMPARE(bics(w27, w28, Operand(w29, ROR, 8)), "bics w27, w28, w29, ror #8");
749 COMPARE(tst(w2, Operand(w3, ROR, 10)), "tst w2, w3, ror #10");
751 COMPARE(tst(x2, Operand(x3, ROR, 4
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H A Dtest-assembler-arm64.cc303 __ Mvn(w8, Operand(w0, ROR, 13));
304 __ Mvn(x9, Operand(x1, ROR, 14));
376 __ Mov(w21, Operand(w11, ROR, 13));
377 __ Mov(x22, Operand(x12, ROR, 14));
532 __ Orr(w8, w0, Operand(w1, ROR, 12));
533 __ Orr(x9, x0, Operand(x1, ROR, 12));
629 __ Orn(w8, w0, Operand(w1, ROR, 16));
630 __ Orn(x9, x0, Operand(x1, ROR, 16));
698 __ And(w8, w0, Operand(w1, ROR, 28));
699 __ And(x9, x0, Operand(x1, ROR, 2
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H A Dtest-assembler-arm.cc1375 __ uxtb16(r2, Operand(r0, ROR, 8));
1378 __ uxtb(r2, Operand(r0, ROR, 8));
1382 __ uxtab(r2, r0, Operand(r1, ROR, 8));
/external/chromium_org/v8/src/
H A Dtoken.h80 T(ROR, "rotate right", 11) /* only used by Crankshaft */ \
199 return BIT_OR <= op && op <= ROR;
/external/valgrind/main/none/tests/arm/
H A Dv6media.stdout.exp3042 sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3043 sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3044 sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3045 sxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3046 sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3047 sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3048 sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3049 sxtab r0, r1, r2, ROR #0 :: rd 0x314158c0 rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3050 sxtab r0, r1, r2, ROR #24 :: rd 0xf7b0b19c rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3051 sxtab r0, r1, r2, ROR #2
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H A Dv6intARM.stdout.exp295 ROR
349 ROR immediate
743 sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
744 sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
745 sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
746 sxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
747 sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000
748 sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000
749 sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000
750 sxtab r0, r1, r2, ROR #
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/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h37 ROR, enumerator in enum:llvm::AArch64_AM::ShiftExtendType
58 case AArch64_AM::ROR: return "ror";
79 case 3: return AArch64_AM::ROR;
107 case AArch64_AM::ROR: STEnc = 3; break;
/external/chromium_org/v8/src/arm/
H A Dcodegen-arm.cc291 __ uxtb16(temp3, Operand(temp1, ROR, 0));
292 __ uxtb16(temp4, Operand(temp1, ROR, 8));
304 __ uxtb(temp3, Operand(temp1, ROR, 8));
306 __ uxtab(temp3, temp3, Operand(temp1, ROR, 0));
H A Dconstants-arm.h232 ROR = 3 << 5, // Rotate right. enumerator in enum:v8::internal::ShiftOp
234 // RRX is encoded as ROR with shift_imm == 0.
237 // detect it and emit the correct ROR shift operand with shift_imm == 0.
H A Ddisasm-arm.cc204 if ((shift == ROR) && (shift_amount == 0)) {
H A Dassembler-arm.cc289 if ((shift_op == ROR) && (shift_imm == 0)) {
290 // ROR #0 is functionally equivalent to LSL #0 and this allow us to encode
291 // RRX as ROR #0 (See below).
294 // encoded as ROR with shift_imm == 0
296 shift_op_ = ROR;
1796 // Operand maps ROR #0 to LSL #0.
1797 DCHECK((src.shift_op() == ROR) ||
1820 // Operand maps ROR #0 to LSL #0.
1821 DCHECK((src2.shift_op() == ROR) ||
1842 // Operand maps ROR #
[all...]
/external/lldb/source/Plugins/Process/Utility/
H A DARMUtils.h190 static inline uint32_t ROR(const uint32_t value, const uint32_t amount, bool *success) function in namespace:lldb_private
/external/vixl/test/
H A Dtest-disasm-a64.cc673 COMPARE(and_(w12, w13, Operand(w14, ROR, 4)), "and w12, w13, w14, ror #4");
679 COMPARE(bic(w27, w28, Operand(w29, ROR, 8)), "bic w27, w28, w29, ror #8");
685 COMPARE(orr(w12, w13, Operand(w14, ROR, 12)), "orr w12, w13, w14, ror #12");
691 COMPARE(orn(w27, w28, Operand(w29, ROR, 16)), "orn w27, w28, w29, ror #16");
697 COMPARE(eor(w12, w13, Operand(w14, ROR, 20)), "eor w12, w13, w14, ror #20");
703 COMPARE(eon(w27, w28, Operand(w29, ROR, 24)), "eon w27, w28, w29, ror #24");
709 COMPARE(ands(w12, w13, Operand(w14, ROR, 4)), "ands w12, w13, w14, ror #4");
715 COMPARE(bics(w27, w28, Operand(w29, ROR, 8)), "bics w27, w28, w29, ror #8");
718 COMPARE(tst(w2, Operand(w3, ROR, 10)), "tst w2, w3, ror #10");
720 COMPARE(tst(x2, Operand(x3, ROR, 4
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H A Dtest-assembler-a64.cc268 __ Mvn(w8, Operand(w0, ROR, 13));
269 __ Mvn(x9, Operand(x1, ROR, 14));
434 __ Mov(w21, Operand(w11, ROR, 13));
435 __ Mov(x22, Operand(x12, ROR, 14));
492 __ Orr(w8, w0, Operand(w1, ROR, 12));
493 __ Orr(x9, x0, Operand(x1, ROR, 12));
581 __ Orn(w8, w0, Operand(w1, ROR, 16));
582 __ Orn(x9, x0, Operand(x1, ROR, 16));
648 __ And(w8, w0, Operand(w1, ROR, 28));
649 __ And(x9, x0, Operand(x1, ROR, 2
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/external/chromium_org/v8/src/compiler/arm/
H A Dcode-generator-arm.cc83 return Operand(InputRegister(index + 0), ROR, InputInt5(index + 1));
85 return Operand(InputRegister(index + 0), ROR, InputRegister(index + 1));
/external/vixl/src/a64/
H A Dmacro-assembler-a64.cc613 (operand.IsShiftedRegister() && (operand.shift() == ROR))) {
681 (operand.IsShiftedRegister() && (operand.shift() == ROR))) {
682 // Add/sub with carry (immediate or ROR shifted register.)
689 VIXL_ASSERT(operand.shift() != ROR);
/external/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp943 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR ||
1009 // A logical shifter is LSL, LSR, ASR or ROR.
1012 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR) &&
2283 .Case("ror", AArch64_AM::ROR)
2304 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR ||
/external/llvm/test/MC/ARM/
H A Dbasic-thumb-instructions.s484 @ ROR
/external/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp1198 R[t] = ROR(data, 8*UInt(address<1:0>));
3196 // A8.6.139 ROR (immediate) -- Encoding T1
3239 // A8.6.139 ROR (immediate)
5793 R[t] = ROR(data, 8*UInt(address<1:0>));
5901 // R[t] = ROR(data, 8*UInt(address<1:0>));
5902 data = ROR (data, Bits32 (address, 1, 0), &success);
5934 R[t] = ROR(data, 8*UInt(address<1:0>));
6109 // R[t] = ROR(data, 8*UInt(address<1:0>));
6110 data = ROR (data, Bits32 (address, 1, 0), &success);
7779 rotated = ROR(
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