Searched refs:VMOV (Results 1 - 25 of 31) sorted by relevance

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/external/libhevc/decoder/arm/
H A Dihevcd_fmt_conv_420sp_to_rgba8888.s117 VMOV.16 D0[0],R10 @//C1
120 VMOV.16 D0[1],R10 @//C2
123 VMOV.16 D0[2],R10 @//C3
126 VMOV.16 D0[3],R10 @//C4
175 @VMOV.I8 Q1,#128
229 VMOV.I8 D17,#0
239 VMOV.I8 D23,#0
280 VMOV.I8 D17,#0
290 VMOV.I8 D23,#0
312 @VMOV
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/external/libhevc/common/arm/
H A Dihevc_sao_edge_offset_class0_chroma.s82 VMOV.I8 Q1,#2 @const_2 = vdupq_n_s8(2)
86 VMOV.I16 Q2,#0 @const_min_clip = vdupq_n_s16(0)
90 VMOV.I16 Q3,#255 @const_max_clip = vdupq_n_u16((1 << bit_depth) - 1)
96 VMOV.S8 Q4,#0xFF @au1_mask = vdupq_n_s8(-1)
126 VMOV.8 D8[0],r12 @vsetq_lane_s8(pu1_avail[0], au1_mask, 0)
127 VMOV.8 D8[1],r12 @vsetq_lane_s8(pu1_avail[0], au1_mask, 1)
132 VMOV.16 D8[0],r12 @au1_mask = vsetq_lane_s8(-1, au1_mask, 0)
138 VMOV.8 D9[6],r12 @au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 14)
139 VMOV.8 D9[7],r12 @au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
153 VMOV
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H A Dihevc_sao_edge_offset_class3_chroma.s274 VMOV.I8 Q0,#2 @const_2 = vdupq_n_s8(2)
275 VMOV.I16 Q1,#0 @const_min_clip = vdupq_n_s16(0)
276 VMOV.I16 Q2,#255 @const_max_clip = vdupq_n_u16((1 << bit_depth) - 1)
284 VMOV.S8 Q4,#0xFF @au1_mask = vdupq_n_s8(-1)
300 VMOV.8 D8[0],r8 @au1_mask = vsetq_lane_s8(-1, au1_mask, 0)
304 VMOV.8 D8[1],r8 @au1_mask = vsetq_lane_s8(-1, au1_mask, 0)
308 VMOV.8 D9[6],r8 @au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
309 VMOV.8 D9[7],r8 @au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
319 VMOV.I8 Q9,#0
350 VMOV
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H A Dihevc_sao_edge_offset_class2_chroma.s262 VMOV.I8 Q0,#2 @const_2 = vdupq_n_s8(2)
266 VMOV.I16 Q1,#0 @const_min_clip = vdupq_n_s16(0)
270 VMOV.I16 Q2,#255 @const_max_clip = vdupq_n_u16((1 << bit_depth) - 1)
292 VMOV.S8 Q4,#0XFF @au1_mask = vdupq_n_s8(-1)
306 VMOV.8 D8[0],r8 @au1_mask = vsetq_lane_s8(-1, au1_mask, 0)
309 VMOV.8 D8[1],r8 @au1_mask = vsetq_lane_s8(-1, au1_mask, 0)
313 VMOV.8 D9[6],r8 @au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
314 VMOV.8 D9[7],r8 @au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
363 VMOV.I8 Q9,#0
367 VMOV
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H A Dihevc_sao_edge_offset_class0.s78 VMOV.I8 Q1,#2 @const_2 = vdupq_n_s8(2)
82 VMOV.I16 Q2,#0 @const_min_clip = vdupq_n_s16(0)
86 VMOV.I16 Q3,#255 @const_max_clip = vdupq_n_u16((1 << bit_depth) - 1)
92 VMOV.S8 Q4,#0xFF @au1_mask = vdupq_n_s8(-1)
122 VMOV.8 D8[0],r12 @vsetq_lane_s8(pu1_avail[0], au1_mask, 0)
127 VMOV.8 D8[0],r12 @au1_mask = vsetq_lane_s8(-1, au1_mask, 0)
133 VMOV.8 D9[7],r12 @au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
147 VMOV.8 D15[7],r11 @vsetq_lane_u8(pu1_src_left[ht - row], pu1_cur_row_tmp, 15)
161 VMOV.8 D29[7],r11 @II Iteration vsetq_lane_u8(pu1_src_left[ht - row], pu1_cur_row_tmp, 15)
173 VMOV
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H A Dihevc_sao_edge_offset_class2.s180 VMOV.I8 Q0,#2 @const_2 = vdupq_n_s8(2)
184 VMOV.I16 Q1,#0 @const_min_clip = vdupq_n_s16(0)
188 VMOV.I16 Q2,#255 @const_max_clip = vdupq_n_u16((1 << bit_depth) - 1)
202 VMOV.S8 Q4,#0xFF @au1_mask = vdupq_n_s8(-1)
220 VMOV.8 d8[0],r8 @au1_mask = vsetq_lane_s8((-1||pu1_avail[0]), au1_mask, 0)
224 VMOV.8 d9[7],r8 @au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
264 VMOV.I8 Q9,#0
274 VMOV.8 D18[0],r5 @I pu1_next_row_tmp = vsetq_lane_u8(pu1_src_cpy[src_strd + 16], pu1_next_row_tmp, 0)
289 VMOV.8 D14[0],r4 @I sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[0] - pu1_src_left_cpy[ht_tmp - 1 - row]), sign_up, 0)
316 VMOV Q
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H A Dihevc_sao_edge_offset_class3.s192 VMOV.I8 Q0,#2 @const_2 = vdupq_n_s8(2)
196 VMOV.I16 Q1,#0 @const_min_clip = vdupq_n_s16(0)
200 VMOV.I16 Q2,#255 @const_max_clip = vdupq_n_u16((1 << bit_depth) - 1)
210 VMOV.S8 Q4,#0xFF @au1_mask = vdupq_n_s8(-1)
229 VMOV.8 d8[0],r8 @au1_mask = vsetq_lane_s8(-1, au1_mask, 0)
234 VMOV.8 d9[7],r8 @au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
271 VMOV.I8 Q9,#0
288 VMOV.8 D19[7],r8 @I vsetq_lane_u8
304 VMOV.8 D15[7],r8 @I sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[15] - pu1_src_cpy[16 - src_strd]), sign_up, 15)
331 VMOV Q
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H A Dihevc_sao_edge_offset_class1.s105 VMOV.I8 Q0,#2 @const_2 = vdupq_n_s8(2)
106 VMOV.I16 Q1,#0 @const_min_clip = vdupq_n_s16(0)
107 VMOV.I16 Q2,#255 @const_max_clip = vdupq_n_u16((1 << bit_depth) - 1)
189 VMOV Q5,Q15 @II pu1_cur_row = pu1_next_row
254 VMOV Q5,Q9 @pu1_cur_row = pu1_next_row
329 VMOV Q5,Q15 @II pu1_cur_row = pu1_next_row
H A Dihevc_sao_edge_offset_class1_chroma.s109 VMOV.I8 Q0,#2 @const_2 = vdupq_n_s8(2)
110 VMOV.I16 Q1,#0 @const_min_clip = vdupq_n_s16(0)
111 VMOV.I16 Q2,#255 @const_max_clip = vdupq_n_u16((1 << bit_depth) - 1)
197 VMOV Q5,Q15 @II pu1_cur_row = pu1_next_row
272 VMOV Q5,Q9 @pu1_cur_row = pu1_next_row
360 VMOV Q5,Q15 @II pu1_cur_row = pu1_next_row
H A Dihevc_sao_band_offset_luma.s132 VMOV.I8 D29,#16 @vdup_n_u8(16)
H A Dihevc_sao_band_offset_chroma.s141 VMOV.I8 D30,#16 @vdup_n_u8(16)
224 VMOV.I8 D29,#16 @vdup_n_u8(16)
/external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/
H A DomxSP_FFTFwd_RToCCS_F32_Sfs_s.S156 VMOV dzero[0],zero
157 VMOV dZero[0],zero
271 VMOV dX0r[1],zero
273 VMOV dX0i[1],zero
300 VMOV half, #0.5
H A DomxSP_FFTInv_CToC_FC32_Sfs_s.S191 VMOV sN,N
193 VMOV one, 1.0
H A DomxSP_FFTFwd_RToCCS_S32_Sfs_s.S171 VMOV dShift[0],scale
172 VMOV dzero[0],zero
174 VMOV dZero[0],zero
414 VMOV dX0r[1],zero
416 VMOV dX0i[1],zero
H A DomxSP_FFTInv_CCSToR_F32_Sfs_s.S261 VMOV sN,N
263 VMOV one, 1.0
H A DarmSP_FFTInv_CCSToR_F32_preTwiddleRadix2_unsafe_s.S138 VMOV half, 0.5
H A DomxSP_FFTFwd_RToCCS_S16_Sfs_s.S428 VMOV dX0r[1],zero
430 VMOV dX0i[1],zero
525 VMOV dX0r[1],zero
527 VMOV dX0i[1],zero
H A DarmSP_FFT_CToC_SC16_Radix8_fs_unsafe_s.S306 VMOV dT0[0],t0
468 VMOV dT0[0],t0
H A DarmSP_FFT_CToC_SC32_Radix8_fs_unsafe_s.S297 VMOV dT0[0],t0
456 VMOV dT0[0],t0
H A DarmSP_FFT_CToC_FC32_Radix4_ls_unsafe_s.S230 VMOV qZ0,qX0
H A DomxSP_FFTInv_CCSToR_S32_Sfs_s.S176 VMOV dShift[0],scale
H A DarmSP_FFT_CToC_FC32_Radix8_fs_unsafe_s.S284 VMOV dT0[0], t0
H A DarmSP_FFT_CToC_SC32_Radix4_ls_unsafe_s.S236 VMOV qZ0,qX0 @// move qX0 so as to load for the next iteration
/external/chromium_org/third_party/opus/src/celt/arm/
H A Dcelt_pitch_xcorr_arm.s80 ; Unlike VMOV, VAND is a data processsing instruction (and doesn't get
81 ; assembled to VMOV, like VORR would), so it dual-issues with the prior VLD1.
172 VMOV.S32 q15, #1
204 VMOV.I32 q0, #0
249 VMOV.32 r0, d30[0]
/external/libopus/celt/arm/
H A Dcelt_pitch_xcorr_arm.s80 ; Unlike VMOV, VAND is a data processsing instruction (and doesn't get
81 ; assembled to VMOV, like VORR would), so it dual-issues with the prior VLD1.
172 VMOV.S32 q15, #1
204 VMOV.I32 q0, #0
249 VMOV.32 r0, d30[0]

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