/external/llvm/include/llvm/CodeGen/ |
H A D | LiveIntervalUnion.h | 119 Query(LiveInterval *VReg, LiveIntervalUnion *LIU): argument 120 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false), 135 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) { argument 136 assert(VReg && LIU && "Invalid arguments"); 137 if (UserTag == UTag && VirtReg == VReg && 144 VirtReg = VReg; 162 bool isSeenInterference(LiveInterval *VReg) const;
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H A D | LiveRangeEdit.h | 102 void MRI_NoteNewVirtualRegister(unsigned VReg) override;
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H A D | MachineRegisterInfo.h | 753 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 755 unsigned getLiveInPhysReg(unsigned VReg) const;
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/external/llvm/lib/CodeGen/ |
H A D | LiveIntervalUnion.cpp | 150 LiveInterval *VReg = LiveUnionI.value(); local 151 if (VReg != RecentReg && !isSeenInterference(VReg)) { 152 RecentReg = VReg; 153 InterferingVRegs.push_back(VReg);
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H A D | LiveRangeEdit.cpp | 35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); local 37 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); 39 LiveInterval &LI = LIS.createEmptyInterval(VReg); 44 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); local 46 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); 48 return VReg; 398 LiveRangeEdit::MRI_NoteNewVirtualRegister(unsigned VReg) argument 403 NewRegs.push_back(VReg);
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H A D | MachineFunction.cpp | 438 unsigned VReg = MRI.getLiveInVirtReg(PReg); local 439 if (VReg) { 440 const TargetRegisterClass *VRegRC = MRI.getRegClass(VReg); 450 return VReg; 452 VReg = MRI.createVirtualRegister(RC); 453 MRI.addLiveIn(PReg, VReg); 454 return VReg;
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H A D | TailDuplication.cpp | 245 unsigned VReg = SSAUpdateVRs[i]; local 246 SSAUpdate.Initialize(VReg); 250 MachineInstr *DefMI = MRI->getVRegDef(VReg); 254 SSAUpdate.AddAvailableValue(DefBB, VReg); 259 SSAUpdateVals.find(VReg); 267 MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg);
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H A D | MachineRegisterInfo.cpp | 343 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 345 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 347 if (I->second == VReg)
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H A D | InlineSpiller.cpp | 184 void insertReload(unsigned VReg, SlotIndex, MachineBasicBlock::iterator MI); 185 void insertSpill(unsigned VReg, bool isKill, MachineBasicBlock::iterator MI); 1034 unsigned VReg =0) { 1051 if (VReg) { 1052 MachineOperand *MO = I->findRegisterDefOperand(VReg);
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H A D | RegAllocFast.cpp | 187 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 284 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); local 287 if (!VReg) { 290 VReg = MRI->createVirtualRegister(RC); 293 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 294 return VReg; 317 unsigned VReg = getVR(Op, VRBaseMap); local 318 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 326 // shrink VReg's register class within reason. For example, if VReg == GR32 327 // and II requires a GR32_NOSP, just constrain VReg t [all...] |
H A D | InstrEmitter.h | 84 /// ConstrainForSubReg - Try to constrain VReg to a register class that 87 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
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/external/llvm/lib/Target/NVPTX/InstPrinter/ |
H A D | NVPTXInstPrinter.cpp | 70 unsigned VReg = RegNo & 0x0FFFFFFF; local 71 OS << VReg; local
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/external/llvm/lib/Target/ARM/ |
H A D | Thumb1RegisterInfo.cpp | 557 unsigned VReg = 0; 649 VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass); 654 emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg, 657 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset); 661 emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII, 664 MI.getOperand(FIOperandNum).ChangeToRegister(VReg, false, false, true);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.cpp | 291 // Find the original register that VReg is copied from. 292 static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) { argument 293 while (TargetRegisterInfo::isVirtualRegister(VReg)) { 294 const MachineInstr *DefMI = MRI.getVRegDef(VReg); 296 return VReg; 297 VReg = DefMI->getOperand(1).getReg(); 299 return VReg; 302 // Determine if VReg is defined by an instruction that can be folded into a 305 static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg, argument 307 VReg [all...] |
H A D | AArch64ISelLowering.cpp | 1862 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass); local 1863 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); 1891 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass); local 1892 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 2374 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); local 2375 if (!VReg) 2376 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); 2378 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2393 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); local 2394 if (!VReg) 2395 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); 2397 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); 2533 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); local 2534 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrV 2570 unsigned VReg; local 2595 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); local 2612 unsigned VReg; local 2637 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ? local 2688 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); local 2857 unsigned VReg; local 2880 unsigned VReg; local 2908 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); local 2926 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); local 2953 unsigned VReg; local 2976 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); local 3048 unsigned VReg; local 4277 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 || local 4300 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 || local [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 875 unsigned VReg = local 877 RegInfo.addLiveIn(VA.getLocReg(), VReg); 878 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); 880 unsigned VReg = local 882 RegInfo.addLiveIn(VA.getLocReg(), VReg); 883 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1329 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); local 1330 RegInfo.addLiveIn(VA.getLocReg(), VReg); 1331 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); 1382 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); local 1383 RegInfo.addLiveIn(ArgRegs[i], VReg); 1384 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 404 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); local 405 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); 406 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 516 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); local 517 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 518 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); 566 unsigned VReg = MF.addLiveIn(VA.getLocReg(), local 568 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT()); 637 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass); local 638 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MV [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 465 unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass); local 466 RegInfo.addLiveIn(VA.getLocReg(), VReg); 467 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
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/external/llvm/lib/Target/R600/ |
H A D | SIISelLowering.cpp | 1294 // VReg or and SReg. In order to get a more accurate 1657 unsigned VReg = MI->getOperand(0).getReg(); local 1674 MRI.setRegClass(VReg, RC); 1716 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT); local 1719 cast<RegisterSDNode>(VReg)->getReg(), VT);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 820 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); local 821 MF.getRegInfo().addLiveIn(PReg, VReg); 822 return VReg; 3564 unsigned VReg = addLiveIn(MF, ArgReg, RC); local 3568 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 716 unsigned VReg = MRI.createVirtualRegister(RC); local 717 MRI.addLiveIn(VA.getLocReg(), VReg); 718 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT); 767 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I], local 769 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 2446 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], local 2448 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2473 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], local 2475 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
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