Searched refs:cp15 (Results 1 - 5 of 5) sorted by relevance

/external/qemu/target-arm/
H A Dmachine.c24 qemu_put_be32(f, env->cp15.c0_cpuid);
25 qemu_put_be32(f, env->cp15.c0_cachetype);
26 qemu_put_be32(f, env->cp15.c0_cssel);
27 qemu_put_be32(f, env->cp15.c1_sys);
28 qemu_put_be32(f, env->cp15.c1_coproc);
29 qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
30 qemu_put_be32(f, env->cp15.c1_secfg);
31 qemu_put_be32(f, env->cp15.c1_sedbg);
32 qemu_put_be32(f, env->cp15.c1_nseac);
33 qemu_put_be32(f, env->cp15
[all...]
H A Dhelper.c57 env->cp15.c0_cpuid = id;
64 env->cp15.c0_cachetype = 0x1dd20d2;
65 env->cp15.c1_sys = 0x00090078;
71 env->cp15.c0_cachetype = 0x0f004006;
72 env->cp15.c1_sys = 0x00000078;
80 env->cp15.c0_cachetype = 0x1dd20d2;
81 env->cp15.c1_sys = 0x00090078;
104 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
105 memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
106 env->cp15
[all...]
H A Dcpu.h96 /* CPU state for each instance of a generic timer (in cp15 c14) */
139 /* System control coprocessor (cp15) */
189 } cp15; member in struct:CPUARMState
312 env->cp15.c13_tls2 = newtls;
442 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
748 #define ARM_CPUID(env) (env->cp15.c0_cpuid)
H A Dtranslate.c2489 return env->cp15.c9_pmuserenr;
2521 tmp = load_cpu_field(cp15.c13_tls1);
2524 tmp = load_cpu_field(cp15.c13_tls2);
2527 tmp = load_cpu_field(cp15.c13_tls3);
2538 store_cpu_field(tmp, cp15.c13_tls1);
2541 store_cpu_field(tmp, cp15.c13_tls2);
2544 store_cpu_field(tmp, cp15.c13_tls3);
2554 /* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2561 /* M profile cores use memory mapped registers instead of cp15. */
2577 /* We special case a number of cp15 instruction
[all...]
/external/qemu/hw/arm/
H A Darmv7m_nvic.c153 return cpu_single_env->cp15.c0_cpuid;

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