/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
H A D | armVCM4P10_InterpolateLuma_HalfDiagHorVer4x4_unsafe_s.S | 32 VLD1.8 {d0,d1},[r0],r1 35 VEXT.8 d4,d0,d1,#1 36 VEXT.8 d2,d0,d1,#2 37 VEXT.8 d3,d0,d1,#3 38 VEXT.8 d5,d0,d1,#4 39 VEXT.8 d1,d0,d1,#5 42 VADDL.U8 q5,d0,d1 43 VLD1.8 {d0,d1},[r0],r1 46 VEXT.8 d4,d0,d1,#1 47 VEXT.8 d2,d0,d [all...] |
H A D | armVCM4P10_TransformResidual4x4_s.S | 32 VLD4.16 {d0,d1,d2,d3},[r1] 34 VADD.I16 d5,d0,d2 35 VSUB.I16 d6,d0,d2 40 VADD.I16 d0,d5,d8 44 VTRN.16 d0,d1 47 VADD.I16 d5,d0,d2 48 VSUB.I16 d6,d0,d2 53 VADD.I16 d0,d5,d8 57 VRSHR.S16 d0,d0,# [all...] |
H A D | omxVCM4P10_PredictIntra_4x4_s.S | 51 VLD1.8 {d0[]},[r0],r10 57 VST1.32 {d0[0]},[r3],r12 63 VLD1.32 {d0[0]},[r1] 67 VST1.32 {d0[0]},[r3],r12 68 VST1.32 {d0[0]},[r11],r12 69 VST1.32 {d0[0]},[r3] 70 VST1.32 {d0[0]},[r11] 77 VLD1.8 {d0[0]},[r0],r10 78 VLD1.8 {d0[1]},[r9],r10 79 VLD1.8 {d0[ [all...] |
H A D | omxVCM4P10_PredictIntra_16x16_s.S | 58 VLD1.8 {d0,d1},[r1] 61 VST1.8 {d0,d1},[r3],r10 62 VST1.8 {d0,d1},[r8],r10 63 VST1.8 {d0,d1},[r3],r10 64 VST1.8 {d0,d1},[r8],r10 65 VST1.8 {d0,d1},[r3],r10 66 VST1.8 {d0,d1},[r8],r10 67 VST1.8 {d0,d1},[r3],r10 68 VST1.8 {d0,d1},[r8],r10 69 VST1.8 {d0,d [all...] |
H A D | omxVCM4P10_TransformDequantChromaDCFromPair_s.S | 33 vmov.i16 d0, #0 35 vst1.16 {d0}, [r1] 61 vmov d0, r5, r6 62 vrev32.16 d0, d0 64 vmull.s16 q1, d0, d1
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H A D | omxVCM4P10_DequantTransformResidualFromPairAndAdd_s.S | 62 VLD1.16 {d0,d1,d2,d3},[r4] 68 VMUL.I16 d0,d0,d8 72 VMOVNE.16 d0[0],r10 73 VTRN.16 d0,d1 77 VADD.I16 d5,d0,d2 78 VSUB.I16 d6,d0,d2 83 VADD.I16 d0,d5,d8 87 VTRN.16 d0,d1 90 VADD.I16 d5,d0,d [all...] |
H A D | omxVCM4P10_TransformDequantLumaDCFromPair_s.S | 33 VLD4.16 {d0,d1,d2,d3},[r0] 38 VADD.I16 d4,d0,d1 40 VSUB.I16 d6,d0,d1 44 VADD.I16 d0,d4,d5 49 VTRN.16 d0,d1 52 VADD.I16 d4,d0,d1 54 VSUB.I16 d6,d0,d1 56 VADD.I16 d0,d4,d5 65 VMLAL.S16 q3,d0,d5 69 VSHRN.I32 d0,q [all...] |
H A D | omxVCM4P10_PredictIntraChroma_8x8_s.S | 66 VLD1.8 {d0},[r1] 68 VPADDL.U8 d2,d0 81 VTBL.8 d0,{d2-d3},d5 86 VST1.8 {d0},[r3],r10 87 VST1.8 {d0},[r9],r10 88 VST1.8 {d0},[r3],r10 89 VST1.8 {d0},[r9],r10 101 VDUP.8 d0,d1[0] 107 VLD1.8 {d0},[r1] 109 VPADDL.U8 d2,d0 [all...] |
H A D | armVCM4P10_Interpolate_Chroma_s.S | 54 VLD1.8 {d0},[r0],r10 69 VMULL.U8 q2,d0,d12 83 VLD1.8 {d0},[r0],r10 88 VMLAL.U8 q12,d0,d14 108 VMULL.U8 q2,d0,d12 113 VLD1.8 {d0},[r0],r10 115 VMLAL.U8 q3,d0,d14 131 VMULL.U8 q2,d0,d12 136 VLD1.8 {d0},[r0],r10 138 VMLAL.U8 q3,d0,d1 [all...] |
H A D | omxVCM4P10_InterpolateLuma_s.S | 116 VRHADD.U8 d0,d0,d9 121 VST1.32 {d0[0]},[r2],r3 133 VRHADD.U8 d22,d22,d0 152 VRHADD.U8 d0,d0,d14 157 VST1.32 {d0[0]},[r2],r3 170 VRHADD.U8 d22,d22,d0 185 VST1.32 {d0[0]},[r2],r3 203 VRHADD.U8 d0,d [all...] |
H A D | armVCM4P10_InterpolateLuma_HalfVer4x4_unsafe_s.S | 45 VMLS.I16 d0,d16,d30 61 VADD.I16 d0,d0,d20 65 VQRSHRUN.S16 d0,q0,#5
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H A D | armVCM4P10_DeblockingChroma_unsafe_s.S | 41 VLD1.8 {d0[]},[r2] 60 VLD1.8 {d0[]},[r2]
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H A D | omxVCM4P10_FilterDeblockingLuma_VerEdge_I_s.S | 35 VLD1.8 {d0[]},[r2] 76 VCGT.U8 d16,d0,d13 115 VLD1.8 {d0[]},[r7] 123 VLD1.8 {d0[]},[r7] 154 VLD1.8 {d0[]},[r7] 162 VLD1.8 {d0[]},[r2]
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H A D | armVCM4P10_InterpolateLuma_HalfDiagVerHor4x4_unsafe_s.S | 32 VLD1.8 {d0,d1},[r0],r1 39 VADDL.U8 q9,d0,d10 86 VEXT.8 d29,d19,d0,#2 122 VQRSHRUN.S32 d0,q0,#10 126 VQMOVN.U16 d0,q0
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H A D | omxVCM4P10_FilterDeblockingChroma_HorEdge_I_s.S | 33 VLD1.8 {d0[]},[r2]! 59 VCGT.U8 d16,d0,d13 90 VLD1.8 {d0[]},[r2]
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H A D | omxVCM4P10_FilterDeblockingLuma_HorEdge_I_s.S | 35 VLD1.8 {d0[]},[r2] 61 VCGT.U8 d16,d0,d13 112 VLD1.8 {d0[]},[r7]
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/frameworks/rs/cpu_ref/ |
H A D | rsCpuIntrinsics_neon_ColorMatrix.S | 72 #vmul.f32 q0,q0,d0[0] 73 #vmla.f32 q0,q0,d0[0] 83 vld4.8 {d0[0],d1[0],d2[0],d3[0]}, [r1]! 84 vld4.8 {d0[1],d1[1],d2[1],d3[1]}, [r1]! 85 vld4.8 {d0[2],d1[2],d2[2],d3[2]}, [r1]! 86 vld4.8 {d0[3],d1[3],d2[3],d3[3]}, [r1]! 90 vld4.8 {d0[0],d1[0],d2[0],d3[0]}, [r1]! 91 vld4.8 {d0[1],d1[1],d2[1],d3[1]}, [r1]! 92 vld4.8 {d0[2],d1[2],d2[2],d3[2]}, [r1]! 93 vld4.8 {d0[ [all...] |
H A D | rsCpuIntrinsics_neon_Convolve.S | 69 vmull.s16 q8, d4, d0[0] 70 vmlal.s16 q8, d5, d0[1] 71 vmlal.s16 q8, d6, d0[2] 72 vmlal.s16 q8, d8, d0[3] 79 vmull.s16 q9, d5, d0[0] 80 vmlal.s16 q9, d6, d0[1] 81 vmlal.s16 q9, d7, d0[2] 82 vmlal.s16 q9, d9, d0[3] 132 vld1.16 {d0, d1, d2, d3}, [r6]! 164 vmull.s16 q4, d18, d0[ [all...] |
H A D | rsCpuIntrinsics_neon_3DLUT.S | 140 2: vld4.u8 {d0,d2,d4,d6}, [r1]! 147 vmovl.u8 q0, d0 189 lanepair dst=d12, src=d12, xr0=d0[0], xr1=d0[1], yr0=d2[0], yr1=d2[1], zr0=d4[0], zr1=d4[1] 192 lanepair dst=d13, src=d13, xr0=d0[2], xr1=d0[3], yr0=d2[2], yr1=d2[3], zr0=d4[2], zr1=d4[3] 218 4: vld1.u32 {d0[]}, [r1] 219 vmov d2, d0 220 vmov d4, d0 221 vmov d6, d0 [all...] |
H A D | rsCpuIntrinsics_neon_Blur.S | 88 vmull.u16 q12, d28, d0[0] 90 vmull.u16 q13, d29, d0[0] 92 vmull.u16 q14, d30, d0[0] 94 vmull.u16 q15, d31, d0[0] 173 vmull.u16 q14, d18, d0[0] 174 vmull.u16 q15, d19, d0[0] 217 vmlal.u16 q14, d24, d0[3] 218 vmlal.u16 q15, d25, d0[3] 219 vmlal.u16 q14, d26, d0[3] 220 vmlal.u16 q15, d27, d0[ [all...] |
H A D | rsCpuIntrinsics_neon_Blend.S | 85 vmull.u8 q0, d14, d0 111 vrshrn.u16 d0, q0, #8 201 vrshrn.u16 d0, q0, #8 214 vmull.u8 q0, d0, d22 240 vrshrn.u16 d0, q0, #8 268 vmull.u8 q0, d22, d0 302 vqrshrn.u16 d0, q0, #8 315 vmull.u8 q0, d22, d0 349 vqrshrn.u16 d0, q0, #8 362 vmull.u8 q0, d0, d1 [all...] |
/frameworks/base/media/tests/audiotests/ |
H A D | shared_mem_test.cpp | 180 long d0; local 182 d0 = 32768. * sin(phi); 184 if(d0 >= 32767) d0 = 32767; 185 if(d0 <= -32768) d0 = -32768; 186 sin1024[i0] = (short)d0;
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/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/reference/vc/m4p10/src/ |
H A D | armVCM4P10_FwdTransformResidual4x4.c | 55 int d0 = pSrc[i+0]; local 59 int e0 = d0 + d3; 60 int e1 = d0 - d3;
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H A D | armVCM4P10_TransformResidual4x4.c | 56 int d0 = pSrc[i+0]; local 60 int e0 = d0 + d2; 61 int e1 = d0 - d2;
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/frameworks/av/media/libstagefright/codecs/aacenc/src/asm/ARMV7/ |
H A D | R4R8First_v7.s | 41 VLD1.I32 {d0, d1, d2, d3}, [r0]! 44 VADD.S32 d4, d0, d1 @ r0 = buf[0] + buf[2]@i0 = buf[1] + buf[3]@ 45 VSUB.S32 d5, d0, d1 @ r1 = buf[0] - buf[2]@i1 = buf[1] - buf[3]@ 78 VADD.S32 d12, d0, d8 79 VSUB.S32 d16, d0, d8 132 VLD1.I32 {d0, d1, d2, d3}, [r0] 134 VADD.S32 d4, d0, d1 @ r0 = buf[0] + buf[2]@ r1 = buf[1] + buf[3]@ 135 VSUB.S32 d5, d0, d1 @ r2 = buf[0] - buf[2]@ r3 = buf[1] - buf[3]@
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