Searched refs:X0011 (Results 1 - 6 of 6) sorted by relevance
/external/valgrind/main/VEX/priv/ |
H A D | host_arm_defs.c | 2732 #define X0011 BITS4(0,0,1,1) macro 2822 instr = XXXXXX__(X1110,X0011,X1010,X0000,rD,X0000); 3408 X0011, scratchNo); 3438 X0011, scratchNo); 3872 insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), 4035 insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), 4039 insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), 4043 insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), 4047 insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), 4061 insn = XXXXXXXX(0xF, X0011, 4871 #undef X0011 macro [all...] |
H A D | host_arm64_defs.c | 3361 #define X0011 BITS4(0,0,1,1) macro 3635 //ZZ #define X0011 BITS4(0,0,1,1) 4935 case ARM64fpb_SUB: b1512 = X0011; break; 4958 case ARM64fpb_SUB: b1512 = X0011; break; 5661 //ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), 5824 //ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), 5828 //ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), 5832 //ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), 5836 //ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), 5850 //ZZ insn = XXXXXXXX(0xF, X0011, [all...] |
/external/oprofile/events/ppc64/970MP/ |
H A D | event_mappings | 13 event:0X0011 mmcr0:0X0000051F mmcr1:0X000000000A46F18C mmcra:0X00002000
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/external/oprofile/events/ppc64/power5++/ |
H A D | event_mappings | 16 event:0X0011 mmcr0:0X00000000 mmcr1:0X000000000A12121E mmcra:0X00000000
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/external/oprofile/events/ppc64/power6/ |
H A D | event_mappings | 17 event:0X0011 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
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/external/oprofile/events/ppc64/power7/ |
H A D | event_mappings | 16 event:0X0011 mmcr0:0X00000000 mmcr1:0X000000001EF4F202 mmcra:0X00000000
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