codegen_util.cc revision 2700f7e1edbcd2518f4978e4cd0e05a4149f91b6
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "dex/compiler_internals.h" 18#include "dex_file-inl.h" 19#include "gc_map.h" 20#include "gc_map_builder.h" 21#include "mapping_table.h" 22#include "mir_to_lir-inl.h" 23#include "dex/quick/dex_file_method_inliner.h" 24#include "dex/quick/dex_file_to_method_inliner_map.h" 25#include "dex/verification_results.h" 26#include "dex/verified_method.h" 27#include "verifier/dex_gc_map.h" 28#include "verifier/method_verifier.h" 29#include "vmap_table.h" 30 31namespace art { 32 33namespace { 34 35/* Dump a mapping table */ 36template <typename It> 37void DumpMappingTable(const char* table_name, const char* descriptor, const char* name, 38 const Signature& signature, uint32_t size, It first) { 39 if (size != 0) { 40 std::string line(StringPrintf("\n %s %s%s_%s_table[%u] = {", table_name, 41 descriptor, name, signature.ToString().c_str(), size)); 42 std::replace(line.begin(), line.end(), ';', '_'); 43 LOG(INFO) << line; 44 for (uint32_t i = 0; i != size; ++i) { 45 line = StringPrintf(" {0x%05x, 0x%04x},", first.NativePcOffset(), first.DexPc()); 46 ++first; 47 LOG(INFO) << line; 48 } 49 LOG(INFO) <<" };\n\n"; 50 } 51} 52 53} // anonymous namespace 54 55bool Mir2Lir::IsInexpensiveConstant(RegLocation rl_src) { 56 bool res = false; 57 if (rl_src.is_const) { 58 if (rl_src.wide) { 59 if (rl_src.fp) { 60 res = InexpensiveConstantDouble(mir_graph_->ConstantValueWide(rl_src)); 61 } else { 62 res = InexpensiveConstantLong(mir_graph_->ConstantValueWide(rl_src)); 63 } 64 } else { 65 if (rl_src.fp) { 66 res = InexpensiveConstantFloat(mir_graph_->ConstantValue(rl_src)); 67 } else { 68 res = InexpensiveConstantInt(mir_graph_->ConstantValue(rl_src)); 69 } 70 } 71 } 72 return res; 73} 74 75void Mir2Lir::MarkSafepointPC(LIR* inst) { 76 DCHECK(!inst->flags.use_def_invalid); 77 inst->u.m.def_mask = ENCODE_ALL; 78 LIR* safepoint_pc = NewLIR0(kPseudoSafepointPC); 79 DCHECK_EQ(safepoint_pc->u.m.def_mask, ENCODE_ALL); 80} 81 82/* Remove a LIR from the list. */ 83void Mir2Lir::UnlinkLIR(LIR* lir) { 84 if (UNLIKELY(lir == first_lir_insn_)) { 85 first_lir_insn_ = lir->next; 86 if (lir->next != NULL) { 87 lir->next->prev = NULL; 88 } else { 89 DCHECK(lir->next == NULL); 90 DCHECK(lir == last_lir_insn_); 91 last_lir_insn_ = NULL; 92 } 93 } else if (lir == last_lir_insn_) { 94 last_lir_insn_ = lir->prev; 95 lir->prev->next = NULL; 96 } else if ((lir->prev != NULL) && (lir->next != NULL)) { 97 lir->prev->next = lir->next; 98 lir->next->prev = lir->prev; 99 } 100} 101 102/* Convert an instruction to a NOP */ 103void Mir2Lir::NopLIR(LIR* lir) { 104 lir->flags.is_nop = true; 105 if (!cu_->verbose) { 106 UnlinkLIR(lir); 107 } 108} 109 110void Mir2Lir::SetMemRefType(LIR* lir, bool is_load, int mem_type) { 111 uint64_t *mask_ptr; 112 uint64_t mask = ENCODE_MEM; 113 DCHECK(GetTargetInstFlags(lir->opcode) & (IS_LOAD | IS_STORE)); 114 DCHECK(!lir->flags.use_def_invalid); 115 if (is_load) { 116 mask_ptr = &lir->u.m.use_mask; 117 } else { 118 mask_ptr = &lir->u.m.def_mask; 119 } 120 /* Clear out the memref flags */ 121 *mask_ptr &= ~mask; 122 /* ..and then add back the one we need */ 123 switch (mem_type) { 124 case kLiteral: 125 DCHECK(is_load); 126 *mask_ptr |= ENCODE_LITERAL; 127 break; 128 case kDalvikReg: 129 *mask_ptr |= ENCODE_DALVIK_REG; 130 break; 131 case kHeapRef: 132 *mask_ptr |= ENCODE_HEAP_REF; 133 break; 134 case kMustNotAlias: 135 /* Currently only loads can be marked as kMustNotAlias */ 136 DCHECK(!(GetTargetInstFlags(lir->opcode) & IS_STORE)); 137 *mask_ptr |= ENCODE_MUST_NOT_ALIAS; 138 break; 139 default: 140 LOG(FATAL) << "Oat: invalid memref kind - " << mem_type; 141 } 142} 143 144/* 145 * Mark load/store instructions that access Dalvik registers through the stack. 146 */ 147void Mir2Lir::AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, 148 bool is64bit) { 149 SetMemRefType(lir, is_load, kDalvikReg); 150 151 /* 152 * Store the Dalvik register id in alias_info. Mark the MSB if it is a 64-bit 153 * access. 154 */ 155 lir->flags.alias_info = ENCODE_ALIAS_INFO(reg_id, is64bit); 156} 157 158/* 159 * Debugging macros 160 */ 161#define DUMP_RESOURCE_MASK(X) 162 163/* Pretty-print a LIR instruction */ 164void Mir2Lir::DumpLIRInsn(LIR* lir, unsigned char* base_addr) { 165 int offset = lir->offset; 166 int dest = lir->operands[0]; 167 const bool dump_nop = (cu_->enable_debug & (1 << kDebugShowNops)); 168 169 /* Handle pseudo-ops individually, and all regular insns as a group */ 170 switch (lir->opcode) { 171 case kPseudoMethodEntry: 172 LOG(INFO) << "-------- method entry " 173 << PrettyMethod(cu_->method_idx, *cu_->dex_file); 174 break; 175 case kPseudoMethodExit: 176 LOG(INFO) << "-------- Method_Exit"; 177 break; 178 case kPseudoBarrier: 179 LOG(INFO) << "-------- BARRIER"; 180 break; 181 case kPseudoEntryBlock: 182 LOG(INFO) << "-------- entry offset: 0x" << std::hex << dest; 183 break; 184 case kPseudoDalvikByteCodeBoundary: 185 if (lir->operands[0] == 0) { 186 // NOTE: only used for debug listings. 187 lir->operands[0] = WrapPointer(ArenaStrdup("No instruction string")); 188 } 189 LOG(INFO) << "-------- dalvik offset: 0x" << std::hex 190 << lir->dalvik_offset << " @ " 191 << reinterpret_cast<char*>(UnwrapPointer(lir->operands[0])); 192 break; 193 case kPseudoExitBlock: 194 LOG(INFO) << "-------- exit offset: 0x" << std::hex << dest; 195 break; 196 case kPseudoPseudoAlign4: 197 LOG(INFO) << reinterpret_cast<uintptr_t>(base_addr) + offset << " (0x" << std::hex 198 << offset << "): .align4"; 199 break; 200 case kPseudoEHBlockLabel: 201 LOG(INFO) << "Exception_Handling:"; 202 break; 203 case kPseudoTargetLabel: 204 case kPseudoNormalBlockLabel: 205 LOG(INFO) << "L" << reinterpret_cast<void*>(lir) << ":"; 206 break; 207 case kPseudoThrowTarget: 208 LOG(INFO) << "LT" << reinterpret_cast<void*>(lir) << ":"; 209 break; 210 case kPseudoIntrinsicRetry: 211 LOG(INFO) << "IR" << reinterpret_cast<void*>(lir) << ":"; 212 break; 213 case kPseudoSuspendTarget: 214 LOG(INFO) << "LS" << reinterpret_cast<void*>(lir) << ":"; 215 break; 216 case kPseudoSafepointPC: 217 LOG(INFO) << "LsafepointPC_0x" << std::hex << lir->offset << "_" << lir->dalvik_offset << ":"; 218 break; 219 case kPseudoExportedPC: 220 LOG(INFO) << "LexportedPC_0x" << std::hex << lir->offset << "_" << lir->dalvik_offset << ":"; 221 break; 222 case kPseudoCaseLabel: 223 LOG(INFO) << "LC" << reinterpret_cast<void*>(lir) << ": Case target 0x" 224 << std::hex << lir->operands[0] << "|" << std::dec << 225 lir->operands[0]; 226 break; 227 default: 228 if (lir->flags.is_nop && !dump_nop) { 229 break; 230 } else { 231 std::string op_name(BuildInsnString(GetTargetInstName(lir->opcode), 232 lir, base_addr)); 233 std::string op_operands(BuildInsnString(GetTargetInstFmt(lir->opcode), 234 lir, base_addr)); 235 LOG(INFO) << StringPrintf("%5p: %-9s%s%s", 236 base_addr + offset, 237 op_name.c_str(), op_operands.c_str(), 238 lir->flags.is_nop ? "(nop)" : ""); 239 } 240 break; 241 } 242 243 if (lir->u.m.use_mask && (!lir->flags.is_nop || dump_nop)) { 244 DUMP_RESOURCE_MASK(DumpResourceMask(lir, lir->u.m.use_mask, "use")); 245 } 246 if (lir->u.m.def_mask && (!lir->flags.is_nop || dump_nop)) { 247 DUMP_RESOURCE_MASK(DumpResourceMask(lir, lir->u.m.def_mask, "def")); 248 } 249} 250 251void Mir2Lir::DumpPromotionMap() { 252 int num_regs = cu_->num_dalvik_registers + mir_graph_->GetNumUsedCompilerTemps(); 253 for (int i = 0; i < num_regs; i++) { 254 PromotionMap v_reg_map = promotion_map_[i]; 255 std::string buf; 256 if (v_reg_map.fp_location == kLocPhysReg) { 257 StringAppendF(&buf, " : s%d", v_reg_map.FpReg & FpRegMask()); 258 } 259 260 std::string buf3; 261 if (i < cu_->num_dalvik_registers) { 262 StringAppendF(&buf3, "%02d", i); 263 } else if (i == mir_graph_->GetMethodSReg()) { 264 buf3 = "Method*"; 265 } else { 266 StringAppendF(&buf3, "ct%d", i - cu_->num_dalvik_registers); 267 } 268 269 LOG(INFO) << StringPrintf("V[%s] -> %s%d%s", buf3.c_str(), 270 v_reg_map.core_location == kLocPhysReg ? 271 "r" : "SP+", v_reg_map.core_location == kLocPhysReg ? 272 v_reg_map.core_reg : SRegOffset(i), 273 buf.c_str()); 274 } 275} 276 277/* Dump instructions and constant pool contents */ 278void Mir2Lir::CodegenDump() { 279 LOG(INFO) << "Dumping LIR insns for " 280 << PrettyMethod(cu_->method_idx, *cu_->dex_file); 281 LIR* lir_insn; 282 int insns_size = cu_->code_item->insns_size_in_code_units_; 283 284 LOG(INFO) << "Regs (excluding ins) : " << cu_->num_regs; 285 LOG(INFO) << "Ins : " << cu_->num_ins; 286 LOG(INFO) << "Outs : " << cu_->num_outs; 287 LOG(INFO) << "CoreSpills : " << num_core_spills_; 288 LOG(INFO) << "FPSpills : " << num_fp_spills_; 289 LOG(INFO) << "CompilerTemps : " << mir_graph_->GetNumUsedCompilerTemps(); 290 LOG(INFO) << "Frame size : " << frame_size_; 291 LOG(INFO) << "code size is " << total_size_ << 292 " bytes, Dalvik size is " << insns_size * 2; 293 LOG(INFO) << "expansion factor: " 294 << static_cast<float>(total_size_) / static_cast<float>(insns_size * 2); 295 DumpPromotionMap(); 296 for (lir_insn = first_lir_insn_; lir_insn != NULL; lir_insn = lir_insn->next) { 297 DumpLIRInsn(lir_insn, 0); 298 } 299 for (lir_insn = literal_list_; lir_insn != NULL; lir_insn = lir_insn->next) { 300 LOG(INFO) << StringPrintf("%x (%04x): .word (%#x)", lir_insn->offset, lir_insn->offset, 301 lir_insn->operands[0]); 302 } 303 304 const DexFile::MethodId& method_id = 305 cu_->dex_file->GetMethodId(cu_->method_idx); 306 const Signature signature = cu_->dex_file->GetMethodSignature(method_id); 307 const char* name = cu_->dex_file->GetMethodName(method_id); 308 const char* descriptor(cu_->dex_file->GetMethodDeclaringClassDescriptor(method_id)); 309 310 // Dump mapping tables 311 if (!encoded_mapping_table_.empty()) { 312 MappingTable table(&encoded_mapping_table_[0]); 313 DumpMappingTable("PC2Dex_MappingTable", descriptor, name, signature, 314 table.PcToDexSize(), table.PcToDexBegin()); 315 DumpMappingTable("Dex2PC_MappingTable", descriptor, name, signature, 316 table.DexToPcSize(), table.DexToPcBegin()); 317 } 318} 319 320/* 321 * Search the existing constants in the literal pool for an exact or close match 322 * within specified delta (greater or equal to 0). 323 */ 324LIR* Mir2Lir::ScanLiteralPool(LIR* data_target, int value, unsigned int delta) { 325 while (data_target) { 326 if ((static_cast<unsigned>(value - data_target->operands[0])) <= delta) 327 return data_target; 328 data_target = data_target->next; 329 } 330 return NULL; 331} 332 333/* Search the existing constants in the literal pool for an exact wide match */ 334LIR* Mir2Lir::ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi) { 335 bool lo_match = false; 336 LIR* lo_target = NULL; 337 while (data_target) { 338 if (lo_match && (data_target->operands[0] == val_hi)) { 339 // Record high word in case we need to expand this later. 340 lo_target->operands[1] = val_hi; 341 return lo_target; 342 } 343 lo_match = false; 344 if (data_target->operands[0] == val_lo) { 345 lo_match = true; 346 lo_target = data_target; 347 } 348 data_target = data_target->next; 349 } 350 return NULL; 351} 352 353/* 354 * The following are building blocks to insert constants into the pool or 355 * instruction streams. 356 */ 357 358/* Add a 32-bit constant to the constant pool */ 359LIR* Mir2Lir::AddWordData(LIR* *constant_list_p, int value) { 360 /* Add the constant to the literal pool */ 361 if (constant_list_p) { 362 LIR* new_value = static_cast<LIR*>(arena_->Alloc(sizeof(LIR), kArenaAllocData)); 363 new_value->operands[0] = value; 364 new_value->next = *constant_list_p; 365 *constant_list_p = new_value; 366 estimated_native_code_size_ += sizeof(value); 367 return new_value; 368 } 369 return NULL; 370} 371 372/* Add a 64-bit constant to the constant pool or mixed with code */ 373LIR* Mir2Lir::AddWideData(LIR* *constant_list_p, int val_lo, int val_hi) { 374 AddWordData(constant_list_p, val_hi); 375 return AddWordData(constant_list_p, val_lo); 376} 377 378static void Push32(std::vector<uint8_t>&buf, int data) { 379 buf.push_back(data & 0xff); 380 buf.push_back((data >> 8) & 0xff); 381 buf.push_back((data >> 16) & 0xff); 382 buf.push_back((data >> 24) & 0xff); 383} 384 385// Push 8 bytes on 64-bit target systems; 4 on 32-bit target systems. 386static void PushPointer(std::vector<uint8_t>&buf, const void* pointer, bool target64) { 387 uint64_t data = reinterpret_cast<uintptr_t>(pointer); 388 if (target64) { 389 Push32(buf, data & 0xFFFFFFFF); 390 Push32(buf, (data >> 32) & 0xFFFFFFFF); 391 } else { 392 Push32(buf, static_cast<uint32_t>(data)); 393 } 394} 395 396static void AlignBuffer(std::vector<uint8_t>&buf, size_t offset) { 397 while (buf.size() < offset) { 398 buf.push_back(0); 399 } 400} 401 402/* Write the literal pool to the output stream */ 403void Mir2Lir::InstallLiteralPools() { 404 AlignBuffer(code_buffer_, data_offset_); 405 LIR* data_lir = literal_list_; 406 while (data_lir != NULL) { 407 Push32(code_buffer_, data_lir->operands[0]); 408 data_lir = NEXT_LIR(data_lir); 409 } 410 // Push code and method literals, record offsets for the compiler to patch. 411 data_lir = code_literal_list_; 412 while (data_lir != NULL) { 413 uint32_t target_method_idx = data_lir->operands[0]; 414 const DexFile* target_dex_file = 415 reinterpret_cast<const DexFile*>(UnwrapPointer(data_lir->operands[1])); 416 cu_->compiler_driver->AddCodePatch(cu_->dex_file, 417 cu_->class_def_idx, 418 cu_->method_idx, 419 cu_->invoke_type, 420 target_method_idx, 421 target_dex_file, 422 static_cast<InvokeType>(data_lir->operands[2]), 423 code_buffer_.size()); 424 const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); 425 // unique value based on target to ensure code deduplication works 426 PushPointer(code_buffer_, &target_method_id, cu_->target64); 427 data_lir = NEXT_LIR(data_lir); 428 } 429 data_lir = method_literal_list_; 430 while (data_lir != NULL) { 431 uint32_t target_method_idx = data_lir->operands[0]; 432 const DexFile* target_dex_file = 433 reinterpret_cast<const DexFile*>(UnwrapPointer(data_lir->operands[1])); 434 cu_->compiler_driver->AddMethodPatch(cu_->dex_file, 435 cu_->class_def_idx, 436 cu_->method_idx, 437 cu_->invoke_type, 438 target_method_idx, 439 target_dex_file, 440 static_cast<InvokeType>(data_lir->operands[2]), 441 code_buffer_.size()); 442 const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); 443 // unique value based on target to ensure code deduplication works 444 PushPointer(code_buffer_, &target_method_id, cu_->target64); 445 data_lir = NEXT_LIR(data_lir); 446 } 447 // Push class literals. 448 data_lir = class_literal_list_; 449 while (data_lir != NULL) { 450 uint32_t target_method_idx = data_lir->operands[0]; 451 cu_->compiler_driver->AddClassPatch(cu_->dex_file, 452 cu_->class_def_idx, 453 cu_->method_idx, 454 target_method_idx, 455 code_buffer_.size()); 456 const DexFile::TypeId& target_method_id = cu_->dex_file->GetTypeId(target_method_idx); 457 // unique value based on target to ensure code deduplication works 458 PushPointer(code_buffer_, &target_method_id, cu_->target64); 459 data_lir = NEXT_LIR(data_lir); 460 } 461} 462 463/* Write the switch tables to the output stream */ 464void Mir2Lir::InstallSwitchTables() { 465 GrowableArray<SwitchTable*>::Iterator iterator(&switch_tables_); 466 while (true) { 467 Mir2Lir::SwitchTable* tab_rec = iterator.Next(); 468 if (tab_rec == NULL) break; 469 AlignBuffer(code_buffer_, tab_rec->offset); 470 /* 471 * For Arm, our reference point is the address of the bx 472 * instruction that does the launch, so we have to subtract 473 * the auto pc-advance. For other targets the reference point 474 * is a label, so we can use the offset as-is. 475 */ 476 int bx_offset = INVALID_OFFSET; 477 switch (cu_->instruction_set) { 478 case kThumb2: 479 DCHECK(tab_rec->anchor->flags.fixup != kFixupNone); 480 bx_offset = tab_rec->anchor->offset + 4; 481 break; 482 case kX86: 483 bx_offset = 0; 484 break; 485 case kMips: 486 bx_offset = tab_rec->anchor->offset; 487 break; 488 default: LOG(FATAL) << "Unexpected instruction set: " << cu_->instruction_set; 489 } 490 if (cu_->verbose) { 491 LOG(INFO) << "Switch table for offset 0x" << std::hex << bx_offset; 492 } 493 if (tab_rec->table[0] == Instruction::kSparseSwitchSignature) { 494 const int32_t* keys = reinterpret_cast<const int32_t*>(&(tab_rec->table[2])); 495 for (int elems = 0; elems < tab_rec->table[1]; elems++) { 496 int disp = tab_rec->targets[elems]->offset - bx_offset; 497 if (cu_->verbose) { 498 LOG(INFO) << " Case[" << elems << "] key: 0x" 499 << std::hex << keys[elems] << ", disp: 0x" 500 << std::hex << disp; 501 } 502 Push32(code_buffer_, keys[elems]); 503 Push32(code_buffer_, 504 tab_rec->targets[elems]->offset - bx_offset); 505 } 506 } else { 507 DCHECK_EQ(static_cast<int>(tab_rec->table[0]), 508 static_cast<int>(Instruction::kPackedSwitchSignature)); 509 for (int elems = 0; elems < tab_rec->table[1]; elems++) { 510 int disp = tab_rec->targets[elems]->offset - bx_offset; 511 if (cu_->verbose) { 512 LOG(INFO) << " Case[" << elems << "] disp: 0x" 513 << std::hex << disp; 514 } 515 Push32(code_buffer_, tab_rec->targets[elems]->offset - bx_offset); 516 } 517 } 518 } 519} 520 521/* Write the fill array dta to the output stream */ 522void Mir2Lir::InstallFillArrayData() { 523 GrowableArray<FillArrayData*>::Iterator iterator(&fill_array_data_); 524 while (true) { 525 Mir2Lir::FillArrayData *tab_rec = iterator.Next(); 526 if (tab_rec == NULL) break; 527 AlignBuffer(code_buffer_, tab_rec->offset); 528 for (int i = 0; i < (tab_rec->size + 1) / 2; i++) { 529 code_buffer_.push_back(tab_rec->table[i] & 0xFF); 530 code_buffer_.push_back((tab_rec->table[i] >> 8) & 0xFF); 531 } 532 } 533} 534 535static int AssignLiteralOffsetCommon(LIR* lir, CodeOffset offset) { 536 for (; lir != NULL; lir = lir->next) { 537 lir->offset = offset; 538 offset += 4; 539 } 540 return offset; 541} 542 543static int AssignLiteralPointerOffsetCommon(LIR* lir, CodeOffset offset) { 544 unsigned int element_size = sizeof(void*); 545 // Align to natural pointer size. 546 offset = (offset + (element_size - 1)) & ~(element_size - 1); 547 for (; lir != NULL; lir = lir->next) { 548 lir->offset = offset; 549 offset += element_size; 550 } 551 return offset; 552} 553 554// Make sure we have a code address for every declared catch entry 555bool Mir2Lir::VerifyCatchEntries() { 556 MappingTable table(&encoded_mapping_table_[0]); 557 std::vector<uint32_t> dex_pcs; 558 dex_pcs.reserve(table.DexToPcSize()); 559 for (auto it = table.DexToPcBegin(), end = table.DexToPcEnd(); it != end; ++it) { 560 dex_pcs.push_back(it.DexPc()); 561 } 562 // Sort dex_pcs, so that we can quickly check it against the ordered mir_graph_->catches_. 563 std::sort(dex_pcs.begin(), dex_pcs.end()); 564 565 bool success = true; 566 auto it = dex_pcs.begin(), end = dex_pcs.end(); 567 for (uint32_t dex_pc : mir_graph_->catches_) { 568 while (it != end && *it < dex_pc) { 569 LOG(INFO) << "Unexpected catch entry @ dex pc 0x" << std::hex << *it; 570 ++it; 571 success = false; 572 } 573 if (it == end || *it > dex_pc) { 574 LOG(INFO) << "Missing native PC for catch entry @ 0x" << std::hex << dex_pc; 575 success = false; 576 } else { 577 ++it; 578 } 579 } 580 if (!success) { 581 LOG(INFO) << "Bad dex2pcMapping table in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); 582 LOG(INFO) << "Entries @ decode: " << mir_graph_->catches_.size() << ", Entries in table: " 583 << table.DexToPcSize(); 584 } 585 return success; 586} 587 588 589void Mir2Lir::CreateMappingTables() { 590 uint32_t pc2dex_data_size = 0u; 591 uint32_t pc2dex_entries = 0u; 592 uint32_t pc2dex_offset = 0u; 593 uint32_t pc2dex_dalvik_offset = 0u; 594 uint32_t dex2pc_data_size = 0u; 595 uint32_t dex2pc_entries = 0u; 596 uint32_t dex2pc_offset = 0u; 597 uint32_t dex2pc_dalvik_offset = 0u; 598 for (LIR* tgt_lir = first_lir_insn_; tgt_lir != NULL; tgt_lir = NEXT_LIR(tgt_lir)) { 599 if (!tgt_lir->flags.is_nop && (tgt_lir->opcode == kPseudoSafepointPC)) { 600 pc2dex_entries += 1; 601 DCHECK(pc2dex_offset <= tgt_lir->offset); 602 pc2dex_data_size += UnsignedLeb128Size(tgt_lir->offset - pc2dex_offset); 603 pc2dex_data_size += SignedLeb128Size(static_cast<int32_t>(tgt_lir->dalvik_offset) - 604 static_cast<int32_t>(pc2dex_dalvik_offset)); 605 pc2dex_offset = tgt_lir->offset; 606 pc2dex_dalvik_offset = tgt_lir->dalvik_offset; 607 } 608 if (!tgt_lir->flags.is_nop && (tgt_lir->opcode == kPseudoExportedPC)) { 609 dex2pc_entries += 1; 610 DCHECK(dex2pc_offset <= tgt_lir->offset); 611 dex2pc_data_size += UnsignedLeb128Size(tgt_lir->offset - dex2pc_offset); 612 dex2pc_data_size += SignedLeb128Size(static_cast<int32_t>(tgt_lir->dalvik_offset) - 613 static_cast<int32_t>(dex2pc_dalvik_offset)); 614 dex2pc_offset = tgt_lir->offset; 615 dex2pc_dalvik_offset = tgt_lir->dalvik_offset; 616 } 617 } 618 619 uint32_t total_entries = pc2dex_entries + dex2pc_entries; 620 uint32_t hdr_data_size = UnsignedLeb128Size(total_entries) + UnsignedLeb128Size(pc2dex_entries); 621 uint32_t data_size = hdr_data_size + pc2dex_data_size + dex2pc_data_size; 622 encoded_mapping_table_.resize(data_size); 623 uint8_t* write_pos = &encoded_mapping_table_[0]; 624 write_pos = EncodeUnsignedLeb128(write_pos, total_entries); 625 write_pos = EncodeUnsignedLeb128(write_pos, pc2dex_entries); 626 DCHECK_EQ(static_cast<size_t>(write_pos - &encoded_mapping_table_[0]), hdr_data_size); 627 uint8_t* write_pos2 = write_pos + pc2dex_data_size; 628 629 pc2dex_offset = 0u; 630 pc2dex_dalvik_offset = 0u; 631 dex2pc_offset = 0u; 632 dex2pc_dalvik_offset = 0u; 633 for (LIR* tgt_lir = first_lir_insn_; tgt_lir != NULL; tgt_lir = NEXT_LIR(tgt_lir)) { 634 if (!tgt_lir->flags.is_nop && (tgt_lir->opcode == kPseudoSafepointPC)) { 635 DCHECK(pc2dex_offset <= tgt_lir->offset); 636 write_pos = EncodeUnsignedLeb128(write_pos, tgt_lir->offset - pc2dex_offset); 637 write_pos = EncodeSignedLeb128(write_pos, static_cast<int32_t>(tgt_lir->dalvik_offset) - 638 static_cast<int32_t>(pc2dex_dalvik_offset)); 639 pc2dex_offset = tgt_lir->offset; 640 pc2dex_dalvik_offset = tgt_lir->dalvik_offset; 641 } 642 if (!tgt_lir->flags.is_nop && (tgt_lir->opcode == kPseudoExportedPC)) { 643 DCHECK(dex2pc_offset <= tgt_lir->offset); 644 write_pos2 = EncodeUnsignedLeb128(write_pos2, tgt_lir->offset - dex2pc_offset); 645 write_pos2 = EncodeSignedLeb128(write_pos2, static_cast<int32_t>(tgt_lir->dalvik_offset) - 646 static_cast<int32_t>(dex2pc_dalvik_offset)); 647 dex2pc_offset = tgt_lir->offset; 648 dex2pc_dalvik_offset = tgt_lir->dalvik_offset; 649 } 650 } 651 DCHECK_EQ(static_cast<size_t>(write_pos - &encoded_mapping_table_[0]), 652 hdr_data_size + pc2dex_data_size); 653 DCHECK_EQ(static_cast<size_t>(write_pos2 - &encoded_mapping_table_[0]), data_size); 654 655 if (kIsDebugBuild) { 656 CHECK(VerifyCatchEntries()); 657 658 // Verify the encoded table holds the expected data. 659 MappingTable table(&encoded_mapping_table_[0]); 660 CHECK_EQ(table.TotalSize(), total_entries); 661 CHECK_EQ(table.PcToDexSize(), pc2dex_entries); 662 auto it = table.PcToDexBegin(); 663 auto it2 = table.DexToPcBegin(); 664 for (LIR* tgt_lir = first_lir_insn_; tgt_lir != NULL; tgt_lir = NEXT_LIR(tgt_lir)) { 665 if (!tgt_lir->flags.is_nop && (tgt_lir->opcode == kPseudoSafepointPC)) { 666 CHECK_EQ(tgt_lir->offset, it.NativePcOffset()); 667 CHECK_EQ(tgt_lir->dalvik_offset, it.DexPc()); 668 ++it; 669 } 670 if (!tgt_lir->flags.is_nop && (tgt_lir->opcode == kPseudoExportedPC)) { 671 CHECK_EQ(tgt_lir->offset, it2.NativePcOffset()); 672 CHECK_EQ(tgt_lir->dalvik_offset, it2.DexPc()); 673 ++it2; 674 } 675 } 676 CHECK(it == table.PcToDexEnd()); 677 CHECK(it2 == table.DexToPcEnd()); 678 } 679} 680 681void Mir2Lir::CreateNativeGcMap() { 682 DCHECK(!encoded_mapping_table_.empty()); 683 MappingTable mapping_table(&encoded_mapping_table_[0]); 684 uint32_t max_native_offset = 0; 685 for (auto it = mapping_table.PcToDexBegin(), end = mapping_table.PcToDexEnd(); it != end; ++it) { 686 uint32_t native_offset = it.NativePcOffset(); 687 if (native_offset > max_native_offset) { 688 max_native_offset = native_offset; 689 } 690 } 691 MethodReference method_ref(cu_->dex_file, cu_->method_idx); 692 const std::vector<uint8_t>& gc_map_raw = 693 mir_graph_->GetCurrentDexCompilationUnit()->GetVerifiedMethod()->GetDexGcMap(); 694 verifier::DexPcToReferenceMap dex_gc_map(&(gc_map_raw)[0]); 695 DCHECK_EQ(gc_map_raw.size(), dex_gc_map.RawSize()); 696 // Compute native offset to references size. 697 GcMapBuilder native_gc_map_builder(&native_gc_map_, 698 mapping_table.PcToDexSize(), 699 max_native_offset, dex_gc_map.RegWidth()); 700 701 for (auto it = mapping_table.PcToDexBegin(), end = mapping_table.PcToDexEnd(); it != end; ++it) { 702 uint32_t native_offset = it.NativePcOffset(); 703 uint32_t dex_pc = it.DexPc(); 704 const uint8_t* references = dex_gc_map.FindBitMap(dex_pc, false); 705 CHECK(references != NULL) << "Missing ref for dex pc 0x" << std::hex << dex_pc; 706 native_gc_map_builder.AddEntry(native_offset, references); 707 } 708} 709 710/* Determine the offset of each literal field */ 711int Mir2Lir::AssignLiteralOffset(CodeOffset offset) { 712 offset = AssignLiteralOffsetCommon(literal_list_, offset); 713 offset = AssignLiteralPointerOffsetCommon(code_literal_list_, offset); 714 offset = AssignLiteralPointerOffsetCommon(method_literal_list_, offset); 715 offset = AssignLiteralPointerOffsetCommon(class_literal_list_, offset); 716 return offset; 717} 718 719int Mir2Lir::AssignSwitchTablesOffset(CodeOffset offset) { 720 GrowableArray<SwitchTable*>::Iterator iterator(&switch_tables_); 721 while (true) { 722 Mir2Lir::SwitchTable* tab_rec = iterator.Next(); 723 if (tab_rec == NULL) break; 724 tab_rec->offset = offset; 725 if (tab_rec->table[0] == Instruction::kSparseSwitchSignature) { 726 offset += tab_rec->table[1] * (sizeof(int) * 2); 727 } else { 728 DCHECK_EQ(static_cast<int>(tab_rec->table[0]), 729 static_cast<int>(Instruction::kPackedSwitchSignature)); 730 offset += tab_rec->table[1] * sizeof(int); 731 } 732 } 733 return offset; 734} 735 736int Mir2Lir::AssignFillArrayDataOffset(CodeOffset offset) { 737 GrowableArray<FillArrayData*>::Iterator iterator(&fill_array_data_); 738 while (true) { 739 Mir2Lir::FillArrayData *tab_rec = iterator.Next(); 740 if (tab_rec == NULL) break; 741 tab_rec->offset = offset; 742 offset += tab_rec->size; 743 // word align 744 offset = (offset + 3) & ~3; 745 } 746 return offset; 747} 748 749/* 750 * Insert a kPseudoCaseLabel at the beginning of the Dalvik 751 * offset vaddr if pretty-printing, otherise use the standard block 752 * label. The selected label will be used to fix up the case 753 * branch table during the assembly phase. All resource flags 754 * are set to prevent code motion. KeyVal is just there for debugging. 755 */ 756LIR* Mir2Lir::InsertCaseLabel(DexOffset vaddr, int keyVal) { 757 LIR* boundary_lir = &block_label_list_[mir_graph_->FindBlock(vaddr)->id]; 758 LIR* res = boundary_lir; 759 if (cu_->verbose) { 760 // Only pay the expense if we're pretty-printing. 761 LIR* new_label = static_cast<LIR*>(arena_->Alloc(sizeof(LIR), kArenaAllocLIR)); 762 new_label->dalvik_offset = vaddr; 763 new_label->opcode = kPseudoCaseLabel; 764 new_label->operands[0] = keyVal; 765 new_label->flags.fixup = kFixupLabel; 766 DCHECK(!new_label->flags.use_def_invalid); 767 new_label->u.m.def_mask = ENCODE_ALL; 768 InsertLIRAfter(boundary_lir, new_label); 769 res = new_label; 770 } 771 return res; 772} 773 774void Mir2Lir::MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec) { 775 const uint16_t* table = tab_rec->table; 776 DexOffset base_vaddr = tab_rec->vaddr; 777 const int32_t *targets = reinterpret_cast<const int32_t*>(&table[4]); 778 int entries = table[1]; 779 int low_key = s4FromSwitchData(&table[2]); 780 for (int i = 0; i < entries; i++) { 781 tab_rec->targets[i] = InsertCaseLabel(base_vaddr + targets[i], i + low_key); 782 } 783} 784 785void Mir2Lir::MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec) { 786 const uint16_t* table = tab_rec->table; 787 DexOffset base_vaddr = tab_rec->vaddr; 788 int entries = table[1]; 789 const int32_t* keys = reinterpret_cast<const int32_t*>(&table[2]); 790 const int32_t* targets = &keys[entries]; 791 for (int i = 0; i < entries; i++) { 792 tab_rec->targets[i] = InsertCaseLabel(base_vaddr + targets[i], keys[i]); 793 } 794} 795 796void Mir2Lir::ProcessSwitchTables() { 797 GrowableArray<SwitchTable*>::Iterator iterator(&switch_tables_); 798 while (true) { 799 Mir2Lir::SwitchTable *tab_rec = iterator.Next(); 800 if (tab_rec == NULL) break; 801 if (tab_rec->table[0] == Instruction::kPackedSwitchSignature) { 802 MarkPackedCaseLabels(tab_rec); 803 } else if (tab_rec->table[0] == Instruction::kSparseSwitchSignature) { 804 MarkSparseCaseLabels(tab_rec); 805 } else { 806 LOG(FATAL) << "Invalid switch table"; 807 } 808 } 809} 810 811void Mir2Lir::DumpSparseSwitchTable(const uint16_t* table) { 812 /* 813 * Sparse switch data format: 814 * ushort ident = 0x0200 magic value 815 * ushort size number of entries in the table; > 0 816 * int keys[size] keys, sorted low-to-high; 32-bit aligned 817 * int targets[size] branch targets, relative to switch opcode 818 * 819 * Total size is (2+size*4) 16-bit code units. 820 */ 821 uint16_t ident = table[0]; 822 int entries = table[1]; 823 const int32_t* keys = reinterpret_cast<const int32_t*>(&table[2]); 824 const int32_t* targets = &keys[entries]; 825 LOG(INFO) << "Sparse switch table - ident:0x" << std::hex << ident 826 << ", entries: " << std::dec << entries; 827 for (int i = 0; i < entries; i++) { 828 LOG(INFO) << " Key[" << keys[i] << "] -> 0x" << std::hex << targets[i]; 829 } 830} 831 832void Mir2Lir::DumpPackedSwitchTable(const uint16_t* table) { 833 /* 834 * Packed switch data format: 835 * ushort ident = 0x0100 magic value 836 * ushort size number of entries in the table 837 * int first_key first (and lowest) switch case value 838 * int targets[size] branch targets, relative to switch opcode 839 * 840 * Total size is (4+size*2) 16-bit code units. 841 */ 842 uint16_t ident = table[0]; 843 const int32_t* targets = reinterpret_cast<const int32_t*>(&table[4]); 844 int entries = table[1]; 845 int low_key = s4FromSwitchData(&table[2]); 846 LOG(INFO) << "Packed switch table - ident:0x" << std::hex << ident 847 << ", entries: " << std::dec << entries << ", low_key: " << low_key; 848 for (int i = 0; i < entries; i++) { 849 LOG(INFO) << " Key[" << (i + low_key) << "] -> 0x" << std::hex 850 << targets[i]; 851 } 852} 853 854/* Set up special LIR to mark a Dalvik byte-code instruction start for pretty printing */ 855void Mir2Lir::MarkBoundary(DexOffset offset, const char* inst_str) { 856 // NOTE: only used for debug listings. 857 NewLIR1(kPseudoDalvikByteCodeBoundary, WrapPointer(ArenaStrdup(inst_str))); 858} 859 860bool Mir2Lir::EvaluateBranch(Instruction::Code opcode, int32_t src1, int32_t src2) { 861 bool is_taken; 862 switch (opcode) { 863 case Instruction::IF_EQ: is_taken = (src1 == src2); break; 864 case Instruction::IF_NE: is_taken = (src1 != src2); break; 865 case Instruction::IF_LT: is_taken = (src1 < src2); break; 866 case Instruction::IF_GE: is_taken = (src1 >= src2); break; 867 case Instruction::IF_GT: is_taken = (src1 > src2); break; 868 case Instruction::IF_LE: is_taken = (src1 <= src2); break; 869 case Instruction::IF_EQZ: is_taken = (src1 == 0); break; 870 case Instruction::IF_NEZ: is_taken = (src1 != 0); break; 871 case Instruction::IF_LTZ: is_taken = (src1 < 0); break; 872 case Instruction::IF_GEZ: is_taken = (src1 >= 0); break; 873 case Instruction::IF_GTZ: is_taken = (src1 > 0); break; 874 case Instruction::IF_LEZ: is_taken = (src1 <= 0); break; 875 default: 876 LOG(FATAL) << "Unexpected opcode " << opcode; 877 is_taken = false; 878 } 879 return is_taken; 880} 881 882// Convert relation of src1/src2 to src2/src1 883ConditionCode Mir2Lir::FlipComparisonOrder(ConditionCode before) { 884 ConditionCode res; 885 switch (before) { 886 case kCondEq: res = kCondEq; break; 887 case kCondNe: res = kCondNe; break; 888 case kCondLt: res = kCondGt; break; 889 case kCondGt: res = kCondLt; break; 890 case kCondLe: res = kCondGe; break; 891 case kCondGe: res = kCondLe; break; 892 default: 893 res = static_cast<ConditionCode>(0); 894 LOG(FATAL) << "Unexpected ccode " << before; 895 } 896 return res; 897} 898 899ConditionCode Mir2Lir::NegateComparison(ConditionCode before) { 900 ConditionCode res; 901 switch (before) { 902 case kCondEq: res = kCondNe; break; 903 case kCondNe: res = kCondEq; break; 904 case kCondLt: res = kCondGe; break; 905 case kCondGt: res = kCondLe; break; 906 case kCondLe: res = kCondGt; break; 907 case kCondGe: res = kCondLt; break; 908 default: 909 res = static_cast<ConditionCode>(0); 910 LOG(FATAL) << "Unexpected ccode " << before; 911 } 912 return res; 913} 914 915// TODO: move to mir_to_lir.cc 916Mir2Lir::Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) 917 : Backend(arena), 918 literal_list_(NULL), 919 method_literal_list_(NULL), 920 class_literal_list_(NULL), 921 code_literal_list_(NULL), 922 first_fixup_(NULL), 923 cu_(cu), 924 mir_graph_(mir_graph), 925 switch_tables_(arena, 4, kGrowableArraySwitchTables), 926 fill_array_data_(arena, 4, kGrowableArrayFillArrayData), 927 throw_launchpads_(arena, 2048, kGrowableArrayThrowLaunchPads), 928 suspend_launchpads_(arena, 4, kGrowableArraySuspendLaunchPads), 929 tempreg_info_(arena, 20, kGrowableArrayMisc), 930 reginfo_map_(arena, 64, kGrowableArrayMisc), 931 pointer_storage_(arena, 128, kGrowableArrayMisc), 932 data_offset_(0), 933 total_size_(0), 934 block_label_list_(NULL), 935 promotion_map_(NULL), 936 current_dalvik_offset_(0), 937 estimated_native_code_size_(0), 938 reg_pool_(NULL), 939 live_sreg_(0), 940 num_core_spills_(0), 941 num_fp_spills_(0), 942 frame_size_(0), 943 core_spill_mask_(0), 944 fp_spill_mask_(0), 945 first_lir_insn_(NULL), 946 last_lir_insn_(NULL), 947 slow_paths_(arena, 32, kGrowableArraySlowPaths) { 948 // Reserve pointer id 0 for NULL. 949 size_t null_idx = WrapPointer(NULL); 950 DCHECK_EQ(null_idx, 0U); 951} 952 953void Mir2Lir::Materialize() { 954 cu_->NewTimingSplit("RegisterAllocation"); 955 CompilerInitializeRegAlloc(); // Needs to happen after SSA naming 956 957 /* Allocate Registers using simple local allocation scheme */ 958 SimpleRegAlloc(); 959 960 /* First try the custom light codegen for special cases. */ 961 DCHECK(cu_->compiler_driver->GetMethodInlinerMap() != nullptr); 962 bool special_worked = cu_->compiler_driver->GetMethodInlinerMap()->GetMethodInliner(cu_->dex_file) 963 ->GenSpecial(this, cu_->method_idx); 964 965 /* Take normal path for converting MIR to LIR only if the special codegen did not succeed. */ 966 if (special_worked == false) { 967 MethodMIR2LIR(); 968 } 969 970 /* Method is not empty */ 971 if (first_lir_insn_) { 972 // mark the targets of switch statement case labels 973 ProcessSwitchTables(); 974 975 /* Convert LIR into machine code. */ 976 AssembleLIR(); 977 978 if (cu_->verbose) { 979 CodegenDump(); 980 } 981 } 982} 983 984CompiledMethod* Mir2Lir::GetCompiledMethod() { 985 // Combine vmap tables - core regs, then fp regs - into vmap_table. 986 Leb128EncodingVector vmap_encoder; 987 if (frame_size_ > 0) { 988 // Prefix the encoded data with its size. 989 size_t size = core_vmap_table_.size() + 1 /* marker */ + fp_vmap_table_.size(); 990 vmap_encoder.Reserve(size + 1u); // All values are likely to be one byte in ULEB128 (<128). 991 vmap_encoder.PushBackUnsigned(size); 992 // Core regs may have been inserted out of order - sort first. 993 std::sort(core_vmap_table_.begin(), core_vmap_table_.end()); 994 for (size_t i = 0 ; i < core_vmap_table_.size(); ++i) { 995 // Copy, stripping out the phys register sort key. 996 vmap_encoder.PushBackUnsigned( 997 ~(-1 << VREG_NUM_WIDTH) & (core_vmap_table_[i] + VmapTable::kEntryAdjustment)); 998 } 999 // Push a marker to take place of lr. 1000 vmap_encoder.PushBackUnsigned(VmapTable::kAdjustedFpMarker); 1001 // fp regs already sorted. 1002 for (uint32_t i = 0; i < fp_vmap_table_.size(); i++) { 1003 vmap_encoder.PushBackUnsigned(fp_vmap_table_[i] + VmapTable::kEntryAdjustment); 1004 } 1005 } else { 1006 DCHECK_EQ(__builtin_popcount(core_spill_mask_), 0); 1007 DCHECK_EQ(__builtin_popcount(fp_spill_mask_), 0); 1008 DCHECK_EQ(core_vmap_table_.size(), 0u); 1009 DCHECK_EQ(fp_vmap_table_.size(), 0u); 1010 vmap_encoder.PushBackUnsigned(0u); // Size is 0. 1011 } 1012 1013 UniquePtr<std::vector<uint8_t> > cfi_info(ReturnCallFrameInformation()); 1014 CompiledMethod* result = 1015 new CompiledMethod(*cu_->compiler_driver, cu_->instruction_set, code_buffer_, frame_size_, 1016 core_spill_mask_, fp_spill_mask_, encoded_mapping_table_, 1017 vmap_encoder.GetData(), native_gc_map_, cfi_info.get()); 1018 return result; 1019} 1020 1021size_t Mir2Lir::GetMaxPossibleCompilerTemps() const { 1022 // Chose a reasonably small value in order to contain stack growth. 1023 // Backends that are smarter about spill region can return larger values. 1024 const size_t max_compiler_temps = 10; 1025 return max_compiler_temps; 1026} 1027 1028size_t Mir2Lir::GetNumBytesForCompilerTempSpillRegion() { 1029 // By default assume that the Mir2Lir will need one slot for each temporary. 1030 // If the backend can better determine temps that have non-overlapping ranges and 1031 // temps that do not need spilled, it can actually provide a small region. 1032 return (mir_graph_->GetNumUsedCompilerTemps() * sizeof(uint32_t)); 1033} 1034 1035int Mir2Lir::ComputeFrameSize() { 1036 /* Figure out the frame size */ 1037 static const uint32_t kAlignMask = kStackAlignment - 1; 1038 uint32_t size = ((num_core_spills_ + num_fp_spills_ + 1039 1 /* filler word */ + cu_->num_regs + cu_->num_outs) 1040 * sizeof(uint32_t)) + 1041 GetNumBytesForCompilerTempSpillRegion(); 1042 /* Align and set */ 1043 return (size + kAlignMask) & ~(kAlignMask); 1044} 1045 1046/* 1047 * Append an LIR instruction to the LIR list maintained by a compilation 1048 * unit 1049 */ 1050void Mir2Lir::AppendLIR(LIR* lir) { 1051 if (first_lir_insn_ == NULL) { 1052 DCHECK(last_lir_insn_ == NULL); 1053 last_lir_insn_ = first_lir_insn_ = lir; 1054 lir->prev = lir->next = NULL; 1055 } else { 1056 last_lir_insn_->next = lir; 1057 lir->prev = last_lir_insn_; 1058 lir->next = NULL; 1059 last_lir_insn_ = lir; 1060 } 1061} 1062 1063/* 1064 * Insert an LIR instruction before the current instruction, which cannot be the 1065 * first instruction. 1066 * 1067 * prev_lir <-> new_lir <-> current_lir 1068 */ 1069void Mir2Lir::InsertLIRBefore(LIR* current_lir, LIR* new_lir) { 1070 DCHECK(current_lir->prev != NULL); 1071 LIR *prev_lir = current_lir->prev; 1072 1073 prev_lir->next = new_lir; 1074 new_lir->prev = prev_lir; 1075 new_lir->next = current_lir; 1076 current_lir->prev = new_lir; 1077} 1078 1079/* 1080 * Insert an LIR instruction after the current instruction, which cannot be the 1081 * first instruction. 1082 * 1083 * current_lir -> new_lir -> old_next 1084 */ 1085void Mir2Lir::InsertLIRAfter(LIR* current_lir, LIR* new_lir) { 1086 new_lir->prev = current_lir; 1087 new_lir->next = current_lir->next; 1088 current_lir->next = new_lir; 1089 new_lir->next->prev = new_lir; 1090} 1091 1092bool Mir2Lir::IsPowerOfTwo(uint64_t x) { 1093 return (x & (x - 1)) == 0; 1094} 1095 1096// Returns the index of the lowest set bit in 'x'. 1097int32_t Mir2Lir::LowestSetBit(uint64_t x) { 1098 int bit_posn = 0; 1099 while ((x & 0xf) == 0) { 1100 bit_posn += 4; 1101 x >>= 4; 1102 } 1103 while ((x & 1) == 0) { 1104 bit_posn++; 1105 x >>= 1; 1106 } 1107 return bit_posn; 1108} 1109 1110bool Mir2Lir::BadOverlap(RegLocation rl_src, RegLocation rl_dest) { 1111 DCHECK(rl_src.wide); 1112 DCHECK(rl_dest.wide); 1113 return (abs(mir_graph_->SRegToVReg(rl_src.s_reg_low) - mir_graph_->SRegToVReg(rl_dest.s_reg_low)) == 1); 1114} 1115 1116LIR *Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 1117 int offset, int check_value, LIR* target) { 1118 // Handle this for architectures that can't compare to memory. 1119 LoadWordDisp(base_reg, offset, temp_reg); 1120 LIR* branch = OpCmpImmBranch(cond, temp_reg, check_value, target); 1121 return branch; 1122} 1123 1124void Mir2Lir::AddSlowPath(LIRSlowPath* slowpath) { 1125 slow_paths_.Insert(slowpath); 1126} 1127 1128void Mir2Lir::LoadCodeAddress(const MethodReference& target_method, InvokeType type, 1129 SpecialTargetRegister symbolic_reg) { 1130 int target_method_idx = target_method.dex_method_index; 1131 LIR* data_target = ScanLiteralPool(code_literal_list_, target_method_idx, 0); 1132 if (data_target == NULL) { 1133 data_target = AddWordData(&code_literal_list_, target_method_idx); 1134 data_target->operands[1] = WrapPointer(const_cast<DexFile*>(target_method.dex_file)); 1135 data_target->operands[2] = type; 1136 } 1137 LIR* load_pc_rel = OpPcRelLoad(TargetReg(symbolic_reg), data_target); 1138 AppendLIR(load_pc_rel); 1139 DCHECK_NE(cu_->instruction_set, kMips) << reinterpret_cast<void*>(data_target); 1140} 1141 1142void Mir2Lir::LoadMethodAddress(const MethodReference& target_method, InvokeType type, 1143 SpecialTargetRegister symbolic_reg) { 1144 int target_method_idx = target_method.dex_method_index; 1145 LIR* data_target = ScanLiteralPool(method_literal_list_, target_method_idx, 0); 1146 if (data_target == NULL) { 1147 data_target = AddWordData(&method_literal_list_, target_method_idx); 1148 data_target->operands[1] = WrapPointer(const_cast<DexFile*>(target_method.dex_file)); 1149 data_target->operands[2] = type; 1150 } 1151 LIR* load_pc_rel = OpPcRelLoad(TargetReg(symbolic_reg), data_target); 1152 AppendLIR(load_pc_rel); 1153 DCHECK_NE(cu_->instruction_set, kMips) << reinterpret_cast<void*>(data_target); 1154} 1155 1156void Mir2Lir::LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg) { 1157 // Use the literal pool and a PC-relative load from a data word. 1158 LIR* data_target = ScanLiteralPool(class_literal_list_, type_idx, 0); 1159 if (data_target == nullptr) { 1160 data_target = AddWordData(&class_literal_list_, type_idx); 1161 } 1162 LIR* load_pc_rel = OpPcRelLoad(TargetReg(symbolic_reg), data_target); 1163 AppendLIR(load_pc_rel); 1164} 1165 1166std::vector<uint8_t>* Mir2Lir::ReturnCallFrameInformation() { 1167 // Default case is to do nothing. 1168 return nullptr; 1169} 1170 1171RegLocation Mir2Lir::NarrowRegLoc(RegLocation loc) { 1172 loc.wide = false; 1173 if (loc.reg.IsPair()) { 1174 loc.reg = loc.reg.GetLow(); 1175 } 1176 return loc; 1177} 1178 1179} // namespace art 1180