ISDOpcodes.h revision 41418d17cced656f91038b2482bc9d173b4974b0 
1//===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares codegen opcodes and related utilities.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_ISDOPCODES_H
15#define LLVM_CODEGEN_ISDOPCODES_H
16
17namespace llvm {
18
19/// ISD namespace - This namespace contains an enum which represents all of the
20/// SelectionDAG node types and value types.
21///
22namespace ISD {
23
24  //===--------------------------------------------------------------------===//
25  /// ISD::NodeType enum - This enum defines the target-independent operators
26  /// for a SelectionDAG.
27  ///
28  /// Targets may also define target-dependent operator codes for SDNodes. For
29  /// example, on x86, these are the enum values in the X86ISD namespace.
30  /// Targets should aim to use target-independent operators to model their
31  /// instruction sets as much as possible, and only use target-dependent
32  /// operators when they have special requirements.
33  ///
34  /// Finally, during and after selection proper, SNodes may use special
35  /// operator codes that correspond directly with MachineInstr opcodes. These
36  /// are used to represent selected instructions. See the isMachineOpcode()
37  /// and getMachineOpcode() member functions of SDNode.
38  ///
39  enum NodeType {
40    /// DELETED_NODE - This is an illegal value that is used to catch
41    /// errors.  This opcode is not a legal opcode for any node.
42    DELETED_NODE,
43
44    /// EntryToken - This is the marker used to indicate the start of a region.
45    EntryToken,
46
47    /// TokenFactor - This node takes multiple tokens as input and produces a
48    /// single token result. This is used to represent the fact that the operand
49    /// operators are independent of each other.
50    TokenFactor,
51
52    /// AssertSext, AssertZext - These nodes record if a register contains a
53    /// value that has already been zero or sign extended from a narrower type.
54    /// These nodes take two operands.  The first is the node that has already
55    /// been extended, and the second is a value type node indicating the width
56    /// of the extension
57    AssertSext, AssertZext,
58
59    /// Various leaf nodes.
60    BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask,
61    Constant, ConstantFP,
62    GlobalAddress, GlobalTLSAddress, FrameIndex,
63    JumpTable, ConstantPool, ExternalSymbol, BlockAddress,
64
65    /// The address of the GOT
66    GLOBAL_OFFSET_TABLE,
67
68    /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and
69    /// llvm.returnaddress on the DAG.  These nodes take one operand, the index
70    /// of the frame or return address to return.  An index of zero corresponds
71    /// to the current function's frame or return address, an index of one to
72    /// the parent's frame or return address, and so on.
73    FRAMEADDR, RETURNADDR,
74
75    /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to
76    /// first (possible) on-stack argument. This is needed for correct stack
77    /// adjustment during unwind.
78    FRAME_TO_ARGS_OFFSET,
79
80    /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents
81    /// 'eh_return' gcc dwarf builtin, which is used to return from
82    /// exception. The general meaning is: adjust stack by OFFSET and pass
83    /// execution to HANDLER. Many platform-related details also :)
84    EH_RETURN,
85
86    /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)
87    /// This corresponds to the eh.sjlj.setjmp intrinsic.
88    /// It takes an input chain and a pointer to the jump buffer as inputs
89    /// and returns an outchain.
90    EH_SJLJ_SETJMP,
91
92    /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)
93    /// This corresponds to the eh.sjlj.longjmp intrinsic.
94    /// It takes an input chain and a pointer to the jump buffer as inputs
95    /// and returns an outchain.
96    EH_SJLJ_LONGJMP,
97
98    /// TargetConstant* - Like Constant*, but the DAG does not do any folding,
99    /// simplification, or lowering of the constant. They are used for constants
100    /// which are known to fit in the immediate fields of their users, or for
101    /// carrying magic numbers which are not values which need to be
102    /// materialized in registers.
103    TargetConstant,
104    TargetConstantFP,
105
106    /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or
107    /// anything else with this node, and this is valid in the target-specific
108    /// dag, turning into a GlobalAddress operand.
109    TargetGlobalAddress,
110    TargetGlobalTLSAddress,
111    TargetFrameIndex,
112    TargetJumpTable,
113    TargetConstantPool,
114    TargetExternalSymbol,
115    TargetBlockAddress,
116
117    /// TargetIndex - Like a constant pool entry, but with completely
118    /// target-dependent semantics. Holds target flags, a 32-bit index, and a
119    /// 64-bit index. Targets can use this however they like.
120    TargetIndex,
121
122    /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
123    /// This node represents a target intrinsic function with no side effects.
124    /// The first operand is the ID number of the intrinsic from the
125    /// llvm::Intrinsic namespace.  The operands to the intrinsic follow.  The
126    /// node returns the result of the intrinsic.
127    INTRINSIC_WO_CHAIN,
128
129    /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...)
130    /// This node represents a target intrinsic function with side effects that
131    /// returns a result.  The first operand is a chain pointer.  The second is
132    /// the ID number of the intrinsic from the llvm::Intrinsic namespace.  The
133    /// operands to the intrinsic follow.  The node has two results, the result
134    /// of the intrinsic and an output chain.
135    INTRINSIC_W_CHAIN,
136
137    /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...)
138    /// This node represents a target intrinsic function with side effects that
139    /// does not return a result.  The first operand is a chain pointer.  The
140    /// second is the ID number of the intrinsic from the llvm::Intrinsic
141    /// namespace.  The operands to the intrinsic follow.
142    INTRINSIC_VOID,
143
144    /// CopyToReg - This node has three operands: a chain, a register number to
145    /// set to this value, and a value.
146    CopyToReg,
147
148    /// CopyFromReg - This node indicates that the input value is a virtual or
149    /// physical register that is defined outside of the scope of this
150    /// SelectionDAG.  The register is available from the RegisterSDNode object.
151    CopyFromReg,
152
153    /// UNDEF - An undefined node.
154    UNDEF,
155
156    /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by
157    /// a Constant, which is required to be operand #1) half of the integer or
158    /// float value specified as operand #0.  This is only for use before
159    /// legalization, for values that will be broken into multiple registers.
160    EXTRACT_ELEMENT,
161
162    /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
163    /// Given two values of the same integer value type, this produces a value
164    /// twice as big.  Like EXTRACT_ELEMENT, this can only be used before
165    /// legalization.
166    BUILD_PAIR,
167
168    /// MERGE_VALUES - This node takes multiple discrete operands and returns
169    /// them all as its individual results.  This nodes has exactly the same
170    /// number of inputs and outputs. This node is useful for some pieces of the
171    /// code generator that want to think about a single node with multiple
172    /// results, not multiple nodes.
173    MERGE_VALUES,
174
175    /// Simple integer binary arithmetic operators.
176    ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
177
178    /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing
179    /// a signed/unsigned value of type i[2*N], and return the full value as
180    /// two results, each of type iN.
181    SMUL_LOHI, UMUL_LOHI,
182
183    /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
184    /// remainder result.
185    SDIVREM, UDIVREM,
186
187    /// CARRY_FALSE - This node is used when folding other nodes,
188    /// like ADDC/SUBC, which indicate the carry result is always false.
189    CARRY_FALSE,
190
191    /// Carry-setting nodes for multiple precision addition and subtraction.
192    /// These nodes take two operands of the same value type, and produce two
193    /// results.  The first result is the normal add or sub result, the second
194    /// result is the carry flag result.
195    ADDC, SUBC,
196
197    /// Carry-using nodes for multiple precision addition and subtraction. These
198    /// nodes take three operands: The first two are the normal lhs and rhs to
199    /// the add or sub, and the third is the input carry flag.  These nodes
200    /// produce two results; the normal result of the add or sub, and the output
201    /// carry flag.  These nodes both read and write a carry flag to allow them
202    /// to them to be chained together for add and sub of arbitrarily large
203    /// values.
204    ADDE, SUBE,
205
206    /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
207    /// These nodes take two operands: the normal LHS and RHS to the add. They
208    /// produce two results: the normal result of the add, and a boolean that
209    /// indicates if an overflow occurred (*not* a flag, because it may be store
210    /// to memory, etc.).  If the type of the boolean is not i1 then the high
211    /// bits conform to getBooleanContents.
212    /// These nodes are generated from llvm.[su]add.with.overflow intrinsics.
213    SADDO, UADDO,
214
215    /// Same for subtraction.
216    SSUBO, USUBO,
217
218    /// Same for multiplication.
219    SMULO, UMULO,
220
221    /// Simple binary floating point operators.
222    FADD, FSUB, FMUL, FMA, FDIV, FREM,
223
224    /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.  NOTE: This
225    /// DAG node does not require that X and Y have the same type, just that the
226    /// are both floating point.  X and the result must have the same type.
227    /// FCOPYSIGN(f32, f64) is allowed.
228    FCOPYSIGN,
229
230    /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point
231    /// value as an integer 0/1 value.
232    FGETSIGN,
233
234    /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the
235    /// specified, possibly variable, elements.  The number of elements is
236    /// required to be a power of two.  The types of the operands must all be
237    /// the same and must match the vector element type, except that integer
238    /// types are allowed to be larger than the element type, in which case
239    /// the operands are implicitly truncated.
240    BUILD_VECTOR,
241
242    /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
243    /// at IDX replaced with VAL.  If the type of VAL is larger than the vector
244    /// element type then VAL is truncated before replacement.
245    INSERT_VECTOR_ELT,
246
247    /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
248    /// identified by the (potentially variable) element number IDX.  If the
249    /// return type is an integer type larger than the element type of the
250    /// vector, the result is extended to the width of the return type.
251    EXTRACT_VECTOR_ELT,
252
253    /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
254    /// vector type with the same length and element type, this produces a
255    /// concatenated vector result value, with length equal to the sum of the
256    /// lengths of the input vectors.
257    CONCAT_VECTORS,
258
259    /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector
260    /// with VECTOR2 inserted into VECTOR1 at the (potentially
261    /// variable) element number IDX, which must be a multiple of the
262    /// VECTOR2 vector length.  The elements of VECTOR1 starting at
263    /// IDX are overwritten with VECTOR2.  Elements IDX through
264    /// vector_length(VECTOR2) must be valid VECTOR1 indices.
265    INSERT_SUBVECTOR,
266
267    /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an
268    /// vector value) starting with the element number IDX, which must be a
269    /// constant multiple of the result vector length.
270    EXTRACT_SUBVECTOR,
271
272    /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as
273    /// VEC1/VEC2.  A VECTOR_SHUFFLE node also contains an array of constant int
274    /// values that indicate which value (or undef) each result element will
275    /// get.  These constant ints are accessible through the
276    /// ShuffleVectorSDNode class.  This is quite similar to the Altivec
277    /// 'vperm' instruction, except that the indices must be constants and are
278    /// in terms of the element size of VEC1/VEC2, not in terms of bytes.
279    VECTOR_SHUFFLE,
280
281    /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a
282    /// scalar value into element 0 of the resultant vector type.  The top
283    /// elements 1 to N-1 of the N-element vector are undefined.  The type
284    /// of the operand must match the vector element type, except when they
285    /// are integer types.  In this case the operand is allowed to be wider
286    /// than the vector element type, and is implicitly truncated to it.
287    SCALAR_TO_VECTOR,
288
289    /// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
290    /// producing an unsigned/signed value of type i[2*N], then return the top
291    /// part.
292    MULHU, MULHS,
293
294    /// Bitwise operators - logical and, logical or, logical xor.
295    AND, OR, XOR,
296
297    /// Shift and rotation operations.  After legalization, the type of the
298    /// shift amount is known to be TLI.getShiftAmountTy().  Before legalization
299    /// the shift amount can be any type, but care must be taken to ensure it is
300    /// large enough.  TLI.getShiftAmountTy() is i8 on some targets, but before
301    /// legalization, types like i1024 can occur and i8 doesn't have enough bits
302    /// to represent the shift amount.
303    /// When the 1st operand is a vector, the shift amount must be in the same
304    /// type. (TLI.getShiftAmountTy() will return the same type when the input
305    /// type is a vector.)
306    SHL, SRA, SRL, ROTL, ROTR,
307
308    /// Byte Swap and Counting operators.
309    BSWAP, CTTZ, CTLZ, CTPOP,
310
311    /// Bit counting operators with an undefined result for zero inputs.
312    CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF,
313
314    /// Select(COND, TRUEVAL, FALSEVAL).  If the type of the boolean COND is not
315    /// i1 then the high bits must conform to getBooleanContents.
316    SELECT,
317
318    /// Select with a vector condition (op #0) and two vector operands (ops #1
319    /// and #2), returning a vector result.  All vectors have the same length.
320    /// Much like the scalar select and setcc, each bit in the condition selects
321    /// whether the corresponding result element is taken from op #1 or op #2.
322    /// At first, the VSELECT condition is of vXi1 type. Later, targets may
323    /// change the condition type in order to match the VSELECT node using a
324    /// pattern. The condition follows the BooleanContent format of the target.
325    VSELECT,
326
327    /// Select with condition operator - This selects between a true value and
328    /// a false value (ops #2 and #3) based on the boolean result of comparing
329    /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
330    /// condition code in op #4, a CondCodeSDNode.
331    SELECT_CC,
332
333    /// SetCC operator - This evaluates to a true value iff the condition is
334    /// true.  If the result value type is not i1 then the high bits conform
335    /// to getBooleanContents.  The operands to this are the left and right
336    /// operands to compare (ops #0, and #1) and the condition code to compare
337    /// them with (op #2) as a CondCodeSDNode. If the operands are vector types
338    /// then the result type must also be a vector type.
339    SETCC,
340
341    /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
342    /// integer shift operations, just like ADD/SUB_PARTS.  The operation
343    /// ordering is:
344    ///       [Lo,Hi] = op [LoLHS,HiLHS], Amt
345    SHL_PARTS, SRA_PARTS, SRL_PARTS,
346
347    /// Conversion operators.  These are all single input single output
348    /// operations.  For all of these, the result type must be strictly
349    /// wider or narrower (depending on the operation) than the source
350    /// type.
351
352    /// SIGN_EXTEND - Used for integer types, replicating the sign bit
353    /// into new bits.
354    SIGN_EXTEND,
355
356    /// ZERO_EXTEND - Used for integer types, zeroing the new bits.
357    ZERO_EXTEND,
358
359    /// ANY_EXTEND - Used for integer types.  The high bits are undefined.
360    ANY_EXTEND,
361
362    /// TRUNCATE - Completely drop the high bits.
363    TRUNCATE,
364
365    /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign
366    /// depends on the first letter) to floating point.
367    SINT_TO_FP,
368    UINT_TO_FP,
369
370    /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
371    /// sign extend a small value in a large integer register (e.g. sign
372    /// extending the low 8 bits of a 32-bit register to fill the top 24 bits
373    /// with the 7th bit).  The size of the smaller type is indicated by the 1th
374    /// operand, a ValueType node.
375    SIGN_EXTEND_INREG,
376
377    /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
378    /// integer.
379    FP_TO_SINT,
380    FP_TO_UINT,
381
382    /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
383    /// down to the precision of the destination VT.  TRUNC is a flag, which is
384    /// always an integer that is zero or one.  If TRUNC is 0, this is a
385    /// normal rounding, if it is 1, this FP_ROUND is known to not change the
386    /// value of Y.
387    ///
388    /// The TRUNC = 1 case is used in cases where we know that the value will
389    /// not be modified by the node, because Y is not using any of the extra
390    /// precision of source type.  This allows certain transformations like
391    /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
392    /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
393    FP_ROUND,
394
395    /// FLT_ROUNDS_ - Returns current rounding mode:
396    /// -1 Undefined
397    ///  0 Round to 0
398    ///  1 Round to nearest
399    ///  2 Round to +inf
400    ///  3 Round to -inf
401    FLT_ROUNDS_,
402
403    /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and
404    /// rounds it to a floating point value.  It then promotes it and returns it
405    /// in a register of the same size.  This operation effectively just
406    /// discards excess precision.  The type to round down to is specified by
407    /// the VT operand, a VTSDNode.
408    FP_ROUND_INREG,
409
410    /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
411    FP_EXTEND,
412
413    /// BITCAST - This operator converts between integer, vector and FP
414    /// values, as if the value was stored to memory with one type and loaded
415    /// from the same address with the other type (or equivalently for vector
416    /// format conversions, etc).  The source and result are required to have
417    /// the same bit size (e.g.  f32 <-> i32).  This can also be used for
418    /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by
419    /// getNode().
420    BITCAST,
421
422    /// CONVERT_RNDSAT - This operator is used to support various conversions
423    /// between various types (float, signed, unsigned and vectors of those
424    /// types) with rounding and saturation. NOTE: Avoid using this operator as
425    /// most target don't support it and the operator might be removed in the
426    /// future. It takes the following arguments:
427    ///   0) value
428    ///   1) dest type (type to convert to)
429    ///   2) src type (type to convert from)
430    ///   3) rounding imm
431    ///   4) saturation imm
432    ///   5) ISD::CvtCode indicating the type of conversion to do
433    CONVERT_RNDSAT,
434
435    /// FP16_TO_FP32, FP32_TO_FP16 - These operators are used to perform
436    /// promotions and truncation for half-precision (16 bit) floating
437    /// numbers. We need special nodes since FP16 is a storage-only type with
438    /// special semantics of operations.
439    FP16_TO_FP32, FP32_TO_FP16,
440
441    /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
442    /// FLOG, FLOG2, FLOG10, FEXP, FEXP2,
443    /// FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary
444    /// floating point operations. These are inspired by libm.
445    FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
446    FLOG, FLOG2, FLOG10, FEXP, FEXP2,
447    FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR,
448
449    /// FSINCOS - Compute both fsin and fcos as a single operation.
450    FSINCOS,
451
452    /// LOAD and STORE have token chains as their first operand, then the same
453    /// operands as an LLVM load/store instruction, then an offset node that
454    /// is added / subtracted from the base pointer to form the address (for
455    /// indexed memory ops).
456    LOAD, STORE,
457
458    /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned
459    /// to a specified boundary.  This node always has two return values: a new
460    /// stack pointer value and a chain. The first operand is the token chain,
461    /// the second is the number of bytes to allocate, and the third is the
462    /// alignment boundary.  The size is guaranteed to be a multiple of the
463    /// stack alignment, and the alignment is guaranteed to be bigger than the
464    /// stack alignment (if required) or 0 to get standard stack alignment.
465    DYNAMIC_STACKALLOC,
466
467    /// Control flow instructions.  These all have token chains.
468
469    /// BR - Unconditional branch.  The first operand is the chain
470    /// operand, the second is the MBB to branch to.
471    BR,
472
473    /// BRIND - Indirect branch.  The first operand is the chain, the second
474    /// is the value to branch to, which must be of the same type as the
475    /// target's pointer type.
476    BRIND,
477
478    /// BR_JT - Jumptable branch. The first operand is the chain, the second
479    /// is the jumptable index, the last one is the jumptable entry index.
480    BR_JT,
481
482    /// BRCOND - Conditional branch.  The first operand is the chain, the
483    /// second is the condition, the third is the block to branch to if the
484    /// condition is true.  If the type of the condition is not i1, then the
485    /// high bits must conform to getBooleanContents.
486    BRCOND,
487
488    /// BR_CC - Conditional branch.  The behavior is like that of SELECT_CC, in
489    /// that the condition is represented as condition code, and two nodes to
490    /// compare, rather than as a combined SetCC node.  The operands in order
491    /// are chain, cc, lhs, rhs, block to branch to if condition is true.
492    BR_CC,
493
494    /// INLINEASM - Represents an inline asm block.  This node always has two
495    /// return values: a chain and a flag result.  The inputs are as follows:
496    ///   Operand #0  : Input chain.
497    ///   Operand #1  : a ExternalSymbolSDNode with a pointer to the asm string.
498    ///   Operand #2  : a MDNodeSDNode with the !srcloc metadata.
499    ///   Operand #3  : HasSideEffect, IsAlignStack bits.
500    ///   After this, it is followed by a list of operands with this format:
501    ///     ConstantSDNode: Flags that encode whether it is a mem or not, the
502    ///                     of operands that follow, etc.  See InlineAsm.h.
503    ///     ... however many operands ...
504    ///   Operand #last: Optional, an incoming flag.
505    ///
506    /// The variable width operands are required to represent target addressing
507    /// modes as a single "operand", even though they may have multiple
508    /// SDOperands.
509    INLINEASM,
510
511    /// EH_LABEL - Represents a label in mid basic block used to track
512    /// locations needed for debug and exception handling tables.  These nodes
513    /// take a chain as input and return a chain.
514    EH_LABEL,
515
516    /// STACKSAVE - STACKSAVE has one operand, an input chain.  It produces a
517    /// value, the same type as the pointer type for the system, and an output
518    /// chain.
519    STACKSAVE,
520
521    /// STACKRESTORE has two operands, an input chain and a pointer to restore
522    /// to it returns an output chain.
523    STACKRESTORE,
524
525    /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end
526    /// of a call sequence, and carry arbitrary information that target might
527    /// want to know.  The first operand is a chain, the rest are specified by
528    /// the target and not touched by the DAG optimizers.
529    /// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
530    CALLSEQ_START,  // Beginning of a call sequence
531    CALLSEQ_END,    // End of a call sequence
532
533    /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE,
534    /// and the alignment. It returns a pair of values: the vaarg value and a
535    /// new chain.
536    VAARG,
537
538    /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer,
539    /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the
540    /// source.
541    VACOPY,
542
543    /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain,
544    /// pointer, and a SRCVALUE.
545    VAEND, VASTART,
546
547    /// SRCVALUE - This is a node type that holds a Value* that is used to
548    /// make reference to a value in the LLVM IR.
549    SRCVALUE,
550
551    /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to
552    /// reference metadata in the IR.
553    MDNODE_SDNODE,
554
555    /// PCMARKER - This corresponds to the pcmarker intrinsic.
556    PCMARKER,
557
558    /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
559    /// The only operand is a chain and a value and a chain are produced.  The
560    /// value is the contents of the architecture specific cycle counter like
561    /// register (or other high accuracy low latency clock source)
562    READCYCLECOUNTER,
563
564    /// HANDLENODE node - Used as a handle for various purposes.
565    HANDLENODE,
566
567    /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.  It
568    /// takes as input a token chain, the pointer to the trampoline, the pointer
569    /// to the nested function, the pointer to pass for the 'nest' parameter, a
570    /// SRCVALUE for the trampoline and another for the nested function
571    /// (allowing targets to access the original Function*).
572    /// It produces a token chain as output.
573    INIT_TRAMPOLINE,
574
575    /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
576    /// It takes a pointer to the trampoline and produces a (possibly) new
577    /// pointer to the same trampoline with platform-specific adjustments
578    /// applied.  The pointer it returns points to an executable block of code.
579    ADJUST_TRAMPOLINE,
580
581    /// TRAP - Trapping instruction
582    TRAP,
583
584    /// DEBUGTRAP - Trap intended to get the attention of a debugger.
585    DEBUGTRAP,
586
587    /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand
588    /// is the chain.  The other operands are the address to prefetch,
589    /// read / write specifier, locality specifier and instruction / data cache
590    /// specifier.
591    PREFETCH,
592
593    /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope)
594    /// This corresponds to the fence instruction. It takes an input chain, and
595    /// two integer constants: an AtomicOrdering and a SynchronizationScope.
596    ATOMIC_FENCE,
597
598    /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
599    /// This corresponds to "load atomic" instruction.
600    ATOMIC_LOAD,
601
602    /// OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr, val)
603    /// This corresponds to "store atomic" instruction.
604    ATOMIC_STORE,
605
606    /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
607    /// This corresponds to the cmpxchg instruction.
608    ATOMIC_CMP_SWAP,
609
610    /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)
611    /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt)
612    /// These correspond to the atomicrmw instruction.
613    ATOMIC_SWAP,
614    ATOMIC_LOAD_ADD,
615    ATOMIC_LOAD_SUB,
616    ATOMIC_LOAD_AND,
617    ATOMIC_LOAD_OR,
618    ATOMIC_LOAD_XOR,
619    ATOMIC_LOAD_NAND,
620    ATOMIC_LOAD_MIN,
621    ATOMIC_LOAD_MAX,
622    ATOMIC_LOAD_UMIN,
623    ATOMIC_LOAD_UMAX,
624
625    /// This corresponds to the llvm.lifetime.* intrinsics. The first operand
626    /// is the chain and the second operand is the alloca pointer.
627    LIFETIME_START, LIFETIME_END,
628
629    /// BUILTIN_OP_END - This must be the last enum value in this list.
630    /// The target-specific pre-isel opcode values start here.
631    BUILTIN_OP_END
632  };
633
634  /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
635  /// which do not reference a specific memory location should be less than
636  /// this value. Those that do must not be less than this value, and can
637  /// be used with SelectionDAG::getMemIntrinsicNode.
638  static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+180;
639
640  //===--------------------------------------------------------------------===//
641  /// MemIndexedMode enum - This enum defines the load / store indexed
642  /// addressing modes.
643  ///
644  /// UNINDEXED    "Normal" load / store. The effective address is already
645  ///              computed and is available in the base pointer. The offset
646  ///              operand is always undefined. In addition to producing a
647  ///              chain, an unindexed load produces one value (result of the
648  ///              load); an unindexed store does not produce a value.
649  ///
650  /// PRE_INC      Similar to the unindexed mode where the effective address is
651  /// PRE_DEC      the value of the base pointer add / subtract the offset.
652  ///              It considers the computation as being folded into the load /
653  ///              store operation (i.e. the load / store does the address
654  ///              computation as well as performing the memory transaction).
655  ///              The base operand is always undefined. In addition to
656  ///              producing a chain, pre-indexed load produces two values
657  ///              (result of the load and the result of the address
658  ///              computation); a pre-indexed store produces one value (result
659  ///              of the address computation).
660  ///
661  /// POST_INC     The effective address is the value of the base pointer. The
662  /// POST_DEC     value of the offset operand is then added to / subtracted
663  ///              from the base after memory transaction. In addition to
664  ///              producing a chain, post-indexed load produces two values
665  ///              (the result of the load and the result of the base +/- offset
666  ///              computation); a post-indexed store produces one value (the
667  ///              the result of the base +/- offset computation).
668  enum MemIndexedMode {
669    UNINDEXED = 0,
670    PRE_INC,
671    PRE_DEC,
672    POST_INC,
673    POST_DEC,
674    LAST_INDEXED_MODE
675  };
676
677  //===--------------------------------------------------------------------===//
678  /// LoadExtType enum - This enum defines the three variants of LOADEXT
679  /// (load with extension).
680  ///
681  /// SEXTLOAD loads the integer operand and sign extends it to a larger
682  ///          integer result type.
683  /// ZEXTLOAD loads the integer operand and zero extends it to a larger
684  ///          integer result type.
685  /// EXTLOAD  is used for two things: floating point extending loads and
686  ///          integer extending loads [the top bits are undefined].
687  enum LoadExtType {
688    NON_EXTLOAD = 0,
689    EXTLOAD,
690    SEXTLOAD,
691    ZEXTLOAD,
692    LAST_LOADEXT_TYPE
693  };
694
695  //===--------------------------------------------------------------------===//
696  /// ISD::CondCode enum - These are ordered carefully to make the bitfields
697  /// below work out, when considering SETFALSE (something that never exists
698  /// dynamically) as 0.  "U" -> Unsigned (for integer operands) or Unordered
699  /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal
700  /// to.  If the "N" column is 1, the result of the comparison is undefined if
701  /// the input is a NAN.
702  ///
703  /// All of these (except for the 'always folded ops') should be handled for
704  /// floating point.  For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
705  /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
706  ///
707  /// Note that these are laid out in a specific order to allow bit-twiddling
708  /// to transform conditions.
709  enum CondCode {
710    // Opcode          N U L G E       Intuitive operation
711    SETFALSE,      //    0 0 0 0       Always false (always folded)
712    SETOEQ,        //    0 0 0 1       True if ordered and equal
713    SETOGT,        //    0 0 1 0       True if ordered and greater than
714    SETOGE,        //    0 0 1 1       True if ordered and greater than or equal
715    SETOLT,        //    0 1 0 0       True if ordered and less than
716    SETOLE,        //    0 1 0 1       True if ordered and less than or equal
717    SETONE,        //    0 1 1 0       True if ordered and operands are unequal
718    SETO,          //    0 1 1 1       True if ordered (no nans)
719    SETUO,         //    1 0 0 0       True if unordered: isnan(X) | isnan(Y)
720    SETUEQ,        //    1 0 0 1       True if unordered or equal
721    SETUGT,        //    1 0 1 0       True if unordered or greater than
722    SETUGE,        //    1 0 1 1       True if unordered, greater than, or equal
723    SETULT,        //    1 1 0 0       True if unordered or less than
724    SETULE,        //    1 1 0 1       True if unordered, less than, or equal
725    SETUNE,        //    1 1 1 0       True if unordered or not equal
726    SETTRUE,       //    1 1 1 1       Always true (always folded)
727    // Don't care operations: undefined if the input is a nan.
728    SETFALSE2,     //  1 X 0 0 0       Always false (always folded)
729    SETEQ,         //  1 X 0 0 1       True if equal
730    SETGT,         //  1 X 0 1 0       True if greater than
731    SETGE,         //  1 X 0 1 1       True if greater than or equal
732    SETLT,         //  1 X 1 0 0       True if less than
733    SETLE,         //  1 X 1 0 1       True if less than or equal
734    SETNE,         //  1 X 1 1 0       True if not equal
735    SETTRUE2,      //  1 X 1 1 1       Always true (always folded)
736
737    SETCC_INVALID       // Marker value.
738  };
739
740  /// isSignedIntSetCC - Return true if this is a setcc instruction that
741  /// performs a signed comparison when used with integer operands.
742  inline bool isSignedIntSetCC(CondCode Code) {
743    return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE;
744  }
745
746  /// isUnsignedIntSetCC - Return true if this is a setcc instruction that
747  /// performs an unsigned comparison when used with integer operands.
748  inline bool isUnsignedIntSetCC(CondCode Code) {
749    return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE;
750  }
751
752  /// isTrueWhenEqual - Return true if the specified condition returns true if
753  /// the two operands to the condition are equal.  Note that if one of the two
754  /// operands is a NaN, this value is meaningless.
755  inline bool isTrueWhenEqual(CondCode Cond) {
756    return ((int)Cond & 1) != 0;
757  }
758
759  /// getUnorderedFlavor - This function returns 0 if the condition is always
760  /// false if an operand is a NaN, 1 if the condition is always true if the
761  /// operand is a NaN, and 2 if the condition is undefined if the operand is a
762  /// NaN.
763  inline unsigned getUnorderedFlavor(CondCode Cond) {
764    return ((int)Cond >> 3) & 3;
765  }
766
767  /// getSetCCInverse - Return the operation corresponding to !(X op Y), where
768  /// 'op' is a valid SetCC operation.
769  CondCode getSetCCInverse(CondCode Operation, bool isInteger);
770
771  /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X)
772  /// when given the operation for (X op Y).
773  CondCode getSetCCSwappedOperands(CondCode Operation);
774
775  /// getSetCCOrOperation - Return the result of a logical OR between different
776  /// comparisons of identical values: ((X op1 Y) | (X op2 Y)).  This
777  /// function returns SETCC_INVALID if it is not possible to represent the
778  /// resultant comparison.
779  CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
780
781  /// getSetCCAndOperation - Return the result of a logical AND between
782  /// different comparisons of identical values: ((X op1 Y) & (X op2 Y)).  This
783  /// function returns SETCC_INVALID if it is not possible to represent the
784  /// resultant comparison.
785  CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
786
787  //===--------------------------------------------------------------------===//
788  /// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT
789  /// supports.
790  enum CvtCode {
791    CVT_FF,     /// Float from Float
792    CVT_FS,     /// Float from Signed
793    CVT_FU,     /// Float from Unsigned
794    CVT_SF,     /// Signed from Float
795    CVT_UF,     /// Unsigned from Float
796    CVT_SS,     /// Signed from Signed
797    CVT_SU,     /// Signed from Unsigned
798    CVT_US,     /// Unsigned from Signed
799    CVT_UU,     /// Unsigned from Unsigned
800    CVT_INVALID /// Marker - Invalid opcode
801  };
802
803} // end llvm::ISD namespace
804
805} // end llvm namespace
806
807#endif
808