19b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey//===-- llvm/CodeGen/SchedulerRegistry.h ------------------------*- C++ -*-===// 29b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey// 39b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey// The LLVM Compiler Infrastructure 49b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey// 57ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// This file is distributed under the University of Illinois Open Source 67ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// License. See LICENSE.TXT for details. 79b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey// 89b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey//===----------------------------------------------------------------------===// 99b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey// 109b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey// This file contains the implementation for instruction scheduler function 119b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey// pass registry (RegisterScheduler). 129b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey// 139b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey//===----------------------------------------------------------------------===// 149b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey 15674be02d525d4e24bc6943ed9274958c580bcfbcJakub Staszak#ifndef LLVM_CODEGEN_SCHEDULERREGISTRY_H 16674be02d525d4e24bc6943ed9274958c580bcfbcJakub Staszak#define LLVM_CODEGEN_SCHEDULERREGISTRY_H 179b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey 189b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey#include "llvm/CodeGen/MachinePassRegistry.h" 1998a366d547772010e94609e4584489b3e5ce0043Bill Wendling#include "llvm/Target/TargetMachine.h" 209b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey 219b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskeynamespace llvm { 229b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey 239b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey//===----------------------------------------------------------------------===// 249b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey/// 259b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey/// RegisterScheduler class - Track the registration of instruction schedulers. 269b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey/// 279b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey//===----------------------------------------------------------------------===// 289b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey 299b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskeyclass SelectionDAGISel; 3047ac0f0c7c39289f5970688154e385be22b7f293Dan Gohmanclass ScheduleDAGSDNodes; 319b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskeyclass SelectionDAG; 329b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskeyclass MachineBasicBlock; 339b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey 349b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskeyclass RegisterScheduler : public MachinePassRegistryNode { 359b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskeypublic: 3698a366d547772010e94609e4584489b3e5ce0043Bill Wendling typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, 3798a366d547772010e94609e4584489b3e5ce0043Bill Wendling CodeGenOpt::Level); 389b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey 399b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey static MachinePassRegistry Registry; 409b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey 419b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey RegisterScheduler(const char *N, const char *D, FunctionPassCtor C) 429b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey : MachinePassRegistryNode(N, D, (MachinePassCtor)C) 439b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey { Registry.Add(this); } 449b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey ~RegisterScheduler() { Registry.Remove(this); } 45ee498d3254b86bceb4f441741e9f442990647ce6Andrew Trick 469b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey 479b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey // Accessors. 489b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey // 499b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey RegisterScheduler *getNext() const { 509b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey return (RegisterScheduler *)MachinePassRegistryNode::getNext(); 519b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey } 529b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey static RegisterScheduler *getList() { 539b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey return (RegisterScheduler *)Registry.getList(); 549b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey } 559b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey static FunctionPassCtor getDefault() { 569b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey return (FunctionPassCtor)Registry.getDefault(); 579b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey } 589b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey static void setDefault(FunctionPassCtor C) { 599b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey Registry.setDefault((MachinePassCtor)C); 609b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey } 619b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey static void setListener(MachinePassRegistryListener *L) { 629b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey Registry.setListener(L); 639b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey } 649b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey}; 659b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey 66ad38b6e4e51bcda85a0ef3e8dbabde72ca3e008fDan Gohman/// createBURRListDAGScheduler - This creates a bottom up register usage 67ad38b6e4e51bcda85a0ef3e8dbabde72ca3e008fDan Gohman/// reduction list scheduler. 6847ac0f0c7c39289f5970688154e385be22b7f293Dan GohmanScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS, 6998a366d547772010e94609e4584489b3e5ce0043Bill Wendling CodeGenOpt::Level OptLevel); 70ad38b6e4e51bcda85a0ef3e8dbabde72ca3e008fDan Gohman 7115a16def6e70c8f7df1023da80ceb89887203b40Evan Cheng/// createBURRListDAGScheduler - This creates a bottom up list scheduler that 7215a16def6e70c8f7df1023da80ceb89887203b40Evan Cheng/// schedules nodes in source code order when possible. 73187361b056823df4ff292561fe47468dad956872Bill WendlingScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS, 74187361b056823df4ff292561fe47468dad956872Bill Wendling CodeGenOpt::Level OptLevel); 75187361b056823df4ff292561fe47468dad956872Bill Wendling 7670017e44cdba1946cc478ce1856a3e855a767e28Evan Cheng/// createHybridListDAGScheduler - This creates a bottom up register pressure 7770017e44cdba1946cc478ce1856a3e855a767e28Evan Cheng/// aware list scheduler that make use of latency information to avoid stalls 7870017e44cdba1946cc478ce1856a3e855a767e28Evan Cheng/// for long latency instructions in low register pressure mode. In high 7970017e44cdba1946cc478ce1856a3e855a767e28Evan Cheng/// register pressure mode it schedules to reduce register pressure. 8015a16def6e70c8f7df1023da80ceb89887203b40Evan ChengScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS, 8115a16def6e70c8f7df1023da80ceb89887203b40Evan Cheng CodeGenOpt::Level); 8215a16def6e70c8f7df1023da80ceb89887203b40Evan Cheng 8370017e44cdba1946cc478ce1856a3e855a767e28Evan Cheng/// createILPListDAGScheduler - This creates a bottom up register pressure 8470017e44cdba1946cc478ce1856a3e855a767e28Evan Cheng/// aware list scheduler that tries to increase instruction level parallelism 8570017e44cdba1946cc478ce1856a3e855a767e28Evan Cheng/// in low register pressure mode. In high register pressure mode it schedules 8670017e44cdba1946cc478ce1856a3e855a767e28Evan Cheng/// to reduce register pressure. 8770017e44cdba1946cc478ce1856a3e855a767e28Evan ChengScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS, 8870017e44cdba1946cc478ce1856a3e855a767e28Evan Cheng CodeGenOpt::Level); 8979ce276083ced01256a0eb7d80731e4948ca6e87Dan Gohman 90ad38b6e4e51bcda85a0ef3e8dbabde72ca3e008fDan Gohman/// createFastDAGScheduler - This creates a "fast" scheduler. 91ad38b6e4e51bcda85a0ef3e8dbabde72ca3e008fDan Gohman/// 9247ac0f0c7c39289f5970688154e385be22b7f293Dan GohmanScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS, 9398a366d547772010e94609e4584489b3e5ce0043Bill Wendling CodeGenOpt::Level OptLevel); 94ad38b6e4e51bcda85a0ef3e8dbabde72ca3e008fDan Gohman 95ee498d3254b86bceb4f441741e9f442990647ce6Andrew Trick/// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down 96ee498d3254b86bceb4f441741e9f442990647ce6Andrew Trick/// DFA driven list scheduler with clustering heuristic to control 97ee498d3254b86bceb4f441741e9f442990647ce6Andrew Trick/// register pressure. 98ee498d3254b86bceb4f441741e9f442990647ce6Andrew TrickScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS, 99ee498d3254b86bceb4f441741e9f442990647ce6Andrew Trick CodeGenOpt::Level OptLevel); 100ad38b6e4e51bcda85a0ef3e8dbabde72ca3e008fDan Gohman/// createDefaultScheduler - This creates an instruction scheduler appropriate 101ad38b6e4e51bcda85a0ef3e8dbabde72ca3e008fDan Gohman/// for the target. 10247ac0f0c7c39289f5970688154e385be22b7f293Dan GohmanScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS, 10398a366d547772010e94609e4584489b3e5ce0043Bill Wendling CodeGenOpt::Level OptLevel); 104ad38b6e4e51bcda85a0ef3e8dbabde72ca3e008fDan Gohman 105d4f759696d1bd0ba7c0e6eefd7ed8b556840419aEvan Cheng/// createDAGLinearizer - This creates a "no-scheduling" scheduler which 106d4f759696d1bd0ba7c0e6eefd7ed8b556840419aEvan Cheng/// linearize the DAG using topological order. 107d4f759696d1bd0ba7c0e6eefd7ed8b556840419aEvan ChengScheduleDAGSDNodes *createDAGLinearizer(SelectionDAGISel *IS, 108d4f759696d1bd0ba7c0e6eefd7ed8b556840419aEvan Cheng CodeGenOpt::Level OptLevel); 109d4f759696d1bd0ba7c0e6eefd7ed8b556840419aEvan Cheng 1109b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey} // end namespace llvm 1119b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey 1129b9528d8f6da5e79b8ef060eab941d07e0860f20Jim Laskey#endif 113