TargetMachine.h revision a3f99f90338d89354384ca25f53ca4450a1a9d18
1//===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the TargetMachine and LLVMTargetMachine classes. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETMACHINE_H 15#define LLVM_TARGET_TARGETMACHINE_H 16 17#include "llvm/Target/TargetInstrItineraries.h" 18#include <cassert> 19 20namespace llvm { 21 22class TargetAsmInfo; 23class TargetData; 24class TargetSubtarget; 25class TargetInstrInfo; 26class TargetIntrinsicInfo; 27class TargetJITInfo; 28class TargetLowering; 29class TargetFrameInfo; 30class MachineCodeEmitter; 31class JITCodeEmitter; 32class TargetRegisterInfo; 33class Module; 34class PassManagerBase; 35class PassManager; 36class Pass; 37class TargetMachOWriterInfo; 38class TargetELFWriterInfo; 39class raw_ostream; 40 41// Relocation model types. 42namespace Reloc { 43 enum Model { 44 Default, 45 Static, 46 PIC_, // Cannot be named PIC due to collision with -DPIC 47 DynamicNoPIC 48 }; 49} 50 51// Code model types. 52namespace CodeModel { 53 enum Model { 54 Default, 55 Small, 56 Kernel, 57 Medium, 58 Large 59 }; 60} 61 62namespace FileModel { 63 enum Model { 64 Error, 65 None, 66 AsmFile, 67 MachOFile, 68 ElfFile 69 }; 70} 71 72// Code generation optimization level. 73namespace CodeGenOpt { 74 enum Level { 75 Default, 76 None, 77 Aggressive 78 }; 79} 80 81//===----------------------------------------------------------------------===// 82/// 83/// TargetMachine - Primary interface to the complete machine description for 84/// the target machine. All target-specific information should be accessible 85/// through this interface. 86/// 87class TargetMachine { 88 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT 89 void operator=(const TargetMachine &); // DO NOT IMPLEMENT 90protected: // Can only create subclasses. 91 TargetMachine() : AsmInfo(0) { } 92 93 /// getSubtargetImpl - virtual method implemented by subclasses that returns 94 /// a reference to that target's TargetSubtarget-derived member variable. 95 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; } 96 97 /// AsmInfo - Contains target specific asm information. 98 /// 99 mutable const TargetAsmInfo *AsmInfo; 100 101 /// createTargetAsmInfo - Create a new instance of target specific asm 102 /// information. 103 virtual const TargetAsmInfo *createTargetAsmInfo() const { return 0; } 104 105public: 106 virtual ~TargetMachine(); 107 108 /// getModuleMatchQuality - This static method should be implemented by 109 /// targets to indicate how closely they match the specified module. This is 110 /// used by the LLC tool to determine which target to use when an explicit 111 /// -march option is not specified. If a target returns zero, it will never 112 /// be chosen without an explicit -march option. 113 static unsigned getModuleMatchQuality(const Module &) { return 0; } 114 115 /// getJITMatchQuality - This static method should be implemented by targets 116 /// that provide JIT capabilities to indicate how suitable they are for 117 /// execution on the current host. If a value of 0 is returned, the target 118 /// will not be used unless an explicit -march option is used. 119 static unsigned getJITMatchQuality() { return 0; } 120 121 // Interfaces to the major aspects of target machine information: 122 // -- Instruction opcode and operand information 123 // -- Pipelines and scheduling information 124 // -- Stack frame information 125 // -- Selection DAG lowering information 126 // 127 virtual const TargetInstrInfo *getInstrInfo() const { return 0; } 128 virtual const TargetFrameInfo *getFrameInfo() const { return 0; } 129 virtual TargetLowering *getTargetLowering() const { return 0; } 130 virtual const TargetData *getTargetData() const { return 0; } 131 132 /// getTargetAsmInfo - Return target specific asm information. 133 /// 134 const TargetAsmInfo *getTargetAsmInfo() const { 135 if (!AsmInfo) AsmInfo = createTargetAsmInfo(); 136 return AsmInfo; 137 } 138 139 /// getSubtarget - This method returns a pointer to the specified type of 140 /// TargetSubtarget. In debug builds, it verifies that the object being 141 /// returned is of the correct type. 142 template<typename STC> const STC &getSubtarget() const { 143 const TargetSubtarget *TST = getSubtargetImpl(); 144 assert(TST && dynamic_cast<const STC*>(TST) && 145 "Not the right kind of subtarget!"); 146 return *static_cast<const STC*>(TST); 147 } 148 149 /// getRegisterInfo - If register information is available, return it. If 150 /// not, return null. This is kept separate from RegInfo until RegInfo has 151 /// details of graph coloring register allocation removed from it. 152 /// 153 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; } 154 155 /// getIntrinsicInfo - If intrinsic information is available, return it. If 156 /// not, return null. 157 /// 158 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; } 159 160 /// getJITInfo - If this target supports a JIT, return information for it, 161 /// otherwise return null. 162 /// 163 virtual TargetJITInfo *getJITInfo() { return 0; } 164 165 /// getInstrItineraryData - Returns instruction itinerary data for the target 166 /// or specific subtarget. 167 /// 168 virtual const InstrItineraryData getInstrItineraryData() const { 169 return InstrItineraryData(); 170 } 171 172 /// getMachOWriterInfo - If this target supports a Mach-O writer, return 173 /// information for it, otherwise return null. 174 /// 175 virtual const TargetMachOWriterInfo *getMachOWriterInfo() const { return 0; } 176 177 /// getELFWriterInfo - If this target supports an ELF writer, return 178 /// information for it, otherwise return null. 179 /// 180 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; } 181 182 /// getRelocationModel - Returns the code generation relocation model. The 183 /// choices are static, PIC, and dynamic-no-pic, and target default. 184 static Reloc::Model getRelocationModel(); 185 186 /// setRelocationModel - Sets the code generation relocation model. 187 /// 188 static void setRelocationModel(Reloc::Model Model); 189 190 /// getCodeModel - Returns the code model. The choices are small, kernel, 191 /// medium, large, and target default. 192 static CodeModel::Model getCodeModel(); 193 194 /// setCodeModel - Sets the code model. 195 /// 196 static void setCodeModel(CodeModel::Model Model); 197 198 /// getAsmVerbosityDefault - Returns the default value of asm verbosity. 199 /// 200 static bool getAsmVerbosityDefault(); 201 202 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default 203 /// is false. 204 static void setAsmVerbosityDefault(bool); 205 206 /// CodeGenFileType - These enums are meant to be passed into 207 /// addPassesToEmitFile to indicate what type of file to emit. 208 enum CodeGenFileType { 209 AssemblyFile, ObjectFile, DynamicLibrary 210 }; 211 212 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge 213 /// on this target. User flag overrides. 214 virtual bool getEnableTailMergeDefault() const { return true; } 215 216 /// addPassesToEmitFile - Add passes to the specified pass manager to get the 217 /// specified file emitted. Typically this will involve several steps of code 218 /// generation. If Fast is set to true, the code generator should emit code 219 /// as fast as possible, though the generated code may be less efficient. 220 /// This method should return FileModel::Error if emission of this file type 221 /// is not supported. 222 /// 223 virtual FileModel::Model addPassesToEmitFile(PassManagerBase &, 224 raw_ostream &, 225 CodeGenFileType, 226 CodeGenOpt::Level) { 227 return FileModel::None; 228 } 229 230 /// addPassesToEmitFileFinish - If the passes to emit the specified file had 231 /// to be split up (e.g., to add an object writer pass), this method can be 232 /// used to finish up adding passes to emit the file, if necessary. 233 /// 234 virtual bool addPassesToEmitFileFinish(PassManagerBase &, 235 MachineCodeEmitter *, 236 CodeGenOpt::Level) { 237 return true; 238 } 239 240 /// addPassesToEmitFileFinish - If the passes to emit the specified file had 241 /// to be split up (e.g., to add an object writer pass), this method can be 242 /// used to finish up adding passes to emit the file, if necessary. 243 /// 244 virtual bool addPassesToEmitFileFinish(PassManagerBase &, 245 JITCodeEmitter *, 246 CodeGenOpt::Level) { 247 return true; 248 } 249 250 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to 251 /// get machine code emitted. This uses a MachineCodeEmitter object to handle 252 /// actually outputting the machine code and resolving things like the address 253 /// of functions. This method returns true if machine code emission is 254 /// not supported. 255 /// 256 virtual bool addPassesToEmitMachineCode(PassManagerBase &, 257 MachineCodeEmitter &, 258 CodeGenOpt::Level) { 259 return true; 260 } 261 262 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to 263 /// get machine code emitted. This uses a MachineCodeEmitter object to handle 264 /// actually outputting the machine code and resolving things like the address 265 /// of functions. This method returns true if machine code emission is 266 /// not supported. 267 /// 268 virtual bool addPassesToEmitMachineCode(PassManagerBase &, 269 JITCodeEmitter &, 270 CodeGenOpt::Level) { 271 return true; 272 } 273 274 /// addPassesToEmitWholeFile - This method can be implemented by targets that 275 /// require having the entire module at once. This is not recommended, do not 276 /// use this. 277 virtual bool WantsWholeFile() const { return false; } 278 virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &, 279 CodeGenFileType, 280 CodeGenOpt::Level) { 281 return true; 282 } 283}; 284 285/// LLVMTargetMachine - This class describes a target machine that is 286/// implemented with the LLVM target-independent code generator. 287/// 288class LLVMTargetMachine : public TargetMachine { 289protected: // Can only create subclasses. 290 LLVMTargetMachine() { } 291 292 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for 293 /// both emitting to assembly files or machine code output. 294 /// 295 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level); 296 297public: 298 299 /// addPassesToEmitFile - Add passes to the specified pass manager to get the 300 /// specified file emitted. Typically this will involve several steps of code 301 /// generation. If OptLevel is None, the code generator should emit code as fast 302 /// as possible, though the generated code may be less efficient. This method 303 /// should return FileModel::Error if emission of this file type is not 304 /// supported. 305 /// 306 /// The default implementation of this method adds components from the 307 /// LLVM retargetable code generator, invoking the methods below to get 308 /// target-specific passes in standard locations. 309 /// 310 virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM, 311 raw_ostream &Out, 312 CodeGenFileType FileType, 313 CodeGenOpt::Level); 314 315 /// addPassesToEmitFileFinish - If the passes to emit the specified file had 316 /// to be split up (e.g., to add an object writer pass), this method can be 317 /// used to finish up adding passes to emit the file, if necessary. 318 /// 319 virtual bool addPassesToEmitFileFinish(PassManagerBase &PM, 320 MachineCodeEmitter *MCE, 321 CodeGenOpt::Level); 322 323 /// addPassesToEmitFileFinish - If the passes to emit the specified file had 324 /// to be split up (e.g., to add an object writer pass), this method can be 325 /// used to finish up adding passes to emit the file, if necessary. 326 /// 327 virtual bool addPassesToEmitFileFinish(PassManagerBase &PM, 328 JITCodeEmitter *MCE, 329 CodeGenOpt::Level); 330 331 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to 332 /// get machine code emitted. This uses a MachineCodeEmitter object to handle 333 /// actually outputting the machine code and resolving things like the address 334 /// of functions. This method returns true if machine code emission is 335 /// not supported. 336 /// 337 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM, 338 MachineCodeEmitter &MCE, 339 CodeGenOpt::Level); 340 341 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to 342 /// get machine code emitted. This uses a MachineCodeEmitter object to handle 343 /// actually outputting the machine code and resolving things like the address 344 /// of functions. This method returns true if machine code emission is 345 /// not supported. 346 /// 347 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM, 348 JITCodeEmitter &MCE, 349 CodeGenOpt::Level); 350 351 /// Target-Independent Code Generator Pass Configuration Options. 352 353 /// addInstSelector - This method should add any "last minute" LLVM->LLVM 354 /// passes, then install an instruction selector pass, which converts from 355 /// LLVM code to machine instructions. 356 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) { 357 return true; 358 } 359 360 /// addPreRegAllocPasses - This method may be implemented by targets that want 361 /// to run passes immediately before register allocation. This should return 362 /// true if -print-machineinstrs should print after these passes. 363 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) { 364 return false; 365 } 366 367 /// addPostRegAllocPasses - This method may be implemented by targets that 368 /// want to run passes after register allocation but before prolog-epilog 369 /// insertion. This should return true if -print-machineinstrs should print 370 /// after these passes. 371 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) { 372 return false; 373 } 374 375 /// addPreEmitPass - This pass may be implemented by targets that want to run 376 /// passes immediately before machine code is emitted. This should return 377 /// true if -print-machineinstrs should print out the code after the passes. 378 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) { 379 return false; 380 } 381 382 383 /// addAssemblyEmitter - This pass should be overridden by the target to add 384 /// the asmprinter, if asm emission is supported. If this is not supported, 385 /// 'true' should be returned. 386 virtual bool addAssemblyEmitter(PassManagerBase &, CodeGenOpt::Level, 387 bool /* VerboseAsmDefault */, raw_ostream &) { 388 return true; 389 } 390 391 /// addCodeEmitter - This pass should be overridden by the target to add a 392 /// code emitter, if supported. If this is not supported, 'true' should be 393 /// returned. If DumpAsm is true, the generated assembly is printed to cerr. 394 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level, 395 bool /*DumpAsm*/, MachineCodeEmitter &) { 396 return true; 397 } 398 399 /// addCodeEmitter - This pass should be overridden by the target to add a 400 /// code emitter, if supported. If this is not supported, 'true' should be 401 /// returned. If DumpAsm is true, the generated assembly is printed to cerr. 402 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level, 403 bool /*DumpAsm*/, JITCodeEmitter &) { 404 return true; 405 } 406 407 /// addSimpleCodeEmitter - This pass should be overridden by the target to add 408 /// a code emitter (without setting flags), if supported. If this is not 409 /// supported, 'true' should be returned. If DumpAsm is true, the generated 410 /// assembly is printed to cerr. 411 virtual bool addSimpleCodeEmitter(PassManagerBase &, CodeGenOpt::Level, 412 bool /*DumpAsm*/, MachineCodeEmitter &) { 413 return true; 414 } 415 416 /// addSimpleCodeEmitter - This pass should be overridden by the target to add 417 /// a code emitter (without setting flags), if supported. If this is not 418 /// supported, 'true' should be returned. If DumpAsm is true, the generated 419 /// assembly is printed to cerr. 420 virtual bool addSimpleCodeEmitter(PassManagerBase &, CodeGenOpt::Level, 421 bool /*DumpAsm*/, JITCodeEmitter &) { 422 return true; 423 } 424 425 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge 426 /// on this target. User flag overrides. 427 virtual bool getEnableTailMergeDefault() const { return true; } 428}; 429 430} // End llvm namespace 431 432#endif 433