15b1b4489cf3a0f56f8be0673fc5cc380a32d277bEvan Cheng//==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==// 2fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman// 3fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman// The LLVM Compiler Infrastructure 4fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman// 57ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// This file is distributed under the University of Illinois Open Source 67ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// License. See LICENSE.TXT for details. 7fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman// 8fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman//===----------------------------------------------------------------------===// 9fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman// 10fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman// This file describes the subtarget options of a Target machine. 11fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman// 12fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman//===----------------------------------------------------------------------===// 13fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman 145b1b4489cf3a0f56f8be0673fc5cc380a32d277bEvan Cheng#ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H 155b1b4489cf3a0f56f8be0673fc5cc380a32d277bEvan Cheng#define LLVM_TARGET_TARGETSUBTARGETINFO_H 16fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman 1794214703d97d8d9dfca88174ffc7e94820a85e62Evan Cheng#include "llvm/MC/MCSubtargetInfo.h" 186c01492ac40bed9529a2f7c8d40da34b8f04365eCraig Topper#include "llvm/Support/CodeGen.h" 19fa16354e0370fe884830286923352268b036737dEvan Cheng 20fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begemannamespace llvm { 21fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman 22789cb5df9ca61f8a3794a4fbde7cc020fd00a02aBill Wendlingclass MachineFunction; 23ee290ba35af88393ba18dd19e6e39d50c7872534Andrew Trickclass MachineInstr; 24710461688bba935f0ad5c75da7fec2ad0f225c00David Goodwinclass SDep; 25dc4bdcdef1c8dd1a28b82deb08df039e5c0ffc5aDavid Goodwinclass SUnit; 26c2e8a7e8d2ab156afaa8ab0d0317dd9ee3db7d30David Goodwinclass TargetRegisterClass; 27ee290ba35af88393ba18dd19e6e39d50c7872534Andrew Trickclass TargetSchedModel; 2838e61122f27a8ca4ef0578eaf6dc5242880d2918Andrew Trickstruct MachineSchedPolicy; 29c2e8a7e8d2ab156afaa8ab0d0317dd9ee3db7d30David Goodwintemplate <typename T> class SmallVectorImpl; 30710461688bba935f0ad5c75da7fec2ad0f225c00David Goodwin 31fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman//===----------------------------------------------------------------------===// 32fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman/// 335b1b4489cf3a0f56f8be0673fc5cc380a32d277bEvan Cheng/// TargetSubtargetInfo - Generic base class for all target subtargets. All 34fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman/// Target-specific options that control code generation and printing should 355b1b4489cf3a0f56f8be0673fc5cc380a32d277bEvan Cheng/// be exposed through a TargetSubtargetInfo-derived class. 36fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman/// 375b1b4489cf3a0f56f8be0673fc5cc380a32d277bEvan Chengclass TargetSubtargetInfo : public MCSubtargetInfo { 38001d3dc976d7cda8a3dd8c7fd4020b0b96033f4eCraig Topper TargetSubtargetInfo(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION; 39001d3dc976d7cda8a3dd8c7fd4020b0b96033f4eCraig Topper void operator=(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION; 40fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begemanprotected: // Can only create subclasses... 415b1b4489cf3a0f56f8be0673fc5cc380a32d277bEvan Cheng TargetSubtargetInfo(); 42fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begemanpublic: 434c3715c2e5e17d7216a96ac2baf9720630f04408David Goodwin // AntiDepBreakMode - Type of anti-dependence breaking that should 444c3715c2e5e17d7216a96ac2baf9720630f04408David Goodwin // be performed before post-RA scheduling. 454c3715c2e5e17d7216a96ac2baf9720630f04408David Goodwin typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode; 4644d23825d61d530b8d562329ec8fc2d4f843bb8dCraig Topper typedef SmallVectorImpl<const TargetRegisterClass*> RegClassVector; 474c3715c2e5e17d7216a96ac2baf9720630f04408David Goodwin 485b1b4489cf3a0f56f8be0673fc5cc380a32d277bEvan Cheng virtual ~TargetSubtargetInfo(); 498749b61178228ba1fb2668034d79da1b247173d7Dan Gohman 50ee290ba35af88393ba18dd19e6e39d50c7872534Andrew Trick /// Resolve a SchedClass at runtime, where SchedClass identifies an 51ee290ba35af88393ba18dd19e6e39d50c7872534Andrew Trick /// MCSchedClassDesc with the isVariant property. This may return the ID of 52ee290ba35af88393ba18dd19e6e39d50c7872534Andrew Trick /// another variant SchedClass, but repeated invocation must quickly terminate 53ee290ba35af88393ba18dd19e6e39d50c7872534Andrew Trick /// in a nonvariant SchedClass. 54ee290ba35af88393ba18dd19e6e39d50c7872534Andrew Trick virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, 55ee290ba35af88393ba18dd19e6e39d50c7872534Andrew Trick const TargetSchedModel* SchedModel) const { 56ee290ba35af88393ba18dd19e6e39d50c7872534Andrew Trick return 0; 57e127dfd0b175b5a336e61fecaad7fc2aec65d95cAndrew Trick } 58e127dfd0b175b5a336e61fecaad7fc2aec65d95cAndrew Trick 59b6ac11cd03e9dd97b45dc97787171f942ef8e344Andrew Trick /// \brief Temporary API to test migration to MI scheduler. 60b6ac11cd03e9dd97b45dc97787171f942ef8e344Andrew Trick bool useMachineScheduler() const; 61b6ac11cd03e9dd97b45dc97787171f942ef8e344Andrew Trick 62ad1cc1d1bfc0accd3f1af5c02ac367ff46a4bfdfAndrew Trick /// \brief True if the subtarget should run MachineScheduler after aggressive 63ad1cc1d1bfc0accd3f1af5c02ac367ff46a4bfdfAndrew Trick /// coalescing. 64ad1cc1d1bfc0accd3f1af5c02ac367ff46a4bfdfAndrew Trick /// 65ad1cc1d1bfc0accd3f1af5c02ac367ff46a4bfdfAndrew Trick /// This currently replaces the SelectionDAG scheduler with the "source" order 66ad1cc1d1bfc0accd3f1af5c02ac367ff46a4bfdfAndrew Trick /// scheduler. It does not yet disable the postRA scheduler. 67ad1cc1d1bfc0accd3f1af5c02ac367ff46a4bfdfAndrew Trick virtual bool enableMachineScheduler() const; 68ad1cc1d1bfc0accd3f1af5c02ac367ff46a4bfdfAndrew Trick 69cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines /// \brief True if the subtarget should run PostMachineScheduler. 70cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines /// 71cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines /// This only takes effect if the target has configured the 72cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines /// PostMachineScheduler pass to run, or if the global cl::opt flag, 73cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines /// MISchedPostRA, is set. 74cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines virtual bool enablePostMachineScheduler() const; 75cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 76cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines /// \brief True if the subtarget should run the atomic expansion pass. 77cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines virtual bool enableAtomicExpandLoadLinked() const; 78cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 7938e61122f27a8ca4ef0578eaf6dc5242880d2918Andrew Trick /// \brief Override generic scheduling policy within a region. 8038e61122f27a8ca4ef0578eaf6dc5242880d2918Andrew Trick /// 8138e61122f27a8ca4ef0578eaf6dc5242880d2918Andrew Trick /// This is a convenient way for targets that don't provide any custom 8238e61122f27a8ca4ef0578eaf6dc5242880d2918Andrew Trick /// scheduling heuristics (no custom MachineSchedStrategy) to make 8338e61122f27a8ca4ef0578eaf6dc5242880d2918Andrew Trick /// changes to the generic scheduling policy. 8438e61122f27a8ca4ef0578eaf6dc5242880d2918Andrew Trick virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, 8538e61122f27a8ca4ef0578eaf6dc5242880d2918Andrew Trick MachineInstr *begin, 8638e61122f27a8ca4ef0578eaf6dc5242880d2918Andrew Trick MachineInstr *end, 8738e61122f27a8ca4ef0578eaf6dc5242880d2918Andrew Trick unsigned NumRegionInstrs) const {} 8838e61122f27a8ca4ef0578eaf6dc5242880d2918Andrew Trick 89dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // \brief Perform target specific adjustments to the latency of a schedule 90dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // dependency. 91dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines virtual void adjustSchedDependency(SUnit *def, SUnit *use, 92dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines SDep& dep) const { } 93dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 94fa16354e0370fe884830286923352268b036737dEvan Cheng // enablePostRAScheduler - If the target can benefit from post-regalloc 95fa16354e0370fe884830286923352268b036737dEvan Cheng // scheduling and the specified optimization level meets the requirement 9687d21b92fc42f6b3bd8567a83fc5b5191c1205e5David Goodwin // return true to enable post-register-allocation scheduling. In 9787d21b92fc42f6b3bd8567a83fc5b5191c1205e5David Goodwin // CriticalPathRCs return any register classes that should only be broken 980303d92b73fdc7ee753e2d4c12104640070752f9Andrew Trick // if on the critical path. 994c3715c2e5e17d7216a96ac2baf9720630f04408David Goodwin virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 1000855dee564f80160abf95497475306af38ab7f84David Goodwin AntiDepBreakMode& Mode, 10187d21b92fc42f6b3bd8567a83fc5b5191c1205e5David Goodwin RegClassVector& CriticalPathRCs) const; 102789cb5df9ca61f8a3794a4fbde7cc020fd00a02aBill Wendling 103cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines /// \brief True if the subtarget should run the local reassignment 104cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines /// heuristic of the register allocator. 105cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines /// This heuristic may be compile time intensive, \p OptLevel provides 106cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines /// a finer grain to tune the register allocator. 107cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const; 108cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 109738073c4aa474e27c9d3c991daf593bddce54718Hal Finkel /// \brief Enable use of alias analysis during code generation (during MI 110738073c4aa474e27c9d3c991daf593bddce54718Hal Finkel /// scheduling, DAGCombine, etc.). 111738073c4aa474e27c9d3c991daf593bddce54718Hal Finkel virtual bool useAA() const; 112738073c4aa474e27c9d3c991daf593bddce54718Hal Finkel 113dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines /// \brief Enable the use of the early if conversion pass. 114dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines virtual bool enableEarlyIfConversion() const { return false; } 115dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 116789cb5df9ca61f8a3794a4fbde7cc020fd00a02aBill Wendling /// \brief Reset the features for the subtarget. 117789cb5df9ca61f8a3794a4fbde7cc020fd00a02aBill Wendling virtual void resetSubtargetFeatures(const MachineFunction *MF) { } 118fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman}; 119fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman 120fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman} // End llvm namespace 121fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman 122fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman#endif 123