TargetSubtargetInfo.h revision 789cb5df9ca61f8a3794a4fbde7cc020fd00a02a
15b1b4489cf3a0f56f8be0673fc5cc380a32d277bEvan Cheng//==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==// 2fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman// 3fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman// The LLVM Compiler Infrastructure 4fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman// 57ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// This file is distributed under the University of Illinois Open Source 67ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// License. See LICENSE.TXT for details. 7fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman// 8fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman//===----------------------------------------------------------------------===// 9fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman// 10fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman// This file describes the subtarget options of a Target machine. 11fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman// 12fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman//===----------------------------------------------------------------------===// 13fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman 145b1b4489cf3a0f56f8be0673fc5cc380a32d277bEvan Cheng#ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H 155b1b4489cf3a0f56f8be0673fc5cc380a32d277bEvan Cheng#define LLVM_TARGET_TARGETSUBTARGETINFO_H 16fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman 1794214703d97d8d9dfca88174ffc7e94820a85e62Evan Cheng#include "llvm/MC/MCSubtargetInfo.h" 186c01492ac40bed9529a2f7c8d40da34b8f04365eCraig Topper#include "llvm/Support/CodeGen.h" 19fa16354e0370fe884830286923352268b036737dEvan Cheng 20fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begemannamespace llvm { 21fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman 22789cb5df9ca61f8a3794a4fbde7cc020fd00a02aBill Wendlingclass MachineFunction; 23ee290ba35af88393ba18dd19e6e39d50c7872534Andrew Trickclass MachineInstr; 24710461688bba935f0ad5c75da7fec2ad0f225c00David Goodwinclass SDep; 25dc4bdcdef1c8dd1a28b82deb08df039e5c0ffc5aDavid Goodwinclass SUnit; 26c2e8a7e8d2ab156afaa8ab0d0317dd9ee3db7d30David Goodwinclass TargetRegisterClass; 27ee290ba35af88393ba18dd19e6e39d50c7872534Andrew Trickclass TargetSchedModel; 28c2e8a7e8d2ab156afaa8ab0d0317dd9ee3db7d30David Goodwintemplate <typename T> class SmallVectorImpl; 29710461688bba935f0ad5c75da7fec2ad0f225c00David Goodwin 30fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman//===----------------------------------------------------------------------===// 31fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman/// 325b1b4489cf3a0f56f8be0673fc5cc380a32d277bEvan Cheng/// TargetSubtargetInfo - Generic base class for all target subtargets. All 33fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman/// Target-specific options that control code generation and printing should 345b1b4489cf3a0f56f8be0673fc5cc380a32d277bEvan Cheng/// be exposed through a TargetSubtargetInfo-derived class. 35fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman/// 365b1b4489cf3a0f56f8be0673fc5cc380a32d277bEvan Chengclass TargetSubtargetInfo : public MCSubtargetInfo { 37001d3dc976d7cda8a3dd8c7fd4020b0b96033f4eCraig Topper TargetSubtargetInfo(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION; 38001d3dc976d7cda8a3dd8c7fd4020b0b96033f4eCraig Topper void operator=(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION; 39fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begemanprotected: // Can only create subclasses... 405b1b4489cf3a0f56f8be0673fc5cc380a32d277bEvan Cheng TargetSubtargetInfo(); 41fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begemanpublic: 424c3715c2e5e17d7216a96ac2baf9720630f04408David Goodwin // AntiDepBreakMode - Type of anti-dependence breaking that should 434c3715c2e5e17d7216a96ac2baf9720630f04408David Goodwin // be performed before post-RA scheduling. 444c3715c2e5e17d7216a96ac2baf9720630f04408David Goodwin typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode; 4544d23825d61d530b8d562329ec8fc2d4f843bb8dCraig Topper typedef SmallVectorImpl<const TargetRegisterClass*> RegClassVector; 464c3715c2e5e17d7216a96ac2baf9720630f04408David Goodwin 475b1b4489cf3a0f56f8be0673fc5cc380a32d277bEvan Cheng virtual ~TargetSubtargetInfo(); 488749b61178228ba1fb2668034d79da1b247173d7Dan Gohman 49ee290ba35af88393ba18dd19e6e39d50c7872534Andrew Trick /// Resolve a SchedClass at runtime, where SchedClass identifies an 50ee290ba35af88393ba18dd19e6e39d50c7872534Andrew Trick /// MCSchedClassDesc with the isVariant property. This may return the ID of 51ee290ba35af88393ba18dd19e6e39d50c7872534Andrew Trick /// another variant SchedClass, but repeated invocation must quickly terminate 52ee290ba35af88393ba18dd19e6e39d50c7872534Andrew Trick /// in a nonvariant SchedClass. 53ee290ba35af88393ba18dd19e6e39d50c7872534Andrew Trick virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, 54ee290ba35af88393ba18dd19e6e39d50c7872534Andrew Trick const TargetSchedModel* SchedModel) const { 55ee290ba35af88393ba18dd19e6e39d50c7872534Andrew Trick return 0; 56e127dfd0b175b5a336e61fecaad7fc2aec65d95cAndrew Trick } 57e127dfd0b175b5a336e61fecaad7fc2aec65d95cAndrew Trick 58ad1cc1d1bfc0accd3f1af5c02ac367ff46a4bfdfAndrew Trick /// \brief True if the subtarget should run MachineScheduler after aggressive 59ad1cc1d1bfc0accd3f1af5c02ac367ff46a4bfdfAndrew Trick /// coalescing. 60ad1cc1d1bfc0accd3f1af5c02ac367ff46a4bfdfAndrew Trick /// 61ad1cc1d1bfc0accd3f1af5c02ac367ff46a4bfdfAndrew Trick /// This currently replaces the SelectionDAG scheduler with the "source" order 62ad1cc1d1bfc0accd3f1af5c02ac367ff46a4bfdfAndrew Trick /// scheduler. It does not yet disable the postRA scheduler. 63ad1cc1d1bfc0accd3f1af5c02ac367ff46a4bfdfAndrew Trick virtual bool enableMachineScheduler() const; 64ad1cc1d1bfc0accd3f1af5c02ac367ff46a4bfdfAndrew Trick 65fa16354e0370fe884830286923352268b036737dEvan Cheng // enablePostRAScheduler - If the target can benefit from post-regalloc 66fa16354e0370fe884830286923352268b036737dEvan Cheng // scheduling and the specified optimization level meets the requirement 6787d21b92fc42f6b3bd8567a83fc5b5191c1205e5David Goodwin // return true to enable post-register-allocation scheduling. In 6887d21b92fc42f6b3bd8567a83fc5b5191c1205e5David Goodwin // CriticalPathRCs return any register classes that should only be broken 690303d92b73fdc7ee753e2d4c12104640070752f9Andrew Trick // if on the critical path. 704c3715c2e5e17d7216a96ac2baf9720630f04408David Goodwin virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 710855dee564f80160abf95497475306af38ab7f84David Goodwin AntiDepBreakMode& Mode, 7287d21b92fc42f6b3bd8567a83fc5b5191c1205e5David Goodwin RegClassVector& CriticalPathRCs) const; 73710461688bba935f0ad5c75da7fec2ad0f225c00David Goodwin // adjustSchedDependency - Perform target specific adjustments to 74710461688bba935f0ad5c75da7fec2ad0f225c00David Goodwin // the latency of a schedule dependency. 750303d92b73fdc7ee753e2d4c12104640070752f9Andrew Trick virtual void adjustSchedDependency(SUnit *def, SUnit *use, 760dad89fa94536284d51f60868326294b725a0c61David Goodwin SDep& dep) const { } 77789cb5df9ca61f8a3794a4fbde7cc020fd00a02aBill Wendling 78789cb5df9ca61f8a3794a4fbde7cc020fd00a02aBill Wendling /// \brief Reset the features for the subtarget. 79789cb5df9ca61f8a3794a4fbde7cc020fd00a02aBill Wendling virtual void resetSubtargetFeatures(const MachineFunction *MF) { } 80fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman}; 81fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman 82fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman} // End llvm namespace 83fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman 84fb5792f416089d8d8d0c6ee62c1f41a55d2cf75dNate Begeman#endif 85