DAGCombiner.cpp revision 2330e4d4c4f8008d17f5a38ac0d7b04e139d4131
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: divide by zero is currently left unfolded. do we want to turn this 26// into an undef? 27// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "dagcombine" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/Analysis/AliasAnalysis.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Target/TargetLowering.h" 38#include "llvm/Target/TargetOptions.h" 39#include "llvm/Support/Compiler.h" 40#include "llvm/Support/CommandLine.h" 41#include <algorithm> 42using namespace llvm; 43 44STATISTIC(NodesCombined , "Number of dag nodes combined"); 45STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 46STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 47 48namespace { 49#ifndef NDEBUG 50 static cl::opt<bool> 51 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 52 cl::desc("Pop up a window to show dags before the first " 53 "dag combine pass")); 54 static cl::opt<bool> 55 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 56 cl::desc("Pop up a window to show dags before the second " 57 "dag combine pass")); 58#else 59 static const bool ViewDAGCombine1 = false; 60 static const bool ViewDAGCombine2 = false; 61#endif 62 63 static cl::opt<bool> 64 CombinerAA("combiner-alias-analysis", cl::Hidden, 65 cl::desc("Turn on alias analysis during testing")); 66 67 static cl::opt<bool> 68 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 69 cl::desc("Include global information in alias analysis")); 70 71//------------------------------ DAGCombiner ---------------------------------// 72 73 class VISIBILITY_HIDDEN DAGCombiner { 74 SelectionDAG &DAG; 75 TargetLowering &TLI; 76 bool AfterLegalize; 77 78 // Worklist of all of the nodes that need to be simplified. 79 std::vector<SDNode*> WorkList; 80 81 // AA - Used for DAG load/store alias analysis. 82 AliasAnalysis &AA; 83 84 /// AddUsersToWorkList - When an instruction is simplified, add all users of 85 /// the instruction to the work lists because they might get more simplified 86 /// now. 87 /// 88 void AddUsersToWorkList(SDNode *N) { 89 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 90 UI != UE; ++UI) 91 AddToWorkList(*UI); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 public: 102 /// AddToWorkList - Add to the work list making sure it's instance is at the 103 /// the back (next to be processed.) 104 void AddToWorkList(SDNode *N) { 105 removeFromWorkList(N); 106 WorkList.push_back(N); 107 } 108 109 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 110 bool AddTo = true) { 111 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 112 ++NodesCombined; 113 DOUT << "\nReplacing.1 "; DEBUG(N->dump()); 114 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 115 DOUT << " and " << NumTo-1 << " other values\n"; 116 std::vector<SDNode*> NowDead; 117 DAG.ReplaceAllUsesWith(N, To, &NowDead); 118 119 if (AddTo) { 120 // Push the new nodes and any users onto the worklist 121 for (unsigned i = 0, e = NumTo; i != e; ++i) { 122 AddToWorkList(To[i].Val); 123 AddUsersToWorkList(To[i].Val); 124 } 125 } 126 127 // Nodes can be reintroduced into the worklist. Make sure we do not 128 // process a node that has been replaced. 129 removeFromWorkList(N); 130 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 131 removeFromWorkList(NowDead[i]); 132 133 // Finally, since the node is now dead, remove it from the graph. 134 DAG.DeleteNode(N); 135 return SDOperand(N, 0); 136 } 137 138 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 139 return CombineTo(N, &Res, 1, AddTo); 140 } 141 142 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 143 bool AddTo = true) { 144 SDOperand To[] = { Res0, Res1 }; 145 return CombineTo(N, To, 2, AddTo); 146 } 147 private: 148 149 /// SimplifyDemandedBits - Check the specified integer node value to see if 150 /// it can be simplified or if things it uses can be simplified by bit 151 /// propagation. If so, return true. 152 bool SimplifyDemandedBits(SDOperand Op) { 153 TargetLowering::TargetLoweringOpt TLO(DAG); 154 uint64_t KnownZero, KnownOne; 155 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 156 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 157 return false; 158 159 // Revisit the node. 160 AddToWorkList(Op.Val); 161 162 // Replace the old value with the new one. 163 ++NodesCombined; 164 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump()); 165 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 166 DOUT << '\n'; 167 168 std::vector<SDNode*> NowDead; 169 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 170 171 // Push the new node and any (possibly new) users onto the worklist. 172 AddToWorkList(TLO.New.Val); 173 AddUsersToWorkList(TLO.New.Val); 174 175 // Nodes can end up on the worklist more than once. Make sure we do 176 // not process a node that has been replaced. 177 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 178 removeFromWorkList(NowDead[i]); 179 180 // Finally, if the node is now dead, remove it from the graph. The node 181 // may not be dead if the replacement process recursively simplified to 182 // something else needing this node. 183 if (TLO.Old.Val->use_empty()) { 184 removeFromWorkList(TLO.Old.Val); 185 186 // If the operands of this node are only used by the node, they will now 187 // be dead. Make sure to visit them first to delete dead nodes early. 188 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 189 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 190 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 191 192 DAG.DeleteNode(TLO.Old.Val); 193 } 194 return true; 195 } 196 197 bool CombineToPreIndexedLoadStore(SDNode *N); 198 bool CombineToPostIndexedLoadStore(SDNode *N); 199 200 201 /// visit - call the node-specific routine that knows how to fold each 202 /// particular type of node. 203 SDOperand visit(SDNode *N); 204 205 // Visitation implementation - Implement dag node combining for different 206 // node types. The semantics are as follows: 207 // Return Value: 208 // SDOperand.Val == 0 - No change was made 209 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 210 // otherwise - N should be replaced by the returned Operand. 211 // 212 SDOperand visitTokenFactor(SDNode *N); 213 SDOperand visitADD(SDNode *N); 214 SDOperand visitSUB(SDNode *N); 215 SDOperand visitADDC(SDNode *N); 216 SDOperand visitADDE(SDNode *N); 217 SDOperand visitMUL(SDNode *N); 218 SDOperand visitSDIV(SDNode *N); 219 SDOperand visitUDIV(SDNode *N); 220 SDOperand visitSREM(SDNode *N); 221 SDOperand visitUREM(SDNode *N); 222 SDOperand visitMULHU(SDNode *N); 223 SDOperand visitMULHS(SDNode *N); 224 SDOperand visitAND(SDNode *N); 225 SDOperand visitOR(SDNode *N); 226 SDOperand visitXOR(SDNode *N); 227 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp); 228 SDOperand visitSHL(SDNode *N); 229 SDOperand visitSRA(SDNode *N); 230 SDOperand visitSRL(SDNode *N); 231 SDOperand visitCTLZ(SDNode *N); 232 SDOperand visitCTTZ(SDNode *N); 233 SDOperand visitCTPOP(SDNode *N); 234 SDOperand visitSELECT(SDNode *N); 235 SDOperand visitSELECT_CC(SDNode *N); 236 SDOperand visitSETCC(SDNode *N); 237 SDOperand visitSIGN_EXTEND(SDNode *N); 238 SDOperand visitZERO_EXTEND(SDNode *N); 239 SDOperand visitANY_EXTEND(SDNode *N); 240 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 241 SDOperand visitTRUNCATE(SDNode *N); 242 SDOperand visitBIT_CONVERT(SDNode *N); 243 SDOperand visitVBIT_CONVERT(SDNode *N); 244 SDOperand visitFADD(SDNode *N); 245 SDOperand visitFSUB(SDNode *N); 246 SDOperand visitFMUL(SDNode *N); 247 SDOperand visitFDIV(SDNode *N); 248 SDOperand visitFREM(SDNode *N); 249 SDOperand visitFCOPYSIGN(SDNode *N); 250 SDOperand visitSINT_TO_FP(SDNode *N); 251 SDOperand visitUINT_TO_FP(SDNode *N); 252 SDOperand visitFP_TO_SINT(SDNode *N); 253 SDOperand visitFP_TO_UINT(SDNode *N); 254 SDOperand visitFP_ROUND(SDNode *N); 255 SDOperand visitFP_ROUND_INREG(SDNode *N); 256 SDOperand visitFP_EXTEND(SDNode *N); 257 SDOperand visitFNEG(SDNode *N); 258 SDOperand visitFABS(SDNode *N); 259 SDOperand visitBRCOND(SDNode *N); 260 SDOperand visitBR_CC(SDNode *N); 261 SDOperand visitLOAD(SDNode *N); 262 SDOperand visitSTORE(SDNode *N); 263 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 264 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N); 265 SDOperand visitVBUILD_VECTOR(SDNode *N); 266 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 267 SDOperand visitVVECTOR_SHUFFLE(SDNode *N); 268 269 SDOperand XformToShuffleWithZero(SDNode *N); 270 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 271 272 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 273 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 274 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 275 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 276 SDOperand N3, ISD::CondCode CC, 277 bool NotExtCompare = false); 278 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 279 ISD::CondCode Cond, bool foldBooleans = true); 280 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType); 281 SDOperand BuildSDIV(SDNode *N); 282 SDOperand BuildUDIV(SDNode *N); 283 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 284 SDOperand ReduceLoadWidth(SDNode *N); 285 286 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 287 /// looking for aliasing nodes and adding them to the Aliases vector. 288 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 289 SmallVector<SDOperand, 8> &Aliases); 290 291 /// isAlias - Return true if there is any possibility that the two addresses 292 /// overlap. 293 bool isAlias(SDOperand Ptr1, int64_t Size1, 294 const Value *SrcValue1, int SrcValueOffset1, 295 SDOperand Ptr2, int64_t Size2, 296 const Value *SrcValue2, int SrcValueOffset2); 297 298 /// FindAliasInfo - Extracts the relevant alias information from the memory 299 /// node. Returns true if the operand was a load. 300 bool FindAliasInfo(SDNode *N, 301 SDOperand &Ptr, int64_t &Size, 302 const Value *&SrcValue, int &SrcValueOffset); 303 304 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 305 /// looking for a better chain (aliasing node.) 306 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 307 308public: 309 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 310 : DAG(D), 311 TLI(D.getTargetLoweringInfo()), 312 AfterLegalize(false), 313 AA(A) {} 314 315 /// Run - runs the dag combiner on all nodes in the work list 316 void Run(bool RunningAfterLegalize); 317 }; 318} 319 320//===----------------------------------------------------------------------===// 321// TargetLowering::DAGCombinerInfo implementation 322//===----------------------------------------------------------------------===// 323 324void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 325 ((DAGCombiner*)DC)->AddToWorkList(N); 326} 327 328SDOperand TargetLowering::DAGCombinerInfo:: 329CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 330 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 331} 332 333SDOperand TargetLowering::DAGCombinerInfo:: 334CombineTo(SDNode *N, SDOperand Res) { 335 return ((DAGCombiner*)DC)->CombineTo(N, Res); 336} 337 338 339SDOperand TargetLowering::DAGCombinerInfo:: 340CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 341 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 342} 343 344 345 346 347//===----------------------------------------------------------------------===// 348 349 350// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 351// that selects between the values 1 and 0, making it equivalent to a setcc. 352// Also, set the incoming LHS, RHS, and CC references to the appropriate 353// nodes based on the type of node we are checking. This simplifies life a 354// bit for the callers. 355static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 356 SDOperand &CC) { 357 if (N.getOpcode() == ISD::SETCC) { 358 LHS = N.getOperand(0); 359 RHS = N.getOperand(1); 360 CC = N.getOperand(2); 361 return true; 362 } 363 if (N.getOpcode() == ISD::SELECT_CC && 364 N.getOperand(2).getOpcode() == ISD::Constant && 365 N.getOperand(3).getOpcode() == ISD::Constant && 366 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 367 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 368 LHS = N.getOperand(0); 369 RHS = N.getOperand(1); 370 CC = N.getOperand(4); 371 return true; 372 } 373 return false; 374} 375 376// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 377// one use. If this is true, it allows the users to invert the operation for 378// free when it is profitable to do so. 379static bool isOneUseSetCC(SDOperand N) { 380 SDOperand N0, N1, N2; 381 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 382 return true; 383 return false; 384} 385 386SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 387 MVT::ValueType VT = N0.getValueType(); 388 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 389 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 390 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 391 if (isa<ConstantSDNode>(N1)) { 392 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 393 AddToWorkList(OpNode.Val); 394 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 395 } else if (N0.hasOneUse()) { 396 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 397 AddToWorkList(OpNode.Val); 398 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 399 } 400 } 401 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 402 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 403 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 404 if (isa<ConstantSDNode>(N0)) { 405 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 406 AddToWorkList(OpNode.Val); 407 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 408 } else if (N1.hasOneUse()) { 409 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 410 AddToWorkList(OpNode.Val); 411 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 412 } 413 } 414 return SDOperand(); 415} 416 417void DAGCombiner::Run(bool RunningAfterLegalize) { 418 // set the instance variable, so that the various visit routines may use it. 419 AfterLegalize = RunningAfterLegalize; 420 421 // Add all the dag nodes to the worklist. 422 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 423 E = DAG.allnodes_end(); I != E; ++I) 424 WorkList.push_back(I); 425 426 // Create a dummy node (which is not added to allnodes), that adds a reference 427 // to the root node, preventing it from being deleted, and tracking any 428 // changes of the root. 429 HandleSDNode Dummy(DAG.getRoot()); 430 431 // The root of the dag may dangle to deleted nodes until the dag combiner is 432 // done. Set it to null to avoid confusion. 433 DAG.setRoot(SDOperand()); 434 435 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 436 TargetLowering::DAGCombinerInfo 437 DagCombineInfo(DAG, !RunningAfterLegalize, false, this); 438 439 // while the worklist isn't empty, inspect the node on the end of it and 440 // try and combine it. 441 while (!WorkList.empty()) { 442 SDNode *N = WorkList.back(); 443 WorkList.pop_back(); 444 445 // If N has no uses, it is dead. Make sure to revisit all N's operands once 446 // N is deleted from the DAG, since they too may now be dead or may have a 447 // reduced number of uses, allowing other xforms. 448 if (N->use_empty() && N != &Dummy) { 449 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 450 AddToWorkList(N->getOperand(i).Val); 451 452 DAG.DeleteNode(N); 453 continue; 454 } 455 456 SDOperand RV = visit(N); 457 458 // If nothing happened, try a target-specific DAG combine. 459 if (RV.Val == 0) { 460 assert(N->getOpcode() != ISD::DELETED_NODE && 461 "Node was deleted but visit returned NULL!"); 462 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 463 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 464 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 465 } 466 467 if (RV.Val) { 468 ++NodesCombined; 469 // If we get back the same node we passed in, rather than a new node or 470 // zero, we know that the node must have defined multiple values and 471 // CombineTo was used. Since CombineTo takes care of the worklist 472 // mechanics for us, we have no work to do in this case. 473 if (RV.Val != N) { 474 assert(N->getOpcode() != ISD::DELETED_NODE && 475 RV.Val->getOpcode() != ISD::DELETED_NODE && 476 "Node was deleted but visit returned new node!"); 477 478 DOUT << "\nReplacing.3 "; DEBUG(N->dump()); 479 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 480 DOUT << '\n'; 481 std::vector<SDNode*> NowDead; 482 if (N->getNumValues() == RV.Val->getNumValues()) 483 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead); 484 else { 485 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch"); 486 SDOperand OpV = RV; 487 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 488 } 489 490 // Push the new node and any users onto the worklist 491 AddToWorkList(RV.Val); 492 AddUsersToWorkList(RV.Val); 493 494 // Nodes can be reintroduced into the worklist. Make sure we do not 495 // process a node that has been replaced. 496 removeFromWorkList(N); 497 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 498 removeFromWorkList(NowDead[i]); 499 500 // Finally, since the node is now dead, remove it from the graph. 501 DAG.DeleteNode(N); 502 } 503 } 504 } 505 506 // If the root changed (e.g. it was a dead load, update the root). 507 DAG.setRoot(Dummy.getValue()); 508} 509 510SDOperand DAGCombiner::visit(SDNode *N) { 511 switch(N->getOpcode()) { 512 default: break; 513 case ISD::TokenFactor: return visitTokenFactor(N); 514 case ISD::ADD: return visitADD(N); 515 case ISD::SUB: return visitSUB(N); 516 case ISD::ADDC: return visitADDC(N); 517 case ISD::ADDE: return visitADDE(N); 518 case ISD::MUL: return visitMUL(N); 519 case ISD::SDIV: return visitSDIV(N); 520 case ISD::UDIV: return visitUDIV(N); 521 case ISD::SREM: return visitSREM(N); 522 case ISD::UREM: return visitUREM(N); 523 case ISD::MULHU: return visitMULHU(N); 524 case ISD::MULHS: return visitMULHS(N); 525 case ISD::AND: return visitAND(N); 526 case ISD::OR: return visitOR(N); 527 case ISD::XOR: return visitXOR(N); 528 case ISD::SHL: return visitSHL(N); 529 case ISD::SRA: return visitSRA(N); 530 case ISD::SRL: return visitSRL(N); 531 case ISD::CTLZ: return visitCTLZ(N); 532 case ISD::CTTZ: return visitCTTZ(N); 533 case ISD::CTPOP: return visitCTPOP(N); 534 case ISD::SELECT: return visitSELECT(N); 535 case ISD::SELECT_CC: return visitSELECT_CC(N); 536 case ISD::SETCC: return visitSETCC(N); 537 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 538 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 539 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 540 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 541 case ISD::TRUNCATE: return visitTRUNCATE(N); 542 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 543 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N); 544 case ISD::FADD: return visitFADD(N); 545 case ISD::FSUB: return visitFSUB(N); 546 case ISD::FMUL: return visitFMUL(N); 547 case ISD::FDIV: return visitFDIV(N); 548 case ISD::FREM: return visitFREM(N); 549 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 550 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 551 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 552 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 553 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 554 case ISD::FP_ROUND: return visitFP_ROUND(N); 555 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 556 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 557 case ISD::FNEG: return visitFNEG(N); 558 case ISD::FABS: return visitFABS(N); 559 case ISD::BRCOND: return visitBRCOND(N); 560 case ISD::BR_CC: return visitBR_CC(N); 561 case ISD::LOAD: return visitLOAD(N); 562 case ISD::STORE: return visitSTORE(N); 563 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 564 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N); 565 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N); 566 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 567 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N); 568 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD); 569 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB); 570 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL); 571 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV); 572 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV); 573 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND); 574 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR); 575 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR); 576 } 577 return SDOperand(); 578} 579 580/// getInputChainForNode - Given a node, return its input chain if it has one, 581/// otherwise return a null sd operand. 582static SDOperand getInputChainForNode(SDNode *N) { 583 if (unsigned NumOps = N->getNumOperands()) { 584 if (N->getOperand(0).getValueType() == MVT::Other) 585 return N->getOperand(0); 586 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 587 return N->getOperand(NumOps-1); 588 for (unsigned i = 1; i < NumOps-1; ++i) 589 if (N->getOperand(i).getValueType() == MVT::Other) 590 return N->getOperand(i); 591 } 592 return SDOperand(0, 0); 593} 594 595SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 596 // If N has two operands, where one has an input chain equal to the other, 597 // the 'other' chain is redundant. 598 if (N->getNumOperands() == 2) { 599 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 600 return N->getOperand(0); 601 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 602 return N->getOperand(1); 603 } 604 605 606 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 607 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 608 bool Changed = false; // If we should replace this token factor. 609 610 // Start out with this token factor. 611 TFs.push_back(N); 612 613 // Iterate through token factors. The TFs grows when new token factors are 614 // encountered. 615 for (unsigned i = 0; i < TFs.size(); ++i) { 616 SDNode *TF = TFs[i]; 617 618 // Check each of the operands. 619 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 620 SDOperand Op = TF->getOperand(i); 621 622 switch (Op.getOpcode()) { 623 case ISD::EntryToken: 624 // Entry tokens don't need to be added to the list. They are 625 // rededundant. 626 Changed = true; 627 break; 628 629 case ISD::TokenFactor: 630 if ((CombinerAA || Op.hasOneUse()) && 631 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 632 // Queue up for processing. 633 TFs.push_back(Op.Val); 634 // Clean up in case the token factor is removed. 635 AddToWorkList(Op.Val); 636 Changed = true; 637 break; 638 } 639 // Fall thru 640 641 default: 642 // Only add if not there prior. 643 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end()) 644 Ops.push_back(Op); 645 break; 646 } 647 } 648 } 649 650 SDOperand Result; 651 652 // If we've change things around then replace token factor. 653 if (Changed) { 654 if (Ops.size() == 0) { 655 // The entry token is the only possible outcome. 656 Result = DAG.getEntryNode(); 657 } else { 658 // New and improved token factor. 659 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 660 } 661 662 // Don't add users to work list. 663 return CombineTo(N, Result, false); 664 } 665 666 return Result; 667} 668 669static 670SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 671 MVT::ValueType VT = N0.getValueType(); 672 SDOperand N00 = N0.getOperand(0); 673 SDOperand N01 = N0.getOperand(1); 674 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 675 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 676 isa<ConstantSDNode>(N00.getOperand(1))) { 677 N0 = DAG.getNode(ISD::ADD, VT, 678 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 679 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 680 return DAG.getNode(ISD::ADD, VT, N0, N1); 681 } 682 return SDOperand(); 683} 684 685SDOperand DAGCombiner::visitADD(SDNode *N) { 686 SDOperand N0 = N->getOperand(0); 687 SDOperand N1 = N->getOperand(1); 688 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 689 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 690 MVT::ValueType VT = N0.getValueType(); 691 692 // fold (add c1, c2) -> c1+c2 693 if (N0C && N1C) 694 return DAG.getNode(ISD::ADD, VT, N0, N1); 695 // canonicalize constant to RHS 696 if (N0C && !N1C) 697 return DAG.getNode(ISD::ADD, VT, N1, N0); 698 // fold (add x, 0) -> x 699 if (N1C && N1C->isNullValue()) 700 return N0; 701 // fold ((c1-A)+c2) -> (c1+c2)-A 702 if (N1C && N0.getOpcode() == ISD::SUB) 703 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 704 return DAG.getNode(ISD::SUB, VT, 705 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 706 N0.getOperand(1)); 707 // reassociate add 708 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 709 if (RADD.Val != 0) 710 return RADD; 711 // fold ((0-A) + B) -> B-A 712 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 713 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 714 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 715 // fold (A + (0-B)) -> A-B 716 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 717 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 718 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 719 // fold (A+(B-A)) -> B 720 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 721 return N1.getOperand(0); 722 723 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 724 return SDOperand(N, 0); 725 726 // fold (a+b) -> (a|b) iff a and b share no bits. 727 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 728 uint64_t LHSZero, LHSOne; 729 uint64_t RHSZero, RHSOne; 730 uint64_t Mask = MVT::getIntVTBitMask(VT); 731 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 732 if (LHSZero) { 733 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 734 735 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 736 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 737 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 738 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 739 return DAG.getNode(ISD::OR, VT, N0, N1); 740 } 741 } 742 743 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 744 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 745 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 746 if (Result.Val) return Result; 747 } 748 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 749 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 750 if (Result.Val) return Result; 751 } 752 753 return SDOperand(); 754} 755 756SDOperand DAGCombiner::visitADDC(SDNode *N) { 757 SDOperand N0 = N->getOperand(0); 758 SDOperand N1 = N->getOperand(1); 759 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 760 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 761 MVT::ValueType VT = N0.getValueType(); 762 763 // If the flag result is dead, turn this into an ADD. 764 if (N->hasNUsesOfValue(0, 1)) 765 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 766 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 767 768 // canonicalize constant to RHS. 769 if (N0C && !N1C) { 770 SDOperand Ops[] = { N1, N0 }; 771 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 772 } 773 774 // fold (addc x, 0) -> x + no carry out 775 if (N1C && N1C->isNullValue()) 776 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 777 778 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 779 uint64_t LHSZero, LHSOne; 780 uint64_t RHSZero, RHSOne; 781 uint64_t Mask = MVT::getIntVTBitMask(VT); 782 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 783 if (LHSZero) { 784 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 785 786 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 787 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 788 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 789 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 790 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 791 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 792 } 793 794 return SDOperand(); 795} 796 797SDOperand DAGCombiner::visitADDE(SDNode *N) { 798 SDOperand N0 = N->getOperand(0); 799 SDOperand N1 = N->getOperand(1); 800 SDOperand CarryIn = N->getOperand(2); 801 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 802 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 803 //MVT::ValueType VT = N0.getValueType(); 804 805 // canonicalize constant to RHS 806 if (N0C && !N1C) { 807 SDOperand Ops[] = { N1, N0, CarryIn }; 808 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 809 } 810 811 // fold (adde x, y, false) -> (addc x, y) 812 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 813 SDOperand Ops[] = { N1, N0 }; 814 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 815 } 816 817 return SDOperand(); 818} 819 820 821 822SDOperand DAGCombiner::visitSUB(SDNode *N) { 823 SDOperand N0 = N->getOperand(0); 824 SDOperand N1 = N->getOperand(1); 825 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 826 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 827 MVT::ValueType VT = N0.getValueType(); 828 829 // fold (sub x, x) -> 0 830 if (N0 == N1) 831 return DAG.getConstant(0, N->getValueType(0)); 832 // fold (sub c1, c2) -> c1-c2 833 if (N0C && N1C) 834 return DAG.getNode(ISD::SUB, VT, N0, N1); 835 // fold (sub x, c) -> (add x, -c) 836 if (N1C) 837 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 838 // fold (A+B)-A -> B 839 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 840 return N0.getOperand(1); 841 // fold (A+B)-B -> A 842 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 843 return N0.getOperand(0); 844 return SDOperand(); 845} 846 847SDOperand DAGCombiner::visitMUL(SDNode *N) { 848 SDOperand N0 = N->getOperand(0); 849 SDOperand N1 = N->getOperand(1); 850 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 851 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 852 MVT::ValueType VT = N0.getValueType(); 853 854 // fold (mul c1, c2) -> c1*c2 855 if (N0C && N1C) 856 return DAG.getNode(ISD::MUL, VT, N0, N1); 857 // canonicalize constant to RHS 858 if (N0C && !N1C) 859 return DAG.getNode(ISD::MUL, VT, N1, N0); 860 // fold (mul x, 0) -> 0 861 if (N1C && N1C->isNullValue()) 862 return N1; 863 // fold (mul x, -1) -> 0-x 864 if (N1C && N1C->isAllOnesValue()) 865 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 866 // fold (mul x, (1 << c)) -> x << c 867 if (N1C && isPowerOf2_64(N1C->getValue())) 868 return DAG.getNode(ISD::SHL, VT, N0, 869 DAG.getConstant(Log2_64(N1C->getValue()), 870 TLI.getShiftAmountTy())); 871 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 872 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 873 // FIXME: If the input is something that is easily negated (e.g. a 874 // single-use add), we should put the negate there. 875 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 876 DAG.getNode(ISD::SHL, VT, N0, 877 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 878 TLI.getShiftAmountTy()))); 879 } 880 881 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 882 if (N1C && N0.getOpcode() == ISD::SHL && 883 isa<ConstantSDNode>(N0.getOperand(1))) { 884 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 885 AddToWorkList(C3.Val); 886 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 887 } 888 889 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 890 // use. 891 { 892 SDOperand Sh(0,0), Y(0,0); 893 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 894 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 895 N0.Val->hasOneUse()) { 896 Sh = N0; Y = N1; 897 } else if (N1.getOpcode() == ISD::SHL && 898 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 899 Sh = N1; Y = N0; 900 } 901 if (Sh.Val) { 902 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 903 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 904 } 905 } 906 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 907 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 908 isa<ConstantSDNode>(N0.getOperand(1))) { 909 return DAG.getNode(ISD::ADD, VT, 910 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 911 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 912 } 913 914 // reassociate mul 915 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 916 if (RMUL.Val != 0) 917 return RMUL; 918 return SDOperand(); 919} 920 921SDOperand DAGCombiner::visitSDIV(SDNode *N) { 922 SDOperand N0 = N->getOperand(0); 923 SDOperand N1 = N->getOperand(1); 924 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 925 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 926 MVT::ValueType VT = N->getValueType(0); 927 928 // fold (sdiv c1, c2) -> c1/c2 929 if (N0C && N1C && !N1C->isNullValue()) 930 return DAG.getNode(ISD::SDIV, VT, N0, N1); 931 // fold (sdiv X, 1) -> X 932 if (N1C && N1C->getSignExtended() == 1LL) 933 return N0; 934 // fold (sdiv X, -1) -> 0-X 935 if (N1C && N1C->isAllOnesValue()) 936 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 937 // If we know the sign bits of both operands are zero, strength reduce to a 938 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 939 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 940 if (TLI.MaskedValueIsZero(N1, SignBit) && 941 TLI.MaskedValueIsZero(N0, SignBit)) 942 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 943 // fold (sdiv X, pow2) -> simple ops after legalize 944 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 945 (isPowerOf2_64(N1C->getSignExtended()) || 946 isPowerOf2_64(-N1C->getSignExtended()))) { 947 // If dividing by powers of two is cheap, then don't perform the following 948 // fold. 949 if (TLI.isPow2DivCheap()) 950 return SDOperand(); 951 int64_t pow2 = N1C->getSignExtended(); 952 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 953 unsigned lg2 = Log2_64(abs2); 954 // Splat the sign bit into the register 955 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 956 DAG.getConstant(MVT::getSizeInBits(VT)-1, 957 TLI.getShiftAmountTy())); 958 AddToWorkList(SGN.Val); 959 // Add (N0 < 0) ? abs2 - 1 : 0; 960 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 961 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 962 TLI.getShiftAmountTy())); 963 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 964 AddToWorkList(SRL.Val); 965 AddToWorkList(ADD.Val); // Divide by pow2 966 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 967 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 968 // If we're dividing by a positive value, we're done. Otherwise, we must 969 // negate the result. 970 if (pow2 > 0) 971 return SRA; 972 AddToWorkList(SRA.Val); 973 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 974 } 975 // if integer divide is expensive and we satisfy the requirements, emit an 976 // alternate sequence. 977 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 978 !TLI.isIntDivCheap()) { 979 SDOperand Op = BuildSDIV(N); 980 if (Op.Val) return Op; 981 } 982 return SDOperand(); 983} 984 985SDOperand DAGCombiner::visitUDIV(SDNode *N) { 986 SDOperand N0 = N->getOperand(0); 987 SDOperand N1 = N->getOperand(1); 988 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 989 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 990 MVT::ValueType VT = N->getValueType(0); 991 992 // fold (udiv c1, c2) -> c1/c2 993 if (N0C && N1C && !N1C->isNullValue()) 994 return DAG.getNode(ISD::UDIV, VT, N0, N1); 995 // fold (udiv x, (1 << c)) -> x >>u c 996 if (N1C && isPowerOf2_64(N1C->getValue())) 997 return DAG.getNode(ISD::SRL, VT, N0, 998 DAG.getConstant(Log2_64(N1C->getValue()), 999 TLI.getShiftAmountTy())); 1000 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1001 if (N1.getOpcode() == ISD::SHL) { 1002 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1003 if (isPowerOf2_64(SHC->getValue())) { 1004 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1005 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1006 DAG.getConstant(Log2_64(SHC->getValue()), 1007 ADDVT)); 1008 AddToWorkList(Add.Val); 1009 return DAG.getNode(ISD::SRL, VT, N0, Add); 1010 } 1011 } 1012 } 1013 // fold (udiv x, c) -> alternate 1014 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1015 SDOperand Op = BuildUDIV(N); 1016 if (Op.Val) return Op; 1017 } 1018 return SDOperand(); 1019} 1020 1021SDOperand DAGCombiner::visitSREM(SDNode *N) { 1022 SDOperand N0 = N->getOperand(0); 1023 SDOperand N1 = N->getOperand(1); 1024 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1025 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1026 MVT::ValueType VT = N->getValueType(0); 1027 1028 // fold (srem c1, c2) -> c1%c2 1029 if (N0C && N1C && !N1C->isNullValue()) 1030 return DAG.getNode(ISD::SREM, VT, N0, N1); 1031 // If we know the sign bits of both operands are zero, strength reduce to a 1032 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1033 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1034 if (TLI.MaskedValueIsZero(N1, SignBit) && 1035 TLI.MaskedValueIsZero(N0, SignBit)) 1036 return DAG.getNode(ISD::UREM, VT, N0, N1); 1037 1038 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1039 // the remainder operation. 1040 if (N1C && !N1C->isNullValue()) { 1041 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1042 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1043 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1044 AddToWorkList(Div.Val); 1045 AddToWorkList(Mul.Val); 1046 return Sub; 1047 } 1048 1049 return SDOperand(); 1050} 1051 1052SDOperand DAGCombiner::visitUREM(SDNode *N) { 1053 SDOperand N0 = N->getOperand(0); 1054 SDOperand N1 = N->getOperand(1); 1055 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1056 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1057 MVT::ValueType VT = N->getValueType(0); 1058 1059 // fold (urem c1, c2) -> c1%c2 1060 if (N0C && N1C && !N1C->isNullValue()) 1061 return DAG.getNode(ISD::UREM, VT, N0, N1); 1062 // fold (urem x, pow2) -> (and x, pow2-1) 1063 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1064 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1065 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1066 if (N1.getOpcode() == ISD::SHL) { 1067 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1068 if (isPowerOf2_64(SHC->getValue())) { 1069 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1070 AddToWorkList(Add.Val); 1071 return DAG.getNode(ISD::AND, VT, N0, Add); 1072 } 1073 } 1074 } 1075 1076 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1077 // the remainder operation. 1078 if (N1C && !N1C->isNullValue()) { 1079 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1080 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1081 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1082 AddToWorkList(Div.Val); 1083 AddToWorkList(Mul.Val); 1084 return Sub; 1085 } 1086 1087 return SDOperand(); 1088} 1089 1090SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1091 SDOperand N0 = N->getOperand(0); 1092 SDOperand N1 = N->getOperand(1); 1093 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1094 1095 // fold (mulhs x, 0) -> 0 1096 if (N1C && N1C->isNullValue()) 1097 return N1; 1098 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1099 if (N1C && N1C->getValue() == 1) 1100 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1101 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1102 TLI.getShiftAmountTy())); 1103 return SDOperand(); 1104} 1105 1106SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1107 SDOperand N0 = N->getOperand(0); 1108 SDOperand N1 = N->getOperand(1); 1109 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1110 1111 // fold (mulhu x, 0) -> 0 1112 if (N1C && N1C->isNullValue()) 1113 return N1; 1114 // fold (mulhu x, 1) -> 0 1115 if (N1C && N1C->getValue() == 1) 1116 return DAG.getConstant(0, N0.getValueType()); 1117 return SDOperand(); 1118} 1119 1120/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1121/// two operands of the same opcode, try to simplify it. 1122SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1123 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1124 MVT::ValueType VT = N0.getValueType(); 1125 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1126 1127 // For each of OP in AND/OR/XOR: 1128 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1129 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1130 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1131 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1132 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1133 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1134 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1135 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1136 N0.getOperand(0).getValueType(), 1137 N0.getOperand(0), N1.getOperand(0)); 1138 AddToWorkList(ORNode.Val); 1139 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1140 } 1141 1142 // For each of OP in SHL/SRL/SRA/AND... 1143 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1144 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1145 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1146 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1147 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1148 N0.getOperand(1) == N1.getOperand(1)) { 1149 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1150 N0.getOperand(0).getValueType(), 1151 N0.getOperand(0), N1.getOperand(0)); 1152 AddToWorkList(ORNode.Val); 1153 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1154 } 1155 1156 return SDOperand(); 1157} 1158 1159SDOperand DAGCombiner::visitAND(SDNode *N) { 1160 SDOperand N0 = N->getOperand(0); 1161 SDOperand N1 = N->getOperand(1); 1162 SDOperand LL, LR, RL, RR, CC0, CC1; 1163 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1164 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1165 MVT::ValueType VT = N1.getValueType(); 1166 1167 // fold (and c1, c2) -> c1&c2 1168 if (N0C && N1C) 1169 return DAG.getNode(ISD::AND, VT, N0, N1); 1170 // canonicalize constant to RHS 1171 if (N0C && !N1C) 1172 return DAG.getNode(ISD::AND, VT, N1, N0); 1173 // fold (and x, -1) -> x 1174 if (N1C && N1C->isAllOnesValue()) 1175 return N0; 1176 // if (and x, c) is known to be zero, return 0 1177 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1178 return DAG.getConstant(0, VT); 1179 // reassociate and 1180 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1181 if (RAND.Val != 0) 1182 return RAND; 1183 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1184 if (N1C && N0.getOpcode() == ISD::OR) 1185 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1186 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1187 return N1; 1188 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1189 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1190 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1191 if (TLI.MaskedValueIsZero(N0.getOperand(0), 1192 ~N1C->getValue() & InMask)) { 1193 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1194 N0.getOperand(0)); 1195 1196 // Replace uses of the AND with uses of the Zero extend node. 1197 CombineTo(N, Zext); 1198 1199 // We actually want to replace all uses of the any_extend with the 1200 // zero_extend, to avoid duplicating things. This will later cause this 1201 // AND to be folded. 1202 CombineTo(N0.Val, Zext); 1203 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1204 } 1205 } 1206 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1207 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1208 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1209 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1210 1211 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1212 MVT::isInteger(LL.getValueType())) { 1213 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1214 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1215 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1216 AddToWorkList(ORNode.Val); 1217 return DAG.getSetCC(VT, ORNode, LR, Op1); 1218 } 1219 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1220 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1221 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1222 AddToWorkList(ANDNode.Val); 1223 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1224 } 1225 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1226 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1227 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1228 AddToWorkList(ORNode.Val); 1229 return DAG.getSetCC(VT, ORNode, LR, Op1); 1230 } 1231 } 1232 // canonicalize equivalent to ll == rl 1233 if (LL == RR && LR == RL) { 1234 Op1 = ISD::getSetCCSwappedOperands(Op1); 1235 std::swap(RL, RR); 1236 } 1237 if (LL == RL && LR == RR) { 1238 bool isInteger = MVT::isInteger(LL.getValueType()); 1239 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1240 if (Result != ISD::SETCC_INVALID) 1241 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1242 } 1243 } 1244 1245 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1246 if (N0.getOpcode() == N1.getOpcode()) { 1247 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1248 if (Tmp.Val) return Tmp; 1249 } 1250 1251 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1252 // fold (and (sra)) -> (and (srl)) when possible. 1253 if (!MVT::isVector(VT) && 1254 SimplifyDemandedBits(SDOperand(N, 0))) 1255 return SDOperand(N, 0); 1256 // fold (zext_inreg (extload x)) -> (zextload x) 1257 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1258 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1259 MVT::ValueType EVT = LN0->getLoadedVT(); 1260 // If we zero all the possible extended bits, then we can turn this into 1261 // a zextload if we are running before legalize or the operation is legal. 1262 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1263 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1264 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1265 LN0->getBasePtr(), LN0->getSrcValue(), 1266 LN0->getSrcValueOffset(), EVT, 1267 LN0->isVolatile(), 1268 LN0->getAlignment()); 1269 AddToWorkList(N); 1270 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1271 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1272 } 1273 } 1274 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1275 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1276 N0.hasOneUse()) { 1277 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1278 MVT::ValueType EVT = LN0->getLoadedVT(); 1279 // If we zero all the possible extended bits, then we can turn this into 1280 // a zextload if we are running before legalize or the operation is legal. 1281 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1282 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1283 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1284 LN0->getBasePtr(), LN0->getSrcValue(), 1285 LN0->getSrcValueOffset(), EVT, 1286 LN0->isVolatile(), 1287 LN0->getAlignment()); 1288 AddToWorkList(N); 1289 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1290 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1291 } 1292 } 1293 1294 // fold (and (load x), 255) -> (zextload x, i8) 1295 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1296 if (N1C && N0.getOpcode() == ISD::LOAD) { 1297 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1298 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1299 LN0->getAddressingMode() == ISD::UNINDEXED && 1300 N0.hasOneUse()) { 1301 MVT::ValueType EVT, LoadedVT; 1302 if (N1C->getValue() == 255) 1303 EVT = MVT::i8; 1304 else if (N1C->getValue() == 65535) 1305 EVT = MVT::i16; 1306 else if (N1C->getValue() == ~0U) 1307 EVT = MVT::i32; 1308 else 1309 EVT = MVT::Other; 1310 1311 LoadedVT = LN0->getLoadedVT(); 1312 if (EVT != MVT::Other && LoadedVT > EVT && 1313 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1314 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1315 // For big endian targets, we need to add an offset to the pointer to 1316 // load the correct bytes. For little endian systems, we merely need to 1317 // read fewer bytes from the same pointer. 1318 unsigned PtrOff = 1319 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1320 SDOperand NewPtr = LN0->getBasePtr(); 1321 if (!TLI.isLittleEndian()) 1322 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1323 DAG.getConstant(PtrOff, PtrType)); 1324 AddToWorkList(NewPtr.Val); 1325 SDOperand Load = 1326 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1327 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1328 LN0->isVolatile(), LN0->getAlignment()); 1329 AddToWorkList(N); 1330 CombineTo(N0.Val, Load, Load.getValue(1)); 1331 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1332 } 1333 } 1334 } 1335 1336 return SDOperand(); 1337} 1338 1339SDOperand DAGCombiner::visitOR(SDNode *N) { 1340 SDOperand N0 = N->getOperand(0); 1341 SDOperand N1 = N->getOperand(1); 1342 SDOperand LL, LR, RL, RR, CC0, CC1; 1343 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1344 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1345 MVT::ValueType VT = N1.getValueType(); 1346 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1347 1348 // fold (or c1, c2) -> c1|c2 1349 if (N0C && N1C) 1350 return DAG.getNode(ISD::OR, VT, N0, N1); 1351 // canonicalize constant to RHS 1352 if (N0C && !N1C) 1353 return DAG.getNode(ISD::OR, VT, N1, N0); 1354 // fold (or x, 0) -> x 1355 if (N1C && N1C->isNullValue()) 1356 return N0; 1357 // fold (or x, -1) -> -1 1358 if (N1C && N1C->isAllOnesValue()) 1359 return N1; 1360 // fold (or x, c) -> c iff (x & ~c) == 0 1361 if (N1C && 1362 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1363 return N1; 1364 // reassociate or 1365 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1366 if (ROR.Val != 0) 1367 return ROR; 1368 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1369 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1370 isa<ConstantSDNode>(N0.getOperand(1))) { 1371 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1372 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1373 N1), 1374 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1375 } 1376 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1377 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1378 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1379 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1380 1381 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1382 MVT::isInteger(LL.getValueType())) { 1383 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1384 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1385 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1386 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1387 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1388 AddToWorkList(ORNode.Val); 1389 return DAG.getSetCC(VT, ORNode, LR, Op1); 1390 } 1391 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1392 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1393 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1394 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1395 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1396 AddToWorkList(ANDNode.Val); 1397 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1398 } 1399 } 1400 // canonicalize equivalent to ll == rl 1401 if (LL == RR && LR == RL) { 1402 Op1 = ISD::getSetCCSwappedOperands(Op1); 1403 std::swap(RL, RR); 1404 } 1405 if (LL == RL && LR == RR) { 1406 bool isInteger = MVT::isInteger(LL.getValueType()); 1407 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1408 if (Result != ISD::SETCC_INVALID) 1409 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1410 } 1411 } 1412 1413 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1414 if (N0.getOpcode() == N1.getOpcode()) { 1415 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1416 if (Tmp.Val) return Tmp; 1417 } 1418 1419 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1420 if (N0.getOpcode() == ISD::AND && 1421 N1.getOpcode() == ISD::AND && 1422 N0.getOperand(1).getOpcode() == ISD::Constant && 1423 N1.getOperand(1).getOpcode() == ISD::Constant && 1424 // Don't increase # computations. 1425 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1426 // We can only do this xform if we know that bits from X that are set in C2 1427 // but not in C1 are already zero. Likewise for Y. 1428 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1429 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1430 1431 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1432 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1433 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1434 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1435 } 1436 } 1437 1438 1439 // See if this is some rotate idiom. 1440 if (SDNode *Rot = MatchRotate(N0, N1)) 1441 return SDOperand(Rot, 0); 1442 1443 return SDOperand(); 1444} 1445 1446 1447/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1448static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1449 if (Op.getOpcode() == ISD::AND) { 1450 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1451 Mask = Op.getOperand(1); 1452 Op = Op.getOperand(0); 1453 } else { 1454 return false; 1455 } 1456 } 1457 1458 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1459 Shift = Op; 1460 return true; 1461 } 1462 return false; 1463} 1464 1465 1466// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1467// idioms for rotate, and if the target supports rotation instructions, generate 1468// a rot[lr]. 1469SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1470 // Must be a legal type. Expanded an promoted things won't work with rotates. 1471 MVT::ValueType VT = LHS.getValueType(); 1472 if (!TLI.isTypeLegal(VT)) return 0; 1473 1474 // The target must have at least one rotate flavor. 1475 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1476 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1477 if (!HasROTL && !HasROTR) return 0; 1478 1479 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1480 SDOperand LHSShift; // The shift. 1481 SDOperand LHSMask; // AND value if any. 1482 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1483 return 0; // Not part of a rotate. 1484 1485 SDOperand RHSShift; // The shift. 1486 SDOperand RHSMask; // AND value if any. 1487 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1488 return 0; // Not part of a rotate. 1489 1490 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1491 return 0; // Not shifting the same value. 1492 1493 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1494 return 0; // Shifts must disagree. 1495 1496 // Canonicalize shl to left side in a shl/srl pair. 1497 if (RHSShift.getOpcode() == ISD::SHL) { 1498 std::swap(LHS, RHS); 1499 std::swap(LHSShift, RHSShift); 1500 std::swap(LHSMask , RHSMask ); 1501 } 1502 1503 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1504 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1505 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1506 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1507 1508 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1509 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1510 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1511 RHSShiftAmt.getOpcode() == ISD::Constant) { 1512 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1513 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1514 if ((LShVal + RShVal) != OpSizeInBits) 1515 return 0; 1516 1517 SDOperand Rot; 1518 if (HasROTL) 1519 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1520 else 1521 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1522 1523 // If there is an AND of either shifted operand, apply it to the result. 1524 if (LHSMask.Val || RHSMask.Val) { 1525 uint64_t Mask = MVT::getIntVTBitMask(VT); 1526 1527 if (LHSMask.Val) { 1528 uint64_t RHSBits = (1ULL << LShVal)-1; 1529 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1530 } 1531 if (RHSMask.Val) { 1532 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1533 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1534 } 1535 1536 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1537 } 1538 1539 return Rot.Val; 1540 } 1541 1542 // If there is a mask here, and we have a variable shift, we can't be sure 1543 // that we're masking out the right stuff. 1544 if (LHSMask.Val || RHSMask.Val) 1545 return 0; 1546 1547 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1548 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1549 if (RHSShiftAmt.getOpcode() == ISD::SUB && 1550 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 1551 if (ConstantSDNode *SUBC = 1552 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 1553 if (SUBC->getValue() == OpSizeInBits) 1554 if (HasROTL) 1555 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1556 else 1557 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1558 } 1559 } 1560 1561 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1562 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1563 if (LHSShiftAmt.getOpcode() == ISD::SUB && 1564 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 1565 if (ConstantSDNode *SUBC = 1566 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 1567 if (SUBC->getValue() == OpSizeInBits) 1568 if (HasROTL) 1569 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1570 else 1571 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1572 } 1573 } 1574 1575 // Look for sign/zext/any-extended cases: 1576 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1577 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1578 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 1579 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1580 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1581 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 1582 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 1583 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 1584 if (RExtOp0.getOpcode() == ISD::SUB && 1585 RExtOp0.getOperand(1) == LExtOp0) { 1586 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1587 // (rotr x, y) 1588 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1589 // (rotl x, (sub 32, y)) 1590 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 1591 if (SUBC->getValue() == OpSizeInBits) { 1592 if (HasROTL) 1593 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1594 else 1595 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1596 } 1597 } 1598 } else if (LExtOp0.getOpcode() == ISD::SUB && 1599 RExtOp0 == LExtOp0.getOperand(1)) { 1600 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 1601 // (rotl x, y) 1602 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 1603 // (rotr x, (sub 32, y)) 1604 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 1605 if (SUBC->getValue() == OpSizeInBits) { 1606 if (HasROTL) 1607 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 1608 else 1609 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1610 } 1611 } 1612 } 1613 } 1614 1615 return 0; 1616} 1617 1618 1619SDOperand DAGCombiner::visitXOR(SDNode *N) { 1620 SDOperand N0 = N->getOperand(0); 1621 SDOperand N1 = N->getOperand(1); 1622 SDOperand LHS, RHS, CC; 1623 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1624 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1625 MVT::ValueType VT = N0.getValueType(); 1626 1627 // fold (xor c1, c2) -> c1^c2 1628 if (N0C && N1C) 1629 return DAG.getNode(ISD::XOR, VT, N0, N1); 1630 // canonicalize constant to RHS 1631 if (N0C && !N1C) 1632 return DAG.getNode(ISD::XOR, VT, N1, N0); 1633 // fold (xor x, 0) -> x 1634 if (N1C && N1C->isNullValue()) 1635 return N0; 1636 // reassociate xor 1637 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1638 if (RXOR.Val != 0) 1639 return RXOR; 1640 // fold !(x cc y) -> (x !cc y) 1641 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1642 bool isInt = MVT::isInteger(LHS.getValueType()); 1643 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1644 isInt); 1645 if (N0.getOpcode() == ISD::SETCC) 1646 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1647 if (N0.getOpcode() == ISD::SELECT_CC) 1648 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1649 assert(0 && "Unhandled SetCC Equivalent!"); 1650 abort(); 1651 } 1652 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1653 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 1654 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1655 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1656 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1657 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1658 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1659 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1660 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1661 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1662 } 1663 } 1664 // fold !(x or y) -> (!x and !y) iff x or y are constants 1665 if (N1C && N1C->isAllOnesValue() && 1666 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1667 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1668 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1669 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1670 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1671 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1672 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1673 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1674 } 1675 } 1676 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1677 if (N1C && N0.getOpcode() == ISD::XOR) { 1678 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1679 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1680 if (N00C) 1681 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1682 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1683 if (N01C) 1684 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1685 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1686 } 1687 // fold (xor x, x) -> 0 1688 if (N0 == N1) { 1689 if (!MVT::isVector(VT)) { 1690 return DAG.getConstant(0, VT); 1691 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1692 // Produce a vector of zeros. 1693 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT)); 1694 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 1695 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1696 } 1697 } 1698 1699 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 1700 if (N0.getOpcode() == N1.getOpcode()) { 1701 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1702 if (Tmp.Val) return Tmp; 1703 } 1704 1705 // Simplify the expression using non-local knowledge. 1706 if (!MVT::isVector(VT) && 1707 SimplifyDemandedBits(SDOperand(N, 0))) 1708 return SDOperand(N, 0); 1709 1710 return SDOperand(); 1711} 1712 1713SDOperand DAGCombiner::visitSHL(SDNode *N) { 1714 SDOperand N0 = N->getOperand(0); 1715 SDOperand N1 = N->getOperand(1); 1716 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1717 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1718 MVT::ValueType VT = N0.getValueType(); 1719 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1720 1721 // fold (shl c1, c2) -> c1<<c2 1722 if (N0C && N1C) 1723 return DAG.getNode(ISD::SHL, VT, N0, N1); 1724 // fold (shl 0, x) -> 0 1725 if (N0C && N0C->isNullValue()) 1726 return N0; 1727 // fold (shl x, c >= size(x)) -> undef 1728 if (N1C && N1C->getValue() >= OpSizeInBits) 1729 return DAG.getNode(ISD::UNDEF, VT); 1730 // fold (shl x, 0) -> x 1731 if (N1C && N1C->isNullValue()) 1732 return N0; 1733 // if (shl x, c) is known to be zero, return 0 1734 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1735 return DAG.getConstant(0, VT); 1736 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 1737 return SDOperand(N, 0); 1738 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1739 if (N1C && N0.getOpcode() == ISD::SHL && 1740 N0.getOperand(1).getOpcode() == ISD::Constant) { 1741 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1742 uint64_t c2 = N1C->getValue(); 1743 if (c1 + c2 > OpSizeInBits) 1744 return DAG.getConstant(0, VT); 1745 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1746 DAG.getConstant(c1 + c2, N1.getValueType())); 1747 } 1748 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1749 // (srl (and x, -1 << c1), c1-c2) 1750 if (N1C && N0.getOpcode() == ISD::SRL && 1751 N0.getOperand(1).getOpcode() == ISD::Constant) { 1752 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1753 uint64_t c2 = N1C->getValue(); 1754 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1755 DAG.getConstant(~0ULL << c1, VT)); 1756 if (c2 > c1) 1757 return DAG.getNode(ISD::SHL, VT, Mask, 1758 DAG.getConstant(c2-c1, N1.getValueType())); 1759 else 1760 return DAG.getNode(ISD::SRL, VT, Mask, 1761 DAG.getConstant(c1-c2, N1.getValueType())); 1762 } 1763 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1764 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1765 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1766 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1767 return SDOperand(); 1768} 1769 1770SDOperand DAGCombiner::visitSRA(SDNode *N) { 1771 SDOperand N0 = N->getOperand(0); 1772 SDOperand N1 = N->getOperand(1); 1773 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1774 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1775 MVT::ValueType VT = N0.getValueType(); 1776 1777 // fold (sra c1, c2) -> c1>>c2 1778 if (N0C && N1C) 1779 return DAG.getNode(ISD::SRA, VT, N0, N1); 1780 // fold (sra 0, x) -> 0 1781 if (N0C && N0C->isNullValue()) 1782 return N0; 1783 // fold (sra -1, x) -> -1 1784 if (N0C && N0C->isAllOnesValue()) 1785 return N0; 1786 // fold (sra x, c >= size(x)) -> undef 1787 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 1788 return DAG.getNode(ISD::UNDEF, VT); 1789 // fold (sra x, 0) -> x 1790 if (N1C && N1C->isNullValue()) 1791 return N0; 1792 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 1793 // sext_inreg. 1794 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 1795 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 1796 MVT::ValueType EVT; 1797 switch (LowBits) { 1798 default: EVT = MVT::Other; break; 1799 case 1: EVT = MVT::i1; break; 1800 case 8: EVT = MVT::i8; break; 1801 case 16: EVT = MVT::i16; break; 1802 case 32: EVT = MVT::i32; break; 1803 } 1804 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 1805 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1806 DAG.getValueType(EVT)); 1807 } 1808 1809 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 1810 if (N1C && N0.getOpcode() == ISD::SRA) { 1811 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1812 unsigned Sum = N1C->getValue() + C1->getValue(); 1813 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 1814 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 1815 DAG.getConstant(Sum, N1C->getValueType(0))); 1816 } 1817 } 1818 1819 // Simplify, based on bits shifted out of the LHS. 1820 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 1821 return SDOperand(N, 0); 1822 1823 1824 // If the sign bit is known to be zero, switch this to a SRL. 1825 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 1826 return DAG.getNode(ISD::SRL, VT, N0, N1); 1827 return SDOperand(); 1828} 1829 1830SDOperand DAGCombiner::visitSRL(SDNode *N) { 1831 SDOperand N0 = N->getOperand(0); 1832 SDOperand N1 = N->getOperand(1); 1833 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1834 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1835 MVT::ValueType VT = N0.getValueType(); 1836 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1837 1838 // fold (srl c1, c2) -> c1 >>u c2 1839 if (N0C && N1C) 1840 return DAG.getNode(ISD::SRL, VT, N0, N1); 1841 // fold (srl 0, x) -> 0 1842 if (N0C && N0C->isNullValue()) 1843 return N0; 1844 // fold (srl x, c >= size(x)) -> undef 1845 if (N1C && N1C->getValue() >= OpSizeInBits) 1846 return DAG.getNode(ISD::UNDEF, VT); 1847 // fold (srl x, 0) -> x 1848 if (N1C && N1C->isNullValue()) 1849 return N0; 1850 // if (srl x, c) is known to be zero, return 0 1851 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1852 return DAG.getConstant(0, VT); 1853 1854 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1855 if (N1C && N0.getOpcode() == ISD::SRL && 1856 N0.getOperand(1).getOpcode() == ISD::Constant) { 1857 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1858 uint64_t c2 = N1C->getValue(); 1859 if (c1 + c2 > OpSizeInBits) 1860 return DAG.getConstant(0, VT); 1861 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1862 DAG.getConstant(c1 + c2, N1.getValueType())); 1863 } 1864 1865 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 1866 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1867 // Shifting in all undef bits? 1868 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 1869 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 1870 return DAG.getNode(ISD::UNDEF, VT); 1871 1872 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 1873 AddToWorkList(SmallShift.Val); 1874 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 1875 } 1876 1877 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 1878 // bit, which is unmodified by sra. 1879 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 1880 if (N0.getOpcode() == ISD::SRA) 1881 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 1882 } 1883 1884 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 1885 if (N1C && N0.getOpcode() == ISD::CTLZ && 1886 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 1887 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 1888 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 1889 1890 // If any of the input bits are KnownOne, then the input couldn't be all 1891 // zeros, thus the result of the srl will always be zero. 1892 if (KnownOne) return DAG.getConstant(0, VT); 1893 1894 // If all of the bits input the to ctlz node are known to be zero, then 1895 // the result of the ctlz is "32" and the result of the shift is one. 1896 uint64_t UnknownBits = ~KnownZero & Mask; 1897 if (UnknownBits == 0) return DAG.getConstant(1, VT); 1898 1899 // Otherwise, check to see if there is exactly one bit input to the ctlz. 1900 if ((UnknownBits & (UnknownBits-1)) == 0) { 1901 // Okay, we know that only that the single bit specified by UnknownBits 1902 // could be set on input to the CTLZ node. If this bit is set, the SRL 1903 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 1904 // to an SRL,XOR pair, which is likely to simplify more. 1905 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 1906 SDOperand Op = N0.getOperand(0); 1907 if (ShAmt) { 1908 Op = DAG.getNode(ISD::SRL, VT, Op, 1909 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 1910 AddToWorkList(Op.Val); 1911 } 1912 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 1913 } 1914 } 1915 1916 // fold operands of srl based on knowledge that the low bits are not 1917 // demanded. 1918 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 1919 return SDOperand(N, 0); 1920 1921 return SDOperand(); 1922} 1923 1924SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1925 SDOperand N0 = N->getOperand(0); 1926 MVT::ValueType VT = N->getValueType(0); 1927 1928 // fold (ctlz c1) -> c2 1929 if (isa<ConstantSDNode>(N0)) 1930 return DAG.getNode(ISD::CTLZ, VT, N0); 1931 return SDOperand(); 1932} 1933 1934SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1935 SDOperand N0 = N->getOperand(0); 1936 MVT::ValueType VT = N->getValueType(0); 1937 1938 // fold (cttz c1) -> c2 1939 if (isa<ConstantSDNode>(N0)) 1940 return DAG.getNode(ISD::CTTZ, VT, N0); 1941 return SDOperand(); 1942} 1943 1944SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1945 SDOperand N0 = N->getOperand(0); 1946 MVT::ValueType VT = N->getValueType(0); 1947 1948 // fold (ctpop c1) -> c2 1949 if (isa<ConstantSDNode>(N0)) 1950 return DAG.getNode(ISD::CTPOP, VT, N0); 1951 return SDOperand(); 1952} 1953 1954SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1955 SDOperand N0 = N->getOperand(0); 1956 SDOperand N1 = N->getOperand(1); 1957 SDOperand N2 = N->getOperand(2); 1958 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1959 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1960 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1961 MVT::ValueType VT = N->getValueType(0); 1962 1963 // fold select C, X, X -> X 1964 if (N1 == N2) 1965 return N1; 1966 // fold select true, X, Y -> X 1967 if (N0C && !N0C->isNullValue()) 1968 return N1; 1969 // fold select false, X, Y -> Y 1970 if (N0C && N0C->isNullValue()) 1971 return N2; 1972 // fold select C, 1, X -> C | X 1973 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1974 return DAG.getNode(ISD::OR, VT, N0, N2); 1975 // fold select C, 0, X -> ~C & X 1976 // FIXME: this should check for C type == X type, not i1? 1977 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1978 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1979 AddToWorkList(XORNode.Val); 1980 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1981 } 1982 // fold select C, X, 1 -> ~C | X 1983 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1984 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1985 AddToWorkList(XORNode.Val); 1986 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1987 } 1988 // fold select C, X, 0 -> C & X 1989 // FIXME: this should check for C type == X type, not i1? 1990 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1991 return DAG.getNode(ISD::AND, VT, N0, N1); 1992 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1993 if (MVT::i1 == VT && N0 == N1) 1994 return DAG.getNode(ISD::OR, VT, N0, N2); 1995 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1996 if (MVT::i1 == VT && N0 == N2) 1997 return DAG.getNode(ISD::AND, VT, N0, N1); 1998 1999 // If we can fold this based on the true/false value, do so. 2000 if (SimplifySelectOps(N, N1, N2)) 2001 return SDOperand(N, 0); // Don't revisit N. 2002 2003 // fold selects based on a setcc into other things, such as min/max/abs 2004 if (N0.getOpcode() == ISD::SETCC) 2005 // FIXME: 2006 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2007 // having to say they don't support SELECT_CC on every type the DAG knows 2008 // about, since there is no way to mark an opcode illegal at all value types 2009 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2010 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2011 N1, N2, N0.getOperand(2)); 2012 else 2013 return SimplifySelect(N0, N1, N2); 2014 return SDOperand(); 2015} 2016 2017SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2018 SDOperand N0 = N->getOperand(0); 2019 SDOperand N1 = N->getOperand(1); 2020 SDOperand N2 = N->getOperand(2); 2021 SDOperand N3 = N->getOperand(3); 2022 SDOperand N4 = N->getOperand(4); 2023 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2024 2025 // fold select_cc lhs, rhs, x, x, cc -> x 2026 if (N2 == N3) 2027 return N2; 2028 2029 // Determine if the condition we're dealing with is constant 2030 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2031 if (SCC.Val) AddToWorkList(SCC.Val); 2032 2033 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2034 if (SCCC->getValue()) 2035 return N2; // cond always true -> true val 2036 else 2037 return N3; // cond always false -> false val 2038 } 2039 2040 // Fold to a simpler select_cc 2041 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2042 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2043 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2044 SCC.getOperand(2)); 2045 2046 // If we can fold this based on the true/false value, do so. 2047 if (SimplifySelectOps(N, N2, N3)) 2048 return SDOperand(N, 0); // Don't revisit N. 2049 2050 // fold select_cc into other things, such as min/max/abs 2051 return SimplifySelectCC(N0, N1, N2, N3, CC); 2052} 2053 2054SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2055 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2056 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2057} 2058 2059SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2060 SDOperand N0 = N->getOperand(0); 2061 MVT::ValueType VT = N->getValueType(0); 2062 2063 // fold (sext c1) -> c1 2064 if (isa<ConstantSDNode>(N0)) 2065 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2066 2067 // fold (sext (sext x)) -> (sext x) 2068 // fold (sext (aext x)) -> (sext x) 2069 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2070 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2071 2072 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2073 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2074 if (N0.getOpcode() == ISD::TRUNCATE) { 2075 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2076 if (NarrowLoad.Val) { 2077 if (NarrowLoad.Val != N0.Val) 2078 CombineTo(N0.Val, NarrowLoad); 2079 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2080 } 2081 } 2082 2083 // See if the value being truncated is already sign extended. If so, just 2084 // eliminate the trunc/sext pair. 2085 if (N0.getOpcode() == ISD::TRUNCATE) { 2086 SDOperand Op = N0.getOperand(0); 2087 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2088 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2089 unsigned DestBits = MVT::getSizeInBits(VT); 2090 unsigned NumSignBits = TLI.ComputeNumSignBits(Op); 2091 2092 if (OpBits == DestBits) { 2093 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2094 // bits, it is already ready. 2095 if (NumSignBits > DestBits-MidBits) 2096 return Op; 2097 } else if (OpBits < DestBits) { 2098 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2099 // bits, just sext from i32. 2100 if (NumSignBits > OpBits-MidBits) 2101 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2102 } else { 2103 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2104 // bits, just truncate to i32. 2105 if (NumSignBits > OpBits-MidBits) 2106 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2107 } 2108 2109 // fold (sext (truncate x)) -> (sextinreg x). 2110 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2111 N0.getValueType())) { 2112 if (Op.getValueType() < VT) 2113 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2114 else if (Op.getValueType() > VT) 2115 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2116 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2117 DAG.getValueType(N0.getValueType())); 2118 } 2119 } 2120 2121 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2122 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2123 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2124 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2125 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2126 LN0->getBasePtr(), LN0->getSrcValue(), 2127 LN0->getSrcValueOffset(), 2128 N0.getValueType(), 2129 LN0->isVolatile()); 2130 CombineTo(N, ExtLoad); 2131 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2132 ExtLoad.getValue(1)); 2133 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2134 } 2135 2136 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2137 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2138 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2139 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2140 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2141 MVT::ValueType EVT = LN0->getLoadedVT(); 2142 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2143 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2144 LN0->getBasePtr(), LN0->getSrcValue(), 2145 LN0->getSrcValueOffset(), EVT, 2146 LN0->isVolatile(), 2147 LN0->getAlignment()); 2148 CombineTo(N, ExtLoad); 2149 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2150 ExtLoad.getValue(1)); 2151 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2152 } 2153 } 2154 2155 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2156 if (N0.getOpcode() == ISD::SETCC) { 2157 SDOperand SCC = 2158 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2159 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2160 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2161 if (SCC.Val) return SCC; 2162 } 2163 2164 return SDOperand(); 2165} 2166 2167SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2168 SDOperand N0 = N->getOperand(0); 2169 MVT::ValueType VT = N->getValueType(0); 2170 2171 // fold (zext c1) -> c1 2172 if (isa<ConstantSDNode>(N0)) 2173 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2174 // fold (zext (zext x)) -> (zext x) 2175 // fold (zext (aext x)) -> (zext x) 2176 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2177 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2178 2179 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2180 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2181 if (N0.getOpcode() == ISD::TRUNCATE) { 2182 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2183 if (NarrowLoad.Val) { 2184 if (NarrowLoad.Val != N0.Val) 2185 CombineTo(N0.Val, NarrowLoad); 2186 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2187 } 2188 } 2189 2190 // fold (zext (truncate x)) -> (and x, mask) 2191 if (N0.getOpcode() == ISD::TRUNCATE && 2192 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2193 SDOperand Op = N0.getOperand(0); 2194 if (Op.getValueType() < VT) { 2195 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2196 } else if (Op.getValueType() > VT) { 2197 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2198 } 2199 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2200 } 2201 2202 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2203 if (N0.getOpcode() == ISD::AND && 2204 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2205 N0.getOperand(1).getOpcode() == ISD::Constant) { 2206 SDOperand X = N0.getOperand(0).getOperand(0); 2207 if (X.getValueType() < VT) { 2208 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2209 } else if (X.getValueType() > VT) { 2210 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2211 } 2212 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2213 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2214 } 2215 2216 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2217 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2218 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2219 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2220 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2221 LN0->getBasePtr(), LN0->getSrcValue(), 2222 LN0->getSrcValueOffset(), 2223 N0.getValueType(), 2224 LN0->isVolatile(), 2225 LN0->getAlignment()); 2226 CombineTo(N, ExtLoad); 2227 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2228 ExtLoad.getValue(1)); 2229 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2230 } 2231 2232 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2233 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2234 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2235 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2236 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2237 MVT::ValueType EVT = LN0->getLoadedVT(); 2238 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2239 LN0->getBasePtr(), LN0->getSrcValue(), 2240 LN0->getSrcValueOffset(), EVT, 2241 LN0->isVolatile(), 2242 LN0->getAlignment()); 2243 CombineTo(N, ExtLoad); 2244 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2245 ExtLoad.getValue(1)); 2246 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2247 } 2248 2249 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2250 if (N0.getOpcode() == ISD::SETCC) { 2251 SDOperand SCC = 2252 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2253 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2254 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2255 if (SCC.Val) return SCC; 2256 } 2257 2258 return SDOperand(); 2259} 2260 2261SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2262 SDOperand N0 = N->getOperand(0); 2263 MVT::ValueType VT = N->getValueType(0); 2264 2265 // fold (aext c1) -> c1 2266 if (isa<ConstantSDNode>(N0)) 2267 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2268 // fold (aext (aext x)) -> (aext x) 2269 // fold (aext (zext x)) -> (zext x) 2270 // fold (aext (sext x)) -> (sext x) 2271 if (N0.getOpcode() == ISD::ANY_EXTEND || 2272 N0.getOpcode() == ISD::ZERO_EXTEND || 2273 N0.getOpcode() == ISD::SIGN_EXTEND) 2274 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2275 2276 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2277 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 2278 if (N0.getOpcode() == ISD::TRUNCATE) { 2279 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2280 if (NarrowLoad.Val) { 2281 if (NarrowLoad.Val != N0.Val) 2282 CombineTo(N0.Val, NarrowLoad); 2283 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 2284 } 2285 } 2286 2287 // fold (aext (truncate x)) 2288 if (N0.getOpcode() == ISD::TRUNCATE) { 2289 SDOperand TruncOp = N0.getOperand(0); 2290 if (TruncOp.getValueType() == VT) 2291 return TruncOp; // x iff x size == zext size. 2292 if (TruncOp.getValueType() > VT) 2293 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2294 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2295 } 2296 2297 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2298 if (N0.getOpcode() == ISD::AND && 2299 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2300 N0.getOperand(1).getOpcode() == ISD::Constant) { 2301 SDOperand X = N0.getOperand(0).getOperand(0); 2302 if (X.getValueType() < VT) { 2303 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2304 } else if (X.getValueType() > VT) { 2305 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2306 } 2307 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2308 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2309 } 2310 2311 // fold (aext (load x)) -> (aext (truncate (extload x))) 2312 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2313 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2314 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2315 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2316 LN0->getBasePtr(), LN0->getSrcValue(), 2317 LN0->getSrcValueOffset(), 2318 N0.getValueType(), 2319 LN0->isVolatile(), 2320 LN0->getAlignment()); 2321 CombineTo(N, ExtLoad); 2322 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2323 ExtLoad.getValue(1)); 2324 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2325 } 2326 2327 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2328 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2329 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2330 if (N0.getOpcode() == ISD::LOAD && 2331 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2332 N0.hasOneUse()) { 2333 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2334 MVT::ValueType EVT = LN0->getLoadedVT(); 2335 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2336 LN0->getChain(), LN0->getBasePtr(), 2337 LN0->getSrcValue(), 2338 LN0->getSrcValueOffset(), EVT, 2339 LN0->isVolatile(), 2340 LN0->getAlignment()); 2341 CombineTo(N, ExtLoad); 2342 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2343 ExtLoad.getValue(1)); 2344 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2345 } 2346 2347 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2348 if (N0.getOpcode() == ISD::SETCC) { 2349 SDOperand SCC = 2350 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2351 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2352 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2353 if (SCC.Val) 2354 return SCC; 2355 } 2356 2357 return SDOperand(); 2358} 2359 2360/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 2361/// bits and then truncated to a narrower type and where N is a multiple 2362/// of number of bits of the narrower type, transform it to a narrower load 2363/// from address + N / num of bits of new type. If the result is to be 2364/// extended, also fold the extension to form a extending load. 2365SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 2366 unsigned Opc = N->getOpcode(); 2367 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 2368 SDOperand N0 = N->getOperand(0); 2369 MVT::ValueType VT = N->getValueType(0); 2370 MVT::ValueType EVT = N->getValueType(0); 2371 2372 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 2373 // extended to VT. 2374 if (Opc == ISD::SIGN_EXTEND_INREG) { 2375 ExtType = ISD::SEXTLOAD; 2376 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2377 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 2378 return SDOperand(); 2379 } 2380 2381 unsigned EVTBits = MVT::getSizeInBits(EVT); 2382 unsigned ShAmt = 0; 2383 bool CombineSRL = false; 2384 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 2385 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2386 ShAmt = N01->getValue(); 2387 // Is the shift amount a multiple of size of VT? 2388 if ((ShAmt & (EVTBits-1)) == 0) { 2389 N0 = N0.getOperand(0); 2390 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 2391 return SDOperand(); 2392 CombineSRL = true; 2393 } 2394 } 2395 } 2396 2397 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2398 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 2399 // zero extended form: by shrinking the load, we lose track of the fact 2400 // that it is already zero extended. 2401 // FIXME: This should be reevaluated. 2402 VT != MVT::i1) { 2403 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 2404 "Cannot truncate to larger type!"); 2405 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2406 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 2407 // For big endian targets, we need to adjust the offset to the pointer to 2408 // load the correct bytes. 2409 if (!TLI.isLittleEndian()) 2410 ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits; 2411 uint64_t PtrOff = ShAmt / 8; 2412 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 2413 DAG.getConstant(PtrOff, PtrType)); 2414 AddToWorkList(NewPtr.Val); 2415 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 2416 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 2417 LN0->getSrcValue(), LN0->getSrcValueOffset(), 2418 LN0->isVolatile(), LN0->getAlignment()) 2419 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 2420 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 2421 LN0->isVolatile(), LN0->getAlignment()); 2422 AddToWorkList(N); 2423 if (CombineSRL) { 2424 std::vector<SDNode*> NowDead; 2425 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead); 2426 CombineTo(N->getOperand(0).Val, Load); 2427 } else 2428 CombineTo(N0.Val, Load, Load.getValue(1)); 2429 if (ShAmt) { 2430 if (Opc == ISD::SIGN_EXTEND_INREG) 2431 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 2432 else 2433 return DAG.getNode(Opc, VT, Load); 2434 } 2435 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2436 } 2437 2438 return SDOperand(); 2439} 2440 2441 2442SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 2443 SDOperand N0 = N->getOperand(0); 2444 SDOperand N1 = N->getOperand(1); 2445 MVT::ValueType VT = N->getValueType(0); 2446 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 2447 unsigned EVTBits = MVT::getSizeInBits(EVT); 2448 2449 // fold (sext_in_reg c1) -> c1 2450 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 2451 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 2452 2453 // If the input is already sign extended, just drop the extension. 2454 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 2455 return N0; 2456 2457 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 2458 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2459 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 2460 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 2461 } 2462 2463 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 2464 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 2465 return DAG.getZeroExtendInReg(N0, EVT); 2466 2467 // fold operands of sext_in_reg based on knowledge that the top bits are not 2468 // demanded. 2469 if (SimplifyDemandedBits(SDOperand(N, 0))) 2470 return SDOperand(N, 0); 2471 2472 // fold (sext_in_reg (load x)) -> (smaller sextload x) 2473 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 2474 SDOperand NarrowLoad = ReduceLoadWidth(N); 2475 if (NarrowLoad.Val) 2476 return NarrowLoad; 2477 2478 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 2479 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 2480 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 2481 if (N0.getOpcode() == ISD::SRL) { 2482 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2483 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 2484 // We can turn this into an SRA iff the input to the SRL is already sign 2485 // extended enough. 2486 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0)); 2487 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 2488 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 2489 } 2490 } 2491 2492 // fold (sext_inreg (extload x)) -> (sextload x) 2493 if (ISD::isEXTLoad(N0.Val) && 2494 ISD::isUNINDEXEDLoad(N0.Val) && 2495 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2496 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2497 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2498 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2499 LN0->getBasePtr(), LN0->getSrcValue(), 2500 LN0->getSrcValueOffset(), EVT, 2501 LN0->isVolatile(), 2502 LN0->getAlignment()); 2503 CombineTo(N, ExtLoad); 2504 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2505 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2506 } 2507 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 2508 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2509 N0.hasOneUse() && 2510 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2511 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2512 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2513 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2514 LN0->getBasePtr(), LN0->getSrcValue(), 2515 LN0->getSrcValueOffset(), EVT, 2516 LN0->isVolatile(), 2517 LN0->getAlignment()); 2518 CombineTo(N, ExtLoad); 2519 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2520 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2521 } 2522 return SDOperand(); 2523} 2524 2525SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 2526 SDOperand N0 = N->getOperand(0); 2527 MVT::ValueType VT = N->getValueType(0); 2528 2529 // noop truncate 2530 if (N0.getValueType() == N->getValueType(0)) 2531 return N0; 2532 // fold (truncate c1) -> c1 2533 if (isa<ConstantSDNode>(N0)) 2534 return DAG.getNode(ISD::TRUNCATE, VT, N0); 2535 // fold (truncate (truncate x)) -> (truncate x) 2536 if (N0.getOpcode() == ISD::TRUNCATE) 2537 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2538 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 2539 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 2540 N0.getOpcode() == ISD::ANY_EXTEND) { 2541 if (N0.getOperand(0).getValueType() < VT) 2542 // if the source is smaller than the dest, we still need an extend 2543 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2544 else if (N0.getOperand(0).getValueType() > VT) 2545 // if the source is larger than the dest, than we just need the truncate 2546 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2547 else 2548 // if the source and dest are the same type, we can drop both the extend 2549 // and the truncate 2550 return N0.getOperand(0); 2551 } 2552 2553 // fold (truncate (load x)) -> (smaller load x) 2554 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 2555 return ReduceLoadWidth(N); 2556} 2557 2558SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 2559 SDOperand N0 = N->getOperand(0); 2560 MVT::ValueType VT = N->getValueType(0); 2561 2562 // If the input is a constant, let getNode() fold it. 2563 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 2564 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 2565 if (Res.Val != N) return Res; 2566 } 2567 2568 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 2569 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 2570 2571 // fold (conv (load x)) -> (load (conv*)x) 2572 // FIXME: These xforms need to know that the resultant load doesn't need a 2573 // higher alignment than the original! 2574 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) { 2575 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2576 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 2577 LN0->getSrcValue(), LN0->getSrcValueOffset(), 2578 LN0->isVolatile(), LN0->getAlignment()); 2579 AddToWorkList(N); 2580 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 2581 Load.getValue(1)); 2582 return Load; 2583 } 2584 2585 return SDOperand(); 2586} 2587 2588SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) { 2589 SDOperand N0 = N->getOperand(0); 2590 MVT::ValueType VT = N->getValueType(0); 2591 2592 // If the input is a VBUILD_VECTOR with all constant elements, fold this now. 2593 // First check to see if this is all constant. 2594 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() && 2595 VT == MVT::Vector) { 2596 bool isSimple = true; 2597 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i) 2598 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 2599 N0.getOperand(i).getOpcode() != ISD::Constant && 2600 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 2601 isSimple = false; 2602 break; 2603 } 2604 2605 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT(); 2606 if (isSimple && !MVT::isVector(DestEltVT)) { 2607 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT); 2608 } 2609 } 2610 2611 return SDOperand(); 2612} 2613 2614/// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector 2615/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 2616/// destination element value type. 2617SDOperand DAGCombiner:: 2618ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 2619 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 2620 2621 // If this is already the right type, we're done. 2622 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 2623 2624 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 2625 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 2626 2627 // If this is a conversion of N elements of one type to N elements of another 2628 // type, convert each element. This handles FP<->INT cases. 2629 if (SrcBitSize == DstBitSize) { 2630 SmallVector<SDOperand, 8> Ops; 2631 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2632 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 2633 AddToWorkList(Ops.back().Val); 2634 } 2635 Ops.push_back(*(BV->op_end()-2)); // Add num elements. 2636 Ops.push_back(DAG.getValueType(DstEltVT)); 2637 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2638 } 2639 2640 // Otherwise, we're growing or shrinking the elements. To avoid having to 2641 // handle annoying details of growing/shrinking FP values, we convert them to 2642 // int first. 2643 if (MVT::isFloatingPoint(SrcEltVT)) { 2644 // Convert the input float vector to a int vector where the elements are the 2645 // same sizes. 2646 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 2647 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2648 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val; 2649 SrcEltVT = IntVT; 2650 } 2651 2652 // Now we know the input is an integer vector. If the output is a FP type, 2653 // convert to integer first, then to FP of the right size. 2654 if (MVT::isFloatingPoint(DstEltVT)) { 2655 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 2656 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2657 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val; 2658 2659 // Next, convert to FP elements of the same size. 2660 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT); 2661 } 2662 2663 // Okay, we know the src/dst types are both integers of differing types. 2664 // Handling growing first. 2665 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 2666 if (SrcBitSize < DstBitSize) { 2667 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 2668 2669 SmallVector<SDOperand, 8> Ops; 2670 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; 2671 i += NumInputsPerOutput) { 2672 bool isLE = TLI.isLittleEndian(); 2673 uint64_t NewBits = 0; 2674 bool EltIsUndef = true; 2675 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 2676 // Shift the previously computed bits over. 2677 NewBits <<= SrcBitSize; 2678 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 2679 if (Op.getOpcode() == ISD::UNDEF) continue; 2680 EltIsUndef = false; 2681 2682 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 2683 } 2684 2685 if (EltIsUndef) 2686 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2687 else 2688 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 2689 } 2690 2691 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2692 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2693 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2694 } 2695 2696 // Finally, this must be the case where we are shrinking elements: each input 2697 // turns into multiple outputs. 2698 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 2699 SmallVector<SDOperand, 8> Ops; 2700 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2701 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 2702 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 2703 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2704 continue; 2705 } 2706 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 2707 2708 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 2709 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 2710 OpVal >>= DstBitSize; 2711 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 2712 } 2713 2714 // For big endian targets, swap the order of the pieces of each element. 2715 if (!TLI.isLittleEndian()) 2716 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 2717 } 2718 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2719 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2720 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2721} 2722 2723 2724 2725SDOperand DAGCombiner::visitFADD(SDNode *N) { 2726 SDOperand N0 = N->getOperand(0); 2727 SDOperand N1 = N->getOperand(1); 2728 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2729 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2730 MVT::ValueType VT = N->getValueType(0); 2731 2732 // fold (fadd c1, c2) -> c1+c2 2733 if (N0CFP && N1CFP) 2734 return DAG.getNode(ISD::FADD, VT, N0, N1); 2735 // canonicalize constant to RHS 2736 if (N0CFP && !N1CFP) 2737 return DAG.getNode(ISD::FADD, VT, N1, N0); 2738 // fold (A + (-B)) -> A-B 2739 if (N1.getOpcode() == ISD::FNEG) 2740 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 2741 // fold ((-A) + B) -> B-A 2742 if (N0.getOpcode() == ISD::FNEG) 2743 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 2744 2745 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 2746 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 2747 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 2748 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 2749 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 2750 2751 return SDOperand(); 2752} 2753 2754SDOperand DAGCombiner::visitFSUB(SDNode *N) { 2755 SDOperand N0 = N->getOperand(0); 2756 SDOperand N1 = N->getOperand(1); 2757 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2758 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2759 MVT::ValueType VT = N->getValueType(0); 2760 2761 // fold (fsub c1, c2) -> c1-c2 2762 if (N0CFP && N1CFP) 2763 return DAG.getNode(ISD::FSUB, VT, N0, N1); 2764 // fold (A-(-B)) -> A+B 2765 if (N1.getOpcode() == ISD::FNEG) 2766 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 2767 return SDOperand(); 2768} 2769 2770SDOperand DAGCombiner::visitFMUL(SDNode *N) { 2771 SDOperand N0 = N->getOperand(0); 2772 SDOperand N1 = N->getOperand(1); 2773 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2774 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2775 MVT::ValueType VT = N->getValueType(0); 2776 2777 // fold (fmul c1, c2) -> c1*c2 2778 if (N0CFP && N1CFP) 2779 return DAG.getNode(ISD::FMUL, VT, N0, N1); 2780 // canonicalize constant to RHS 2781 if (N0CFP && !N1CFP) 2782 return DAG.getNode(ISD::FMUL, VT, N1, N0); 2783 // fold (fmul X, 2.0) -> (fadd X, X) 2784 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 2785 return DAG.getNode(ISD::FADD, VT, N0, N0); 2786 2787 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 2788 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 2789 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 2790 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 2791 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 2792 2793 return SDOperand(); 2794} 2795 2796SDOperand DAGCombiner::visitFDIV(SDNode *N) { 2797 SDOperand N0 = N->getOperand(0); 2798 SDOperand N1 = N->getOperand(1); 2799 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2800 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2801 MVT::ValueType VT = N->getValueType(0); 2802 2803 // fold (fdiv c1, c2) -> c1/c2 2804 if (N0CFP && N1CFP) 2805 return DAG.getNode(ISD::FDIV, VT, N0, N1); 2806 return SDOperand(); 2807} 2808 2809SDOperand DAGCombiner::visitFREM(SDNode *N) { 2810 SDOperand N0 = N->getOperand(0); 2811 SDOperand N1 = N->getOperand(1); 2812 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2813 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2814 MVT::ValueType VT = N->getValueType(0); 2815 2816 // fold (frem c1, c2) -> fmod(c1,c2) 2817 if (N0CFP && N1CFP) 2818 return DAG.getNode(ISD::FREM, VT, N0, N1); 2819 return SDOperand(); 2820} 2821 2822SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 2823 SDOperand N0 = N->getOperand(0); 2824 SDOperand N1 = N->getOperand(1); 2825 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2826 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2827 MVT::ValueType VT = N->getValueType(0); 2828 2829 if (N0CFP && N1CFP) // Constant fold 2830 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 2831 2832 if (N1CFP) { 2833 // copysign(x, c1) -> fabs(x) iff ispos(c1) 2834 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 2835 union { 2836 double d; 2837 int64_t i; 2838 } u; 2839 u.d = N1CFP->getValue(); 2840 if (u.i >= 0) 2841 return DAG.getNode(ISD::FABS, VT, N0); 2842 else 2843 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 2844 } 2845 2846 // copysign(fabs(x), y) -> copysign(x, y) 2847 // copysign(fneg(x), y) -> copysign(x, y) 2848 // copysign(copysign(x,z), y) -> copysign(x, y) 2849 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 2850 N0.getOpcode() == ISD::FCOPYSIGN) 2851 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 2852 2853 // copysign(x, abs(y)) -> abs(x) 2854 if (N1.getOpcode() == ISD::FABS) 2855 return DAG.getNode(ISD::FABS, VT, N0); 2856 2857 // copysign(x, copysign(y,z)) -> copysign(x, z) 2858 if (N1.getOpcode() == ISD::FCOPYSIGN) 2859 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 2860 2861 // copysign(x, fp_extend(y)) -> copysign(x, y) 2862 // copysign(x, fp_round(y)) -> copysign(x, y) 2863 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 2864 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 2865 2866 return SDOperand(); 2867} 2868 2869 2870 2871SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 2872 SDOperand N0 = N->getOperand(0); 2873 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2874 MVT::ValueType VT = N->getValueType(0); 2875 2876 // fold (sint_to_fp c1) -> c1fp 2877 if (N0C) 2878 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 2879 return SDOperand(); 2880} 2881 2882SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 2883 SDOperand N0 = N->getOperand(0); 2884 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2885 MVT::ValueType VT = N->getValueType(0); 2886 2887 // fold (uint_to_fp c1) -> c1fp 2888 if (N0C) 2889 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 2890 return SDOperand(); 2891} 2892 2893SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 2894 SDOperand N0 = N->getOperand(0); 2895 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2896 MVT::ValueType VT = N->getValueType(0); 2897 2898 // fold (fp_to_sint c1fp) -> c1 2899 if (N0CFP) 2900 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 2901 return SDOperand(); 2902} 2903 2904SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 2905 SDOperand N0 = N->getOperand(0); 2906 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2907 MVT::ValueType VT = N->getValueType(0); 2908 2909 // fold (fp_to_uint c1fp) -> c1 2910 if (N0CFP) 2911 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 2912 return SDOperand(); 2913} 2914 2915SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 2916 SDOperand N0 = N->getOperand(0); 2917 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2918 MVT::ValueType VT = N->getValueType(0); 2919 2920 // fold (fp_round c1fp) -> c1fp 2921 if (N0CFP) 2922 return DAG.getNode(ISD::FP_ROUND, VT, N0); 2923 2924 // fold (fp_round (fp_extend x)) -> x 2925 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 2926 return N0.getOperand(0); 2927 2928 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 2929 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 2930 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 2931 AddToWorkList(Tmp.Val); 2932 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 2933 } 2934 2935 return SDOperand(); 2936} 2937 2938SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 2939 SDOperand N0 = N->getOperand(0); 2940 MVT::ValueType VT = N->getValueType(0); 2941 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2942 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2943 2944 // fold (fp_round_inreg c1fp) -> c1fp 2945 if (N0CFP) { 2946 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 2947 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 2948 } 2949 return SDOperand(); 2950} 2951 2952SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 2953 SDOperand N0 = N->getOperand(0); 2954 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2955 MVT::ValueType VT = N->getValueType(0); 2956 2957 // fold (fp_extend c1fp) -> c1fp 2958 if (N0CFP) 2959 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 2960 2961 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 2962 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2963 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2964 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2965 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2966 LN0->getBasePtr(), LN0->getSrcValue(), 2967 LN0->getSrcValueOffset(), 2968 N0.getValueType(), 2969 LN0->isVolatile(), 2970 LN0->getAlignment()); 2971 CombineTo(N, ExtLoad); 2972 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 2973 ExtLoad.getValue(1)); 2974 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2975 } 2976 2977 2978 return SDOperand(); 2979} 2980 2981SDOperand DAGCombiner::visitFNEG(SDNode *N) { 2982 SDOperand N0 = N->getOperand(0); 2983 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2984 MVT::ValueType VT = N->getValueType(0); 2985 2986 // fold (fneg c1) -> -c1 2987 if (N0CFP) 2988 return DAG.getNode(ISD::FNEG, VT, N0); 2989 // fold (fneg (sub x, y)) -> (sub y, x) 2990 if (N0.getOpcode() == ISD::SUB) 2991 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0)); 2992 // fold (fneg (fneg x)) -> x 2993 if (N0.getOpcode() == ISD::FNEG) 2994 return N0.getOperand(0); 2995 return SDOperand(); 2996} 2997 2998SDOperand DAGCombiner::visitFABS(SDNode *N) { 2999 SDOperand N0 = N->getOperand(0); 3000 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3001 MVT::ValueType VT = N->getValueType(0); 3002 3003 // fold (fabs c1) -> fabs(c1) 3004 if (N0CFP) 3005 return DAG.getNode(ISD::FABS, VT, N0); 3006 // fold (fabs (fabs x)) -> (fabs x) 3007 if (N0.getOpcode() == ISD::FABS) 3008 return N->getOperand(0); 3009 // fold (fabs (fneg x)) -> (fabs x) 3010 // fold (fabs (fcopysign x, y)) -> (fabs x) 3011 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3012 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3013 3014 return SDOperand(); 3015} 3016 3017SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3018 SDOperand Chain = N->getOperand(0); 3019 SDOperand N1 = N->getOperand(1); 3020 SDOperand N2 = N->getOperand(2); 3021 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3022 3023 // never taken branch, fold to chain 3024 if (N1C && N1C->isNullValue()) 3025 return Chain; 3026 // unconditional branch 3027 if (N1C && N1C->getValue() == 1) 3028 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3029 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3030 // on the target. 3031 if (N1.getOpcode() == ISD::SETCC && 3032 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3033 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3034 N1.getOperand(0), N1.getOperand(1), N2); 3035 } 3036 return SDOperand(); 3037} 3038 3039// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3040// 3041SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3042 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3043 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3044 3045 // Use SimplifySetCC to simplify SETCC's. 3046 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3047 if (Simp.Val) AddToWorkList(Simp.Val); 3048 3049 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3050 3051 // fold br_cc true, dest -> br dest (unconditional branch) 3052 if (SCCC && SCCC->getValue()) 3053 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3054 N->getOperand(4)); 3055 // fold br_cc false, dest -> unconditional fall through 3056 if (SCCC && SCCC->isNullValue()) 3057 return N->getOperand(0); 3058 3059 // fold to a simpler setcc 3060 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 3061 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 3062 Simp.getOperand(2), Simp.getOperand(0), 3063 Simp.getOperand(1), N->getOperand(4)); 3064 return SDOperand(); 3065} 3066 3067 3068/// CombineToPreIndexedLoadStore - Try turning a load / store and a 3069/// pre-indexed load / store when the base pointer is a add or subtract 3070/// and it has other uses besides the load / store. After the 3071/// transformation, the new indexed load / store has effectively folded 3072/// the add / subtract in and all of its other uses are redirected to the 3073/// new load / store. 3074bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 3075 if (!AfterLegalize) 3076 return false; 3077 3078 bool isLoad = true; 3079 SDOperand Ptr; 3080 MVT::ValueType VT; 3081 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3082 if (LD->getAddressingMode() != ISD::UNINDEXED) 3083 return false; 3084 VT = LD->getLoadedVT(); 3085 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 3086 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 3087 return false; 3088 Ptr = LD->getBasePtr(); 3089 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3090 if (ST->getAddressingMode() != ISD::UNINDEXED) 3091 return false; 3092 VT = ST->getStoredVT(); 3093 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 3094 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 3095 return false; 3096 Ptr = ST->getBasePtr(); 3097 isLoad = false; 3098 } else 3099 return false; 3100 3101 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 3102 // out. There is no reason to make this a preinc/predec. 3103 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 3104 Ptr.Val->hasOneUse()) 3105 return false; 3106 3107 // Ask the target to do addressing mode selection. 3108 SDOperand BasePtr; 3109 SDOperand Offset; 3110 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3111 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 3112 return false; 3113 3114 // Try turning it into a pre-indexed load / store except when: 3115 // 1) The base is a frame index. 3116 // 2) If N is a store and the ptr is either the same as or is a 3117 // predecessor of the value being stored. 3118 // 3) Another use of base ptr is a predecessor of N. If ptr is folded 3119 // that would create a cycle. 3120 // 4) All uses are load / store ops that use it as base ptr. 3121 3122 // Check #1. Preinc'ing a frame index would require copying the stack pointer 3123 // (plus the implicit offset) to a register to preinc anyway. 3124 if (isa<FrameIndexSDNode>(BasePtr)) 3125 return false; 3126 3127 // Check #2. 3128 if (!isLoad) { 3129 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 3130 if (Val == Ptr || Ptr.Val->isPredecessor(Val.Val)) 3131 return false; 3132 } 3133 3134 // Now check for #2 and #3. 3135 bool RealUse = false; 3136 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3137 E = Ptr.Val->use_end(); I != E; ++I) { 3138 SDNode *Use = *I; 3139 if (Use == N) 3140 continue; 3141 if (Use->isPredecessor(N)) 3142 return false; 3143 3144 if (!((Use->getOpcode() == ISD::LOAD && 3145 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 3146 (Use->getOpcode() == ISD::STORE) && 3147 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 3148 RealUse = true; 3149 } 3150 if (!RealUse) 3151 return false; 3152 3153 SDOperand Result; 3154 if (isLoad) 3155 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 3156 else 3157 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3158 ++PreIndexedNodes; 3159 ++NodesCombined; 3160 DOUT << "\nReplacing.4 "; DEBUG(N->dump()); 3161 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3162 DOUT << '\n'; 3163 std::vector<SDNode*> NowDead; 3164 if (isLoad) { 3165 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3166 NowDead); 3167 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3168 NowDead); 3169 } else { 3170 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3171 NowDead); 3172 } 3173 3174 // Nodes can end up on the worklist more than once. Make sure we do 3175 // not process a node that has been replaced. 3176 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3177 removeFromWorkList(NowDead[i]); 3178 // Finally, since the node is now dead, remove it from the graph. 3179 DAG.DeleteNode(N); 3180 3181 // Replace the uses of Ptr with uses of the updated base value. 3182 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 3183 NowDead); 3184 removeFromWorkList(Ptr.Val); 3185 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3186 removeFromWorkList(NowDead[i]); 3187 DAG.DeleteNode(Ptr.Val); 3188 3189 return true; 3190} 3191 3192/// CombineToPostIndexedLoadStore - Try combine a load / store with a 3193/// add / sub of the base pointer node into a post-indexed load / store. 3194/// The transformation folded the add / subtract into the new indexed 3195/// load / store effectively and all of its uses are redirected to the 3196/// new load / store. 3197bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 3198 if (!AfterLegalize) 3199 return false; 3200 3201 bool isLoad = true; 3202 SDOperand Ptr; 3203 MVT::ValueType VT; 3204 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3205 if (LD->getAddressingMode() != ISD::UNINDEXED) 3206 return false; 3207 VT = LD->getLoadedVT(); 3208 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 3209 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 3210 return false; 3211 Ptr = LD->getBasePtr(); 3212 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3213 if (ST->getAddressingMode() != ISD::UNINDEXED) 3214 return false; 3215 VT = ST->getStoredVT(); 3216 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 3217 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 3218 return false; 3219 Ptr = ST->getBasePtr(); 3220 isLoad = false; 3221 } else 3222 return false; 3223 3224 if (Ptr.Val->hasOneUse()) 3225 return false; 3226 3227 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3228 E = Ptr.Val->use_end(); I != E; ++I) { 3229 SDNode *Op = *I; 3230 if (Op == N || 3231 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 3232 continue; 3233 3234 SDOperand BasePtr; 3235 SDOperand Offset; 3236 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3237 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 3238 if (Ptr == Offset) 3239 std::swap(BasePtr, Offset); 3240 if (Ptr != BasePtr) 3241 continue; 3242 3243 // Try turning it into a post-indexed load / store except when 3244 // 1) All uses are load / store ops that use it as base ptr. 3245 // 2) Op must be independent of N, i.e. Op is neither a predecessor 3246 // nor a successor of N. Otherwise, if Op is folded that would 3247 // create a cycle. 3248 3249 // Check for #1. 3250 bool TryNext = false; 3251 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 3252 EE = BasePtr.Val->use_end(); II != EE; ++II) { 3253 SDNode *Use = *II; 3254 if (Use == Ptr.Val) 3255 continue; 3256 3257 // If all the uses are load / store addresses, then don't do the 3258 // transformation. 3259 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 3260 bool RealUse = false; 3261 for (SDNode::use_iterator III = Use->use_begin(), 3262 EEE = Use->use_end(); III != EEE; ++III) { 3263 SDNode *UseUse = *III; 3264 if (!((UseUse->getOpcode() == ISD::LOAD && 3265 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 3266 (UseUse->getOpcode() == ISD::STORE) && 3267 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 3268 RealUse = true; 3269 } 3270 3271 if (!RealUse) { 3272 TryNext = true; 3273 break; 3274 } 3275 } 3276 } 3277 if (TryNext) 3278 continue; 3279 3280 // Check for #2 3281 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 3282 SDOperand Result = isLoad 3283 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 3284 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3285 ++PostIndexedNodes; 3286 ++NodesCombined; 3287 DOUT << "\nReplacing.5 "; DEBUG(N->dump()); 3288 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3289 DOUT << '\n'; 3290 std::vector<SDNode*> NowDead; 3291 if (isLoad) { 3292 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3293 NowDead); 3294 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3295 NowDead); 3296 } else { 3297 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3298 NowDead); 3299 } 3300 3301 // Nodes can end up on the worklist more than once. Make sure we do 3302 // not process a node that has been replaced. 3303 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3304 removeFromWorkList(NowDead[i]); 3305 // Finally, since the node is now dead, remove it from the graph. 3306 DAG.DeleteNode(N); 3307 3308 // Replace the uses of Use with uses of the updated base value. 3309 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 3310 Result.getValue(isLoad ? 1 : 0), 3311 NowDead); 3312 removeFromWorkList(Op); 3313 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3314 removeFromWorkList(NowDead[i]); 3315 DAG.DeleteNode(Op); 3316 3317 return true; 3318 } 3319 } 3320 } 3321 return false; 3322} 3323 3324 3325SDOperand DAGCombiner::visitLOAD(SDNode *N) { 3326 LoadSDNode *LD = cast<LoadSDNode>(N); 3327 SDOperand Chain = LD->getChain(); 3328 SDOperand Ptr = LD->getBasePtr(); 3329 3330 // If there are no uses of the loaded value, change uses of the chain value 3331 // into uses of the chain input (i.e. delete the dead load). 3332 if (N->hasNUsesOfValue(0, 0)) 3333 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 3334 3335 // If this load is directly stored, replace the load value with the stored 3336 // value. 3337 // TODO: Handle store large -> read small portion. 3338 // TODO: Handle TRUNCSTORE/LOADEXT 3339 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3340 if (ISD::isNON_TRUNCStore(Chain.Val)) { 3341 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 3342 if (PrevST->getBasePtr() == Ptr && 3343 PrevST->getValue().getValueType() == N->getValueType(0)) 3344 return CombineTo(N, Chain.getOperand(1), Chain); 3345 } 3346 } 3347 3348 if (CombinerAA) { 3349 // Walk up chain skipping non-aliasing memory nodes. 3350 SDOperand BetterChain = FindBetterChain(N, Chain); 3351 3352 // If there is a better chain. 3353 if (Chain != BetterChain) { 3354 SDOperand ReplLoad; 3355 3356 // Replace the chain to void dependency. 3357 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3358 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 3359 LD->getSrcValue(), LD->getSrcValueOffset(), 3360 LD->isVolatile(), LD->getAlignment()); 3361 } else { 3362 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 3363 LD->getValueType(0), 3364 BetterChain, Ptr, LD->getSrcValue(), 3365 LD->getSrcValueOffset(), 3366 LD->getLoadedVT(), 3367 LD->isVolatile(), 3368 LD->getAlignment()); 3369 } 3370 3371 // Create token factor to keep old chain connected. 3372 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 3373 Chain, ReplLoad.getValue(1)); 3374 3375 // Replace uses with load result and token factor. Don't add users 3376 // to work list. 3377 return CombineTo(N, ReplLoad.getValue(0), Token, false); 3378 } 3379 } 3380 3381 // Try transforming N to an indexed load. 3382 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3383 return SDOperand(N, 0); 3384 3385 return SDOperand(); 3386} 3387 3388SDOperand DAGCombiner::visitSTORE(SDNode *N) { 3389 StoreSDNode *ST = cast<StoreSDNode>(N); 3390 SDOperand Chain = ST->getChain(); 3391 SDOperand Value = ST->getValue(); 3392 SDOperand Ptr = ST->getBasePtr(); 3393 3394 // If this is a store of a bit convert, store the input value. 3395 // FIXME: This needs to know that the resultant store does not need a 3396 // higher alignment than the original. 3397 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) { 3398 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 3399 ST->getSrcValueOffset()); 3400 } 3401 3402 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 3403 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 3404 if (Value.getOpcode() != ISD::TargetConstantFP) { 3405 SDOperand Tmp; 3406 switch (CFP->getValueType(0)) { 3407 default: assert(0 && "Unknown FP type"); 3408 case MVT::f32: 3409 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 3410 Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 3411 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3412 ST->getSrcValueOffset()); 3413 } 3414 break; 3415 case MVT::f64: 3416 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 3417 Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 3418 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3419 ST->getSrcValueOffset()); 3420 } else if (TLI.isTypeLegal(MVT::i32)) { 3421 // Many FP stores are not make apparent until after legalize, e.g. for 3422 // argument passing. Since this is so common, custom legalize the 3423 // 64-bit integer store into two 32-bit stores. 3424 uint64_t Val = DoubleToBits(CFP->getValue()); 3425 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 3426 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 3427 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 3428 3429 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 3430 ST->getSrcValueOffset()); 3431 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3432 DAG.getConstant(4, Ptr.getValueType())); 3433 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 3434 ST->getSrcValueOffset()+4); 3435 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 3436 } 3437 break; 3438 } 3439 } 3440 } 3441 3442 if (CombinerAA) { 3443 // Walk up chain skipping non-aliasing memory nodes. 3444 SDOperand BetterChain = FindBetterChain(N, Chain); 3445 3446 // If there is a better chain. 3447 if (Chain != BetterChain) { 3448 // Replace the chain to avoid dependency. 3449 SDOperand ReplStore; 3450 if (ST->isTruncatingStore()) { 3451 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 3452 ST->getSrcValue(),ST->getSrcValueOffset(), ST->getStoredVT()); 3453 } else { 3454 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 3455 ST->getSrcValue(), ST->getSrcValueOffset()); 3456 } 3457 3458 // Create token to keep both nodes around. 3459 SDOperand Token = 3460 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 3461 3462 // Don't add users to work list. 3463 return CombineTo(N, Token, false); 3464 } 3465 } 3466 3467 // Try transforming N to an indexed store. 3468 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3469 return SDOperand(N, 0); 3470 3471 return SDOperand(); 3472} 3473 3474SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 3475 SDOperand InVec = N->getOperand(0); 3476 SDOperand InVal = N->getOperand(1); 3477 SDOperand EltNo = N->getOperand(2); 3478 3479 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 3480 // vector with the inserted element. 3481 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 3482 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 3483 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 3484 if (Elt < Ops.size()) 3485 Ops[Elt] = InVal; 3486 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 3487 &Ops[0], Ops.size()); 3488 } 3489 3490 return SDOperand(); 3491} 3492 3493SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) { 3494 SDOperand InVec = N->getOperand(0); 3495 SDOperand InVal = N->getOperand(1); 3496 SDOperand EltNo = N->getOperand(2); 3497 SDOperand NumElts = N->getOperand(3); 3498 SDOperand EltType = N->getOperand(4); 3499 3500 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new 3501 // vector with the inserted element. 3502 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 3503 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 3504 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 3505 if (Elt < Ops.size()-2) 3506 Ops[Elt] = InVal; 3507 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), 3508 &Ops[0], Ops.size()); 3509 } 3510 3511 return SDOperand(); 3512} 3513 3514SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) { 3515 unsigned NumInScalars = N->getNumOperands()-2; 3516 SDOperand NumElts = N->getOperand(NumInScalars); 3517 SDOperand EltType = N->getOperand(NumInScalars+1); 3518 3519 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT 3520 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most 3521 // two distinct vectors, turn this into a shuffle node. 3522 SDOperand VecIn1, VecIn2; 3523 for (unsigned i = 0; i != NumInScalars; ++i) { 3524 // Ignore undef inputs. 3525 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 3526 3527 // If this input is something other than a VEXTRACT_VECTOR_ELT with a 3528 // constant index, bail out. 3529 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT || 3530 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 3531 VecIn1 = VecIn2 = SDOperand(0, 0); 3532 break; 3533 } 3534 3535 // If the input vector type disagrees with the result of the vbuild_vector, 3536 // we can't make a shuffle. 3537 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 3538 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts || 3539 *(ExtractedFromVec.Val->op_end()-1) != EltType) { 3540 VecIn1 = VecIn2 = SDOperand(0, 0); 3541 break; 3542 } 3543 3544 // Otherwise, remember this. We allow up to two distinct input vectors. 3545 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 3546 continue; 3547 3548 if (VecIn1.Val == 0) { 3549 VecIn1 = ExtractedFromVec; 3550 } else if (VecIn2.Val == 0) { 3551 VecIn2 = ExtractedFromVec; 3552 } else { 3553 // Too many inputs. 3554 VecIn1 = VecIn2 = SDOperand(0, 0); 3555 break; 3556 } 3557 } 3558 3559 // If everything is good, we can make a shuffle operation. 3560 if (VecIn1.Val) { 3561 SmallVector<SDOperand, 8> BuildVecIndices; 3562 for (unsigned i = 0; i != NumInScalars; ++i) { 3563 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 3564 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 3565 continue; 3566 } 3567 3568 SDOperand Extract = N->getOperand(i); 3569 3570 // If extracting from the first vector, just use the index directly. 3571 if (Extract.getOperand(0) == VecIn1) { 3572 BuildVecIndices.push_back(Extract.getOperand(1)); 3573 continue; 3574 } 3575 3576 // Otherwise, use InIdx + VecSize 3577 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 3578 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, 3579 TLI.getPointerTy())); 3580 } 3581 3582 // Add count and size info. 3583 BuildVecIndices.push_back(NumElts); 3584 BuildVecIndices.push_back(DAG.getValueType(TLI.getPointerTy())); 3585 3586 // Return the new VVECTOR_SHUFFLE node. 3587 SDOperand Ops[5]; 3588 Ops[0] = VecIn1; 3589 if (VecIn2.Val) { 3590 Ops[1] = VecIn2; 3591 } else { 3592 // Use an undef vbuild_vector as input for the second operand. 3593 std::vector<SDOperand> UnOps(NumInScalars, 3594 DAG.getNode(ISD::UNDEF, 3595 cast<VTSDNode>(EltType)->getVT())); 3596 UnOps.push_back(NumElts); 3597 UnOps.push_back(EltType); 3598 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3599 &UnOps[0], UnOps.size()); 3600 AddToWorkList(Ops[1].Val); 3601 } 3602 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3603 &BuildVecIndices[0], BuildVecIndices.size()); 3604 Ops[3] = NumElts; 3605 Ops[4] = EltType; 3606 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5); 3607 } 3608 3609 return SDOperand(); 3610} 3611 3612SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 3613 SDOperand ShufMask = N->getOperand(2); 3614 unsigned NumElts = ShufMask.getNumOperands(); 3615 3616 // If the shuffle mask is an identity operation on the LHS, return the LHS. 3617 bool isIdentity = true; 3618 for (unsigned i = 0; i != NumElts; ++i) { 3619 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3620 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 3621 isIdentity = false; 3622 break; 3623 } 3624 } 3625 if (isIdentity) return N->getOperand(0); 3626 3627 // If the shuffle mask is an identity operation on the RHS, return the RHS. 3628 isIdentity = true; 3629 for (unsigned i = 0; i != NumElts; ++i) { 3630 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3631 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 3632 isIdentity = false; 3633 break; 3634 } 3635 } 3636 if (isIdentity) return N->getOperand(1); 3637 3638 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 3639 // needed at all. 3640 bool isUnary = true; 3641 bool isSplat = true; 3642 int VecNum = -1; 3643 unsigned BaseIdx = 0; 3644 for (unsigned i = 0; i != NumElts; ++i) 3645 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 3646 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 3647 int V = (Idx < NumElts) ? 0 : 1; 3648 if (VecNum == -1) { 3649 VecNum = V; 3650 BaseIdx = Idx; 3651 } else { 3652 if (BaseIdx != Idx) 3653 isSplat = false; 3654 if (VecNum != V) { 3655 isUnary = false; 3656 break; 3657 } 3658 } 3659 } 3660 3661 SDOperand N0 = N->getOperand(0); 3662 SDOperand N1 = N->getOperand(1); 3663 // Normalize unary shuffle so the RHS is undef. 3664 if (isUnary && VecNum == 1) 3665 std::swap(N0, N1); 3666 3667 // If it is a splat, check if the argument vector is a build_vector with 3668 // all scalar elements the same. 3669 if (isSplat) { 3670 SDNode *V = N0.Val; 3671 if (V->getOpcode() == ISD::BIT_CONVERT) 3672 V = V->getOperand(0).Val; 3673 if (V->getOpcode() == ISD::BUILD_VECTOR) { 3674 unsigned NumElems = V->getNumOperands()-2; 3675 if (NumElems > BaseIdx) { 3676 SDOperand Base; 3677 bool AllSame = true; 3678 for (unsigned i = 0; i != NumElems; ++i) { 3679 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 3680 Base = V->getOperand(i); 3681 break; 3682 } 3683 } 3684 // Splat of <u, u, u, u>, return <u, u, u, u> 3685 if (!Base.Val) 3686 return N0; 3687 for (unsigned i = 0; i != NumElems; ++i) { 3688 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 3689 V->getOperand(i) != Base) { 3690 AllSame = false; 3691 break; 3692 } 3693 } 3694 // Splat of <x, x, x, x>, return <x, x, x, x> 3695 if (AllSame) 3696 return N0; 3697 } 3698 } 3699 } 3700 3701 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 3702 // into an undef. 3703 if (isUnary || N0 == N1) { 3704 if (N0.getOpcode() == ISD::UNDEF) 3705 return DAG.getNode(ISD::UNDEF, N->getValueType(0)); 3706 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 3707 // first operand. 3708 SmallVector<SDOperand, 8> MappedOps; 3709 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) { 3710 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 3711 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 3712 MappedOps.push_back(ShufMask.getOperand(i)); 3713 } else { 3714 unsigned NewIdx = 3715 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 3716 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 3717 } 3718 } 3719 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 3720 &MappedOps[0], MappedOps.size()); 3721 AddToWorkList(ShufMask.Val); 3722 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 3723 N0, 3724 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 3725 ShufMask); 3726 } 3727 3728 return SDOperand(); 3729} 3730 3731SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) { 3732 SDOperand ShufMask = N->getOperand(2); 3733 unsigned NumElts = ShufMask.getNumOperands()-2; 3734 3735 // If the shuffle mask is an identity operation on the LHS, return the LHS. 3736 bool isIdentity = true; 3737 for (unsigned i = 0; i != NumElts; ++i) { 3738 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3739 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 3740 isIdentity = false; 3741 break; 3742 } 3743 } 3744 if (isIdentity) return N->getOperand(0); 3745 3746 // If the shuffle mask is an identity operation on the RHS, return the RHS. 3747 isIdentity = true; 3748 for (unsigned i = 0; i != NumElts; ++i) { 3749 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3750 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 3751 isIdentity = false; 3752 break; 3753 } 3754 } 3755 if (isIdentity) return N->getOperand(1); 3756 3757 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 3758 // needed at all. 3759 bool isUnary = true; 3760 bool isSplat = true; 3761 int VecNum = -1; 3762 unsigned BaseIdx = 0; 3763 for (unsigned i = 0; i != NumElts; ++i) 3764 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 3765 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 3766 int V = (Idx < NumElts) ? 0 : 1; 3767 if (VecNum == -1) { 3768 VecNum = V; 3769 BaseIdx = Idx; 3770 } else { 3771 if (BaseIdx != Idx) 3772 isSplat = false; 3773 if (VecNum != V) { 3774 isUnary = false; 3775 break; 3776 } 3777 } 3778 } 3779 3780 SDOperand N0 = N->getOperand(0); 3781 SDOperand N1 = N->getOperand(1); 3782 // Normalize unary shuffle so the RHS is undef. 3783 if (isUnary && VecNum == 1) 3784 std::swap(N0, N1); 3785 3786 // If it is a splat, check if the argument vector is a build_vector with 3787 // all scalar elements the same. 3788 if (isSplat) { 3789 SDNode *V = N0.Val; 3790 3791 // If this is a vbit convert that changes the element type of the vector but 3792 // not the number of vector elements, look through it. Be careful not to 3793 // look though conversions that change things like v4f32 to v2f64. 3794 if (V->getOpcode() == ISD::VBIT_CONVERT) { 3795 SDOperand ConvInput = V->getOperand(0); 3796 if (ConvInput.getValueType() == MVT::Vector && 3797 NumElts == 3798 ConvInput.getConstantOperandVal(ConvInput.getNumOperands()-2)) 3799 V = ConvInput.Val; 3800 } 3801 3802 if (V->getOpcode() == ISD::VBUILD_VECTOR) { 3803 unsigned NumElems = V->getNumOperands()-2; 3804 if (NumElems > BaseIdx) { 3805 SDOperand Base; 3806 bool AllSame = true; 3807 for (unsigned i = 0; i != NumElems; ++i) { 3808 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 3809 Base = V->getOperand(i); 3810 break; 3811 } 3812 } 3813 // Splat of <u, u, u, u>, return <u, u, u, u> 3814 if (!Base.Val) 3815 return N0; 3816 for (unsigned i = 0; i != NumElems; ++i) { 3817 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 3818 V->getOperand(i) != Base) { 3819 AllSame = false; 3820 break; 3821 } 3822 } 3823 // Splat of <x, x, x, x>, return <x, x, x, x> 3824 if (AllSame) 3825 return N0; 3826 } 3827 } 3828 } 3829 3830 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 3831 // into an undef. 3832 if (isUnary || N0 == N1) { 3833 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 3834 // first operand. 3835 SmallVector<SDOperand, 8> MappedOps; 3836 for (unsigned i = 0; i != NumElts; ++i) { 3837 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 3838 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 3839 MappedOps.push_back(ShufMask.getOperand(i)); 3840 } else { 3841 unsigned NewIdx = 3842 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 3843 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 3844 } 3845 } 3846 // Add the type/#elts values. 3847 MappedOps.push_back(ShufMask.getOperand(NumElts)); 3848 MappedOps.push_back(ShufMask.getOperand(NumElts+1)); 3849 3850 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(), 3851 &MappedOps[0], MappedOps.size()); 3852 AddToWorkList(ShufMask.Val); 3853 3854 // Build the undef vector. 3855 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType()); 3856 for (unsigned i = 0; i != NumElts; ++i) 3857 MappedOps[i] = UDVal; 3858 MappedOps[NumElts ] = *(N0.Val->op_end()-2); 3859 MappedOps[NumElts+1] = *(N0.Val->op_end()-1); 3860 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3861 &MappedOps[0], MappedOps.size()); 3862 3863 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 3864 N0, UDVal, ShufMask, 3865 MappedOps[NumElts], MappedOps[NumElts+1]); 3866 } 3867 3868 return SDOperand(); 3869} 3870 3871/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 3872/// a VAND to a vector_shuffle with the destination vector and a zero vector. 3873/// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 3874/// vector_shuffle V, Zero, <0, 4, 2, 4> 3875SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 3876 SDOperand LHS = N->getOperand(0); 3877 SDOperand RHS = N->getOperand(1); 3878 if (N->getOpcode() == ISD::VAND) { 3879 SDOperand DstVecSize = *(LHS.Val->op_end()-2); 3880 SDOperand DstVecEVT = *(LHS.Val->op_end()-1); 3881 if (RHS.getOpcode() == ISD::VBIT_CONVERT) 3882 RHS = RHS.getOperand(0); 3883 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) { 3884 std::vector<SDOperand> IdxOps; 3885 unsigned NumOps = RHS.getNumOperands(); 3886 unsigned NumElts = NumOps-2; 3887 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT(); 3888 for (unsigned i = 0; i != NumElts; ++i) { 3889 SDOperand Elt = RHS.getOperand(i); 3890 if (!isa<ConstantSDNode>(Elt)) 3891 return SDOperand(); 3892 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 3893 IdxOps.push_back(DAG.getConstant(i, EVT)); 3894 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 3895 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 3896 else 3897 return SDOperand(); 3898 } 3899 3900 // Let's see if the target supports this vector_shuffle. 3901 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 3902 return SDOperand(); 3903 3904 // Return the new VVECTOR_SHUFFLE node. 3905 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32); 3906 SDOperand EVTNode = DAG.getValueType(EVT); 3907 std::vector<SDOperand> Ops; 3908 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode, 3909 EVTNode); 3910 Ops.push_back(LHS); 3911 AddToWorkList(LHS.Val); 3912 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 3913 ZeroOps.push_back(NumEltsNode); 3914 ZeroOps.push_back(EVTNode); 3915 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3916 &ZeroOps[0], ZeroOps.size())); 3917 IdxOps.push_back(NumEltsNode); 3918 IdxOps.push_back(EVTNode); 3919 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3920 &IdxOps[0], IdxOps.size())); 3921 Ops.push_back(NumEltsNode); 3922 Ops.push_back(EVTNode); 3923 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 3924 &Ops[0], Ops.size()); 3925 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) { 3926 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 3927 DstVecSize, DstVecEVT); 3928 } 3929 return Result; 3930 } 3931 } 3932 return SDOperand(); 3933} 3934 3935/// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates 3936/// the scalar operation of the vop if it is operating on an integer vector 3937/// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD). 3938SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp, 3939 ISD::NodeType FPOp) { 3940 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT(); 3941 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp; 3942 SDOperand LHS = N->getOperand(0); 3943 SDOperand RHS = N->getOperand(1); 3944 SDOperand Shuffle = XformToShuffleWithZero(N); 3945 if (Shuffle.Val) return Shuffle; 3946 3947 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold 3948 // this operation. 3949 if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 3950 RHS.getOpcode() == ISD::VBUILD_VECTOR) { 3951 SmallVector<SDOperand, 8> Ops; 3952 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) { 3953 SDOperand LHSOp = LHS.getOperand(i); 3954 SDOperand RHSOp = RHS.getOperand(i); 3955 // If these two elements can't be folded, bail out. 3956 if ((LHSOp.getOpcode() != ISD::UNDEF && 3957 LHSOp.getOpcode() != ISD::Constant && 3958 LHSOp.getOpcode() != ISD::ConstantFP) || 3959 (RHSOp.getOpcode() != ISD::UNDEF && 3960 RHSOp.getOpcode() != ISD::Constant && 3961 RHSOp.getOpcode() != ISD::ConstantFP)) 3962 break; 3963 // Can't fold divide by zero. 3964 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) { 3965 if ((RHSOp.getOpcode() == ISD::Constant && 3966 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 3967 (RHSOp.getOpcode() == ISD::ConstantFP && 3968 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue())) 3969 break; 3970 } 3971 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp)); 3972 AddToWorkList(Ops.back().Val); 3973 assert((Ops.back().getOpcode() == ISD::UNDEF || 3974 Ops.back().getOpcode() == ISD::Constant || 3975 Ops.back().getOpcode() == ISD::ConstantFP) && 3976 "Scalar binop didn't fold!"); 3977 } 3978 3979 if (Ops.size() == LHS.getNumOperands()-2) { 3980 Ops.push_back(*(LHS.Val->op_end()-2)); 3981 Ops.push_back(*(LHS.Val->op_end()-1)); 3982 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 3983 } 3984 } 3985 3986 return SDOperand(); 3987} 3988 3989SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 3990 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 3991 3992 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 3993 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3994 // If we got a simplified select_cc node back from SimplifySelectCC, then 3995 // break it down into a new SETCC node, and a new SELECT node, and then return 3996 // the SELECT node, since we were called with a SELECT node. 3997 if (SCC.Val) { 3998 // Check to see if we got a select_cc back (to turn into setcc/select). 3999 // Otherwise, just return whatever node we got back, like fabs. 4000 if (SCC.getOpcode() == ISD::SELECT_CC) { 4001 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 4002 SCC.getOperand(0), SCC.getOperand(1), 4003 SCC.getOperand(4)); 4004 AddToWorkList(SETCC.Val); 4005 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 4006 SCC.getOperand(3), SETCC); 4007 } 4008 return SCC; 4009 } 4010 return SDOperand(); 4011} 4012 4013/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 4014/// are the two values being selected between, see if we can simplify the 4015/// select. Callers of this should assume that TheSelect is deleted if this 4016/// returns true. As such, they should return the appropriate thing (e.g. the 4017/// node) back to the top-level of the DAG combiner loop to avoid it being 4018/// looked at. 4019/// 4020bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 4021 SDOperand RHS) { 4022 4023 // If this is a select from two identical things, try to pull the operation 4024 // through the select. 4025 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 4026 // If this is a load and the token chain is identical, replace the select 4027 // of two loads with a load through a select of the address to load from. 4028 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 4029 // constants have been dropped into the constant pool. 4030 if (LHS.getOpcode() == ISD::LOAD && 4031 // Token chains must be identical. 4032 LHS.getOperand(0) == RHS.getOperand(0)) { 4033 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 4034 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 4035 4036 // If this is an EXTLOAD, the VT's must match. 4037 if (LLD->getLoadedVT() == RLD->getLoadedVT()) { 4038 // FIXME: this conflates two src values, discarding one. This is not 4039 // the right thing to do, but nothing uses srcvalues now. When they do, 4040 // turn SrcValue into a list of locations. 4041 SDOperand Addr; 4042 if (TheSelect->getOpcode() == ISD::SELECT) { 4043 // Check that the condition doesn't reach either load. If so, folding 4044 // this will induce a cycle into the DAG. 4045 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4046 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 4047 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 4048 TheSelect->getOperand(0), LLD->getBasePtr(), 4049 RLD->getBasePtr()); 4050 } 4051 } else { 4052 // Check that the condition doesn't reach either load. If so, folding 4053 // this will induce a cycle into the DAG. 4054 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4055 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 4056 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 4057 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 4058 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 4059 TheSelect->getOperand(0), 4060 TheSelect->getOperand(1), 4061 LLD->getBasePtr(), RLD->getBasePtr(), 4062 TheSelect->getOperand(4)); 4063 } 4064 } 4065 4066 if (Addr.Val) { 4067 SDOperand Load; 4068 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 4069 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 4070 Addr,LLD->getSrcValue(), 4071 LLD->getSrcValueOffset(), 4072 LLD->isVolatile(), 4073 LLD->getAlignment()); 4074 else { 4075 Load = DAG.getExtLoad(LLD->getExtensionType(), 4076 TheSelect->getValueType(0), 4077 LLD->getChain(), Addr, LLD->getSrcValue(), 4078 LLD->getSrcValueOffset(), 4079 LLD->getLoadedVT(), 4080 LLD->isVolatile(), 4081 LLD->getAlignment()); 4082 } 4083 // Users of the select now use the result of the load. 4084 CombineTo(TheSelect, Load); 4085 4086 // Users of the old loads now use the new load's chain. We know the 4087 // old-load value is dead now. 4088 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 4089 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 4090 return true; 4091 } 4092 } 4093 } 4094 } 4095 4096 return false; 4097} 4098 4099SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 4100 SDOperand N2, SDOperand N3, 4101 ISD::CondCode CC, bool NotExtCompare) { 4102 4103 MVT::ValueType VT = N2.getValueType(); 4104 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 4105 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 4106 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 4107 4108 // Determine if the condition we're dealing with is constant 4109 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 4110 if (SCC.Val) AddToWorkList(SCC.Val); 4111 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 4112 4113 // fold select_cc true, x, y -> x 4114 if (SCCC && SCCC->getValue()) 4115 return N2; 4116 // fold select_cc false, x, y -> y 4117 if (SCCC && SCCC->getValue() == 0) 4118 return N3; 4119 4120 // Check to see if we can simplify the select into an fabs node 4121 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 4122 // Allow either -0.0 or 0.0 4123 if (CFP->getValue() == 0.0) { 4124 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 4125 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 4126 N0 == N2 && N3.getOpcode() == ISD::FNEG && 4127 N2 == N3.getOperand(0)) 4128 return DAG.getNode(ISD::FABS, VT, N0); 4129 4130 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 4131 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 4132 N0 == N3 && N2.getOpcode() == ISD::FNEG && 4133 N2.getOperand(0) == N3) 4134 return DAG.getNode(ISD::FABS, VT, N3); 4135 } 4136 } 4137 4138 // Check to see if we can perform the "gzip trick", transforming 4139 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 4140 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 4141 MVT::isInteger(N0.getValueType()) && 4142 MVT::isInteger(N2.getValueType()) && 4143 (N1C->isNullValue() || // (a < 0) ? b : 0 4144 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 4145 MVT::ValueType XType = N0.getValueType(); 4146 MVT::ValueType AType = N2.getValueType(); 4147 if (XType >= AType) { 4148 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 4149 // single-bit constant. 4150 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 4151 unsigned ShCtV = Log2_64(N2C->getValue()); 4152 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 4153 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 4154 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 4155 AddToWorkList(Shift.Val); 4156 if (XType > AType) { 4157 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4158 AddToWorkList(Shift.Val); 4159 } 4160 return DAG.getNode(ISD::AND, AType, Shift, N2); 4161 } 4162 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4163 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4164 TLI.getShiftAmountTy())); 4165 AddToWorkList(Shift.Val); 4166 if (XType > AType) { 4167 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4168 AddToWorkList(Shift.Val); 4169 } 4170 return DAG.getNode(ISD::AND, AType, Shift, N2); 4171 } 4172 } 4173 4174 // fold select C, 16, 0 -> shl C, 4 4175 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 4176 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 4177 4178 // If the caller doesn't want us to simplify this into a zext of a compare, 4179 // don't do it. 4180 if (NotExtCompare && N2C->getValue() == 1) 4181 return SDOperand(); 4182 4183 // Get a SetCC of the condition 4184 // FIXME: Should probably make sure that setcc is legal if we ever have a 4185 // target where it isn't. 4186 SDOperand Temp, SCC; 4187 // cast from setcc result type to select result type 4188 if (AfterLegalize) { 4189 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4190 if (N2.getValueType() < SCC.getValueType()) 4191 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 4192 else 4193 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4194 } else { 4195 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 4196 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4197 } 4198 AddToWorkList(SCC.Val); 4199 AddToWorkList(Temp.Val); 4200 4201 if (N2C->getValue() == 1) 4202 return Temp; 4203 // shl setcc result by log2 n2c 4204 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 4205 DAG.getConstant(Log2_64(N2C->getValue()), 4206 TLI.getShiftAmountTy())); 4207 } 4208 4209 // Check to see if this is the equivalent of setcc 4210 // FIXME: Turn all of these into setcc if setcc if setcc is legal 4211 // otherwise, go ahead with the folds. 4212 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 4213 MVT::ValueType XType = N0.getValueType(); 4214 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 4215 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4216 if (Res.getValueType() != VT) 4217 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 4218 return Res; 4219 } 4220 4221 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 4222 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 4223 TLI.isOperationLegal(ISD::CTLZ, XType)) { 4224 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 4225 return DAG.getNode(ISD::SRL, XType, Ctlz, 4226 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 4227 TLI.getShiftAmountTy())); 4228 } 4229 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 4230 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 4231 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 4232 N0); 4233 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 4234 DAG.getConstant(~0ULL, XType)); 4235 return DAG.getNode(ISD::SRL, XType, 4236 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 4237 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4238 TLI.getShiftAmountTy())); 4239 } 4240 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 4241 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 4242 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 4243 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4244 TLI.getShiftAmountTy())); 4245 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 4246 } 4247 } 4248 4249 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 4250 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4251 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 4252 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 4253 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 4254 MVT::ValueType XType = N0.getValueType(); 4255 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4256 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4257 TLI.getShiftAmountTy())); 4258 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4259 AddToWorkList(Shift.Val); 4260 AddToWorkList(Add.Val); 4261 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4262 } 4263 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 4264 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4265 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 4266 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 4267 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 4268 MVT::ValueType XType = N0.getValueType(); 4269 if (SubC->isNullValue() && MVT::isInteger(XType)) { 4270 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4271 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4272 TLI.getShiftAmountTy())); 4273 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4274 AddToWorkList(Shift.Val); 4275 AddToWorkList(Add.Val); 4276 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4277 } 4278 } 4279 } 4280 4281 return SDOperand(); 4282} 4283 4284/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 4285SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 4286 SDOperand N1, ISD::CondCode Cond, 4287 bool foldBooleans) { 4288 TargetLowering::DAGCombinerInfo 4289 DagCombineInfo(DAG, !AfterLegalize, false, this); 4290 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 4291} 4292 4293/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 4294/// return a DAG expression to select that will generate the same value by 4295/// multiplying by a magic number. See: 4296/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4297SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 4298 std::vector<SDNode*> Built; 4299 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 4300 4301 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4302 ii != ee; ++ii) 4303 AddToWorkList(*ii); 4304 return S; 4305} 4306 4307/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 4308/// return a DAG expression to select that will generate the same value by 4309/// multiplying by a magic number. See: 4310/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4311SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 4312 std::vector<SDNode*> Built; 4313 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 4314 4315 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4316 ii != ee; ++ii) 4317 AddToWorkList(*ii); 4318 return S; 4319} 4320 4321/// FindBaseOffset - Return true if base is known not to alias with anything 4322/// but itself. Provides base object and offset as results. 4323static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 4324 // Assume it is a primitive operation. 4325 Base = Ptr; Offset = 0; 4326 4327 // If it's an adding a simple constant then integrate the offset. 4328 if (Base.getOpcode() == ISD::ADD) { 4329 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 4330 Base = Base.getOperand(0); 4331 Offset += C->getValue(); 4332 } 4333 } 4334 4335 // If it's any of the following then it can't alias with anything but itself. 4336 return isa<FrameIndexSDNode>(Base) || 4337 isa<ConstantPoolSDNode>(Base) || 4338 isa<GlobalAddressSDNode>(Base); 4339} 4340 4341/// isAlias - Return true if there is any possibility that the two addresses 4342/// overlap. 4343bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 4344 const Value *SrcValue1, int SrcValueOffset1, 4345 SDOperand Ptr2, int64_t Size2, 4346 const Value *SrcValue2, int SrcValueOffset2) 4347{ 4348 // If they are the same then they must be aliases. 4349 if (Ptr1 == Ptr2) return true; 4350 4351 // Gather base node and offset information. 4352 SDOperand Base1, Base2; 4353 int64_t Offset1, Offset2; 4354 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 4355 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 4356 4357 // If they have a same base address then... 4358 if (Base1 == Base2) { 4359 // Check to see if the addresses overlap. 4360 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 4361 } 4362 4363 // If we know both bases then they can't alias. 4364 if (KnownBase1 && KnownBase2) return false; 4365 4366 if (CombinerGlobalAA) { 4367 // Use alias analysis information. 4368 int Overlap1 = Size1 + SrcValueOffset1 + Offset1; 4369 int Overlap2 = Size2 + SrcValueOffset2 + Offset2; 4370 AliasAnalysis::AliasResult AAResult = 4371 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 4372 if (AAResult == AliasAnalysis::NoAlias) 4373 return false; 4374 } 4375 4376 // Otherwise we have to assume they alias. 4377 return true; 4378} 4379 4380/// FindAliasInfo - Extracts the relevant alias information from the memory 4381/// node. Returns true if the operand was a load. 4382bool DAGCombiner::FindAliasInfo(SDNode *N, 4383 SDOperand &Ptr, int64_t &Size, 4384 const Value *&SrcValue, int &SrcValueOffset) { 4385 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4386 Ptr = LD->getBasePtr(); 4387 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3; 4388 SrcValue = LD->getSrcValue(); 4389 SrcValueOffset = LD->getSrcValueOffset(); 4390 return true; 4391 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4392 Ptr = ST->getBasePtr(); 4393 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3; 4394 SrcValue = ST->getSrcValue(); 4395 SrcValueOffset = ST->getSrcValueOffset(); 4396 } else { 4397 assert(0 && "FindAliasInfo expected a memory operand"); 4398 } 4399 4400 return false; 4401} 4402 4403/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 4404/// looking for aliasing nodes and adding them to the Aliases vector. 4405void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 4406 SmallVector<SDOperand, 8> &Aliases) { 4407 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 4408 std::set<SDNode *> Visited; // Visited node set. 4409 4410 // Get alias information for node. 4411 SDOperand Ptr; 4412 int64_t Size; 4413 const Value *SrcValue; 4414 int SrcValueOffset; 4415 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 4416 4417 // Starting off. 4418 Chains.push_back(OriginalChain); 4419 4420 // Look at each chain and determine if it is an alias. If so, add it to the 4421 // aliases list. If not, then continue up the chain looking for the next 4422 // candidate. 4423 while (!Chains.empty()) { 4424 SDOperand Chain = Chains.back(); 4425 Chains.pop_back(); 4426 4427 // Don't bother if we've been before. 4428 if (Visited.find(Chain.Val) != Visited.end()) continue; 4429 Visited.insert(Chain.Val); 4430 4431 switch (Chain.getOpcode()) { 4432 case ISD::EntryToken: 4433 // Entry token is ideal chain operand, but handled in FindBetterChain. 4434 break; 4435 4436 case ISD::LOAD: 4437 case ISD::STORE: { 4438 // Get alias information for Chain. 4439 SDOperand OpPtr; 4440 int64_t OpSize; 4441 const Value *OpSrcValue; 4442 int OpSrcValueOffset; 4443 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 4444 OpSrcValue, OpSrcValueOffset); 4445 4446 // If chain is alias then stop here. 4447 if (!(IsLoad && IsOpLoad) && 4448 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 4449 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 4450 Aliases.push_back(Chain); 4451 } else { 4452 // Look further up the chain. 4453 Chains.push_back(Chain.getOperand(0)); 4454 // Clean up old chain. 4455 AddToWorkList(Chain.Val); 4456 } 4457 break; 4458 } 4459 4460 case ISD::TokenFactor: 4461 // We have to check each of the operands of the token factor, so we queue 4462 // then up. Adding the operands to the queue (stack) in reverse order 4463 // maintains the original order and increases the likelihood that getNode 4464 // will find a matching token factor (CSE.) 4465 for (unsigned n = Chain.getNumOperands(); n;) 4466 Chains.push_back(Chain.getOperand(--n)); 4467 // Eliminate the token factor if we can. 4468 AddToWorkList(Chain.Val); 4469 break; 4470 4471 default: 4472 // For all other instructions we will just have to take what we can get. 4473 Aliases.push_back(Chain); 4474 break; 4475 } 4476 } 4477} 4478 4479/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 4480/// for a better chain (aliasing node.) 4481SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 4482 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 4483 4484 // Accumulate all the aliases to this node. 4485 GatherAllAliases(N, OldChain, Aliases); 4486 4487 if (Aliases.size() == 0) { 4488 // If no operands then chain to entry token. 4489 return DAG.getEntryNode(); 4490 } else if (Aliases.size() == 1) { 4491 // If a single operand then chain to it. We don't need to revisit it. 4492 return Aliases[0]; 4493 } 4494 4495 // Construct a custom tailored token factor. 4496 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4497 &Aliases[0], Aliases.size()); 4498 4499 // Make sure the old chain gets cleaned up. 4500 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 4501 4502 return NewChain; 4503} 4504 4505// SelectionDAG::Combine - This is the entry point for the file. 4506// 4507void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 4508 if (!RunningAfterLegalize && ViewDAGCombine1) 4509 viewGraph(); 4510 if (RunningAfterLegalize && ViewDAGCombine2) 4511 viewGraph(); 4512 /// run - This is the main entry point to this class. 4513 /// 4514 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 4515} 4516