DAGCombiner.cpp revision 71d9ebcbc1c74848372e11c96989ede974b2366d
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: make truncate see through SIGN_EXTEND and AND 26// FIXME: divide by zero is currently left unfolded. do we want to turn this 27// into an undef? 28// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 29// 30//===----------------------------------------------------------------------===// 31 32#define DEBUG_TYPE "dagcombine" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Target/TargetLowering.h" 38#include <algorithm> 39#include <cmath> 40#include <iostream> 41using namespace llvm; 42 43namespace { 44 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined"); 45 46 class DAGCombiner { 47 SelectionDAG &DAG; 48 TargetLowering &TLI; 49 bool AfterLegalize; 50 51 // Worklist of all of the nodes that need to be simplified. 52 std::vector<SDNode*> WorkList; 53 54 /// AddUsersToWorkList - When an instruction is simplified, add all users of 55 /// the instruction to the work lists because they might get more simplified 56 /// now. 57 /// 58 void AddUsersToWorkList(SDNode *N) { 59 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 60 UI != UE; ++UI) 61 WorkList.push_back(*UI); 62 } 63 64 /// removeFromWorkList - remove all instances of N from the worklist. 65 void removeFromWorkList(SDNode *N) { 66 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 67 WorkList.end()); 68 } 69 70 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 71 ++NodesCombined; 72 DEBUG(std::cerr << "\nReplacing "; N->dump(); 73 std::cerr << "\nWith: "; To[0].Val->dump(); 74 std::cerr << " and " << To.size()-1 << " other values\n"); 75 std::vector<SDNode*> NowDead; 76 DAG.ReplaceAllUsesWith(N, To, &NowDead); 77 78 // Push the new nodes and any users onto the worklist 79 for (unsigned i = 0, e = To.size(); i != e; ++i) { 80 WorkList.push_back(To[i].Val); 81 AddUsersToWorkList(To[i].Val); 82 } 83 84 // Nodes can end up on the worklist more than once. Make sure we do 85 // not process a node that has been replaced. 86 removeFromWorkList(N); 87 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 88 removeFromWorkList(NowDead[i]); 89 90 // Finally, since the node is now dead, remove it from the graph. 91 DAG.DeleteNode(N); 92 return SDOperand(N, 0); 93 } 94 95 /// SimplifyDemandedBits - Check the specified integer node value to see if 96 /// it can be simplified or if things is uses can be simplified by bit 97 /// propagation. If so, return true. 98 bool SimplifyDemandedBits(SDOperand Op) { 99 TargetLowering::TargetLoweringOpt TLO(DAG); 100 uint64_t KnownZero, KnownOne; 101 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 102 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 103 return false; 104 105 // Revisit the node. 106 WorkList.push_back(Op.Val); 107 108 // Replace the old value with the new one. 109 ++NodesCombined; 110 DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump(); 111 std::cerr << "\nWith: "; TLO.New.Val->dump()); 112 113 std::vector<SDNode*> NowDead; 114 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 115 116 // Push the new node and any (possibly new) users onto the worklist. 117 WorkList.push_back(TLO.New.Val); 118 AddUsersToWorkList(TLO.New.Val); 119 120 // Nodes can end up on the worklist more than once. Make sure we do 121 // not process a node that has been replaced. 122 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 123 removeFromWorkList(NowDead[i]); 124 125 // Finally, if the node is now dead, remove it from the graph. The node 126 // may not be dead if the replacement process recursively simplified to 127 // something else needing this node. 128 if (TLO.Old.Val->use_empty()) { 129 removeFromWorkList(TLO.Old.Val); 130 DAG.DeleteNode(TLO.Old.Val); 131 } 132 return true; 133 } 134 135 SDOperand CombineTo(SDNode *N, SDOperand Res) { 136 std::vector<SDOperand> To; 137 To.push_back(Res); 138 return CombineTo(N, To); 139 } 140 141 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 142 std::vector<SDOperand> To; 143 To.push_back(Res0); 144 To.push_back(Res1); 145 return CombineTo(N, To); 146 } 147 148 /// visit - call the node-specific routine that knows how to fold each 149 /// particular type of node. 150 SDOperand visit(SDNode *N); 151 152 // Visitation implementation - Implement dag node combining for different 153 // node types. The semantics are as follows: 154 // Return Value: 155 // SDOperand.Val == 0 - No change was made 156 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 157 // otherwise - N should be replaced by the returned Operand. 158 // 159 SDOperand visitTokenFactor(SDNode *N); 160 SDOperand visitADD(SDNode *N); 161 SDOperand visitSUB(SDNode *N); 162 SDOperand visitMUL(SDNode *N); 163 SDOperand visitSDIV(SDNode *N); 164 SDOperand visitUDIV(SDNode *N); 165 SDOperand visitSREM(SDNode *N); 166 SDOperand visitUREM(SDNode *N); 167 SDOperand visitMULHU(SDNode *N); 168 SDOperand visitMULHS(SDNode *N); 169 SDOperand visitAND(SDNode *N); 170 SDOperand visitOR(SDNode *N); 171 SDOperand visitXOR(SDNode *N); 172 SDOperand visitSHL(SDNode *N); 173 SDOperand visitSRA(SDNode *N); 174 SDOperand visitSRL(SDNode *N); 175 SDOperand visitCTLZ(SDNode *N); 176 SDOperand visitCTTZ(SDNode *N); 177 SDOperand visitCTPOP(SDNode *N); 178 SDOperand visitSELECT(SDNode *N); 179 SDOperand visitSELECT_CC(SDNode *N); 180 SDOperand visitSETCC(SDNode *N); 181 SDOperand visitSIGN_EXTEND(SDNode *N); 182 SDOperand visitZERO_EXTEND(SDNode *N); 183 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 184 SDOperand visitTRUNCATE(SDNode *N); 185 SDOperand visitBIT_CONVERT(SDNode *N); 186 SDOperand visitFADD(SDNode *N); 187 SDOperand visitFSUB(SDNode *N); 188 SDOperand visitFMUL(SDNode *N); 189 SDOperand visitFDIV(SDNode *N); 190 SDOperand visitFREM(SDNode *N); 191 SDOperand visitSINT_TO_FP(SDNode *N); 192 SDOperand visitUINT_TO_FP(SDNode *N); 193 SDOperand visitFP_TO_SINT(SDNode *N); 194 SDOperand visitFP_TO_UINT(SDNode *N); 195 SDOperand visitFP_ROUND(SDNode *N); 196 SDOperand visitFP_ROUND_INREG(SDNode *N); 197 SDOperand visitFP_EXTEND(SDNode *N); 198 SDOperand visitFNEG(SDNode *N); 199 SDOperand visitFABS(SDNode *N); 200 SDOperand visitBRCOND(SDNode *N); 201 SDOperand visitBRCONDTWOWAY(SDNode *N); 202 SDOperand visitBR_CC(SDNode *N); 203 SDOperand visitBRTWOWAY_CC(SDNode *N); 204 SDOperand visitLOAD(SDNode *N); 205 SDOperand visitSTORE(SDNode *N); 206 207 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 208 209 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 210 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 211 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 212 SDOperand N3, ISD::CondCode CC); 213 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 214 ISD::CondCode Cond, bool foldBooleans = true); 215 216 SDOperand BuildSDIV(SDNode *N); 217 SDOperand BuildUDIV(SDNode *N); 218public: 219 DAGCombiner(SelectionDAG &D) 220 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 221 222 /// Run - runs the dag combiner on all nodes in the work list 223 void Run(bool RunningAfterLegalize); 224 }; 225} 226 227struct ms { 228 int64_t m; // magic number 229 int64_t s; // shift amount 230}; 231 232struct mu { 233 uint64_t m; // magic number 234 int64_t a; // add indicator 235 int64_t s; // shift amount 236}; 237 238/// magic - calculate the magic numbers required to codegen an integer sdiv as 239/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 240/// or -1. 241static ms magic32(int32_t d) { 242 int32_t p; 243 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 244 const uint32_t two31 = 0x80000000U; 245 struct ms mag; 246 247 ad = abs(d); 248 t = two31 + ((uint32_t)d >> 31); 249 anc = t - 1 - t%ad; // absolute value of nc 250 p = 31; // initialize p 251 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 252 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 253 q2 = two31/ad; // initialize q2 = 2p/abs(d) 254 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 255 do { 256 p = p + 1; 257 q1 = 2*q1; // update q1 = 2p/abs(nc) 258 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 259 if (r1 >= anc) { // must be unsigned comparison 260 q1 = q1 + 1; 261 r1 = r1 - anc; 262 } 263 q2 = 2*q2; // update q2 = 2p/abs(d) 264 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 265 if (r2 >= ad) { // must be unsigned comparison 266 q2 = q2 + 1; 267 r2 = r2 - ad; 268 } 269 delta = ad - r2; 270 } while (q1 < delta || (q1 == delta && r1 == 0)); 271 272 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 273 if (d < 0) mag.m = -mag.m; // resulting magic number 274 mag.s = p - 32; // resulting shift 275 return mag; 276} 277 278/// magicu - calculate the magic numbers required to codegen an integer udiv as 279/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 280static mu magicu32(uint32_t d) { 281 int32_t p; 282 uint32_t nc, delta, q1, r1, q2, r2; 283 struct mu magu; 284 magu.a = 0; // initialize "add" indicator 285 nc = - 1 - (-d)%d; 286 p = 31; // initialize p 287 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 288 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 289 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 290 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 291 do { 292 p = p + 1; 293 if (r1 >= nc - r1 ) { 294 q1 = 2*q1 + 1; // update q1 295 r1 = 2*r1 - nc; // update r1 296 } 297 else { 298 q1 = 2*q1; // update q1 299 r1 = 2*r1; // update r1 300 } 301 if (r2 + 1 >= d - r2) { 302 if (q2 >= 0x7FFFFFFF) magu.a = 1; 303 q2 = 2*q2 + 1; // update q2 304 r2 = 2*r2 + 1 - d; // update r2 305 } 306 else { 307 if (q2 >= 0x80000000) magu.a = 1; 308 q2 = 2*q2; // update q2 309 r2 = 2*r2 + 1; // update r2 310 } 311 delta = d - 1 - r2; 312 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 313 magu.m = q2 + 1; // resulting magic number 314 magu.s = p - 32; // resulting shift 315 return magu; 316} 317 318/// magic - calculate the magic numbers required to codegen an integer sdiv as 319/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 320/// or -1. 321static ms magic64(int64_t d) { 322 int64_t p; 323 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 324 const uint64_t two63 = 9223372036854775808ULL; // 2^63 325 struct ms mag; 326 327 ad = d >= 0 ? d : -d; 328 t = two63 + ((uint64_t)d >> 63); 329 anc = t - 1 - t%ad; // absolute value of nc 330 p = 63; // initialize p 331 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 332 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 333 q2 = two63/ad; // initialize q2 = 2p/abs(d) 334 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 335 do { 336 p = p + 1; 337 q1 = 2*q1; // update q1 = 2p/abs(nc) 338 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 339 if (r1 >= anc) { // must be unsigned comparison 340 q1 = q1 + 1; 341 r1 = r1 - anc; 342 } 343 q2 = 2*q2; // update q2 = 2p/abs(d) 344 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 345 if (r2 >= ad) { // must be unsigned comparison 346 q2 = q2 + 1; 347 r2 = r2 - ad; 348 } 349 delta = ad - r2; 350 } while (q1 < delta || (q1 == delta && r1 == 0)); 351 352 mag.m = q2 + 1; 353 if (d < 0) mag.m = -mag.m; // resulting magic number 354 mag.s = p - 64; // resulting shift 355 return mag; 356} 357 358/// magicu - calculate the magic numbers required to codegen an integer udiv as 359/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 360static mu magicu64(uint64_t d) 361{ 362 int64_t p; 363 uint64_t nc, delta, q1, r1, q2, r2; 364 struct mu magu; 365 magu.a = 0; // initialize "add" indicator 366 nc = - 1 - (-d)%d; 367 p = 63; // initialize p 368 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 369 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 370 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 371 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 372 do { 373 p = p + 1; 374 if (r1 >= nc - r1 ) { 375 q1 = 2*q1 + 1; // update q1 376 r1 = 2*r1 - nc; // update r1 377 } 378 else { 379 q1 = 2*q1; // update q1 380 r1 = 2*r1; // update r1 381 } 382 if (r2 + 1 >= d - r2) { 383 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 384 q2 = 2*q2 + 1; // update q2 385 r2 = 2*r2 + 1 - d; // update r2 386 } 387 else { 388 if (q2 >= 0x8000000000000000ull) magu.a = 1; 389 q2 = 2*q2; // update q2 390 r2 = 2*r2 + 1; // update r2 391 } 392 delta = d - 1 - r2; 393 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 394 magu.m = q2 + 1; // resulting magic number 395 magu.s = p - 64; // resulting shift 396 return magu; 397} 398 399// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 400// that selects between the values 1 and 0, making it equivalent to a setcc. 401// Also, set the incoming LHS, RHS, and CC references to the appropriate 402// nodes based on the type of node we are checking. This simplifies life a 403// bit for the callers. 404static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 405 SDOperand &CC) { 406 if (N.getOpcode() == ISD::SETCC) { 407 LHS = N.getOperand(0); 408 RHS = N.getOperand(1); 409 CC = N.getOperand(2); 410 return true; 411 } 412 if (N.getOpcode() == ISD::SELECT_CC && 413 N.getOperand(2).getOpcode() == ISD::Constant && 414 N.getOperand(3).getOpcode() == ISD::Constant && 415 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 416 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 417 LHS = N.getOperand(0); 418 RHS = N.getOperand(1); 419 CC = N.getOperand(4); 420 return true; 421 } 422 return false; 423} 424 425// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 426// one use. If this is true, it allows the users to invert the operation for 427// free when it is profitable to do so. 428static bool isOneUseSetCC(SDOperand N) { 429 SDOperand N0, N1, N2; 430 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 431 return true; 432 return false; 433} 434 435// FIXME: This should probably go in the ISD class rather than being duplicated 436// in several files. 437static bool isCommutativeBinOp(unsigned Opcode) { 438 switch (Opcode) { 439 case ISD::ADD: 440 case ISD::MUL: 441 case ISD::AND: 442 case ISD::OR: 443 case ISD::XOR: return true; 444 default: return false; // FIXME: Need commutative info for user ops! 445 } 446} 447 448SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 449 MVT::ValueType VT = N0.getValueType(); 450 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 451 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 452 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 453 if (isa<ConstantSDNode>(N1)) { 454 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 455 WorkList.push_back(OpNode.Val); 456 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 457 } else if (N0.hasOneUse()) { 458 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 459 WorkList.push_back(OpNode.Val); 460 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 461 } 462 } 463 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 464 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 465 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 466 if (isa<ConstantSDNode>(N0)) { 467 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 468 WorkList.push_back(OpNode.Val); 469 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 470 } else if (N1.hasOneUse()) { 471 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 472 WorkList.push_back(OpNode.Val); 473 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 474 } 475 } 476 return SDOperand(); 477} 478 479void DAGCombiner::Run(bool RunningAfterLegalize) { 480 // set the instance variable, so that the various visit routines may use it. 481 AfterLegalize = RunningAfterLegalize; 482 483 // Add all the dag nodes to the worklist. 484 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 485 E = DAG.allnodes_end(); I != E; ++I) 486 WorkList.push_back(I); 487 488 // Create a dummy node (which is not added to allnodes), that adds a reference 489 // to the root node, preventing it from being deleted, and tracking any 490 // changes of the root. 491 HandleSDNode Dummy(DAG.getRoot()); 492 493 // while the worklist isn't empty, inspect the node on the end of it and 494 // try and combine it. 495 while (!WorkList.empty()) { 496 SDNode *N = WorkList.back(); 497 WorkList.pop_back(); 498 499 // If N has no uses, it is dead. Make sure to revisit all N's operands once 500 // N is deleted from the DAG, since they too may now be dead or may have a 501 // reduced number of uses, allowing other xforms. 502 if (N->use_empty() && N != &Dummy) { 503 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 504 WorkList.push_back(N->getOperand(i).Val); 505 506 removeFromWorkList(N); 507 DAG.DeleteNode(N); 508 continue; 509 } 510 511 SDOperand RV = visit(N); 512 if (RV.Val) { 513 ++NodesCombined; 514 // If we get back the same node we passed in, rather than a new node or 515 // zero, we know that the node must have defined multiple values and 516 // CombineTo was used. Since CombineTo takes care of the worklist 517 // mechanics for us, we have no work to do in this case. 518 if (RV.Val != N) { 519 DEBUG(std::cerr << "\nReplacing "; N->dump(); 520 std::cerr << "\nWith: "; RV.Val->dump(); 521 std::cerr << '\n'); 522 std::vector<SDNode*> NowDead; 523 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead); 524 525 // Push the new node and any users onto the worklist 526 WorkList.push_back(RV.Val); 527 AddUsersToWorkList(RV.Val); 528 529 // Nodes can end up on the worklist more than once. Make sure we do 530 // not process a node that has been replaced. 531 removeFromWorkList(N); 532 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 533 removeFromWorkList(NowDead[i]); 534 535 // Finally, since the node is now dead, remove it from the graph. 536 DAG.DeleteNode(N); 537 } 538 } 539 } 540 541 // If the root changed (e.g. it was a dead load, update the root). 542 DAG.setRoot(Dummy.getValue()); 543} 544 545SDOperand DAGCombiner::visit(SDNode *N) { 546 switch(N->getOpcode()) { 547 default: break; 548 case ISD::TokenFactor: return visitTokenFactor(N); 549 case ISD::ADD: return visitADD(N); 550 case ISD::SUB: return visitSUB(N); 551 case ISD::MUL: return visitMUL(N); 552 case ISD::SDIV: return visitSDIV(N); 553 case ISD::UDIV: return visitUDIV(N); 554 case ISD::SREM: return visitSREM(N); 555 case ISD::UREM: return visitUREM(N); 556 case ISD::MULHU: return visitMULHU(N); 557 case ISD::MULHS: return visitMULHS(N); 558 case ISD::AND: return visitAND(N); 559 case ISD::OR: return visitOR(N); 560 case ISD::XOR: return visitXOR(N); 561 case ISD::SHL: return visitSHL(N); 562 case ISD::SRA: return visitSRA(N); 563 case ISD::SRL: return visitSRL(N); 564 case ISD::CTLZ: return visitCTLZ(N); 565 case ISD::CTTZ: return visitCTTZ(N); 566 case ISD::CTPOP: return visitCTPOP(N); 567 case ISD::SELECT: return visitSELECT(N); 568 case ISD::SELECT_CC: return visitSELECT_CC(N); 569 case ISD::SETCC: return visitSETCC(N); 570 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 571 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 572 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 573 case ISD::TRUNCATE: return visitTRUNCATE(N); 574 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 575 case ISD::FADD: return visitFADD(N); 576 case ISD::FSUB: return visitFSUB(N); 577 case ISD::FMUL: return visitFMUL(N); 578 case ISD::FDIV: return visitFDIV(N); 579 case ISD::FREM: return visitFREM(N); 580 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 581 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 582 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 583 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 584 case ISD::FP_ROUND: return visitFP_ROUND(N); 585 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 586 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 587 case ISD::FNEG: return visitFNEG(N); 588 case ISD::FABS: return visitFABS(N); 589 case ISD::BRCOND: return visitBRCOND(N); 590 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N); 591 case ISD::BR_CC: return visitBR_CC(N); 592 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N); 593 case ISD::LOAD: return visitLOAD(N); 594 case ISD::STORE: return visitSTORE(N); 595 } 596 return SDOperand(); 597} 598 599SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 600 std::vector<SDOperand> Ops; 601 bool Changed = false; 602 603 // If the token factor has two operands and one is the entry token, replace 604 // the token factor with the other operand. 605 if (N->getNumOperands() == 2) { 606 if (N->getOperand(0).getOpcode() == ISD::EntryToken) 607 return N->getOperand(1); 608 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 609 return N->getOperand(0); 610 } 611 612 // fold (tokenfactor (tokenfactor)) -> tokenfactor 613 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 614 SDOperand Op = N->getOperand(i); 615 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 616 Changed = true; 617 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 618 Ops.push_back(Op.getOperand(j)); 619 } else { 620 Ops.push_back(Op); 621 } 622 } 623 if (Changed) 624 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 625 return SDOperand(); 626} 627 628SDOperand DAGCombiner::visitADD(SDNode *N) { 629 SDOperand N0 = N->getOperand(0); 630 SDOperand N1 = N->getOperand(1); 631 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 632 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 633 MVT::ValueType VT = N0.getValueType(); 634 635 // fold (add c1, c2) -> c1+c2 636 if (N0C && N1C) 637 return DAG.getNode(ISD::ADD, VT, N0, N1); 638 // canonicalize constant to RHS 639 if (N0C && !N1C) 640 return DAG.getNode(ISD::ADD, VT, N1, N0); 641 // fold (add x, 0) -> x 642 if (N1C && N1C->isNullValue()) 643 return N0; 644 // fold ((c1-A)+c2) -> (c1+c2)-A 645 if (N1C && N0.getOpcode() == ISD::SUB) 646 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 647 return DAG.getNode(ISD::SUB, VT, 648 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 649 N0.getOperand(1)); 650 // reassociate add 651 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 652 if (RADD.Val != 0) 653 return RADD; 654 // fold ((0-A) + B) -> B-A 655 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 656 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 657 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 658 // fold (A + (0-B)) -> A-B 659 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 660 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 661 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 662 // fold (A+(B-A)) -> B 663 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 664 return N1.getOperand(0); 665 // 666 if (SimplifyDemandedBits(SDOperand(N, 0))) 667 return SDOperand(); 668 return SDOperand(); 669} 670 671SDOperand DAGCombiner::visitSUB(SDNode *N) { 672 SDOperand N0 = N->getOperand(0); 673 SDOperand N1 = N->getOperand(1); 674 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 675 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 676 MVT::ValueType VT = N0.getValueType(); 677 678 // fold (sub x, x) -> 0 679 if (N0 == N1) 680 return DAG.getConstant(0, N->getValueType(0)); 681 // fold (sub c1, c2) -> c1-c2 682 if (N0C && N1C) 683 return DAG.getNode(ISD::SUB, VT, N0, N1); 684 // fold (sub x, c) -> (add x, -c) 685 if (N1C) 686 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 687 // fold (A+B)-A -> B 688 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 689 return N0.getOperand(1); 690 // fold (A+B)-B -> A 691 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 692 return N0.getOperand(0); 693 return SDOperand(); 694} 695 696SDOperand DAGCombiner::visitMUL(SDNode *N) { 697 SDOperand N0 = N->getOperand(0); 698 SDOperand N1 = N->getOperand(1); 699 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 700 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 701 MVT::ValueType VT = N0.getValueType(); 702 703 // fold (mul c1, c2) -> c1*c2 704 if (N0C && N1C) 705 return DAG.getNode(ISD::MUL, VT, N0, N1); 706 // canonicalize constant to RHS 707 if (N0C && !N1C) 708 return DAG.getNode(ISD::MUL, VT, N1, N0); 709 // fold (mul x, 0) -> 0 710 if (N1C && N1C->isNullValue()) 711 return N1; 712 // fold (mul x, -1) -> 0-x 713 if (N1C && N1C->isAllOnesValue()) 714 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 715 // fold (mul x, (1 << c)) -> x << c 716 if (N1C && isPowerOf2_64(N1C->getValue())) 717 return DAG.getNode(ISD::SHL, VT, N0, 718 DAG.getConstant(Log2_64(N1C->getValue()), 719 TLI.getShiftAmountTy())); 720 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 721 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 722 // FIXME: If the input is something that is easily negated (e.g. a 723 // single-use add), we should put the negate there. 724 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 725 DAG.getNode(ISD::SHL, VT, N0, 726 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 727 TLI.getShiftAmountTy()))); 728 } 729 // reassociate mul 730 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 731 if (RMUL.Val != 0) 732 return RMUL; 733 return SDOperand(); 734} 735 736SDOperand DAGCombiner::visitSDIV(SDNode *N) { 737 SDOperand N0 = N->getOperand(0); 738 SDOperand N1 = N->getOperand(1); 739 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 740 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 741 MVT::ValueType VT = N->getValueType(0); 742 743 // fold (sdiv c1, c2) -> c1/c2 744 if (N0C && N1C && !N1C->isNullValue()) 745 return DAG.getNode(ISD::SDIV, VT, N0, N1); 746 // fold (sdiv X, 1) -> X 747 if (N1C && N1C->getSignExtended() == 1LL) 748 return N0; 749 // fold (sdiv X, -1) -> 0-X 750 if (N1C && N1C->isAllOnesValue()) 751 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 752 // If we know the sign bits of both operands are zero, strength reduce to a 753 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 754 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 755 if (TLI.MaskedValueIsZero(N1, SignBit) && 756 TLI.MaskedValueIsZero(N0, SignBit)) 757 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 758 // fold (sdiv X, pow2) -> simple ops after legalize 759 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 760 (isPowerOf2_64(N1C->getSignExtended()) || 761 isPowerOf2_64(-N1C->getSignExtended()))) { 762 // If dividing by powers of two is cheap, then don't perform the following 763 // fold. 764 if (TLI.isPow2DivCheap()) 765 return SDOperand(); 766 int64_t pow2 = N1C->getSignExtended(); 767 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 768 unsigned lg2 = Log2_64(abs2); 769 // Splat the sign bit into the register 770 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 771 DAG.getConstant(MVT::getSizeInBits(VT)-1, 772 TLI.getShiftAmountTy())); 773 WorkList.push_back(SGN.Val); 774 // Add (N0 < 0) ? abs2 - 1 : 0; 775 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 776 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 777 TLI.getShiftAmountTy())); 778 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 779 WorkList.push_back(SRL.Val); 780 WorkList.push_back(ADD.Val); // Divide by pow2 781 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 782 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 783 // If we're dividing by a positive value, we're done. Otherwise, we must 784 // negate the result. 785 if (pow2 > 0) 786 return SRA; 787 WorkList.push_back(SRA.Val); 788 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 789 } 790 // if integer divide is expensive and we satisfy the requirements, emit an 791 // alternate sequence. 792 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 793 !TLI.isIntDivCheap()) { 794 SDOperand Op = BuildSDIV(N); 795 if (Op.Val) return Op; 796 } 797 return SDOperand(); 798} 799 800SDOperand DAGCombiner::visitUDIV(SDNode *N) { 801 SDOperand N0 = N->getOperand(0); 802 SDOperand N1 = N->getOperand(1); 803 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 804 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 805 MVT::ValueType VT = N->getValueType(0); 806 807 // fold (udiv c1, c2) -> c1/c2 808 if (N0C && N1C && !N1C->isNullValue()) 809 return DAG.getNode(ISD::UDIV, VT, N0, N1); 810 // fold (udiv x, (1 << c)) -> x >>u c 811 if (N1C && isPowerOf2_64(N1C->getValue())) 812 return DAG.getNode(ISD::SRL, VT, N0, 813 DAG.getConstant(Log2_64(N1C->getValue()), 814 TLI.getShiftAmountTy())); 815 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 816 if (N1.getOpcode() == ISD::SHL) { 817 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 818 if (isPowerOf2_64(SHC->getValue())) { 819 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 820 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 821 DAG.getConstant(Log2_64(SHC->getValue()), 822 ADDVT)); 823 WorkList.push_back(Add.Val); 824 return DAG.getNode(ISD::SRL, VT, N0, Add); 825 } 826 } 827 } 828 // fold (udiv x, c) -> alternate 829 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 830 SDOperand Op = BuildUDIV(N); 831 if (Op.Val) return Op; 832 } 833 return SDOperand(); 834} 835 836SDOperand DAGCombiner::visitSREM(SDNode *N) { 837 SDOperand N0 = N->getOperand(0); 838 SDOperand N1 = N->getOperand(1); 839 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 840 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 841 MVT::ValueType VT = N->getValueType(0); 842 843 // fold (srem c1, c2) -> c1%c2 844 if (N0C && N1C && !N1C->isNullValue()) 845 return DAG.getNode(ISD::SREM, VT, N0, N1); 846 // If we know the sign bits of both operands are zero, strength reduce to a 847 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 848 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 849 if (TLI.MaskedValueIsZero(N1, SignBit) && 850 TLI.MaskedValueIsZero(N0, SignBit)) 851 return DAG.getNode(ISD::UREM, VT, N0, N1); 852 return SDOperand(); 853} 854 855SDOperand DAGCombiner::visitUREM(SDNode *N) { 856 SDOperand N0 = N->getOperand(0); 857 SDOperand N1 = N->getOperand(1); 858 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 859 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 860 MVT::ValueType VT = N->getValueType(0); 861 862 // fold (urem c1, c2) -> c1%c2 863 if (N0C && N1C && !N1C->isNullValue()) 864 return DAG.getNode(ISD::UREM, VT, N0, N1); 865 // fold (urem x, pow2) -> (and x, pow2-1) 866 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 867 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 868 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 869 if (N1.getOpcode() == ISD::SHL) { 870 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 871 if (isPowerOf2_64(SHC->getValue())) { 872 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 873 WorkList.push_back(Add.Val); 874 return DAG.getNode(ISD::AND, VT, N0, Add); 875 } 876 } 877 } 878 return SDOperand(); 879} 880 881SDOperand DAGCombiner::visitMULHS(SDNode *N) { 882 SDOperand N0 = N->getOperand(0); 883 SDOperand N1 = N->getOperand(1); 884 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 885 886 // fold (mulhs x, 0) -> 0 887 if (N1C && N1C->isNullValue()) 888 return N1; 889 // fold (mulhs x, 1) -> (sra x, size(x)-1) 890 if (N1C && N1C->getValue() == 1) 891 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 892 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 893 TLI.getShiftAmountTy())); 894 return SDOperand(); 895} 896 897SDOperand DAGCombiner::visitMULHU(SDNode *N) { 898 SDOperand N0 = N->getOperand(0); 899 SDOperand N1 = N->getOperand(1); 900 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 901 902 // fold (mulhu x, 0) -> 0 903 if (N1C && N1C->isNullValue()) 904 return N1; 905 // fold (mulhu x, 1) -> 0 906 if (N1C && N1C->getValue() == 1) 907 return DAG.getConstant(0, N0.getValueType()); 908 return SDOperand(); 909} 910 911SDOperand DAGCombiner::visitAND(SDNode *N) { 912 SDOperand N0 = N->getOperand(0); 913 SDOperand N1 = N->getOperand(1); 914 SDOperand LL, LR, RL, RR, CC0, CC1; 915 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 916 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 917 MVT::ValueType VT = N1.getValueType(); 918 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 919 920 // fold (and c1, c2) -> c1&c2 921 if (N0C && N1C) 922 return DAG.getNode(ISD::AND, VT, N0, N1); 923 // canonicalize constant to RHS 924 if (N0C && !N1C) 925 return DAG.getNode(ISD::AND, VT, N1, N0); 926 // fold (and x, -1) -> x 927 if (N1C && N1C->isAllOnesValue()) 928 return N0; 929 // if (and x, c) is known to be zero, return 0 930 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 931 return DAG.getConstant(0, VT); 932 // reassociate and 933 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 934 if (RAND.Val != 0) 935 return RAND; 936 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 937 if (N1C && N0.getOpcode() == ISD::OR) 938 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 939 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 940 return N1; 941 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 942 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 943 unsigned InBits = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 944 if (TLI.MaskedValueIsZero(N0.getOperand(0), 945 ~N1C->getValue() & ((1ULL << InBits)-1))) { 946 // We actually want to replace all uses of the any_extend with the 947 // zero_extend, to avoid duplicating things. This will later cause this 948 // AND to be folded. 949 CombineTo(N0.Val, DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 950 N0.getOperand(0))); 951 return SDOperand(); 952 } 953 } 954 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 955 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 956 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 957 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 958 959 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 960 MVT::isInteger(LL.getValueType())) { 961 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 962 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 963 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 964 WorkList.push_back(ORNode.Val); 965 return DAG.getSetCC(VT, ORNode, LR, Op1); 966 } 967 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 968 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 969 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 970 WorkList.push_back(ANDNode.Val); 971 return DAG.getSetCC(VT, ANDNode, LR, Op1); 972 } 973 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 974 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 975 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 976 WorkList.push_back(ORNode.Val); 977 return DAG.getSetCC(VT, ORNode, LR, Op1); 978 } 979 } 980 // canonicalize equivalent to ll == rl 981 if (LL == RR && LR == RL) { 982 Op1 = ISD::getSetCCSwappedOperands(Op1); 983 std::swap(RL, RR); 984 } 985 if (LL == RL && LR == RR) { 986 bool isInteger = MVT::isInteger(LL.getValueType()); 987 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 988 if (Result != ISD::SETCC_INVALID) 989 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 990 } 991 } 992 // fold (and (zext x), (zext y)) -> (zext (and x, y)) 993 if (N0.getOpcode() == ISD::ZERO_EXTEND && 994 N1.getOpcode() == ISD::ZERO_EXTEND && 995 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 996 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 997 N0.getOperand(0), N1.getOperand(0)); 998 WorkList.push_back(ANDNode.Val); 999 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode); 1000 } 1001 // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y)) 1002 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1003 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1004 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1005 N0.getOperand(1) == N1.getOperand(1)) { 1006 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 1007 N0.getOperand(0), N1.getOperand(0)); 1008 WorkList.push_back(ANDNode.Val); 1009 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1)); 1010 } 1011 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1012 // fold (and (sra)) -> (and (srl)) when possible. 1013 if (SimplifyDemandedBits(SDOperand(N, 0))) 1014 return SDOperand(); 1015 // fold (zext_inreg (extload x)) -> (zextload x) 1016 if (N0.getOpcode() == ISD::EXTLOAD) { 1017 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1018 // If we zero all the possible extended bits, then we can turn this into 1019 // a zextload if we are running before legalize or the operation is legal. 1020 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1021 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1022 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1023 N0.getOperand(1), N0.getOperand(2), 1024 EVT); 1025 WorkList.push_back(N); 1026 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1027 return SDOperand(); 1028 } 1029 } 1030 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1031 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) { 1032 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1033 // If we zero all the possible extended bits, then we can turn this into 1034 // a zextload if we are running before legalize or the operation is legal. 1035 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1036 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1037 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1038 N0.getOperand(1), N0.getOperand(2), 1039 EVT); 1040 WorkList.push_back(N); 1041 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1042 return SDOperand(); 1043 } 1044 } 1045 return SDOperand(); 1046} 1047 1048SDOperand DAGCombiner::visitOR(SDNode *N) { 1049 SDOperand N0 = N->getOperand(0); 1050 SDOperand N1 = N->getOperand(1); 1051 SDOperand LL, LR, RL, RR, CC0, CC1; 1052 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1053 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1054 MVT::ValueType VT = N1.getValueType(); 1055 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1056 1057 // fold (or c1, c2) -> c1|c2 1058 if (N0C && N1C) 1059 return DAG.getNode(ISD::OR, VT, N0, N1); 1060 // canonicalize constant to RHS 1061 if (N0C && !N1C) 1062 return DAG.getNode(ISD::OR, VT, N1, N0); 1063 // fold (or x, 0) -> x 1064 if (N1C && N1C->isNullValue()) 1065 return N0; 1066 // fold (or x, -1) -> -1 1067 if (N1C && N1C->isAllOnesValue()) 1068 return N1; 1069 // fold (or x, c) -> c iff (x & ~c) == 0 1070 if (N1C && 1071 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1072 return N1; 1073 // reassociate or 1074 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1075 if (ROR.Val != 0) 1076 return ROR; 1077 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1078 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1079 isa<ConstantSDNode>(N0.getOperand(1))) { 1080 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1081 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1082 N1), 1083 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1084 } 1085 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1086 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1087 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1088 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1089 1090 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1091 MVT::isInteger(LL.getValueType())) { 1092 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1093 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1094 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1095 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1096 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1097 WorkList.push_back(ORNode.Val); 1098 return DAG.getSetCC(VT, ORNode, LR, Op1); 1099 } 1100 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1101 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1102 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1103 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1104 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1105 WorkList.push_back(ANDNode.Val); 1106 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1107 } 1108 } 1109 // canonicalize equivalent to ll == rl 1110 if (LL == RR && LR == RL) { 1111 Op1 = ISD::getSetCCSwappedOperands(Op1); 1112 std::swap(RL, RR); 1113 } 1114 if (LL == RL && LR == RR) { 1115 bool isInteger = MVT::isInteger(LL.getValueType()); 1116 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1117 if (Result != ISD::SETCC_INVALID) 1118 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1119 } 1120 } 1121 // fold (or (zext x), (zext y)) -> (zext (or x, y)) 1122 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1123 N1.getOpcode() == ISD::ZERO_EXTEND && 1124 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1125 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 1126 N0.getOperand(0), N1.getOperand(0)); 1127 WorkList.push_back(ORNode.Val); 1128 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode); 1129 } 1130 // fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y)) 1131 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1132 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1133 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1134 N0.getOperand(1) == N1.getOperand(1)) { 1135 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 1136 N0.getOperand(0), N1.getOperand(0)); 1137 WorkList.push_back(ORNode.Val); 1138 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1139 } 1140 // canonicalize shl to left side in a shl/srl pair, to match rotate 1141 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 1142 std::swap(N0, N1); 1143 // check for rotl, rotr 1144 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL && 1145 N0.getOperand(0) == N1.getOperand(0) && 1146 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) { 1147 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1148 if (N0.getOperand(1).getOpcode() == ISD::Constant && 1149 N1.getOperand(1).getOpcode() == ISD::Constant) { 1150 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1151 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1152 if ((c1val + c2val) == OpSizeInBits) 1153 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1154 } 1155 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1156 if (N1.getOperand(1).getOpcode() == ISD::SUB && 1157 N0.getOperand(1) == N1.getOperand(1).getOperand(1)) 1158 if (ConstantSDNode *SUBC = 1159 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0))) 1160 if (SUBC->getValue() == OpSizeInBits) 1161 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1162 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1163 if (N0.getOperand(1).getOpcode() == ISD::SUB && 1164 N1.getOperand(1) == N0.getOperand(1).getOperand(1)) 1165 if (ConstantSDNode *SUBC = 1166 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0))) 1167 if (SUBC->getValue() == OpSizeInBits) { 1168 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT)) 1169 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0), 1170 N1.getOperand(1)); 1171 else 1172 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), 1173 N0.getOperand(1)); 1174 } 1175 } 1176 return SDOperand(); 1177} 1178 1179SDOperand DAGCombiner::visitXOR(SDNode *N) { 1180 SDOperand N0 = N->getOperand(0); 1181 SDOperand N1 = N->getOperand(1); 1182 SDOperand LHS, RHS, CC; 1183 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1184 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1185 MVT::ValueType VT = N0.getValueType(); 1186 1187 // fold (xor c1, c2) -> c1^c2 1188 if (N0C && N1C) 1189 return DAG.getNode(ISD::XOR, VT, N0, N1); 1190 // canonicalize constant to RHS 1191 if (N0C && !N1C) 1192 return DAG.getNode(ISD::XOR, VT, N1, N0); 1193 // fold (xor x, 0) -> x 1194 if (N1C && N1C->isNullValue()) 1195 return N0; 1196 // reassociate xor 1197 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1198 if (RXOR.Val != 0) 1199 return RXOR; 1200 // fold !(x cc y) -> (x !cc y) 1201 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1202 bool isInt = MVT::isInteger(LHS.getValueType()); 1203 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1204 isInt); 1205 if (N0.getOpcode() == ISD::SETCC) 1206 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1207 if (N0.getOpcode() == ISD::SELECT_CC) 1208 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1209 assert(0 && "Unhandled SetCC Equivalent!"); 1210 abort(); 1211 } 1212 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1213 if (N1C && N1C->getValue() == 1 && 1214 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1215 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1216 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1217 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1218 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1219 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1220 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 1221 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1222 } 1223 } 1224 // fold !(x or y) -> (!x and !y) iff x or y are constants 1225 if (N1C && N1C->isAllOnesValue() && 1226 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1227 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1228 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1229 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1230 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1231 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1232 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 1233 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1234 } 1235 } 1236 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1237 if (N1C && N0.getOpcode() == ISD::XOR) { 1238 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1239 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1240 if (N00C) 1241 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1242 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1243 if (N01C) 1244 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1245 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1246 } 1247 // fold (xor x, x) -> 0 1248 if (N0 == N1) 1249 return DAG.getConstant(0, VT); 1250 // fold (xor (zext x), (zext y)) -> (zext (xor x, y)) 1251 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1252 N1.getOpcode() == ISD::ZERO_EXTEND && 1253 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1254 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 1255 N0.getOperand(0), N1.getOperand(0)); 1256 WorkList.push_back(XORNode.Val); 1257 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 1258 } 1259 // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y)) 1260 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1261 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1262 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1263 N0.getOperand(1) == N1.getOperand(1)) { 1264 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 1265 N0.getOperand(0), N1.getOperand(0)); 1266 WorkList.push_back(XORNode.Val); 1267 return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1)); 1268 } 1269 return SDOperand(); 1270} 1271 1272SDOperand DAGCombiner::visitSHL(SDNode *N) { 1273 SDOperand N0 = N->getOperand(0); 1274 SDOperand N1 = N->getOperand(1); 1275 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1276 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1277 MVT::ValueType VT = N0.getValueType(); 1278 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1279 1280 // fold (shl c1, c2) -> c1<<c2 1281 if (N0C && N1C) 1282 return DAG.getNode(ISD::SHL, VT, N0, N1); 1283 // fold (shl 0, x) -> 0 1284 if (N0C && N0C->isNullValue()) 1285 return N0; 1286 // fold (shl x, c >= size(x)) -> undef 1287 if (N1C && N1C->getValue() >= OpSizeInBits) 1288 return DAG.getNode(ISD::UNDEF, VT); 1289 // fold (shl x, 0) -> x 1290 if (N1C && N1C->isNullValue()) 1291 return N0; 1292 // if (shl x, c) is known to be zero, return 0 1293 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1294 return DAG.getConstant(0, VT); 1295 if (SimplifyDemandedBits(SDOperand(N, 0))) 1296 return SDOperand(); 1297 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1298 if (N1C && N0.getOpcode() == ISD::SHL && 1299 N0.getOperand(1).getOpcode() == ISD::Constant) { 1300 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1301 uint64_t c2 = N1C->getValue(); 1302 if (c1 + c2 > OpSizeInBits) 1303 return DAG.getConstant(0, VT); 1304 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1305 DAG.getConstant(c1 + c2, N1.getValueType())); 1306 } 1307 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1308 // (srl (and x, -1 << c1), c1-c2) 1309 if (N1C && N0.getOpcode() == ISD::SRL && 1310 N0.getOperand(1).getOpcode() == ISD::Constant) { 1311 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1312 uint64_t c2 = N1C->getValue(); 1313 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1314 DAG.getConstant(~0ULL << c1, VT)); 1315 if (c2 > c1) 1316 return DAG.getNode(ISD::SHL, VT, Mask, 1317 DAG.getConstant(c2-c1, N1.getValueType())); 1318 else 1319 return DAG.getNode(ISD::SRL, VT, Mask, 1320 DAG.getConstant(c1-c2, N1.getValueType())); 1321 } 1322 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1323 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1324 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1325 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1326 return SDOperand(); 1327} 1328 1329SDOperand DAGCombiner::visitSRA(SDNode *N) { 1330 SDOperand N0 = N->getOperand(0); 1331 SDOperand N1 = N->getOperand(1); 1332 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1333 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1334 MVT::ValueType VT = N0.getValueType(); 1335 1336 // fold (sra c1, c2) -> c1>>c2 1337 if (N0C && N1C) 1338 return DAG.getNode(ISD::SRA, VT, N0, N1); 1339 // fold (sra 0, x) -> 0 1340 if (N0C && N0C->isNullValue()) 1341 return N0; 1342 // fold (sra -1, x) -> -1 1343 if (N0C && N0C->isAllOnesValue()) 1344 return N0; 1345 // fold (sra x, c >= size(x)) -> undef 1346 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 1347 return DAG.getNode(ISD::UNDEF, VT); 1348 // fold (sra x, 0) -> x 1349 if (N1C && N1C->isNullValue()) 1350 return N0; 1351 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 1352 // sext_inreg. 1353 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 1354 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 1355 MVT::ValueType EVT; 1356 switch (LowBits) { 1357 default: EVT = MVT::Other; break; 1358 case 1: EVT = MVT::i1; break; 1359 case 8: EVT = MVT::i8; break; 1360 case 16: EVT = MVT::i16; break; 1361 case 32: EVT = MVT::i32; break; 1362 } 1363 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 1364 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1365 DAG.getValueType(EVT)); 1366 } 1367 1368 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 1369 if (N1C && N0.getOpcode() == ISD::SRA) { 1370 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1371 unsigned Sum = N1C->getValue() + C1->getValue(); 1372 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 1373 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 1374 DAG.getConstant(Sum, N1C->getValueType(0))); 1375 } 1376 } 1377 1378 // If the sign bit is known to be zero, switch this to a SRL. 1379 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 1380 return DAG.getNode(ISD::SRL, VT, N0, N1); 1381 return SDOperand(); 1382} 1383 1384SDOperand DAGCombiner::visitSRL(SDNode *N) { 1385 SDOperand N0 = N->getOperand(0); 1386 SDOperand N1 = N->getOperand(1); 1387 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1388 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1389 MVT::ValueType VT = N0.getValueType(); 1390 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1391 1392 // fold (srl c1, c2) -> c1 >>u c2 1393 if (N0C && N1C) 1394 return DAG.getNode(ISD::SRL, VT, N0, N1); 1395 // fold (srl 0, x) -> 0 1396 if (N0C && N0C->isNullValue()) 1397 return N0; 1398 // fold (srl x, c >= size(x)) -> undef 1399 if (N1C && N1C->getValue() >= OpSizeInBits) 1400 return DAG.getNode(ISD::UNDEF, VT); 1401 // fold (srl x, 0) -> x 1402 if (N1C && N1C->isNullValue()) 1403 return N0; 1404 // if (srl x, c) is known to be zero, return 0 1405 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1406 return DAG.getConstant(0, VT); 1407 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1408 if (N1C && N0.getOpcode() == ISD::SRL && 1409 N0.getOperand(1).getOpcode() == ISD::Constant) { 1410 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1411 uint64_t c2 = N1C->getValue(); 1412 if (c1 + c2 > OpSizeInBits) 1413 return DAG.getConstant(0, VT); 1414 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1415 DAG.getConstant(c1 + c2, N1.getValueType())); 1416 } 1417 return SDOperand(); 1418} 1419 1420SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1421 SDOperand N0 = N->getOperand(0); 1422 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1423 MVT::ValueType VT = N->getValueType(0); 1424 1425 // fold (ctlz c1) -> c2 1426 if (N0C) 1427 return DAG.getNode(ISD::CTLZ, VT, N0); 1428 return SDOperand(); 1429} 1430 1431SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1432 SDOperand N0 = N->getOperand(0); 1433 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1434 MVT::ValueType VT = N->getValueType(0); 1435 1436 // fold (cttz c1) -> c2 1437 if (N0C) 1438 return DAG.getNode(ISD::CTTZ, VT, N0); 1439 return SDOperand(); 1440} 1441 1442SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1443 SDOperand N0 = N->getOperand(0); 1444 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1445 MVT::ValueType VT = N->getValueType(0); 1446 1447 // fold (ctpop c1) -> c2 1448 if (N0C) 1449 return DAG.getNode(ISD::CTPOP, VT, N0); 1450 return SDOperand(); 1451} 1452 1453SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1454 SDOperand N0 = N->getOperand(0); 1455 SDOperand N1 = N->getOperand(1); 1456 SDOperand N2 = N->getOperand(2); 1457 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1458 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1459 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1460 MVT::ValueType VT = N->getValueType(0); 1461 1462 // fold select C, X, X -> X 1463 if (N1 == N2) 1464 return N1; 1465 // fold select true, X, Y -> X 1466 if (N0C && !N0C->isNullValue()) 1467 return N1; 1468 // fold select false, X, Y -> Y 1469 if (N0C && N0C->isNullValue()) 1470 return N2; 1471 // fold select C, 1, X -> C | X 1472 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1473 return DAG.getNode(ISD::OR, VT, N0, N2); 1474 // fold select C, 0, X -> ~C & X 1475 // FIXME: this should check for C type == X type, not i1? 1476 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1477 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1478 WorkList.push_back(XORNode.Val); 1479 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1480 } 1481 // fold select C, X, 1 -> ~C | X 1482 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1483 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1484 WorkList.push_back(XORNode.Val); 1485 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1486 } 1487 // fold select C, X, 0 -> C & X 1488 // FIXME: this should check for C type == X type, not i1? 1489 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1490 return DAG.getNode(ISD::AND, VT, N0, N1); 1491 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1492 if (MVT::i1 == VT && N0 == N1) 1493 return DAG.getNode(ISD::OR, VT, N0, N2); 1494 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1495 if (MVT::i1 == VT && N0 == N2) 1496 return DAG.getNode(ISD::AND, VT, N0, N1); 1497 // If we can fold this based on the true/false value, do so. 1498 if (SimplifySelectOps(N, N1, N2)) 1499 return SDOperand(); 1500 // fold selects based on a setcc into other things, such as min/max/abs 1501 if (N0.getOpcode() == ISD::SETCC) 1502 // FIXME: 1503 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 1504 // having to say they don't support SELECT_CC on every type the DAG knows 1505 // about, since there is no way to mark an opcode illegal at all value types 1506 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 1507 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 1508 N1, N2, N0.getOperand(2)); 1509 else 1510 return SimplifySelect(N0, N1, N2); 1511 return SDOperand(); 1512} 1513 1514SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1515 SDOperand N0 = N->getOperand(0); 1516 SDOperand N1 = N->getOperand(1); 1517 SDOperand N2 = N->getOperand(2); 1518 SDOperand N3 = N->getOperand(3); 1519 SDOperand N4 = N->getOperand(4); 1520 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1521 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1522 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1523 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1524 1525 // Determine if the condition we're dealing with is constant 1526 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1527 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1528 1529 // fold select_cc lhs, rhs, x, x, cc -> x 1530 if (N2 == N3) 1531 return N2; 1532 1533 // If we can fold this based on the true/false value, do so. 1534 if (SimplifySelectOps(N, N2, N3)) 1535 return SDOperand(); 1536 1537 // fold select_cc into other things, such as min/max/abs 1538 return SimplifySelectCC(N0, N1, N2, N3, CC); 1539} 1540 1541SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1542 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1543 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1544} 1545 1546SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1547 SDOperand N0 = N->getOperand(0); 1548 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1549 MVT::ValueType VT = N->getValueType(0); 1550 1551 // fold (sext c1) -> c1 1552 if (N0C) 1553 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 1554 // fold (sext (sext x)) -> (sext x) 1555 if (N0.getOpcode() == ISD::SIGN_EXTEND) 1556 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1557 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size. 1558 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1559 (!AfterLegalize || 1560 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType()))) 1561 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1562 DAG.getValueType(N0.getValueType())); 1563 // fold (sext (load x)) -> (sext (truncate (sextload x))) 1564 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1565 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){ 1566 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1567 N0.getOperand(1), N0.getOperand(2), 1568 N0.getValueType()); 1569 CombineTo(N, ExtLoad); 1570 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1571 ExtLoad.getValue(1)); 1572 return SDOperand(); 1573 } 1574 1575 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 1576 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 1577 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1578 N0.hasOneUse()) { 1579 SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0), 1580 N0.getOperand(1), N0.getOperand(2), 1581 N0.getOperand(3)); 1582 CombineTo(N, ExtLoad); 1583 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1584 ExtLoad.getValue(1)); 1585 return SDOperand(); 1586 } 1587 1588 return SDOperand(); 1589} 1590 1591SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1592 SDOperand N0 = N->getOperand(0); 1593 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1594 MVT::ValueType VT = N->getValueType(0); 1595 1596 // fold (zext c1) -> c1 1597 if (N0C) 1598 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1599 // fold (zext (zext x)) -> (zext x) 1600 if (N0.getOpcode() == ISD::ZERO_EXTEND) 1601 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1602 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size. 1603 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1604 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType()))) 1605 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType()); 1606 // fold (zext (load x)) -> (zext (truncate (zextload x))) 1607 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1608 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){ 1609 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1610 N0.getOperand(1), N0.getOperand(2), 1611 N0.getValueType()); 1612 CombineTo(N, ExtLoad); 1613 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1614 ExtLoad.getValue(1)); 1615 return SDOperand(); 1616 } 1617 1618 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 1619 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 1620 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1621 N0.hasOneUse()) { 1622 SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1623 N0.getOperand(1), N0.getOperand(2), 1624 N0.getOperand(3)); 1625 CombineTo(N, ExtLoad); 1626 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1627 ExtLoad.getValue(1)); 1628 return SDOperand(); 1629 } 1630 return SDOperand(); 1631} 1632 1633SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1634 SDOperand N0 = N->getOperand(0); 1635 SDOperand N1 = N->getOperand(1); 1636 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1637 MVT::ValueType VT = N->getValueType(0); 1638 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1639 unsigned EVTBits = MVT::getSizeInBits(EVT); 1640 1641 // fold (sext_in_reg c1) -> c1 1642 if (N0C) { 1643 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT); 1644 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); 1645 } 1646 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 1647 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1648 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1649 return N0; 1650 } 1651 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1652 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1653 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1654 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1655 } 1656 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x) 1657 if (N0.getOpcode() == ISD::AssertSext && 1658 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1659 return N0; 1660 } 1661 // fold (sext_in_reg (sextload x)) -> (sextload x) 1662 if (N0.getOpcode() == ISD::SEXTLOAD && 1663 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) { 1664 return N0; 1665 } 1666 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1 1667 if (N0.getOpcode() == ISD::SETCC && 1668 TLI.getSetCCResultContents() == 1669 TargetLowering::ZeroOrNegativeOneSetCCResult) 1670 return N0; 1671 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1672 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 1673 return DAG.getZeroExtendInReg(N0, EVT); 1674 // fold (sext_in_reg (srl x)) -> sra x 1675 if (N0.getOpcode() == ISD::SRL && 1676 N0.getOperand(1).getOpcode() == ISD::Constant && 1677 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) { 1678 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0), 1679 N0.getOperand(1)); 1680 } 1681 // fold (sext_inreg (extload x)) -> (sextload x) 1682 if (N0.getOpcode() == ISD::EXTLOAD && 1683 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1684 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1685 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1686 N0.getOperand(1), N0.getOperand(2), 1687 EVT); 1688 CombineTo(N, ExtLoad); 1689 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1690 return SDOperand(); 1691 } 1692 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 1693 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() && 1694 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1695 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1696 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1697 N0.getOperand(1), N0.getOperand(2), 1698 EVT); 1699 CombineTo(N, ExtLoad); 1700 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1701 return SDOperand(); 1702 } 1703 return SDOperand(); 1704} 1705 1706SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 1707 SDOperand N0 = N->getOperand(0); 1708 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1709 MVT::ValueType VT = N->getValueType(0); 1710 1711 // noop truncate 1712 if (N0.getValueType() == N->getValueType(0)) 1713 return N0; 1714 // fold (truncate c1) -> c1 1715 if (N0C) 1716 return DAG.getNode(ISD::TRUNCATE, VT, N0); 1717 // fold (truncate (truncate x)) -> (truncate x) 1718 if (N0.getOpcode() == ISD::TRUNCATE) 1719 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1720 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 1721 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){ 1722 if (N0.getValueType() < VT) 1723 // if the source is smaller than the dest, we still need an extend 1724 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1725 else if (N0.getValueType() > VT) 1726 // if the source is larger than the dest, than we just need the truncate 1727 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1728 else 1729 // if the source and dest are the same type, we can drop both the extend 1730 // and the truncate 1731 return N0.getOperand(0); 1732 } 1733 // fold (truncate (load x)) -> (smaller load x) 1734 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1735 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 1736 "Cannot truncate to larger type!"); 1737 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1738 // For big endian targets, we need to add an offset to the pointer to load 1739 // the correct bytes. For little endian systems, we merely need to read 1740 // fewer bytes from the same pointer. 1741 uint64_t PtrOff = 1742 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 1743 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 1744 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 1745 DAG.getConstant(PtrOff, PtrType)); 1746 WorkList.push_back(NewPtr.Val); 1747 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 1748 WorkList.push_back(N); 1749 CombineTo(N0.Val, Load, Load.getValue(1)); 1750 return SDOperand(); 1751 } 1752 return SDOperand(); 1753} 1754 1755SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 1756 SDOperand N0 = N->getOperand(0); 1757 MVT::ValueType VT = N->getValueType(0); 1758 1759 // If the input is a constant, let getNode() fold it. 1760 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 1761 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 1762 if (Res.Val != N) return Res; 1763 } 1764 1765 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 1766 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 1767 1768 // fold (conv (load x)) -> (load (conv*)x) 1769 // FIXME: These xforms need to know that the resultant load doesn't need a 1770 // higher alignment than the original! 1771 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1772 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1), 1773 N0.getOperand(2)); 1774 WorkList.push_back(N); 1775 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 1776 Load.getValue(1)); 1777 return Load; 1778 } 1779 1780 return SDOperand(); 1781} 1782 1783SDOperand DAGCombiner::visitFADD(SDNode *N) { 1784 SDOperand N0 = N->getOperand(0); 1785 SDOperand N1 = N->getOperand(1); 1786 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1787 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1788 MVT::ValueType VT = N->getValueType(0); 1789 1790 // fold (fadd c1, c2) -> c1+c2 1791 if (N0CFP && N1CFP) 1792 return DAG.getNode(ISD::FADD, VT, N0, N1); 1793 // canonicalize constant to RHS 1794 if (N0CFP && !N1CFP) 1795 return DAG.getNode(ISD::FADD, VT, N1, N0); 1796 // fold (A + (-B)) -> A-B 1797 if (N1.getOpcode() == ISD::FNEG) 1798 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 1799 // fold ((-A) + B) -> B-A 1800 if (N0.getOpcode() == ISD::FNEG) 1801 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 1802 return SDOperand(); 1803} 1804 1805SDOperand DAGCombiner::visitFSUB(SDNode *N) { 1806 SDOperand N0 = N->getOperand(0); 1807 SDOperand N1 = N->getOperand(1); 1808 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1809 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1810 MVT::ValueType VT = N->getValueType(0); 1811 1812 // fold (fsub c1, c2) -> c1-c2 1813 if (N0CFP && N1CFP) 1814 return DAG.getNode(ISD::FSUB, VT, N0, N1); 1815 // fold (A-(-B)) -> A+B 1816 if (N1.getOpcode() == ISD::FNEG) 1817 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 1818 return SDOperand(); 1819} 1820 1821SDOperand DAGCombiner::visitFMUL(SDNode *N) { 1822 SDOperand N0 = N->getOperand(0); 1823 SDOperand N1 = N->getOperand(1); 1824 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1825 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1826 MVT::ValueType VT = N->getValueType(0); 1827 1828 // fold (fmul c1, c2) -> c1*c2 1829 if (N0CFP && N1CFP) 1830 return DAG.getNode(ISD::FMUL, VT, N0, N1); 1831 // canonicalize constant to RHS 1832 if (N0CFP && !N1CFP) 1833 return DAG.getNode(ISD::FMUL, VT, N1, N0); 1834 // fold (fmul X, 2.0) -> (fadd X, X) 1835 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 1836 return DAG.getNode(ISD::FADD, VT, N0, N0); 1837 return SDOperand(); 1838} 1839 1840SDOperand DAGCombiner::visitFDIV(SDNode *N) { 1841 SDOperand N0 = N->getOperand(0); 1842 SDOperand N1 = N->getOperand(1); 1843 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1844 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1845 MVT::ValueType VT = N->getValueType(0); 1846 1847 // fold (fdiv c1, c2) -> c1/c2 1848 if (N0CFP && N1CFP) 1849 return DAG.getNode(ISD::FDIV, VT, N0, N1); 1850 return SDOperand(); 1851} 1852 1853SDOperand DAGCombiner::visitFREM(SDNode *N) { 1854 SDOperand N0 = N->getOperand(0); 1855 SDOperand N1 = N->getOperand(1); 1856 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1857 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1858 MVT::ValueType VT = N->getValueType(0); 1859 1860 // fold (frem c1, c2) -> fmod(c1,c2) 1861 if (N0CFP && N1CFP) 1862 return DAG.getNode(ISD::FREM, VT, N0, N1); 1863 return SDOperand(); 1864} 1865 1866 1867SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 1868 SDOperand N0 = N->getOperand(0); 1869 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1870 MVT::ValueType VT = N->getValueType(0); 1871 1872 // fold (sint_to_fp c1) -> c1fp 1873 if (N0C) 1874 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 1875 return SDOperand(); 1876} 1877 1878SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 1879 SDOperand N0 = N->getOperand(0); 1880 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1881 MVT::ValueType VT = N->getValueType(0); 1882 1883 // fold (uint_to_fp c1) -> c1fp 1884 if (N0C) 1885 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 1886 return SDOperand(); 1887} 1888 1889SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 1890 SDOperand N0 = N->getOperand(0); 1891 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1892 MVT::ValueType VT = N->getValueType(0); 1893 1894 // fold (fp_to_sint c1fp) -> c1 1895 if (N0CFP) 1896 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 1897 return SDOperand(); 1898} 1899 1900SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 1901 SDOperand N0 = N->getOperand(0); 1902 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1903 MVT::ValueType VT = N->getValueType(0); 1904 1905 // fold (fp_to_uint c1fp) -> c1 1906 if (N0CFP) 1907 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 1908 return SDOperand(); 1909} 1910 1911SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 1912 SDOperand N0 = N->getOperand(0); 1913 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1914 MVT::ValueType VT = N->getValueType(0); 1915 1916 // fold (fp_round c1fp) -> c1fp 1917 if (N0CFP) 1918 return DAG.getNode(ISD::FP_ROUND, VT, N0); 1919 return SDOperand(); 1920} 1921 1922SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 1923 SDOperand N0 = N->getOperand(0); 1924 MVT::ValueType VT = N->getValueType(0); 1925 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1926 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1927 1928 // fold (fp_round_inreg c1fp) -> c1fp 1929 if (N0CFP) { 1930 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 1931 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 1932 } 1933 return SDOperand(); 1934} 1935 1936SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 1937 SDOperand N0 = N->getOperand(0); 1938 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1939 MVT::ValueType VT = N->getValueType(0); 1940 1941 // fold (fp_extend c1fp) -> c1fp 1942 if (N0CFP) 1943 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 1944 return SDOperand(); 1945} 1946 1947SDOperand DAGCombiner::visitFNEG(SDNode *N) { 1948 SDOperand N0 = N->getOperand(0); 1949 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1950 MVT::ValueType VT = N->getValueType(0); 1951 1952 // fold (fneg c1) -> -c1 1953 if (N0CFP) 1954 return DAG.getNode(ISD::FNEG, VT, N0); 1955 // fold (fneg (sub x, y)) -> (sub y, x) 1956 if (N->getOperand(0).getOpcode() == ISD::SUB) 1957 return DAG.getNode(ISD::SUB, VT, N->getOperand(1), N->getOperand(0)); 1958 // fold (fneg (fneg x)) -> x 1959 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1960 return N->getOperand(0).getOperand(0); 1961 return SDOperand(); 1962} 1963 1964SDOperand DAGCombiner::visitFABS(SDNode *N) { 1965 SDOperand N0 = N->getOperand(0); 1966 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1967 MVT::ValueType VT = N->getValueType(0); 1968 1969 // fold (fabs c1) -> fabs(c1) 1970 if (N0CFP) 1971 return DAG.getNode(ISD::FABS, VT, N0); 1972 // fold (fabs (fabs x)) -> (fabs x) 1973 if (N->getOperand(0).getOpcode() == ISD::FABS) 1974 return N->getOperand(0); 1975 // fold (fabs (fneg x)) -> (fabs x) 1976 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1977 return DAG.getNode(ISD::FABS, VT, N->getOperand(0).getOperand(0)); 1978 return SDOperand(); 1979} 1980 1981SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 1982 SDOperand Chain = N->getOperand(0); 1983 SDOperand N1 = N->getOperand(1); 1984 SDOperand N2 = N->getOperand(2); 1985 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1986 1987 // never taken branch, fold to chain 1988 if (N1C && N1C->isNullValue()) 1989 return Chain; 1990 // unconditional branch 1991 if (N1C && N1C->getValue() == 1) 1992 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 1993 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 1994 // on the target. 1995 if (N1.getOpcode() == ISD::SETCC && 1996 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 1997 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 1998 N1.getOperand(0), N1.getOperand(1), N2); 1999 } 2000 return SDOperand(); 2001} 2002 2003SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) { 2004 SDOperand Chain = N->getOperand(0); 2005 SDOperand N1 = N->getOperand(1); 2006 SDOperand N2 = N->getOperand(2); 2007 SDOperand N3 = N->getOperand(3); 2008 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2009 2010 // unconditional branch to true mbb 2011 if (N1C && N1C->getValue() == 1) 2012 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2013 // unconditional branch to false mbb 2014 if (N1C && N1C->isNullValue()) 2015 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3); 2016 // fold a brcondtwoway with a setcc condition into a BRTWOWAY_CC node if 2017 // BRTWOWAY_CC is legal on the target. 2018 if (N1.getOpcode() == ISD::SETCC && 2019 TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 2020 std::vector<SDOperand> Ops; 2021 Ops.push_back(Chain); 2022 Ops.push_back(N1.getOperand(2)); 2023 Ops.push_back(N1.getOperand(0)); 2024 Ops.push_back(N1.getOperand(1)); 2025 Ops.push_back(N2); 2026 Ops.push_back(N3); 2027 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); 2028 } 2029 return SDOperand(); 2030} 2031 2032// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 2033// 2034SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 2035 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 2036 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 2037 2038 // Use SimplifySetCC to simplify SETCC's. 2039 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 2040 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 2041 2042 // fold br_cc true, dest -> br dest (unconditional branch) 2043 if (SCCC && SCCC->getValue()) 2044 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 2045 N->getOperand(4)); 2046 // fold br_cc false, dest -> unconditional fall through 2047 if (SCCC && SCCC->isNullValue()) 2048 return N->getOperand(0); 2049 // fold to a simpler setcc 2050 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 2051 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 2052 Simp.getOperand(2), Simp.getOperand(0), 2053 Simp.getOperand(1), N->getOperand(4)); 2054 return SDOperand(); 2055} 2056 2057SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) { 2058 SDOperand Chain = N->getOperand(0); 2059 SDOperand CCN = N->getOperand(1); 2060 SDOperand LHS = N->getOperand(2); 2061 SDOperand RHS = N->getOperand(3); 2062 SDOperand N4 = N->getOperand(4); 2063 SDOperand N5 = N->getOperand(5); 2064 2065 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS, 2066 cast<CondCodeSDNode>(CCN)->get(), false); 2067 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 2068 2069 // fold select_cc lhs, rhs, x, x, cc -> x 2070 if (N4 == N5) 2071 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 2072 // fold select_cc true, x, y -> x 2073 if (SCCC && SCCC->getValue()) 2074 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 2075 // fold select_cc false, x, y -> y 2076 if (SCCC && SCCC->isNullValue()) 2077 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5); 2078 // fold to a simpler setcc 2079 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) { 2080 std::vector<SDOperand> Ops; 2081 Ops.push_back(Chain); 2082 Ops.push_back(SCC.getOperand(2)); 2083 Ops.push_back(SCC.getOperand(0)); 2084 Ops.push_back(SCC.getOperand(1)); 2085 Ops.push_back(N4); 2086 Ops.push_back(N5); 2087 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); 2088 } 2089 return SDOperand(); 2090} 2091 2092SDOperand DAGCombiner::visitLOAD(SDNode *N) { 2093 SDOperand Chain = N->getOperand(0); 2094 SDOperand Ptr = N->getOperand(1); 2095 SDOperand SrcValue = N->getOperand(2); 2096 2097 // If this load is directly stored, replace the load value with the stored 2098 // value. 2099 // TODO: Handle store large -> read small portion. 2100 // TODO: Handle TRUNCSTORE/EXTLOAD 2101 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2102 Chain.getOperand(1).getValueType() == N->getValueType(0)) 2103 return CombineTo(N, Chain.getOperand(1), Chain); 2104 2105 return SDOperand(); 2106} 2107 2108SDOperand DAGCombiner::visitSTORE(SDNode *N) { 2109 SDOperand Chain = N->getOperand(0); 2110 SDOperand Value = N->getOperand(1); 2111 SDOperand Ptr = N->getOperand(2); 2112 SDOperand SrcValue = N->getOperand(3); 2113 2114 // If this is a store that kills a previous store, remove the previous store. 2115 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2116 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ && 2117 // Make sure that these stores are the same value type: 2118 // FIXME: we really care that the second store is >= size of the first. 2119 Value.getValueType() == Chain.getOperand(1).getValueType()) { 2120 // Create a new store of Value that replaces both stores. 2121 SDNode *PrevStore = Chain.Val; 2122 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 2123 return Chain; 2124 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 2125 PrevStore->getOperand(0), Value, Ptr, 2126 SrcValue); 2127 CombineTo(N, NewStore); // Nuke this store. 2128 CombineTo(PrevStore, NewStore); // Nuke the previous store. 2129 return SDOperand(N, 0); 2130 } 2131 2132 // If this is a store of a bit convert, store the input value. 2133 // FIXME: This needs to know that the resultant store does not need a 2134 // higher alignment than the original. 2135 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) 2136 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0), 2137 Ptr, SrcValue); 2138 2139 return SDOperand(); 2140} 2141 2142SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 2143 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 2144 2145 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 2146 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 2147 // If we got a simplified select_cc node back from SimplifySelectCC, then 2148 // break it down into a new SETCC node, and a new SELECT node, and then return 2149 // the SELECT node, since we were called with a SELECT node. 2150 if (SCC.Val) { 2151 // Check to see if we got a select_cc back (to turn into setcc/select). 2152 // Otherwise, just return whatever node we got back, like fabs. 2153 if (SCC.getOpcode() == ISD::SELECT_CC) { 2154 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 2155 SCC.getOperand(0), SCC.getOperand(1), 2156 SCC.getOperand(4)); 2157 WorkList.push_back(SETCC.Val); 2158 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 2159 SCC.getOperand(3), SETCC); 2160 } 2161 return SCC; 2162 } 2163 return SDOperand(); 2164} 2165 2166/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 2167/// are the two values being selected between, see if we can simplify the 2168/// select. 2169/// 2170bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 2171 SDOperand RHS) { 2172 2173 // If this is a select from two identical things, try to pull the operation 2174 // through the select. 2175 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 2176#if 0 2177 std::cerr << "SELECT: ["; LHS.Val->dump(); 2178 std::cerr << "] ["; RHS.Val->dump(); 2179 std::cerr << "]\n"; 2180#endif 2181 2182 // If this is a load and the token chain is identical, replace the select 2183 // of two loads with a load through a select of the address to load from. 2184 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 2185 // constants have been dropped into the constant pool. 2186 if ((LHS.getOpcode() == ISD::LOAD || 2187 LHS.getOpcode() == ISD::EXTLOAD || 2188 LHS.getOpcode() == ISD::ZEXTLOAD || 2189 LHS.getOpcode() == ISD::SEXTLOAD) && 2190 // Token chains must be identical. 2191 LHS.getOperand(0) == RHS.getOperand(0) && 2192 // If this is an EXTLOAD, the VT's must match. 2193 (LHS.getOpcode() == ISD::LOAD || 2194 LHS.getOperand(3) == RHS.getOperand(3))) { 2195 // FIXME: this conflates two src values, discarding one. This is not 2196 // the right thing to do, but nothing uses srcvalues now. When they do, 2197 // turn SrcValue into a list of locations. 2198 SDOperand Addr; 2199 if (TheSelect->getOpcode() == ISD::SELECT) 2200 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(), 2201 TheSelect->getOperand(0), LHS.getOperand(1), 2202 RHS.getOperand(1)); 2203 else 2204 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(), 2205 TheSelect->getOperand(0), 2206 TheSelect->getOperand(1), 2207 LHS.getOperand(1), RHS.getOperand(1), 2208 TheSelect->getOperand(4)); 2209 2210 SDOperand Load; 2211 if (LHS.getOpcode() == ISD::LOAD) 2212 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0), 2213 Addr, LHS.getOperand(2)); 2214 else 2215 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0), 2216 LHS.getOperand(0), Addr, LHS.getOperand(2), 2217 cast<VTSDNode>(LHS.getOperand(3))->getVT()); 2218 // Users of the select now use the result of the load. 2219 CombineTo(TheSelect, Load); 2220 2221 // Users of the old loads now use the new load's chain. We know the 2222 // old-load value is dead now. 2223 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 2224 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 2225 return true; 2226 } 2227 } 2228 2229 return false; 2230} 2231 2232SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 2233 SDOperand N2, SDOperand N3, 2234 ISD::CondCode CC) { 2235 2236 MVT::ValueType VT = N2.getValueType(); 2237 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 2238 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 2239 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 2240 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 2241 2242 // Determine if the condition we're dealing with is constant 2243 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2244 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 2245 2246 // fold select_cc true, x, y -> x 2247 if (SCCC && SCCC->getValue()) 2248 return N2; 2249 // fold select_cc false, x, y -> y 2250 if (SCCC && SCCC->getValue() == 0) 2251 return N3; 2252 2253 // Check to see if we can simplify the select into an fabs node 2254 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 2255 // Allow either -0.0 or 0.0 2256 if (CFP->getValue() == 0.0) { 2257 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 2258 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 2259 N0 == N2 && N3.getOpcode() == ISD::FNEG && 2260 N2 == N3.getOperand(0)) 2261 return DAG.getNode(ISD::FABS, VT, N0); 2262 2263 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 2264 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 2265 N0 == N3 && N2.getOpcode() == ISD::FNEG && 2266 N2.getOperand(0) == N3) 2267 return DAG.getNode(ISD::FABS, VT, N3); 2268 } 2269 } 2270 2271 // Check to see if we can perform the "gzip trick", transforming 2272 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 2273 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 2274 MVT::isInteger(N0.getValueType()) && 2275 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 2276 MVT::ValueType XType = N0.getValueType(); 2277 MVT::ValueType AType = N2.getValueType(); 2278 if (XType >= AType) { 2279 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 2280 // single-bit constant. 2281 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 2282 unsigned ShCtV = Log2_64(N2C->getValue()); 2283 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 2284 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 2285 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 2286 WorkList.push_back(Shift.Val); 2287 if (XType > AType) { 2288 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2289 WorkList.push_back(Shift.Val); 2290 } 2291 return DAG.getNode(ISD::AND, AType, Shift, N2); 2292 } 2293 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2294 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2295 TLI.getShiftAmountTy())); 2296 WorkList.push_back(Shift.Val); 2297 if (XType > AType) { 2298 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2299 WorkList.push_back(Shift.Val); 2300 } 2301 return DAG.getNode(ISD::AND, AType, Shift, N2); 2302 } 2303 } 2304 2305 // fold select C, 16, 0 -> shl C, 4 2306 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 2307 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 2308 // Get a SetCC of the condition 2309 // FIXME: Should probably make sure that setcc is legal if we ever have a 2310 // target where it isn't. 2311 SDOperand Temp, SCC; 2312 // cast from setcc result type to select result type 2313 if (AfterLegalize) { 2314 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2315 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 2316 } else { 2317 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 2318 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 2319 } 2320 WorkList.push_back(SCC.Val); 2321 WorkList.push_back(Temp.Val); 2322 // shl setcc result by log2 n2c 2323 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 2324 DAG.getConstant(Log2_64(N2C->getValue()), 2325 TLI.getShiftAmountTy())); 2326 } 2327 2328 // Check to see if this is the equivalent of setcc 2329 // FIXME: Turn all of these into setcc if setcc if setcc is legal 2330 // otherwise, go ahead with the folds. 2331 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 2332 MVT::ValueType XType = N0.getValueType(); 2333 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 2334 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2335 if (Res.getValueType() != VT) 2336 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 2337 return Res; 2338 } 2339 2340 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 2341 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 2342 TLI.isOperationLegal(ISD::CTLZ, XType)) { 2343 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 2344 return DAG.getNode(ISD::SRL, XType, Ctlz, 2345 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 2346 TLI.getShiftAmountTy())); 2347 } 2348 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 2349 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 2350 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 2351 N0); 2352 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 2353 DAG.getConstant(~0ULL, XType)); 2354 return DAG.getNode(ISD::SRL, XType, 2355 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 2356 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2357 TLI.getShiftAmountTy())); 2358 } 2359 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 2360 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 2361 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 2362 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2363 TLI.getShiftAmountTy())); 2364 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 2365 } 2366 } 2367 2368 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 2369 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 2370 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 2371 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 2372 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 2373 MVT::ValueType XType = N0.getValueType(); 2374 if (SubC->isNullValue() && MVT::isInteger(XType)) { 2375 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2376 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2377 TLI.getShiftAmountTy())); 2378 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 2379 WorkList.push_back(Shift.Val); 2380 WorkList.push_back(Add.Val); 2381 return DAG.getNode(ISD::XOR, XType, Add, Shift); 2382 } 2383 } 2384 } 2385 2386 return SDOperand(); 2387} 2388 2389SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 2390 SDOperand N1, ISD::CondCode Cond, 2391 bool foldBooleans) { 2392 // These setcc operations always fold. 2393 switch (Cond) { 2394 default: break; 2395 case ISD::SETFALSE: 2396 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 2397 case ISD::SETTRUE: 2398 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 2399 } 2400 2401 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 2402 uint64_t C1 = N1C->getValue(); 2403 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 2404 uint64_t C0 = N0C->getValue(); 2405 2406 // Sign extend the operands if required 2407 if (ISD::isSignedIntSetCC(Cond)) { 2408 C0 = N0C->getSignExtended(); 2409 C1 = N1C->getSignExtended(); 2410 } 2411 2412 switch (Cond) { 2413 default: assert(0 && "Unknown integer setcc!"); 2414 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2415 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2416 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 2417 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 2418 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 2419 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 2420 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 2421 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 2422 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 2423 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 2424 } 2425 } else { 2426 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 2427 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 2428 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 2429 2430 // If the comparison constant has bits in the upper part, the 2431 // zero-extended value could never match. 2432 if (C1 & (~0ULL << InSize)) { 2433 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 2434 switch (Cond) { 2435 case ISD::SETUGT: 2436 case ISD::SETUGE: 2437 case ISD::SETEQ: return DAG.getConstant(0, VT); 2438 case ISD::SETULT: 2439 case ISD::SETULE: 2440 case ISD::SETNE: return DAG.getConstant(1, VT); 2441 case ISD::SETGT: 2442 case ISD::SETGE: 2443 // True if the sign bit of C1 is set. 2444 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 2445 case ISD::SETLT: 2446 case ISD::SETLE: 2447 // True if the sign bit of C1 isn't set. 2448 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 2449 default: 2450 break; 2451 } 2452 } 2453 2454 // Otherwise, we can perform the comparison with the low bits. 2455 switch (Cond) { 2456 case ISD::SETEQ: 2457 case ISD::SETNE: 2458 case ISD::SETUGT: 2459 case ISD::SETUGE: 2460 case ISD::SETULT: 2461 case ISD::SETULE: 2462 return DAG.getSetCC(VT, N0.getOperand(0), 2463 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 2464 Cond); 2465 default: 2466 break; // todo, be more careful with signed comparisons 2467 } 2468 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2469 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2470 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2471 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 2472 MVT::ValueType ExtDstTy = N0.getValueType(); 2473 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 2474 2475 // If the extended part has any inconsistent bits, it cannot ever 2476 // compare equal. In other words, they have to be all ones or all 2477 // zeros. 2478 uint64_t ExtBits = 2479 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 2480 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 2481 return DAG.getConstant(Cond == ISD::SETNE, VT); 2482 2483 SDOperand ZextOp; 2484 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 2485 if (Op0Ty == ExtSrcTy) { 2486 ZextOp = N0.getOperand(0); 2487 } else { 2488 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 2489 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 2490 DAG.getConstant(Imm, Op0Ty)); 2491 } 2492 WorkList.push_back(ZextOp.Val); 2493 // Otherwise, make this a use of a zext. 2494 return DAG.getSetCC(VT, ZextOp, 2495 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 2496 ExtDstTy), 2497 Cond); 2498 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && 2499 (Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2500 (N0.getOpcode() == ISD::XOR || 2501 (N0.getOpcode() == ISD::AND && 2502 N0.getOperand(0).getOpcode() == ISD::XOR && 2503 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 2504 isa<ConstantSDNode>(N0.getOperand(1)) && 2505 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { 2506 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can 2507 // only do this if the top bits are known zero. 2508 if (TLI.MaskedValueIsZero(N1, 2509 MVT::getIntVTBitMask(N0.getValueType())-1)) { 2510 // Okay, get the un-inverted input value. 2511 SDOperand Val; 2512 if (N0.getOpcode() == ISD::XOR) 2513 Val = N0.getOperand(0); 2514 else { 2515 assert(N0.getOpcode() == ISD::AND && 2516 N0.getOperand(0).getOpcode() == ISD::XOR); 2517 // ((X^1)&1)^1 -> X & 1 2518 Val = DAG.getNode(ISD::AND, N0.getValueType(), 2519 N0.getOperand(0).getOperand(0), N0.getOperand(1)); 2520 } 2521 return DAG.getSetCC(VT, Val, N1, 2522 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2523 } 2524 } 2525 2526 uint64_t MinVal, MaxVal; 2527 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 2528 if (ISD::isSignedIntSetCC(Cond)) { 2529 MinVal = 1ULL << (OperandBitSize-1); 2530 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 2531 MaxVal = ~0ULL >> (65-OperandBitSize); 2532 else 2533 MaxVal = 0; 2534 } else { 2535 MinVal = 0; 2536 MaxVal = ~0ULL >> (64-OperandBitSize); 2537 } 2538 2539 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2540 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2541 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2542 --C1; // X >= C0 --> X > (C0-1) 2543 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2544 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2545 } 2546 2547 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2548 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2549 ++C1; // X <= C0 --> X < (C0+1) 2550 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2551 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2552 } 2553 2554 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2555 return DAG.getConstant(0, VT); // X < MIN --> false 2556 2557 // Canonicalize setgt X, Min --> setne X, Min 2558 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2559 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2560 // Canonicalize setlt X, Max --> setne X, Max 2561 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2562 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2563 2564 // If we have setult X, 1, turn it into seteq X, 0 2565 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2566 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 2567 ISD::SETEQ); 2568 // If we have setugt X, Max-1, turn it into seteq X, Max 2569 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2570 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 2571 ISD::SETEQ); 2572 2573 // If we have "setcc X, C0", check to see if we can shrink the immediate 2574 // by changing cc. 2575 2576 // SETUGT X, SINTMAX -> SETLT X, 0 2577 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 2578 C1 == (~0ULL >> (65-OperandBitSize))) 2579 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 2580 ISD::SETLT); 2581 2582 // FIXME: Implement the rest of these. 2583 2584 // Fold bit comparisons when we can. 2585 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2586 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 2587 if (ConstantSDNode *AndRHS = 2588 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2589 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2590 // Perform the xform if the AND RHS is a single bit. 2591 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 2592 return DAG.getNode(ISD::SRL, VT, N0, 2593 DAG.getConstant(Log2_64(AndRHS->getValue()), 2594 TLI.getShiftAmountTy())); 2595 } 2596 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 2597 // (X & 8) == 8 --> (X & 8) >> 3 2598 // Perform the xform if C1 is a single bit. 2599 if ((C1 & (C1-1)) == 0) { 2600 return DAG.getNode(ISD::SRL, VT, N0, 2601 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 2602 } 2603 } 2604 } 2605 } 2606 } else if (isa<ConstantSDNode>(N0.Val)) { 2607 // Ensure that the constant occurs on the RHS. 2608 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2609 } 2610 2611 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 2612 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 2613 double C0 = N0C->getValue(), C1 = N1C->getValue(); 2614 2615 switch (Cond) { 2616 default: break; // FIXME: Implement the rest of these! 2617 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2618 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2619 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 2620 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 2621 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 2622 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 2623 } 2624 } else { 2625 // Ensure that the constant occurs on the RHS. 2626 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2627 } 2628 2629 if (N0 == N1) { 2630 // We can always fold X == Y for integer setcc's. 2631 if (MVT::isInteger(N0.getValueType())) 2632 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2633 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2634 if (UOF == 2) // FP operators that are undefined on NaNs. 2635 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2636 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2637 return DAG.getConstant(UOF, VT); 2638 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2639 // if it is not already. 2640 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2641 if (NewCond != Cond) 2642 return DAG.getSetCC(VT, N0, N1, NewCond); 2643 } 2644 2645 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2646 MVT::isInteger(N0.getValueType())) { 2647 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2648 N0.getOpcode() == ISD::XOR) { 2649 // Simplify (X+Y) == (X+Z) --> Y == Z 2650 if (N0.getOpcode() == N1.getOpcode()) { 2651 if (N0.getOperand(0) == N1.getOperand(0)) 2652 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 2653 if (N0.getOperand(1) == N1.getOperand(1)) 2654 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 2655 if (isCommutativeBinOp(N0.getOpcode())) { 2656 // If X op Y == Y op X, try other combinations. 2657 if (N0.getOperand(0) == N1.getOperand(1)) 2658 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 2659 if (N0.getOperand(1) == N1.getOperand(0)) 2660 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 2661 } 2662 } 2663 2664 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2665 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2666 // Turn (X+C1) == C2 --> X == C2-C1 2667 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 2668 return DAG.getSetCC(VT, N0.getOperand(0), 2669 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 2670 N0.getValueType()), Cond); 2671 } 2672 2673 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2674 if (N0.getOpcode() == ISD::XOR) 2675 // If we know that all of the inverted bits are zero, don't bother 2676 // performing the inversion. 2677 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) 2678 return DAG.getSetCC(VT, N0.getOperand(0), 2679 DAG.getConstant(LHSR->getValue()^RHSC->getValue(), 2680 N0.getValueType()), Cond); 2681 } 2682 2683 // Turn (C1-X) == C2 --> X == C1-C2 2684 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2685 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 2686 return DAG.getSetCC(VT, N0.getOperand(1), 2687 DAG.getConstant(SUBC->getValue()-RHSC->getValue(), 2688 N0.getValueType()), Cond); 2689 } 2690 } 2691 } 2692 2693 // Simplify (X+Z) == X --> Z == 0 2694 if (N0.getOperand(0) == N1) 2695 return DAG.getSetCC(VT, N0.getOperand(1), 2696 DAG.getConstant(0, N0.getValueType()), Cond); 2697 if (N0.getOperand(1) == N1) { 2698 if (isCommutativeBinOp(N0.getOpcode())) 2699 return DAG.getSetCC(VT, N0.getOperand(0), 2700 DAG.getConstant(0, N0.getValueType()), Cond); 2701 else { 2702 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2703 // (Z-X) == X --> Z == X<<1 2704 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 2705 N1, 2706 DAG.getConstant(1,TLI.getShiftAmountTy())); 2707 WorkList.push_back(SH.Val); 2708 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 2709 } 2710 } 2711 } 2712 2713 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2714 N1.getOpcode() == ISD::XOR) { 2715 // Simplify X == (X+Z) --> Z == 0 2716 if (N1.getOperand(0) == N0) { 2717 return DAG.getSetCC(VT, N1.getOperand(1), 2718 DAG.getConstant(0, N1.getValueType()), Cond); 2719 } else if (N1.getOperand(1) == N0) { 2720 if (isCommutativeBinOp(N1.getOpcode())) { 2721 return DAG.getSetCC(VT, N1.getOperand(0), 2722 DAG.getConstant(0, N1.getValueType()), Cond); 2723 } else { 2724 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2725 // X == (Z-X) --> X<<1 == Z 2726 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 2727 DAG.getConstant(1,TLI.getShiftAmountTy())); 2728 WorkList.push_back(SH.Val); 2729 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 2730 } 2731 } 2732 } 2733 } 2734 2735 // Fold away ALL boolean setcc's. 2736 SDOperand Temp; 2737 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2738 switch (Cond) { 2739 default: assert(0 && "Unknown integer setcc!"); 2740 case ISD::SETEQ: // X == Y -> (X^Y)^1 2741 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2742 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 2743 WorkList.push_back(Temp.Val); 2744 break; 2745 case ISD::SETNE: // X != Y --> (X^Y) 2746 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2747 break; 2748 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 2749 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 2750 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2751 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 2752 WorkList.push_back(Temp.Val); 2753 break; 2754 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 2755 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 2756 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2757 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 2758 WorkList.push_back(Temp.Val); 2759 break; 2760 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 2761 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 2762 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2763 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 2764 WorkList.push_back(Temp.Val); 2765 break; 2766 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 2767 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 2768 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2769 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 2770 break; 2771 } 2772 if (VT != MVT::i1) { 2773 WorkList.push_back(N0.Val); 2774 // FIXME: If running after legalize, we probably can't do this. 2775 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2776 } 2777 return N0; 2778 } 2779 2780 // Could not fold it. 2781 return SDOperand(); 2782} 2783 2784/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2785/// return a DAG expression to select that will generate the same value by 2786/// multiplying by a magic number. See: 2787/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2788SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 2789 MVT::ValueType VT = N->getValueType(0); 2790 2791 // Check to see if we can do this. 2792 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2793 return SDOperand(); // BuildSDIV only operates on i32 or i64 2794 if (!TLI.isOperationLegal(ISD::MULHS, VT)) 2795 return SDOperand(); // Make sure the target supports MULHS. 2796 2797 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 2798 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 2799 2800 // Multiply the numerator (operand 0) by the magic value 2801 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 2802 DAG.getConstant(magics.m, VT)); 2803 // If d > 0 and m < 0, add the numerator 2804 if (d > 0 && magics.m < 0) { 2805 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 2806 WorkList.push_back(Q.Val); 2807 } 2808 // If d < 0 and m > 0, subtract the numerator. 2809 if (d < 0 && magics.m > 0) { 2810 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 2811 WorkList.push_back(Q.Val); 2812 } 2813 // Shift right algebraic if shift value is nonzero 2814 if (magics.s > 0) { 2815 Q = DAG.getNode(ISD::SRA, VT, Q, 2816 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 2817 WorkList.push_back(Q.Val); 2818 } 2819 // Extract the sign bit and add it to the quotient 2820 SDOperand T = 2821 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 2822 TLI.getShiftAmountTy())); 2823 WorkList.push_back(T.Val); 2824 return DAG.getNode(ISD::ADD, VT, Q, T); 2825} 2826 2827/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2828/// return a DAG expression to select that will generate the same value by 2829/// multiplying by a magic number. See: 2830/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2831SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 2832 MVT::ValueType VT = N->getValueType(0); 2833 2834 // Check to see if we can do this. 2835 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2836 return SDOperand(); // BuildUDIV only operates on i32 or i64 2837 if (!TLI.isOperationLegal(ISD::MULHU, VT)) 2838 return SDOperand(); // Make sure the target supports MULHU. 2839 2840 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 2841 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 2842 2843 // Multiply the numerator (operand 0) by the magic value 2844 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 2845 DAG.getConstant(magics.m, VT)); 2846 WorkList.push_back(Q.Val); 2847 2848 if (magics.a == 0) { 2849 return DAG.getNode(ISD::SRL, VT, Q, 2850 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 2851 } else { 2852 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 2853 WorkList.push_back(NPQ.Val); 2854 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 2855 DAG.getConstant(1, TLI.getShiftAmountTy())); 2856 WorkList.push_back(NPQ.Val); 2857 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 2858 WorkList.push_back(NPQ.Val); 2859 return DAG.getNode(ISD::SRL, VT, NPQ, 2860 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy())); 2861 } 2862} 2863 2864// SelectionDAG::Combine - This is the entry point for the file. 2865// 2866void SelectionDAG::Combine(bool RunningAfterLegalize) { 2867 /// run - This is the main entry point to this class. 2868 /// 2869 DAGCombiner(*this).Run(RunningAfterLegalize); 2870} 2871