DAGCombiner.cpp revision 71dc7c9d895afc1e678b28d24a1ecc85ecd42178
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetLowering.h" 29#include "llvm/Target/TargetMachine.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/ADT/SmallPtrSet.h" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Support/raw_ostream.h" 38#include <algorithm> 39using namespace llvm; 40 41STATISTIC(NodesCombined , "Number of dag nodes combined"); 42STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 43STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 44STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 45STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 136 SDValue PromoteIntBinOp(SDValue Op); 137 SDValue PromoteIntShiftOp(SDValue Op); 138 SDValue PromoteExtend(SDValue Op); 139 bool PromoteLoad(SDValue Op); 140 141 /// combine - call the node-specific routine that knows how to fold each 142 /// particular type of node. If that doesn't do anything, try the 143 /// target-specific DAG combines. 144 SDValue combine(SDNode *N); 145 146 // Visitation implementation - Implement dag node combining for different 147 // node types. The semantics are as follows: 148 // Return Value: 149 // SDValue.getNode() == 0 - No change was made 150 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 151 // otherwise - N should be replaced by the returned Operand. 152 // 153 SDValue visitTokenFactor(SDNode *N); 154 SDValue visitMERGE_VALUES(SDNode *N); 155 SDValue visitADD(SDNode *N); 156 SDValue visitSUB(SDNode *N); 157 SDValue visitADDC(SDNode *N); 158 SDValue visitADDE(SDNode *N); 159 SDValue visitMUL(SDNode *N); 160 SDValue visitSDIV(SDNode *N); 161 SDValue visitUDIV(SDNode *N); 162 SDValue visitSREM(SDNode *N); 163 SDValue visitUREM(SDNode *N); 164 SDValue visitMULHU(SDNode *N); 165 SDValue visitMULHS(SDNode *N); 166 SDValue visitSMUL_LOHI(SDNode *N); 167 SDValue visitUMUL_LOHI(SDNode *N); 168 SDValue visitSDIVREM(SDNode *N); 169 SDValue visitUDIVREM(SDNode *N); 170 SDValue visitAND(SDNode *N); 171 SDValue visitOR(SDNode *N); 172 SDValue visitXOR(SDNode *N); 173 SDValue SimplifyVBinOp(SDNode *N); 174 SDValue visitSHL(SDNode *N); 175 SDValue visitSRA(SDNode *N); 176 SDValue visitSRL(SDNode *N); 177 SDValue visitCTLZ(SDNode *N); 178 SDValue visitCTTZ(SDNode *N); 179 SDValue visitCTPOP(SDNode *N); 180 SDValue visitSELECT(SDNode *N); 181 SDValue visitSELECT_CC(SDNode *N); 182 SDValue visitSETCC(SDNode *N); 183 SDValue visitSIGN_EXTEND(SDNode *N); 184 SDValue visitZERO_EXTEND(SDNode *N); 185 SDValue visitANY_EXTEND(SDNode *N); 186 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 187 SDValue visitTRUNCATE(SDNode *N); 188 SDValue visitBITCAST(SDNode *N); 189 SDValue visitBUILD_PAIR(SDNode *N); 190 SDValue visitFADD(SDNode *N); 191 SDValue visitFSUB(SDNode *N); 192 SDValue visitFMUL(SDNode *N); 193 SDValue visitFDIV(SDNode *N); 194 SDValue visitFREM(SDNode *N); 195 SDValue visitFCOPYSIGN(SDNode *N); 196 SDValue visitSINT_TO_FP(SDNode *N); 197 SDValue visitUINT_TO_FP(SDNode *N); 198 SDValue visitFP_TO_SINT(SDNode *N); 199 SDValue visitFP_TO_UINT(SDNode *N); 200 SDValue visitFP_ROUND(SDNode *N); 201 SDValue visitFP_ROUND_INREG(SDNode *N); 202 SDValue visitFP_EXTEND(SDNode *N); 203 SDValue visitFNEG(SDNode *N); 204 SDValue visitFABS(SDNode *N); 205 SDValue visitBRCOND(SDNode *N); 206 SDValue visitBR_CC(SDNode *N); 207 SDValue visitLOAD(SDNode *N); 208 SDValue visitSTORE(SDNode *N); 209 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 210 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 211 SDValue visitBUILD_VECTOR(SDNode *N); 212 SDValue visitCONCAT_VECTORS(SDNode *N); 213 SDValue visitVECTOR_SHUFFLE(SDNode *N); 214 SDValue visitMEMBARRIER(SDNode *N); 215 216 SDValue XformToShuffleWithZero(SDNode *N); 217 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 218 219 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 220 221 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 222 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 223 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 224 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 225 SDValue N3, ISD::CondCode CC, 226 bool NotExtCompare = false); 227 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 228 DebugLoc DL, bool foldBooleans = true); 229 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 230 unsigned HiOp); 231 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 232 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 233 SDValue BuildSDIV(SDNode *N); 234 SDValue BuildUDIV(SDNode *N); 235 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 236 SDValue ReduceLoadWidth(SDNode *N); 237 SDValue ReduceLoadOpStoreWidth(SDNode *N); 238 SDValue TransformFPLoadStorePair(SDNode *N); 239 240 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 241 242 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 243 /// looking for aliasing nodes and adding them to the Aliases vector. 244 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 245 SmallVector<SDValue, 8> &Aliases); 246 247 /// isAlias - Return true if there is any possibility that the two addresses 248 /// overlap. 249 bool isAlias(SDValue Ptr1, int64_t Size1, 250 const Value *SrcValue1, int SrcValueOffset1, 251 unsigned SrcValueAlign1, 252 const MDNode *TBAAInfo1, 253 SDValue Ptr2, int64_t Size2, 254 const Value *SrcValue2, int SrcValueOffset2, 255 unsigned SrcValueAlign2, 256 const MDNode *TBAAInfo2) const; 257 258 /// FindAliasInfo - Extracts the relevant alias information from the memory 259 /// node. Returns true if the operand was a load. 260 bool FindAliasInfo(SDNode *N, 261 SDValue &Ptr, int64_t &Size, 262 const Value *&SrcValue, int &SrcValueOffset, 263 unsigned &SrcValueAlignment, 264 const MDNode *&TBAAInfo) const; 265 266 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 267 /// looking for a better chain (aliasing node.) 268 SDValue FindBetterChain(SDNode *N, SDValue Chain); 269 270 public: 271 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 272 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), 273 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 274 275 /// Run - runs the dag combiner on all nodes in the work list 276 void Run(CombineLevel AtLevel); 277 278 SelectionDAG &getDAG() const { return DAG; } 279 280 /// getShiftAmountTy - Returns a type large enough to hold any valid 281 /// shift amount - before type legalization these can be huge. 282 EVT getShiftAmountTy(EVT LHSTy) { 283 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 284 } 285 286 /// isTypeLegal - This method returns true if we are running before type 287 /// legalization or if the specified VT is legal. 288 bool isTypeLegal(const EVT &VT) { 289 if (!LegalTypes) return true; 290 return TLI.isTypeLegal(VT); 291 } 292 }; 293} 294 295 296namespace { 297/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 298/// nodes from the worklist. 299class WorkListRemover : public SelectionDAG::DAGUpdateListener { 300 DAGCombiner &DC; 301public: 302 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 303 304 virtual void NodeDeleted(SDNode *N, SDNode *E) { 305 DC.removeFromWorkList(N); 306 } 307 308 virtual void NodeUpdated(SDNode *N) { 309 // Ignore updates. 310 } 311}; 312} 313 314//===----------------------------------------------------------------------===// 315// TargetLowering::DAGCombinerInfo implementation 316//===----------------------------------------------------------------------===// 317 318void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 319 ((DAGCombiner*)DC)->AddToWorkList(N); 320} 321 322void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 323 ((DAGCombiner*)DC)->removeFromWorkList(N); 324} 325 326SDValue TargetLowering::DAGCombinerInfo:: 327CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 328 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 329} 330 331SDValue TargetLowering::DAGCombinerInfo:: 332CombineTo(SDNode *N, SDValue Res, bool AddTo) { 333 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 334} 335 336 337SDValue TargetLowering::DAGCombinerInfo:: 338CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 339 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 340} 341 342void TargetLowering::DAGCombinerInfo:: 343CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 344 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 345} 346 347//===----------------------------------------------------------------------===// 348// Helper Functions 349//===----------------------------------------------------------------------===// 350 351/// isNegatibleForFree - Return 1 if we can compute the negated form of the 352/// specified expression for the same cost as the expression itself, or 2 if we 353/// can compute the negated form more cheaply than the expression itself. 354static char isNegatibleForFree(SDValue Op, bool LegalOperations, 355 unsigned Depth = 0) { 356 // No compile time optimizations on this type. 357 if (Op.getValueType() == MVT::ppcf128) 358 return 0; 359 360 // fneg is removable even if it has multiple uses. 361 if (Op.getOpcode() == ISD::FNEG) return 2; 362 363 // Don't allow anything with multiple uses. 364 if (!Op.hasOneUse()) return 0; 365 366 // Don't recurse exponentially. 367 if (Depth > 6) return 0; 368 369 switch (Op.getOpcode()) { 370 default: return false; 371 case ISD::ConstantFP: 372 // Don't invert constant FP values after legalize. The negated constant 373 // isn't necessarily legal. 374 return LegalOperations ? 0 : 1; 375 case ISD::FADD: 376 // FIXME: determine better conditions for this xform. 377 if (!UnsafeFPMath) return 0; 378 379 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 380 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 381 return V; 382 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 383 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 384 case ISD::FSUB: 385 // We can't turn -(A-B) into B-A when we honor signed zeros. 386 if (!UnsafeFPMath) return 0; 387 388 // fold (fneg (fsub A, B)) -> (fsub B, A) 389 return 1; 390 391 case ISD::FMUL: 392 case ISD::FDIV: 393 if (HonorSignDependentRoundingFPMath()) return 0; 394 395 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 396 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 397 return V; 398 399 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 400 401 case ISD::FP_EXTEND: 402 case ISD::FP_ROUND: 403 case ISD::FSIN: 404 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 405 } 406} 407 408/// GetNegatedExpression - If isNegatibleForFree returns true, this function 409/// returns the newly negated expression. 410static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 411 bool LegalOperations, unsigned Depth = 0) { 412 // fneg is removable even if it has multiple uses. 413 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 414 415 // Don't allow anything with multiple uses. 416 assert(Op.hasOneUse() && "Unknown reuse!"); 417 418 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 419 switch (Op.getOpcode()) { 420 default: llvm_unreachable("Unknown code"); 421 case ISD::ConstantFP: { 422 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 423 V.changeSign(); 424 return DAG.getConstantFP(V, Op.getValueType()); 425 } 426 case ISD::FADD: 427 // FIXME: determine better conditions for this xform. 428 assert(UnsafeFPMath); 429 430 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 431 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 432 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 433 GetNegatedExpression(Op.getOperand(0), DAG, 434 LegalOperations, Depth+1), 435 Op.getOperand(1)); 436 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 437 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 438 GetNegatedExpression(Op.getOperand(1), DAG, 439 LegalOperations, Depth+1), 440 Op.getOperand(0)); 441 case ISD::FSUB: 442 // We can't turn -(A-B) into B-A when we honor signed zeros. 443 assert(UnsafeFPMath); 444 445 // fold (fneg (fsub 0, B)) -> B 446 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 447 if (N0CFP->getValueAPF().isZero()) 448 return Op.getOperand(1); 449 450 // fold (fneg (fsub A, B)) -> (fsub B, A) 451 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 452 Op.getOperand(1), Op.getOperand(0)); 453 454 case ISD::FMUL: 455 case ISD::FDIV: 456 assert(!HonorSignDependentRoundingFPMath()); 457 458 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 459 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 460 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 461 GetNegatedExpression(Op.getOperand(0), DAG, 462 LegalOperations, Depth+1), 463 Op.getOperand(1)); 464 465 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 466 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 467 Op.getOperand(0), 468 GetNegatedExpression(Op.getOperand(1), DAG, 469 LegalOperations, Depth+1)); 470 471 case ISD::FP_EXTEND: 472 case ISD::FSIN: 473 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 474 GetNegatedExpression(Op.getOperand(0), DAG, 475 LegalOperations, Depth+1)); 476 case ISD::FP_ROUND: 477 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 478 GetNegatedExpression(Op.getOperand(0), DAG, 479 LegalOperations, Depth+1), 480 Op.getOperand(1)); 481 } 482} 483 484 485// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 486// that selects between the values 1 and 0, making it equivalent to a setcc. 487// Also, set the incoming LHS, RHS, and CC references to the appropriate 488// nodes based on the type of node we are checking. This simplifies life a 489// bit for the callers. 490static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 491 SDValue &CC) { 492 if (N.getOpcode() == ISD::SETCC) { 493 LHS = N.getOperand(0); 494 RHS = N.getOperand(1); 495 CC = N.getOperand(2); 496 return true; 497 } 498 if (N.getOpcode() == ISD::SELECT_CC && 499 N.getOperand(2).getOpcode() == ISD::Constant && 500 N.getOperand(3).getOpcode() == ISD::Constant && 501 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 502 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 503 LHS = N.getOperand(0); 504 RHS = N.getOperand(1); 505 CC = N.getOperand(4); 506 return true; 507 } 508 return false; 509} 510 511// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 512// one use. If this is true, it allows the users to invert the operation for 513// free when it is profitable to do so. 514static bool isOneUseSetCC(SDValue N) { 515 SDValue N0, N1, N2; 516 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 517 return true; 518 return false; 519} 520 521SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 522 SDValue N0, SDValue N1) { 523 EVT VT = N0.getValueType(); 524 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 525 if (isa<ConstantSDNode>(N1)) { 526 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 527 SDValue OpNode = 528 DAG.FoldConstantArithmetic(Opc, VT, 529 cast<ConstantSDNode>(N0.getOperand(1)), 530 cast<ConstantSDNode>(N1)); 531 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 532 } 533 if (N0.hasOneUse()) { 534 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 535 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 536 N0.getOperand(0), N1); 537 AddToWorkList(OpNode.getNode()); 538 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 539 } 540 } 541 542 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 543 if (isa<ConstantSDNode>(N0)) { 544 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 545 SDValue OpNode = 546 DAG.FoldConstantArithmetic(Opc, VT, 547 cast<ConstantSDNode>(N1.getOperand(1)), 548 cast<ConstantSDNode>(N0)); 549 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 550 } 551 if (N1.hasOneUse()) { 552 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 553 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 554 N1.getOperand(0), N0); 555 AddToWorkList(OpNode.getNode()); 556 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 557 } 558 } 559 560 return SDValue(); 561} 562 563SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 564 bool AddTo) { 565 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 566 ++NodesCombined; 567 DEBUG(dbgs() << "\nReplacing.1 "; 568 N->dump(&DAG); 569 dbgs() << "\nWith: "; 570 To[0].getNode()->dump(&DAG); 571 dbgs() << " and " << NumTo-1 << " other values\n"; 572 for (unsigned i = 0, e = NumTo; i != e; ++i) 573 assert((!To[i].getNode() || 574 N->getValueType(i) == To[i].getValueType()) && 575 "Cannot combine value to value of different type!")); 576 WorkListRemover DeadNodes(*this); 577 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 578 579 if (AddTo) { 580 // Push the new nodes and any users onto the worklist 581 for (unsigned i = 0, e = NumTo; i != e; ++i) { 582 if (To[i].getNode()) { 583 AddToWorkList(To[i].getNode()); 584 AddUsersToWorkList(To[i].getNode()); 585 } 586 } 587 } 588 589 // Finally, if the node is now dead, remove it from the graph. The node 590 // may not be dead if the replacement process recursively simplified to 591 // something else needing this node. 592 if (N->use_empty()) { 593 // Nodes can be reintroduced into the worklist. Make sure we do not 594 // process a node that has been replaced. 595 removeFromWorkList(N); 596 597 // Finally, since the node is now dead, remove it from the graph. 598 DAG.DeleteNode(N); 599 } 600 return SDValue(N, 0); 601} 602 603void DAGCombiner:: 604CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 605 // Replace all uses. If any nodes become isomorphic to other nodes and 606 // are deleted, make sure to remove them from our worklist. 607 WorkListRemover DeadNodes(*this); 608 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 609 610 // Push the new node and any (possibly new) users onto the worklist. 611 AddToWorkList(TLO.New.getNode()); 612 AddUsersToWorkList(TLO.New.getNode()); 613 614 // Finally, if the node is now dead, remove it from the graph. The node 615 // may not be dead if the replacement process recursively simplified to 616 // something else needing this node. 617 if (TLO.Old.getNode()->use_empty()) { 618 removeFromWorkList(TLO.Old.getNode()); 619 620 // If the operands of this node are only used by the node, they will now 621 // be dead. Make sure to visit them first to delete dead nodes early. 622 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 623 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 624 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 625 626 DAG.DeleteNode(TLO.Old.getNode()); 627 } 628} 629 630/// SimplifyDemandedBits - Check the specified integer node value to see if 631/// it can be simplified or if things it uses can be simplified by bit 632/// propagation. If so, return true. 633bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 634 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 635 APInt KnownZero, KnownOne; 636 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 637 return false; 638 639 // Revisit the node. 640 AddToWorkList(Op.getNode()); 641 642 // Replace the old value with the new one. 643 ++NodesCombined; 644 DEBUG(dbgs() << "\nReplacing.2 "; 645 TLO.Old.getNode()->dump(&DAG); 646 dbgs() << "\nWith: "; 647 TLO.New.getNode()->dump(&DAG); 648 dbgs() << '\n'); 649 650 CommitTargetLoweringOpt(TLO); 651 return true; 652} 653 654void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 655 DebugLoc dl = Load->getDebugLoc(); 656 EVT VT = Load->getValueType(0); 657 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 658 659 DEBUG(dbgs() << "\nReplacing.9 "; 660 Load->dump(&DAG); 661 dbgs() << "\nWith: "; 662 Trunc.getNode()->dump(&DAG); 663 dbgs() << '\n'); 664 WorkListRemover DeadNodes(*this); 665 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 666 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 667 &DeadNodes); 668 removeFromWorkList(Load); 669 DAG.DeleteNode(Load); 670 AddToWorkList(Trunc.getNode()); 671} 672 673SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 674 Replace = false; 675 DebugLoc dl = Op.getDebugLoc(); 676 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 677 EVT MemVT = LD->getMemoryVT(); 678 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 679 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 680 : ISD::EXTLOAD) 681 : LD->getExtensionType(); 682 Replace = true; 683 return DAG.getExtLoad(ExtType, dl, PVT, 684 LD->getChain(), LD->getBasePtr(), 685 LD->getPointerInfo(), 686 MemVT, LD->isVolatile(), 687 LD->isNonTemporal(), LD->getAlignment()); 688 } 689 690 unsigned Opc = Op.getOpcode(); 691 switch (Opc) { 692 default: break; 693 case ISD::AssertSext: 694 return DAG.getNode(ISD::AssertSext, dl, PVT, 695 SExtPromoteOperand(Op.getOperand(0), PVT), 696 Op.getOperand(1)); 697 case ISD::AssertZext: 698 return DAG.getNode(ISD::AssertZext, dl, PVT, 699 ZExtPromoteOperand(Op.getOperand(0), PVT), 700 Op.getOperand(1)); 701 case ISD::Constant: { 702 unsigned ExtOpc = 703 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 704 return DAG.getNode(ExtOpc, dl, PVT, Op); 705 } 706 } 707 708 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 709 return SDValue(); 710 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 711} 712 713SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 714 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 715 return SDValue(); 716 EVT OldVT = Op.getValueType(); 717 DebugLoc dl = Op.getDebugLoc(); 718 bool Replace = false; 719 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 720 if (NewOp.getNode() == 0) 721 return SDValue(); 722 AddToWorkList(NewOp.getNode()); 723 724 if (Replace) 725 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 726 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 727 DAG.getValueType(OldVT)); 728} 729 730SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 731 EVT OldVT = Op.getValueType(); 732 DebugLoc dl = Op.getDebugLoc(); 733 bool Replace = false; 734 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 735 if (NewOp.getNode() == 0) 736 return SDValue(); 737 AddToWorkList(NewOp.getNode()); 738 739 if (Replace) 740 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 741 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 742} 743 744/// PromoteIntBinOp - Promote the specified integer binary operation if the 745/// target indicates it is beneficial. e.g. On x86, it's usually better to 746/// promote i16 operations to i32 since i16 instructions are longer. 747SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 748 if (!LegalOperations) 749 return SDValue(); 750 751 EVT VT = Op.getValueType(); 752 if (VT.isVector() || !VT.isInteger()) 753 return SDValue(); 754 755 // If operation type is 'undesirable', e.g. i16 on x86, consider 756 // promoting it. 757 unsigned Opc = Op.getOpcode(); 758 if (TLI.isTypeDesirableForOp(Opc, VT)) 759 return SDValue(); 760 761 EVT PVT = VT; 762 // Consult target whether it is a good idea to promote this operation and 763 // what's the right type to promote it to. 764 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 765 assert(PVT != VT && "Don't know what type to promote to!"); 766 767 bool Replace0 = false; 768 SDValue N0 = Op.getOperand(0); 769 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 770 if (NN0.getNode() == 0) 771 return SDValue(); 772 773 bool Replace1 = false; 774 SDValue N1 = Op.getOperand(1); 775 SDValue NN1; 776 if (N0 == N1) 777 NN1 = NN0; 778 else { 779 NN1 = PromoteOperand(N1, PVT, Replace1); 780 if (NN1.getNode() == 0) 781 return SDValue(); 782 } 783 784 AddToWorkList(NN0.getNode()); 785 if (NN1.getNode()) 786 AddToWorkList(NN1.getNode()); 787 788 if (Replace0) 789 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 790 if (Replace1) 791 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 792 793 DEBUG(dbgs() << "\nPromoting "; 794 Op.getNode()->dump(&DAG)); 795 DebugLoc dl = Op.getDebugLoc(); 796 return DAG.getNode(ISD::TRUNCATE, dl, VT, 797 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 798 } 799 return SDValue(); 800} 801 802/// PromoteIntShiftOp - Promote the specified integer shift operation if the 803/// target indicates it is beneficial. e.g. On x86, it's usually better to 804/// promote i16 operations to i32 since i16 instructions are longer. 805SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 806 if (!LegalOperations) 807 return SDValue(); 808 809 EVT VT = Op.getValueType(); 810 if (VT.isVector() || !VT.isInteger()) 811 return SDValue(); 812 813 // If operation type is 'undesirable', e.g. i16 on x86, consider 814 // promoting it. 815 unsigned Opc = Op.getOpcode(); 816 if (TLI.isTypeDesirableForOp(Opc, VT)) 817 return SDValue(); 818 819 EVT PVT = VT; 820 // Consult target whether it is a good idea to promote this operation and 821 // what's the right type to promote it to. 822 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 823 assert(PVT != VT && "Don't know what type to promote to!"); 824 825 bool Replace = false; 826 SDValue N0 = Op.getOperand(0); 827 if (Opc == ISD::SRA) 828 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 829 else if (Opc == ISD::SRL) 830 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 831 else 832 N0 = PromoteOperand(N0, PVT, Replace); 833 if (N0.getNode() == 0) 834 return SDValue(); 835 836 AddToWorkList(N0.getNode()); 837 if (Replace) 838 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 839 840 DEBUG(dbgs() << "\nPromoting "; 841 Op.getNode()->dump(&DAG)); 842 DebugLoc dl = Op.getDebugLoc(); 843 return DAG.getNode(ISD::TRUNCATE, dl, VT, 844 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 845 } 846 return SDValue(); 847} 848 849SDValue DAGCombiner::PromoteExtend(SDValue Op) { 850 if (!LegalOperations) 851 return SDValue(); 852 853 EVT VT = Op.getValueType(); 854 if (VT.isVector() || !VT.isInteger()) 855 return SDValue(); 856 857 // If operation type is 'undesirable', e.g. i16 on x86, consider 858 // promoting it. 859 unsigned Opc = Op.getOpcode(); 860 if (TLI.isTypeDesirableForOp(Opc, VT)) 861 return SDValue(); 862 863 EVT PVT = VT; 864 // Consult target whether it is a good idea to promote this operation and 865 // what's the right type to promote it to. 866 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 867 assert(PVT != VT && "Don't know what type to promote to!"); 868 // fold (aext (aext x)) -> (aext x) 869 // fold (aext (zext x)) -> (zext x) 870 // fold (aext (sext x)) -> (sext x) 871 DEBUG(dbgs() << "\nPromoting "; 872 Op.getNode()->dump(&DAG)); 873 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 874 } 875 return SDValue(); 876} 877 878bool DAGCombiner::PromoteLoad(SDValue Op) { 879 if (!LegalOperations) 880 return false; 881 882 EVT VT = Op.getValueType(); 883 if (VT.isVector() || !VT.isInteger()) 884 return false; 885 886 // If operation type is 'undesirable', e.g. i16 on x86, consider 887 // promoting it. 888 unsigned Opc = Op.getOpcode(); 889 if (TLI.isTypeDesirableForOp(Opc, VT)) 890 return false; 891 892 EVT PVT = VT; 893 // Consult target whether it is a good idea to promote this operation and 894 // what's the right type to promote it to. 895 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 896 assert(PVT != VT && "Don't know what type to promote to!"); 897 898 DebugLoc dl = Op.getDebugLoc(); 899 SDNode *N = Op.getNode(); 900 LoadSDNode *LD = cast<LoadSDNode>(N); 901 EVT MemVT = LD->getMemoryVT(); 902 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 903 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 904 : ISD::EXTLOAD) 905 : LD->getExtensionType(); 906 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 907 LD->getChain(), LD->getBasePtr(), 908 LD->getPointerInfo(), 909 MemVT, LD->isVolatile(), 910 LD->isNonTemporal(), LD->getAlignment()); 911 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 912 913 DEBUG(dbgs() << "\nPromoting "; 914 N->dump(&DAG); 915 dbgs() << "\nTo: "; 916 Result.getNode()->dump(&DAG); 917 dbgs() << '\n'); 918 WorkListRemover DeadNodes(*this); 919 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 920 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 921 removeFromWorkList(N); 922 DAG.DeleteNode(N); 923 AddToWorkList(Result.getNode()); 924 return true; 925 } 926 return false; 927} 928 929 930//===----------------------------------------------------------------------===// 931// Main DAG Combiner implementation 932//===----------------------------------------------------------------------===// 933 934void DAGCombiner::Run(CombineLevel AtLevel) { 935 // set the instance variables, so that the various visit routines may use it. 936 Level = AtLevel; 937 LegalOperations = Level >= NoIllegalOperations; 938 LegalTypes = Level >= NoIllegalTypes; 939 940 // Add all the dag nodes to the worklist. 941 WorkList.reserve(DAG.allnodes_size()); 942 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 943 E = DAG.allnodes_end(); I != E; ++I) 944 WorkList.push_back(I); 945 946 // Create a dummy node (which is not added to allnodes), that adds a reference 947 // to the root node, preventing it from being deleted, and tracking any 948 // changes of the root. 949 HandleSDNode Dummy(DAG.getRoot()); 950 951 // The root of the dag may dangle to deleted nodes until the dag combiner is 952 // done. Set it to null to avoid confusion. 953 DAG.setRoot(SDValue()); 954 955 // while the worklist isn't empty, inspect the node on the end of it and 956 // try and combine it. 957 while (!WorkList.empty()) { 958 SDNode *N = WorkList.back(); 959 WorkList.pop_back(); 960 961 // If N has no uses, it is dead. Make sure to revisit all N's operands once 962 // N is deleted from the DAG, since they too may now be dead or may have a 963 // reduced number of uses, allowing other xforms. 964 if (N->use_empty() && N != &Dummy) { 965 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 966 AddToWorkList(N->getOperand(i).getNode()); 967 968 DAG.DeleteNode(N); 969 continue; 970 } 971 972 SDValue RV = combine(N); 973 974 if (RV.getNode() == 0) 975 continue; 976 977 ++NodesCombined; 978 979 // If we get back the same node we passed in, rather than a new node or 980 // zero, we know that the node must have defined multiple values and 981 // CombineTo was used. Since CombineTo takes care of the worklist 982 // mechanics for us, we have no work to do in this case. 983 if (RV.getNode() == N) 984 continue; 985 986 assert(N->getOpcode() != ISD::DELETED_NODE && 987 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 988 "Node was deleted but visit returned new node!"); 989 990 DEBUG(dbgs() << "\nReplacing.3 "; 991 N->dump(&DAG); 992 dbgs() << "\nWith: "; 993 RV.getNode()->dump(&DAG); 994 dbgs() << '\n'); 995 WorkListRemover DeadNodes(*this); 996 if (N->getNumValues() == RV.getNode()->getNumValues()) 997 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 998 else { 999 assert(N->getValueType(0) == RV.getValueType() && 1000 N->getNumValues() == 1 && "Type mismatch"); 1001 SDValue OpV = RV; 1002 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 1003 } 1004 1005 // Push the new node and any users onto the worklist 1006 AddToWorkList(RV.getNode()); 1007 AddUsersToWorkList(RV.getNode()); 1008 1009 // Add any uses of the old node to the worklist in case this node is the 1010 // last one that uses them. They may become dead after this node is 1011 // deleted. 1012 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1013 AddToWorkList(N->getOperand(i).getNode()); 1014 1015 // Finally, if the node is now dead, remove it from the graph. The node 1016 // may not be dead if the replacement process recursively simplified to 1017 // something else needing this node. 1018 if (N->use_empty()) { 1019 // Nodes can be reintroduced into the worklist. Make sure we do not 1020 // process a node that has been replaced. 1021 removeFromWorkList(N); 1022 1023 // Finally, since the node is now dead, remove it from the graph. 1024 DAG.DeleteNode(N); 1025 } 1026 } 1027 1028 // If the root changed (e.g. it was a dead load, update the root). 1029 DAG.setRoot(Dummy.getValue()); 1030} 1031 1032SDValue DAGCombiner::visit(SDNode *N) { 1033 switch (N->getOpcode()) { 1034 default: break; 1035 case ISD::TokenFactor: return visitTokenFactor(N); 1036 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1037 case ISD::ADD: return visitADD(N); 1038 case ISD::SUB: return visitSUB(N); 1039 case ISD::ADDC: return visitADDC(N); 1040 case ISD::ADDE: return visitADDE(N); 1041 case ISD::MUL: return visitMUL(N); 1042 case ISD::SDIV: return visitSDIV(N); 1043 case ISD::UDIV: return visitUDIV(N); 1044 case ISD::SREM: return visitSREM(N); 1045 case ISD::UREM: return visitUREM(N); 1046 case ISD::MULHU: return visitMULHU(N); 1047 case ISD::MULHS: return visitMULHS(N); 1048 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1049 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1050 case ISD::SDIVREM: return visitSDIVREM(N); 1051 case ISD::UDIVREM: return visitUDIVREM(N); 1052 case ISD::AND: return visitAND(N); 1053 case ISD::OR: return visitOR(N); 1054 case ISD::XOR: return visitXOR(N); 1055 case ISD::SHL: return visitSHL(N); 1056 case ISD::SRA: return visitSRA(N); 1057 case ISD::SRL: return visitSRL(N); 1058 case ISD::CTLZ: return visitCTLZ(N); 1059 case ISD::CTTZ: return visitCTTZ(N); 1060 case ISD::CTPOP: return visitCTPOP(N); 1061 case ISD::SELECT: return visitSELECT(N); 1062 case ISD::SELECT_CC: return visitSELECT_CC(N); 1063 case ISD::SETCC: return visitSETCC(N); 1064 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1065 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1066 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1067 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1068 case ISD::TRUNCATE: return visitTRUNCATE(N); 1069 case ISD::BITCAST: return visitBITCAST(N); 1070 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1071 case ISD::FADD: return visitFADD(N); 1072 case ISD::FSUB: return visitFSUB(N); 1073 case ISD::FMUL: return visitFMUL(N); 1074 case ISD::FDIV: return visitFDIV(N); 1075 case ISD::FREM: return visitFREM(N); 1076 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1077 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1078 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1079 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1080 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1081 case ISD::FP_ROUND: return visitFP_ROUND(N); 1082 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1083 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1084 case ISD::FNEG: return visitFNEG(N); 1085 case ISD::FABS: return visitFABS(N); 1086 case ISD::BRCOND: return visitBRCOND(N); 1087 case ISD::BR_CC: return visitBR_CC(N); 1088 case ISD::LOAD: return visitLOAD(N); 1089 case ISD::STORE: return visitSTORE(N); 1090 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1091 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1092 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1093 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1094 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1095 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1096 } 1097 return SDValue(); 1098} 1099 1100SDValue DAGCombiner::combine(SDNode *N) { 1101 SDValue RV = visit(N); 1102 1103 // If nothing happened, try a target-specific DAG combine. 1104 if (RV.getNode() == 0) { 1105 assert(N->getOpcode() != ISD::DELETED_NODE && 1106 "Node was deleted but visit returned NULL!"); 1107 1108 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1109 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1110 1111 // Expose the DAG combiner to the target combiner impls. 1112 TargetLowering::DAGCombinerInfo 1113 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1114 1115 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1116 } 1117 } 1118 1119 // If nothing happened still, try promoting the operation. 1120 if (RV.getNode() == 0) { 1121 switch (N->getOpcode()) { 1122 default: break; 1123 case ISD::ADD: 1124 case ISD::SUB: 1125 case ISD::MUL: 1126 case ISD::AND: 1127 case ISD::OR: 1128 case ISD::XOR: 1129 RV = PromoteIntBinOp(SDValue(N, 0)); 1130 break; 1131 case ISD::SHL: 1132 case ISD::SRA: 1133 case ISD::SRL: 1134 RV = PromoteIntShiftOp(SDValue(N, 0)); 1135 break; 1136 case ISD::SIGN_EXTEND: 1137 case ISD::ZERO_EXTEND: 1138 case ISD::ANY_EXTEND: 1139 RV = PromoteExtend(SDValue(N, 0)); 1140 break; 1141 case ISD::LOAD: 1142 if (PromoteLoad(SDValue(N, 0))) 1143 RV = SDValue(N, 0); 1144 break; 1145 } 1146 } 1147 1148 // If N is a commutative binary node, try commuting it to enable more 1149 // sdisel CSE. 1150 if (RV.getNode() == 0 && 1151 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1152 N->getNumValues() == 1) { 1153 SDValue N0 = N->getOperand(0); 1154 SDValue N1 = N->getOperand(1); 1155 1156 // Constant operands are canonicalized to RHS. 1157 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1158 SDValue Ops[] = { N1, N0 }; 1159 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1160 Ops, 2); 1161 if (CSENode) 1162 return SDValue(CSENode, 0); 1163 } 1164 } 1165 1166 return RV; 1167} 1168 1169/// getInputChainForNode - Given a node, return its input chain if it has one, 1170/// otherwise return a null sd operand. 1171static SDValue getInputChainForNode(SDNode *N) { 1172 if (unsigned NumOps = N->getNumOperands()) { 1173 if (N->getOperand(0).getValueType() == MVT::Other) 1174 return N->getOperand(0); 1175 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1176 return N->getOperand(NumOps-1); 1177 for (unsigned i = 1; i < NumOps-1; ++i) 1178 if (N->getOperand(i).getValueType() == MVT::Other) 1179 return N->getOperand(i); 1180 } 1181 return SDValue(); 1182} 1183 1184SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1185 // If N has two operands, where one has an input chain equal to the other, 1186 // the 'other' chain is redundant. 1187 if (N->getNumOperands() == 2) { 1188 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1189 return N->getOperand(0); 1190 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1191 return N->getOperand(1); 1192 } 1193 1194 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1195 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1196 SmallPtrSet<SDNode*, 16> SeenOps; 1197 bool Changed = false; // If we should replace this token factor. 1198 1199 // Start out with this token factor. 1200 TFs.push_back(N); 1201 1202 // Iterate through token factors. The TFs grows when new token factors are 1203 // encountered. 1204 for (unsigned i = 0; i < TFs.size(); ++i) { 1205 SDNode *TF = TFs[i]; 1206 1207 // Check each of the operands. 1208 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1209 SDValue Op = TF->getOperand(i); 1210 1211 switch (Op.getOpcode()) { 1212 case ISD::EntryToken: 1213 // Entry tokens don't need to be added to the list. They are 1214 // rededundant. 1215 Changed = true; 1216 break; 1217 1218 case ISD::TokenFactor: 1219 if (Op.hasOneUse() && 1220 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1221 // Queue up for processing. 1222 TFs.push_back(Op.getNode()); 1223 // Clean up in case the token factor is removed. 1224 AddToWorkList(Op.getNode()); 1225 Changed = true; 1226 break; 1227 } 1228 // Fall thru 1229 1230 default: 1231 // Only add if it isn't already in the list. 1232 if (SeenOps.insert(Op.getNode())) 1233 Ops.push_back(Op); 1234 else 1235 Changed = true; 1236 break; 1237 } 1238 } 1239 } 1240 1241 SDValue Result; 1242 1243 // If we've change things around then replace token factor. 1244 if (Changed) { 1245 if (Ops.empty()) { 1246 // The entry token is the only possible outcome. 1247 Result = DAG.getEntryNode(); 1248 } else { 1249 // New and improved token factor. 1250 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1251 MVT::Other, &Ops[0], Ops.size()); 1252 } 1253 1254 // Don't add users to work list. 1255 return CombineTo(N, Result, false); 1256 } 1257 1258 return Result; 1259} 1260 1261/// MERGE_VALUES can always be eliminated. 1262SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1263 WorkListRemover DeadNodes(*this); 1264 // Replacing results may cause a different MERGE_VALUES to suddenly 1265 // be CSE'd with N, and carry its uses with it. Iterate until no 1266 // uses remain, to ensure that the node can be safely deleted. 1267 do { 1268 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1269 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1270 &DeadNodes); 1271 } while (!N->use_empty()); 1272 removeFromWorkList(N); 1273 DAG.DeleteNode(N); 1274 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1275} 1276 1277static 1278SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1279 SelectionDAG &DAG) { 1280 EVT VT = N0.getValueType(); 1281 SDValue N00 = N0.getOperand(0); 1282 SDValue N01 = N0.getOperand(1); 1283 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1284 1285 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1286 isa<ConstantSDNode>(N00.getOperand(1))) { 1287 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1288 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1289 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1290 N00.getOperand(0), N01), 1291 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1292 N00.getOperand(1), N01)); 1293 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1294 } 1295 1296 return SDValue(); 1297} 1298 1299/// isCarryMaterialization - Returns true if V is an ADDE node that is known to 1300/// return 0 or 1 depending on the carry flag. 1301static bool isCarryMaterialization(SDValue V) { 1302 if (V.getOpcode() != ISD::ADDE) 1303 return false; 1304 1305 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(0)); 1306 return C && C->isNullValue() && V.getOperand(0) == V.getOperand(1); 1307} 1308 1309SDValue DAGCombiner::visitADD(SDNode *N) { 1310 SDValue N0 = N->getOperand(0); 1311 SDValue N1 = N->getOperand(1); 1312 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1313 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1314 EVT VT = N0.getValueType(); 1315 1316 // fold vector ops 1317 if (VT.isVector()) { 1318 SDValue FoldedVOp = SimplifyVBinOp(N); 1319 if (FoldedVOp.getNode()) return FoldedVOp; 1320 } 1321 1322 // fold (add x, undef) -> undef 1323 if (N0.getOpcode() == ISD::UNDEF) 1324 return N0; 1325 if (N1.getOpcode() == ISD::UNDEF) 1326 return N1; 1327 // fold (add c1, c2) -> c1+c2 1328 if (N0C && N1C) 1329 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1330 // canonicalize constant to RHS 1331 if (N0C && !N1C) 1332 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1333 // fold (add x, 0) -> x 1334 if (N1C && N1C->isNullValue()) 1335 return N0; 1336 // fold (add Sym, c) -> Sym+c 1337 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1338 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1339 GA->getOpcode() == ISD::GlobalAddress) 1340 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1341 GA->getOffset() + 1342 (uint64_t)N1C->getSExtValue()); 1343 // fold ((c1-A)+c2) -> (c1+c2)-A 1344 if (N1C && N0.getOpcode() == ISD::SUB) 1345 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1346 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1347 DAG.getConstant(N1C->getAPIntValue()+ 1348 N0C->getAPIntValue(), VT), 1349 N0.getOperand(1)); 1350 // reassociate add 1351 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1352 if (RADD.getNode() != 0) 1353 return RADD; 1354 // fold ((0-A) + B) -> B-A 1355 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1356 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1357 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1358 // fold (A + (0-B)) -> A-B 1359 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1360 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1361 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1362 // fold (A+(B-A)) -> B 1363 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1364 return N1.getOperand(0); 1365 // fold ((B-A)+A) -> B 1366 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1367 return N0.getOperand(0); 1368 // fold (A+(B-(A+C))) to (B-C) 1369 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1370 N0 == N1.getOperand(1).getOperand(0)) 1371 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1372 N1.getOperand(1).getOperand(1)); 1373 // fold (A+(B-(C+A))) to (B-C) 1374 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1375 N0 == N1.getOperand(1).getOperand(1)) 1376 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1377 N1.getOperand(1).getOperand(0)); 1378 // fold (A+((B-A)+or-C)) to (B+or-C) 1379 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1380 N1.getOperand(0).getOpcode() == ISD::SUB && 1381 N0 == N1.getOperand(0).getOperand(1)) 1382 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1383 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1384 1385 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1386 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1387 SDValue N00 = N0.getOperand(0); 1388 SDValue N01 = N0.getOperand(1); 1389 SDValue N10 = N1.getOperand(0); 1390 SDValue N11 = N1.getOperand(1); 1391 1392 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1393 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1394 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1395 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1396 } 1397 1398 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1399 return SDValue(N, 0); 1400 1401 // fold (a+b) -> (a|b) iff a and b share no bits. 1402 if (VT.isInteger() && !VT.isVector()) { 1403 APInt LHSZero, LHSOne; 1404 APInt RHSZero, RHSOne; 1405 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1406 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1407 1408 if (LHSZero.getBoolValue()) { 1409 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1410 1411 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1412 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1413 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1414 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1415 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1416 } 1417 } 1418 1419 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1420 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1421 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1422 if (Result.getNode()) return Result; 1423 } 1424 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1425 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1426 if (Result.getNode()) return Result; 1427 } 1428 1429 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1430 if (N1.getOpcode() == ISD::SHL && 1431 N1.getOperand(0).getOpcode() == ISD::SUB) 1432 if (ConstantSDNode *C = 1433 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1434 if (C->getAPIntValue() == 0) 1435 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1436 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1437 N1.getOperand(0).getOperand(1), 1438 N1.getOperand(1))); 1439 if (N0.getOpcode() == ISD::SHL && 1440 N0.getOperand(0).getOpcode() == ISD::SUB) 1441 if (ConstantSDNode *C = 1442 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1443 if (C->getAPIntValue() == 0) 1444 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1445 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1446 N0.getOperand(0).getOperand(1), 1447 N0.getOperand(1))); 1448 1449 if (N1.getOpcode() == ISD::AND) { 1450 SDValue AndOp0 = N1.getOperand(0); 1451 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1452 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1453 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1454 1455 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1456 // and similar xforms where the inner op is either ~0 or 0. 1457 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1458 DebugLoc DL = N->getDebugLoc(); 1459 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1460 } 1461 } 1462 1463 // add (sext i1), X -> sub X, (zext i1) 1464 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1465 N0.getOperand(0).getValueType() == MVT::i1 && 1466 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1467 DebugLoc DL = N->getDebugLoc(); 1468 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1469 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1470 } 1471 1472 // add (adde 0, 0, glue), X -> adde X, 0, glue 1473 if (N0->hasOneUse() && isCarryMaterialization(N0)) 1474 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), 1475 DAG.getVTList(VT, MVT::Glue), N1, N0.getOperand(0), 1476 N0.getOperand(2)); 1477 1478 // add X, (adde 0, 0, glue) -> adde X, 0, glue 1479 if (N1->hasOneUse() && isCarryMaterialization(N1)) 1480 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), 1481 DAG.getVTList(VT, MVT::Glue), N0, N1.getOperand(0), 1482 N1.getOperand(2)); 1483 1484 return SDValue(); 1485} 1486 1487SDValue DAGCombiner::visitADDC(SDNode *N) { 1488 SDValue N0 = N->getOperand(0); 1489 SDValue N1 = N->getOperand(1); 1490 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1491 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1492 EVT VT = N0.getValueType(); 1493 1494 // If the flag result is dead, turn this into an ADD. 1495 if (N->hasNUsesOfValue(0, 1)) 1496 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1497 DAG.getNode(ISD::CARRY_FALSE, 1498 N->getDebugLoc(), MVT::Glue)); 1499 1500 // canonicalize constant to RHS. 1501 if (N0C && !N1C) 1502 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1503 1504 // fold (addc x, 0) -> x + no carry out 1505 if (N1C && N1C->isNullValue()) 1506 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1507 N->getDebugLoc(), MVT::Glue)); 1508 1509 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1510 APInt LHSZero, LHSOne; 1511 APInt RHSZero, RHSOne; 1512 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1513 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1514 1515 if (LHSZero.getBoolValue()) { 1516 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1517 1518 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1519 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1520 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1521 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1522 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1523 DAG.getNode(ISD::CARRY_FALSE, 1524 N->getDebugLoc(), MVT::Glue)); 1525 } 1526 1527 // addc (adde 0, 0, glue), X -> adde X, 0, glue 1528 if (N0->hasOneUse() && isCarryMaterialization(N0)) 1529 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N1, 1530 DAG.getConstant(0, VT), N0.getOperand(2)); 1531 1532 // addc X, (adde 0, 0, glue) -> adde X, 0, glue 1533 if (N1->hasOneUse() && isCarryMaterialization(N1)) 1534 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N0, 1535 DAG.getConstant(0, VT), N1.getOperand(2)); 1536 1537 return SDValue(); 1538} 1539 1540SDValue DAGCombiner::visitADDE(SDNode *N) { 1541 SDValue N0 = N->getOperand(0); 1542 SDValue N1 = N->getOperand(1); 1543 SDValue CarryIn = N->getOperand(2); 1544 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1545 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1546 1547 // If both operands are null we know that carry out will always be false. 1548 if (N0C && N0C->isNullValue() && N0 == N1) 1549 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), DAG.getNode(ISD::CARRY_FALSE, 1550 N->getDebugLoc(), 1551 MVT::Glue)); 1552 1553 // canonicalize constant to RHS 1554 if (N0C && !N1C) 1555 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1556 N1, N0, CarryIn); 1557 1558 // fold (adde x, y, false) -> (addc x, y) 1559 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1560 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1561 1562 return SDValue(); 1563} 1564 1565// Since it may not be valid to emit a fold to zero for vector initializers 1566// check if we can before folding. 1567static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1568 SelectionDAG &DAG, bool LegalOperations) { 1569 if (!VT.isVector()) { 1570 return DAG.getConstant(0, VT); 1571 } 1572 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1573 // Produce a vector of zeros. 1574 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1575 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1576 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1577 &Ops[0], Ops.size()); 1578 } 1579 return SDValue(); 1580} 1581 1582SDValue DAGCombiner::visitSUB(SDNode *N) { 1583 SDValue N0 = N->getOperand(0); 1584 SDValue N1 = N->getOperand(1); 1585 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1586 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1587 EVT VT = N0.getValueType(); 1588 1589 // fold vector ops 1590 if (VT.isVector()) { 1591 SDValue FoldedVOp = SimplifyVBinOp(N); 1592 if (FoldedVOp.getNode()) return FoldedVOp; 1593 } 1594 1595 // fold (sub x, x) -> 0 1596 // FIXME: Refactor this and xor and other similar operations together. 1597 if (N0 == N1) 1598 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1599 // fold (sub c1, c2) -> c1-c2 1600 if (N0C && N1C) 1601 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1602 // fold (sub x, c) -> (add x, -c) 1603 if (N1C) 1604 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1605 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1606 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1607 if (N0C && N0C->isAllOnesValue()) 1608 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1609 // fold A-(A-B) -> B 1610 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1611 return N1.getOperand(1); 1612 // fold (A+B)-A -> B 1613 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1614 return N0.getOperand(1); 1615 // fold (A+B)-B -> A 1616 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1617 return N0.getOperand(0); 1618 // fold ((A+(B+or-C))-B) -> A+or-C 1619 if (N0.getOpcode() == ISD::ADD && 1620 (N0.getOperand(1).getOpcode() == ISD::SUB || 1621 N0.getOperand(1).getOpcode() == ISD::ADD) && 1622 N0.getOperand(1).getOperand(0) == N1) 1623 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1624 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1625 // fold ((A+(C+B))-B) -> A+C 1626 if (N0.getOpcode() == ISD::ADD && 1627 N0.getOperand(1).getOpcode() == ISD::ADD && 1628 N0.getOperand(1).getOperand(1) == N1) 1629 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1630 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1631 // fold ((A-(B-C))-C) -> A-B 1632 if (N0.getOpcode() == ISD::SUB && 1633 N0.getOperand(1).getOpcode() == ISD::SUB && 1634 N0.getOperand(1).getOperand(1) == N1) 1635 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1636 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1637 1638 // If either operand of a sub is undef, the result is undef 1639 if (N0.getOpcode() == ISD::UNDEF) 1640 return N0; 1641 if (N1.getOpcode() == ISD::UNDEF) 1642 return N1; 1643 1644 // If the relocation model supports it, consider symbol offsets. 1645 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1646 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1647 // fold (sub Sym, c) -> Sym-c 1648 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1649 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1650 GA->getOffset() - 1651 (uint64_t)N1C->getSExtValue()); 1652 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1653 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1654 if (GA->getGlobal() == GB->getGlobal()) 1655 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1656 VT); 1657 } 1658 1659 return SDValue(); 1660} 1661 1662SDValue DAGCombiner::visitMUL(SDNode *N) { 1663 SDValue N0 = N->getOperand(0); 1664 SDValue N1 = N->getOperand(1); 1665 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1666 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1667 EVT VT = N0.getValueType(); 1668 1669 // fold vector ops 1670 if (VT.isVector()) { 1671 SDValue FoldedVOp = SimplifyVBinOp(N); 1672 if (FoldedVOp.getNode()) return FoldedVOp; 1673 } 1674 1675 // fold (mul x, undef) -> 0 1676 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1677 return DAG.getConstant(0, VT); 1678 // fold (mul c1, c2) -> c1*c2 1679 if (N0C && N1C) 1680 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1681 // canonicalize constant to RHS 1682 if (N0C && !N1C) 1683 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1684 // fold (mul x, 0) -> 0 1685 if (N1C && N1C->isNullValue()) 1686 return N1; 1687 // fold (mul x, -1) -> 0-x 1688 if (N1C && N1C->isAllOnesValue()) 1689 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1690 DAG.getConstant(0, VT), N0); 1691 // fold (mul x, (1 << c)) -> x << c 1692 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1693 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1694 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1695 getShiftAmountTy(N0.getValueType()))); 1696 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1697 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1698 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1699 // FIXME: If the input is something that is easily negated (e.g. a 1700 // single-use add), we should put the negate there. 1701 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1702 DAG.getConstant(0, VT), 1703 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1704 DAG.getConstant(Log2Val, 1705 getShiftAmountTy(N0.getValueType())))); 1706 } 1707 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1708 if (N1C && N0.getOpcode() == ISD::SHL && 1709 isa<ConstantSDNode>(N0.getOperand(1))) { 1710 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1711 N1, N0.getOperand(1)); 1712 AddToWorkList(C3.getNode()); 1713 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1714 N0.getOperand(0), C3); 1715 } 1716 1717 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1718 // use. 1719 { 1720 SDValue Sh(0,0), Y(0,0); 1721 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1722 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1723 N0.getNode()->hasOneUse()) { 1724 Sh = N0; Y = N1; 1725 } else if (N1.getOpcode() == ISD::SHL && 1726 isa<ConstantSDNode>(N1.getOperand(1)) && 1727 N1.getNode()->hasOneUse()) { 1728 Sh = N1; Y = N0; 1729 } 1730 1731 if (Sh.getNode()) { 1732 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1733 Sh.getOperand(0), Y); 1734 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1735 Mul, Sh.getOperand(1)); 1736 } 1737 } 1738 1739 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1740 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1741 isa<ConstantSDNode>(N0.getOperand(1))) 1742 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1743 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1744 N0.getOperand(0), N1), 1745 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1746 N0.getOperand(1), N1)); 1747 1748 // reassociate mul 1749 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1750 if (RMUL.getNode() != 0) 1751 return RMUL; 1752 1753 return SDValue(); 1754} 1755 1756SDValue DAGCombiner::visitSDIV(SDNode *N) { 1757 SDValue N0 = N->getOperand(0); 1758 SDValue N1 = N->getOperand(1); 1759 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1760 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1761 EVT VT = N->getValueType(0); 1762 1763 // fold vector ops 1764 if (VT.isVector()) { 1765 SDValue FoldedVOp = SimplifyVBinOp(N); 1766 if (FoldedVOp.getNode()) return FoldedVOp; 1767 } 1768 1769 // fold (sdiv c1, c2) -> c1/c2 1770 if (N0C && N1C && !N1C->isNullValue()) 1771 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1772 // fold (sdiv X, 1) -> X 1773 if (N1C && N1C->getSExtValue() == 1LL) 1774 return N0; 1775 // fold (sdiv X, -1) -> 0-X 1776 if (N1C && N1C->isAllOnesValue()) 1777 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1778 DAG.getConstant(0, VT), N0); 1779 // If we know the sign bits of both operands are zero, strength reduce to a 1780 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1781 if (!VT.isVector()) { 1782 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1783 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1784 N0, N1); 1785 } 1786 // fold (sdiv X, pow2) -> simple ops after legalize 1787 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1788 (isPowerOf2_64(N1C->getSExtValue()) || 1789 isPowerOf2_64(-N1C->getSExtValue()))) { 1790 // If dividing by powers of two is cheap, then don't perform the following 1791 // fold. 1792 if (TLI.isPow2DivCheap()) 1793 return SDValue(); 1794 1795 int64_t pow2 = N1C->getSExtValue(); 1796 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1797 unsigned lg2 = Log2_64(abs2); 1798 1799 // Splat the sign bit into the register 1800 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1801 DAG.getConstant(VT.getSizeInBits()-1, 1802 getShiftAmountTy(N0.getValueType()))); 1803 AddToWorkList(SGN.getNode()); 1804 1805 // Add (N0 < 0) ? abs2 - 1 : 0; 1806 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1807 DAG.getConstant(VT.getSizeInBits() - lg2, 1808 getShiftAmountTy(SGN.getValueType()))); 1809 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1810 AddToWorkList(SRL.getNode()); 1811 AddToWorkList(ADD.getNode()); // Divide by pow2 1812 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1813 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1814 1815 // If we're dividing by a positive value, we're done. Otherwise, we must 1816 // negate the result. 1817 if (pow2 > 0) 1818 return SRA; 1819 1820 AddToWorkList(SRA.getNode()); 1821 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1822 DAG.getConstant(0, VT), SRA); 1823 } 1824 1825 // if integer divide is expensive and we satisfy the requirements, emit an 1826 // alternate sequence. 1827 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1828 !TLI.isIntDivCheap()) { 1829 SDValue Op = BuildSDIV(N); 1830 if (Op.getNode()) return Op; 1831 } 1832 1833 // undef / X -> 0 1834 if (N0.getOpcode() == ISD::UNDEF) 1835 return DAG.getConstant(0, VT); 1836 // X / undef -> undef 1837 if (N1.getOpcode() == ISD::UNDEF) 1838 return N1; 1839 1840 return SDValue(); 1841} 1842 1843SDValue DAGCombiner::visitUDIV(SDNode *N) { 1844 SDValue N0 = N->getOperand(0); 1845 SDValue N1 = N->getOperand(1); 1846 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1847 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1848 EVT VT = N->getValueType(0); 1849 1850 // fold vector ops 1851 if (VT.isVector()) { 1852 SDValue FoldedVOp = SimplifyVBinOp(N); 1853 if (FoldedVOp.getNode()) return FoldedVOp; 1854 } 1855 1856 // fold (udiv c1, c2) -> c1/c2 1857 if (N0C && N1C && !N1C->isNullValue()) 1858 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1859 // fold (udiv x, (1 << c)) -> x >>u c 1860 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1861 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1862 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1863 getShiftAmountTy(N0.getValueType()))); 1864 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1865 if (N1.getOpcode() == ISD::SHL) { 1866 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1867 if (SHC->getAPIntValue().isPowerOf2()) { 1868 EVT ADDVT = N1.getOperand(1).getValueType(); 1869 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1870 N1.getOperand(1), 1871 DAG.getConstant(SHC->getAPIntValue() 1872 .logBase2(), 1873 ADDVT)); 1874 AddToWorkList(Add.getNode()); 1875 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1876 } 1877 } 1878 } 1879 // fold (udiv x, c) -> alternate 1880 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1881 SDValue Op = BuildUDIV(N); 1882 if (Op.getNode()) return Op; 1883 } 1884 1885 // undef / X -> 0 1886 if (N0.getOpcode() == ISD::UNDEF) 1887 return DAG.getConstant(0, VT); 1888 // X / undef -> undef 1889 if (N1.getOpcode() == ISD::UNDEF) 1890 return N1; 1891 1892 return SDValue(); 1893} 1894 1895SDValue DAGCombiner::visitSREM(SDNode *N) { 1896 SDValue N0 = N->getOperand(0); 1897 SDValue N1 = N->getOperand(1); 1898 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1899 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1900 EVT VT = N->getValueType(0); 1901 1902 // fold (srem c1, c2) -> c1%c2 1903 if (N0C && N1C && !N1C->isNullValue()) 1904 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1905 // If we know the sign bits of both operands are zero, strength reduce to a 1906 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1907 if (!VT.isVector()) { 1908 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1909 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1910 } 1911 1912 // If X/C can be simplified by the division-by-constant logic, lower 1913 // X%C to the equivalent of X-X/C*C. 1914 if (N1C && !N1C->isNullValue()) { 1915 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1916 AddToWorkList(Div.getNode()); 1917 SDValue OptimizedDiv = combine(Div.getNode()); 1918 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1919 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1920 OptimizedDiv, N1); 1921 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1922 AddToWorkList(Mul.getNode()); 1923 return Sub; 1924 } 1925 } 1926 1927 // undef % X -> 0 1928 if (N0.getOpcode() == ISD::UNDEF) 1929 return DAG.getConstant(0, VT); 1930 // X % undef -> undef 1931 if (N1.getOpcode() == ISD::UNDEF) 1932 return N1; 1933 1934 return SDValue(); 1935} 1936 1937SDValue DAGCombiner::visitUREM(SDNode *N) { 1938 SDValue N0 = N->getOperand(0); 1939 SDValue N1 = N->getOperand(1); 1940 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1941 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1942 EVT VT = N->getValueType(0); 1943 1944 // fold (urem c1, c2) -> c1%c2 1945 if (N0C && N1C && !N1C->isNullValue()) 1946 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1947 // fold (urem x, pow2) -> (and x, pow2-1) 1948 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1949 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1950 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1951 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1952 if (N1.getOpcode() == ISD::SHL) { 1953 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1954 if (SHC->getAPIntValue().isPowerOf2()) { 1955 SDValue Add = 1956 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1957 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1958 VT)); 1959 AddToWorkList(Add.getNode()); 1960 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1961 } 1962 } 1963 } 1964 1965 // If X/C can be simplified by the division-by-constant logic, lower 1966 // X%C to the equivalent of X-X/C*C. 1967 if (N1C && !N1C->isNullValue()) { 1968 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1969 AddToWorkList(Div.getNode()); 1970 SDValue OptimizedDiv = combine(Div.getNode()); 1971 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1972 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1973 OptimizedDiv, N1); 1974 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1975 AddToWorkList(Mul.getNode()); 1976 return Sub; 1977 } 1978 } 1979 1980 // undef % X -> 0 1981 if (N0.getOpcode() == ISD::UNDEF) 1982 return DAG.getConstant(0, VT); 1983 // X % undef -> undef 1984 if (N1.getOpcode() == ISD::UNDEF) 1985 return N1; 1986 1987 return SDValue(); 1988} 1989 1990SDValue DAGCombiner::visitMULHS(SDNode *N) { 1991 SDValue N0 = N->getOperand(0); 1992 SDValue N1 = N->getOperand(1); 1993 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1994 EVT VT = N->getValueType(0); 1995 DebugLoc DL = N->getDebugLoc(); 1996 1997 // fold (mulhs x, 0) -> 0 1998 if (N1C && N1C->isNullValue()) 1999 return N1; 2000 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2001 if (N1C && N1C->getAPIntValue() == 1) 2002 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2003 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2004 getShiftAmountTy(N0.getValueType()))); 2005 // fold (mulhs x, undef) -> 0 2006 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2007 return DAG.getConstant(0, VT); 2008 2009 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2010 // plus a shift. 2011 if (VT.isSimple() && !VT.isVector()) { 2012 MVT Simple = VT.getSimpleVT(); 2013 unsigned SimpleSize = Simple.getSizeInBits(); 2014 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2015 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2016 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2017 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2018 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2019 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2020 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2021 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2022 } 2023 } 2024 2025 return SDValue(); 2026} 2027 2028SDValue DAGCombiner::visitMULHU(SDNode *N) { 2029 SDValue N0 = N->getOperand(0); 2030 SDValue N1 = N->getOperand(1); 2031 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2032 EVT VT = N->getValueType(0); 2033 DebugLoc DL = N->getDebugLoc(); 2034 2035 // fold (mulhu x, 0) -> 0 2036 if (N1C && N1C->isNullValue()) 2037 return N1; 2038 // fold (mulhu x, 1) -> 0 2039 if (N1C && N1C->getAPIntValue() == 1) 2040 return DAG.getConstant(0, N0.getValueType()); 2041 // fold (mulhu x, undef) -> 0 2042 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2043 return DAG.getConstant(0, VT); 2044 2045 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2046 // plus a shift. 2047 if (VT.isSimple() && !VT.isVector()) { 2048 MVT Simple = VT.getSimpleVT(); 2049 unsigned SimpleSize = Simple.getSizeInBits(); 2050 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2051 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2052 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2053 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2054 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2055 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2056 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2057 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2058 } 2059 } 2060 2061 return SDValue(); 2062} 2063 2064/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2065/// compute two values. LoOp and HiOp give the opcodes for the two computations 2066/// that are being performed. Return true if a simplification was made. 2067/// 2068SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2069 unsigned HiOp) { 2070 // If the high half is not needed, just compute the low half. 2071 bool HiExists = N->hasAnyUseOfValue(1); 2072 if (!HiExists && 2073 (!LegalOperations || 2074 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2075 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2076 N->op_begin(), N->getNumOperands()); 2077 return CombineTo(N, Res, Res); 2078 } 2079 2080 // If the low half is not needed, just compute the high half. 2081 bool LoExists = N->hasAnyUseOfValue(0); 2082 if (!LoExists && 2083 (!LegalOperations || 2084 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2085 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2086 N->op_begin(), N->getNumOperands()); 2087 return CombineTo(N, Res, Res); 2088 } 2089 2090 // If both halves are used, return as it is. 2091 if (LoExists && HiExists) 2092 return SDValue(); 2093 2094 // If the two computed results can be simplified separately, separate them. 2095 if (LoExists) { 2096 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2097 N->op_begin(), N->getNumOperands()); 2098 AddToWorkList(Lo.getNode()); 2099 SDValue LoOpt = combine(Lo.getNode()); 2100 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2101 (!LegalOperations || 2102 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2103 return CombineTo(N, LoOpt, LoOpt); 2104 } 2105 2106 if (HiExists) { 2107 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2108 N->op_begin(), N->getNumOperands()); 2109 AddToWorkList(Hi.getNode()); 2110 SDValue HiOpt = combine(Hi.getNode()); 2111 if (HiOpt.getNode() && HiOpt != Hi && 2112 (!LegalOperations || 2113 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2114 return CombineTo(N, HiOpt, HiOpt); 2115 } 2116 2117 return SDValue(); 2118} 2119 2120SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2121 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2122 if (Res.getNode()) return Res; 2123 2124 EVT VT = N->getValueType(0); 2125 DebugLoc DL = N->getDebugLoc(); 2126 2127 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2128 // plus a shift. 2129 if (VT.isSimple() && !VT.isVector()) { 2130 MVT Simple = VT.getSimpleVT(); 2131 unsigned SimpleSize = Simple.getSizeInBits(); 2132 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2133 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2134 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2135 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2136 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2137 // Compute the high part as N1. 2138 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2139 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2140 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2141 // Compute the low part as N0. 2142 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2143 return CombineTo(N, Lo, Hi); 2144 } 2145 } 2146 2147 return SDValue(); 2148} 2149 2150SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2151 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2152 if (Res.getNode()) return Res; 2153 2154 EVT VT = N->getValueType(0); 2155 DebugLoc DL = N->getDebugLoc(); 2156 2157 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2158 // plus a shift. 2159 if (VT.isSimple() && !VT.isVector()) { 2160 MVT Simple = VT.getSimpleVT(); 2161 unsigned SimpleSize = Simple.getSizeInBits(); 2162 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2163 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2164 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2165 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2166 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2167 // Compute the high part as N1. 2168 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2169 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2170 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2171 // Compute the low part as N0. 2172 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2173 return CombineTo(N, Lo, Hi); 2174 } 2175 } 2176 2177 return SDValue(); 2178} 2179 2180SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2181 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2182 if (Res.getNode()) return Res; 2183 2184 return SDValue(); 2185} 2186 2187SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2188 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2189 if (Res.getNode()) return Res; 2190 2191 return SDValue(); 2192} 2193 2194/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2195/// two operands of the same opcode, try to simplify it. 2196SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2197 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2198 EVT VT = N0.getValueType(); 2199 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2200 2201 // Bail early if none of these transforms apply. 2202 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2203 2204 // For each of OP in AND/OR/XOR: 2205 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2206 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2207 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2208 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2209 // 2210 // do not sink logical op inside of a vector extend, since it may combine 2211 // into a vsetcc. 2212 EVT Op0VT = N0.getOperand(0).getValueType(); 2213 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2214 N0.getOpcode() == ISD::SIGN_EXTEND || 2215 // Avoid infinite looping with PromoteIntBinOp. 2216 (N0.getOpcode() == ISD::ANY_EXTEND && 2217 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2218 (N0.getOpcode() == ISD::TRUNCATE && 2219 (!TLI.isZExtFree(VT, Op0VT) || 2220 !TLI.isTruncateFree(Op0VT, VT)) && 2221 TLI.isTypeLegal(Op0VT))) && 2222 !VT.isVector() && 2223 Op0VT == N1.getOperand(0).getValueType() && 2224 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2225 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2226 N0.getOperand(0).getValueType(), 2227 N0.getOperand(0), N1.getOperand(0)); 2228 AddToWorkList(ORNode.getNode()); 2229 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2230 } 2231 2232 // For each of OP in SHL/SRL/SRA/AND... 2233 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2234 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2235 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2236 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2237 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2238 N0.getOperand(1) == N1.getOperand(1)) { 2239 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2240 N0.getOperand(0).getValueType(), 2241 N0.getOperand(0), N1.getOperand(0)); 2242 AddToWorkList(ORNode.getNode()); 2243 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2244 ORNode, N0.getOperand(1)); 2245 } 2246 2247 return SDValue(); 2248} 2249 2250SDValue DAGCombiner::visitAND(SDNode *N) { 2251 SDValue N0 = N->getOperand(0); 2252 SDValue N1 = N->getOperand(1); 2253 SDValue LL, LR, RL, RR, CC0, CC1; 2254 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2255 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2256 EVT VT = N1.getValueType(); 2257 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2258 2259 // fold vector ops 2260 if (VT.isVector()) { 2261 SDValue FoldedVOp = SimplifyVBinOp(N); 2262 if (FoldedVOp.getNode()) return FoldedVOp; 2263 } 2264 2265 // fold (and x, undef) -> 0 2266 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2267 return DAG.getConstant(0, VT); 2268 // fold (and c1, c2) -> c1&c2 2269 if (N0C && N1C) 2270 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2271 // canonicalize constant to RHS 2272 if (N0C && !N1C) 2273 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2274 // fold (and x, -1) -> x 2275 if (N1C && N1C->isAllOnesValue()) 2276 return N0; 2277 // if (and x, c) is known to be zero, return 0 2278 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2279 APInt::getAllOnesValue(BitWidth))) 2280 return DAG.getConstant(0, VT); 2281 // reassociate and 2282 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2283 if (RAND.getNode() != 0) 2284 return RAND; 2285 // fold (and (or x, C), D) -> D if (C & D) == D 2286 if (N1C && N0.getOpcode() == ISD::OR) 2287 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2288 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2289 return N1; 2290 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2291 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2292 SDValue N0Op0 = N0.getOperand(0); 2293 APInt Mask = ~N1C->getAPIntValue(); 2294 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2295 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2296 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2297 N0.getValueType(), N0Op0); 2298 2299 // Replace uses of the AND with uses of the Zero extend node. 2300 CombineTo(N, Zext); 2301 2302 // We actually want to replace all uses of the any_extend with the 2303 // zero_extend, to avoid duplicating things. This will later cause this 2304 // AND to be folded. 2305 CombineTo(N0.getNode(), Zext); 2306 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2307 } 2308 } 2309 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2310 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2311 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2312 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2313 2314 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2315 LL.getValueType().isInteger()) { 2316 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2317 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2318 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2319 LR.getValueType(), LL, RL); 2320 AddToWorkList(ORNode.getNode()); 2321 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2322 } 2323 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2324 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2325 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2326 LR.getValueType(), LL, RL); 2327 AddToWorkList(ANDNode.getNode()); 2328 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2329 } 2330 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2331 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2332 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2333 LR.getValueType(), LL, RL); 2334 AddToWorkList(ORNode.getNode()); 2335 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2336 } 2337 } 2338 // canonicalize equivalent to ll == rl 2339 if (LL == RR && LR == RL) { 2340 Op1 = ISD::getSetCCSwappedOperands(Op1); 2341 std::swap(RL, RR); 2342 } 2343 if (LL == RL && LR == RR) { 2344 bool isInteger = LL.getValueType().isInteger(); 2345 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2346 if (Result != ISD::SETCC_INVALID && 2347 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2348 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2349 LL, LR, Result); 2350 } 2351 } 2352 2353 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2354 if (N0.getOpcode() == N1.getOpcode()) { 2355 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2356 if (Tmp.getNode()) return Tmp; 2357 } 2358 2359 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2360 // fold (and (sra)) -> (and (srl)) when possible. 2361 if (!VT.isVector() && 2362 SimplifyDemandedBits(SDValue(N, 0))) 2363 return SDValue(N, 0); 2364 2365 // fold (zext_inreg (extload x)) -> (zextload x) 2366 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2367 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2368 EVT MemVT = LN0->getMemoryVT(); 2369 // If we zero all the possible extended bits, then we can turn this into 2370 // a zextload if we are running before legalize or the operation is legal. 2371 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2372 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2373 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2374 ((!LegalOperations && !LN0->isVolatile()) || 2375 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2376 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2377 LN0->getChain(), LN0->getBasePtr(), 2378 LN0->getPointerInfo(), MemVT, 2379 LN0->isVolatile(), LN0->isNonTemporal(), 2380 LN0->getAlignment()); 2381 AddToWorkList(N); 2382 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2383 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2384 } 2385 } 2386 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2387 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2388 N0.hasOneUse()) { 2389 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2390 EVT MemVT = LN0->getMemoryVT(); 2391 // If we zero all the possible extended bits, then we can turn this into 2392 // a zextload if we are running before legalize or the operation is legal. 2393 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2394 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2395 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2396 ((!LegalOperations && !LN0->isVolatile()) || 2397 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2398 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2399 LN0->getChain(), 2400 LN0->getBasePtr(), LN0->getPointerInfo(), 2401 MemVT, 2402 LN0->isVolatile(), LN0->isNonTemporal(), 2403 LN0->getAlignment()); 2404 AddToWorkList(N); 2405 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2406 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2407 } 2408 } 2409 2410 // fold (and (load x), 255) -> (zextload x, i8) 2411 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2412 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2413 if (N1C && (N0.getOpcode() == ISD::LOAD || 2414 (N0.getOpcode() == ISD::ANY_EXTEND && 2415 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2416 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2417 LoadSDNode *LN0 = HasAnyExt 2418 ? cast<LoadSDNode>(N0.getOperand(0)) 2419 : cast<LoadSDNode>(N0); 2420 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2421 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2422 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2423 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2424 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2425 EVT LoadedVT = LN0->getMemoryVT(); 2426 2427 if (ExtVT == LoadedVT && 2428 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2429 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2430 2431 SDValue NewLoad = 2432 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2433 LN0->getChain(), LN0->getBasePtr(), 2434 LN0->getPointerInfo(), 2435 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2436 LN0->getAlignment()); 2437 AddToWorkList(N); 2438 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2439 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2440 } 2441 2442 // Do not change the width of a volatile load. 2443 // Do not generate loads of non-round integer types since these can 2444 // be expensive (and would be wrong if the type is not byte sized). 2445 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2446 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2447 EVT PtrType = LN0->getOperand(1).getValueType(); 2448 2449 unsigned Alignment = LN0->getAlignment(); 2450 SDValue NewPtr = LN0->getBasePtr(); 2451 2452 // For big endian targets, we need to add an offset to the pointer 2453 // to load the correct bytes. For little endian systems, we merely 2454 // need to read fewer bytes from the same pointer. 2455 if (TLI.isBigEndian()) { 2456 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2457 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2458 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2459 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2460 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2461 Alignment = MinAlign(Alignment, PtrOff); 2462 } 2463 2464 AddToWorkList(NewPtr.getNode()); 2465 2466 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2467 SDValue Load = 2468 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2469 LN0->getChain(), NewPtr, 2470 LN0->getPointerInfo(), 2471 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2472 Alignment); 2473 AddToWorkList(N); 2474 CombineTo(LN0, Load, Load.getValue(1)); 2475 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2476 } 2477 } 2478 } 2479 } 2480 2481 return SDValue(); 2482} 2483 2484SDValue DAGCombiner::visitOR(SDNode *N) { 2485 SDValue N0 = N->getOperand(0); 2486 SDValue N1 = N->getOperand(1); 2487 SDValue LL, LR, RL, RR, CC0, CC1; 2488 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2489 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2490 EVT VT = N1.getValueType(); 2491 2492 // fold vector ops 2493 if (VT.isVector()) { 2494 SDValue FoldedVOp = SimplifyVBinOp(N); 2495 if (FoldedVOp.getNode()) return FoldedVOp; 2496 } 2497 2498 // fold (or x, undef) -> -1 2499 if (!LegalOperations && 2500 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2501 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2502 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2503 } 2504 // fold (or c1, c2) -> c1|c2 2505 if (N0C && N1C) 2506 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2507 // canonicalize constant to RHS 2508 if (N0C && !N1C) 2509 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2510 // fold (or x, 0) -> x 2511 if (N1C && N1C->isNullValue()) 2512 return N0; 2513 // fold (or x, -1) -> -1 2514 if (N1C && N1C->isAllOnesValue()) 2515 return N1; 2516 // fold (or x, c) -> c iff (x & ~c) == 0 2517 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2518 return N1; 2519 // reassociate or 2520 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2521 if (ROR.getNode() != 0) 2522 return ROR; 2523 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2524 // iff (c1 & c2) == 0. 2525 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2526 isa<ConstantSDNode>(N0.getOperand(1))) { 2527 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2528 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2529 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2530 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2531 N0.getOperand(0), N1), 2532 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2533 } 2534 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2535 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2536 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2537 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2538 2539 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2540 LL.getValueType().isInteger()) { 2541 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2542 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2543 if (cast<ConstantSDNode>(LR)->isNullValue() && 2544 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2545 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2546 LR.getValueType(), LL, RL); 2547 AddToWorkList(ORNode.getNode()); 2548 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2549 } 2550 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2551 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2552 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2553 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2554 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2555 LR.getValueType(), LL, RL); 2556 AddToWorkList(ANDNode.getNode()); 2557 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2558 } 2559 } 2560 // canonicalize equivalent to ll == rl 2561 if (LL == RR && LR == RL) { 2562 Op1 = ISD::getSetCCSwappedOperands(Op1); 2563 std::swap(RL, RR); 2564 } 2565 if (LL == RL && LR == RR) { 2566 bool isInteger = LL.getValueType().isInteger(); 2567 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2568 if (Result != ISD::SETCC_INVALID && 2569 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2570 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2571 LL, LR, Result); 2572 } 2573 } 2574 2575 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2576 if (N0.getOpcode() == N1.getOpcode()) { 2577 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2578 if (Tmp.getNode()) return Tmp; 2579 } 2580 2581 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2582 if (N0.getOpcode() == ISD::AND && 2583 N1.getOpcode() == ISD::AND && 2584 N0.getOperand(1).getOpcode() == ISD::Constant && 2585 N1.getOperand(1).getOpcode() == ISD::Constant && 2586 // Don't increase # computations. 2587 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2588 // We can only do this xform if we know that bits from X that are set in C2 2589 // but not in C1 are already zero. Likewise for Y. 2590 const APInt &LHSMask = 2591 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2592 const APInt &RHSMask = 2593 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2594 2595 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2596 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2597 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2598 N0.getOperand(0), N1.getOperand(0)); 2599 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2600 DAG.getConstant(LHSMask | RHSMask, VT)); 2601 } 2602 } 2603 2604 // See if this is some rotate idiom. 2605 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2606 return SDValue(Rot, 0); 2607 2608 // Simplify the operands using demanded-bits information. 2609 if (!VT.isVector() && 2610 SimplifyDemandedBits(SDValue(N, 0))) 2611 return SDValue(N, 0); 2612 2613 return SDValue(); 2614} 2615 2616/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2617static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2618 if (Op.getOpcode() == ISD::AND) { 2619 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2620 Mask = Op.getOperand(1); 2621 Op = Op.getOperand(0); 2622 } else { 2623 return false; 2624 } 2625 } 2626 2627 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2628 Shift = Op; 2629 return true; 2630 } 2631 2632 return false; 2633} 2634 2635// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2636// idioms for rotate, and if the target supports rotation instructions, generate 2637// a rot[lr]. 2638SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2639 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2640 EVT VT = LHS.getValueType(); 2641 if (!TLI.isTypeLegal(VT)) return 0; 2642 2643 // The target must have at least one rotate flavor. 2644 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2645 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2646 if (!HasROTL && !HasROTR) return 0; 2647 2648 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2649 SDValue LHSShift; // The shift. 2650 SDValue LHSMask; // AND value if any. 2651 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2652 return 0; // Not part of a rotate. 2653 2654 SDValue RHSShift; // The shift. 2655 SDValue RHSMask; // AND value if any. 2656 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2657 return 0; // Not part of a rotate. 2658 2659 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2660 return 0; // Not shifting the same value. 2661 2662 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2663 return 0; // Shifts must disagree. 2664 2665 // Canonicalize shl to left side in a shl/srl pair. 2666 if (RHSShift.getOpcode() == ISD::SHL) { 2667 std::swap(LHS, RHS); 2668 std::swap(LHSShift, RHSShift); 2669 std::swap(LHSMask , RHSMask ); 2670 } 2671 2672 unsigned OpSizeInBits = VT.getSizeInBits(); 2673 SDValue LHSShiftArg = LHSShift.getOperand(0); 2674 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2675 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2676 2677 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2678 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2679 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2680 RHSShiftAmt.getOpcode() == ISD::Constant) { 2681 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2682 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2683 if ((LShVal + RShVal) != OpSizeInBits) 2684 return 0; 2685 2686 SDValue Rot; 2687 if (HasROTL) 2688 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2689 else 2690 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2691 2692 // If there is an AND of either shifted operand, apply it to the result. 2693 if (LHSMask.getNode() || RHSMask.getNode()) { 2694 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2695 2696 if (LHSMask.getNode()) { 2697 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2698 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2699 } 2700 if (RHSMask.getNode()) { 2701 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2702 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2703 } 2704 2705 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2706 } 2707 2708 return Rot.getNode(); 2709 } 2710 2711 // If there is a mask here, and we have a variable shift, we can't be sure 2712 // that we're masking out the right stuff. 2713 if (LHSMask.getNode() || RHSMask.getNode()) 2714 return 0; 2715 2716 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2717 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2718 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2719 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2720 if (ConstantSDNode *SUBC = 2721 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2722 if (SUBC->getAPIntValue() == OpSizeInBits) { 2723 if (HasROTL) 2724 return DAG.getNode(ISD::ROTL, DL, VT, 2725 LHSShiftArg, LHSShiftAmt).getNode(); 2726 else 2727 return DAG.getNode(ISD::ROTR, DL, VT, 2728 LHSShiftArg, RHSShiftAmt).getNode(); 2729 } 2730 } 2731 } 2732 2733 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2734 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2735 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2736 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2737 if (ConstantSDNode *SUBC = 2738 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2739 if (SUBC->getAPIntValue() == OpSizeInBits) { 2740 if (HasROTR) 2741 return DAG.getNode(ISD::ROTR, DL, VT, 2742 LHSShiftArg, RHSShiftAmt).getNode(); 2743 else 2744 return DAG.getNode(ISD::ROTL, DL, VT, 2745 LHSShiftArg, LHSShiftAmt).getNode(); 2746 } 2747 } 2748 } 2749 2750 // Look for sign/zext/any-extended or truncate cases: 2751 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2752 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2753 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2754 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2755 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2756 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2757 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2758 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2759 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2760 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2761 if (RExtOp0.getOpcode() == ISD::SUB && 2762 RExtOp0.getOperand(1) == LExtOp0) { 2763 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2764 // (rotl x, y) 2765 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2766 // (rotr x, (sub 32, y)) 2767 if (ConstantSDNode *SUBC = 2768 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2769 if (SUBC->getAPIntValue() == OpSizeInBits) { 2770 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2771 LHSShiftArg, 2772 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2773 } 2774 } 2775 } else if (LExtOp0.getOpcode() == ISD::SUB && 2776 RExtOp0 == LExtOp0.getOperand(1)) { 2777 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2778 // (rotr x, y) 2779 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2780 // (rotl x, (sub 32, y)) 2781 if (ConstantSDNode *SUBC = 2782 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2783 if (SUBC->getAPIntValue() == OpSizeInBits) { 2784 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2785 LHSShiftArg, 2786 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2787 } 2788 } 2789 } 2790 } 2791 2792 return 0; 2793} 2794 2795SDValue DAGCombiner::visitXOR(SDNode *N) { 2796 SDValue N0 = N->getOperand(0); 2797 SDValue N1 = N->getOperand(1); 2798 SDValue LHS, RHS, CC; 2799 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2800 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2801 EVT VT = N0.getValueType(); 2802 2803 // fold vector ops 2804 if (VT.isVector()) { 2805 SDValue FoldedVOp = SimplifyVBinOp(N); 2806 if (FoldedVOp.getNode()) return FoldedVOp; 2807 } 2808 2809 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2810 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2811 return DAG.getConstant(0, VT); 2812 // fold (xor x, undef) -> undef 2813 if (N0.getOpcode() == ISD::UNDEF) 2814 return N0; 2815 if (N1.getOpcode() == ISD::UNDEF) 2816 return N1; 2817 // fold (xor c1, c2) -> c1^c2 2818 if (N0C && N1C) 2819 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2820 // canonicalize constant to RHS 2821 if (N0C && !N1C) 2822 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2823 // fold (xor x, 0) -> x 2824 if (N1C && N1C->isNullValue()) 2825 return N0; 2826 // reassociate xor 2827 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2828 if (RXOR.getNode() != 0) 2829 return RXOR; 2830 2831 // fold !(x cc y) -> (x !cc y) 2832 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2833 bool isInt = LHS.getValueType().isInteger(); 2834 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2835 isInt); 2836 2837 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2838 switch (N0.getOpcode()) { 2839 default: 2840 llvm_unreachable("Unhandled SetCC Equivalent!"); 2841 case ISD::SETCC: 2842 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2843 case ISD::SELECT_CC: 2844 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2845 N0.getOperand(3), NotCC); 2846 } 2847 } 2848 } 2849 2850 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2851 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2852 N0.getNode()->hasOneUse() && 2853 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2854 SDValue V = N0.getOperand(0); 2855 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2856 DAG.getConstant(1, V.getValueType())); 2857 AddToWorkList(V.getNode()); 2858 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2859 } 2860 2861 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2862 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2863 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2864 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2865 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2866 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2867 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2868 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2869 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2870 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2871 } 2872 } 2873 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2874 if (N1C && N1C->isAllOnesValue() && 2875 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2876 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2877 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2878 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2879 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2880 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2881 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2882 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2883 } 2884 } 2885 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2886 if (N1C && N0.getOpcode() == ISD::XOR) { 2887 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2888 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2889 if (N00C) 2890 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2891 DAG.getConstant(N1C->getAPIntValue() ^ 2892 N00C->getAPIntValue(), VT)); 2893 if (N01C) 2894 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2895 DAG.getConstant(N1C->getAPIntValue() ^ 2896 N01C->getAPIntValue(), VT)); 2897 } 2898 // fold (xor x, x) -> 0 2899 if (N0 == N1) 2900 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 2901 2902 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2903 if (N0.getOpcode() == N1.getOpcode()) { 2904 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2905 if (Tmp.getNode()) return Tmp; 2906 } 2907 2908 // Simplify the expression using non-local knowledge. 2909 if (!VT.isVector() && 2910 SimplifyDemandedBits(SDValue(N, 0))) 2911 return SDValue(N, 0); 2912 2913 return SDValue(); 2914} 2915 2916/// visitShiftByConstant - Handle transforms common to the three shifts, when 2917/// the shift amount is a constant. 2918SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2919 SDNode *LHS = N->getOperand(0).getNode(); 2920 if (!LHS->hasOneUse()) return SDValue(); 2921 2922 // We want to pull some binops through shifts, so that we have (and (shift)) 2923 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2924 // thing happens with address calculations, so it's important to canonicalize 2925 // it. 2926 bool HighBitSet = false; // Can we transform this if the high bit is set? 2927 2928 switch (LHS->getOpcode()) { 2929 default: return SDValue(); 2930 case ISD::OR: 2931 case ISD::XOR: 2932 HighBitSet = false; // We can only transform sra if the high bit is clear. 2933 break; 2934 case ISD::AND: 2935 HighBitSet = true; // We can only transform sra if the high bit is set. 2936 break; 2937 case ISD::ADD: 2938 if (N->getOpcode() != ISD::SHL) 2939 return SDValue(); // only shl(add) not sr[al](add). 2940 HighBitSet = false; // We can only transform sra if the high bit is clear. 2941 break; 2942 } 2943 2944 // We require the RHS of the binop to be a constant as well. 2945 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2946 if (!BinOpCst) return SDValue(); 2947 2948 // FIXME: disable this unless the input to the binop is a shift by a constant. 2949 // If it is not a shift, it pessimizes some common cases like: 2950 // 2951 // void foo(int *X, int i) { X[i & 1235] = 1; } 2952 // int bar(int *X, int i) { return X[i & 255]; } 2953 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2954 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2955 BinOpLHSVal->getOpcode() != ISD::SRA && 2956 BinOpLHSVal->getOpcode() != ISD::SRL) || 2957 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2958 return SDValue(); 2959 2960 EVT VT = N->getValueType(0); 2961 2962 // If this is a signed shift right, and the high bit is modified by the 2963 // logical operation, do not perform the transformation. The highBitSet 2964 // boolean indicates the value of the high bit of the constant which would 2965 // cause it to be modified for this operation. 2966 if (N->getOpcode() == ISD::SRA) { 2967 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2968 if (BinOpRHSSignSet != HighBitSet) 2969 return SDValue(); 2970 } 2971 2972 // Fold the constants, shifting the binop RHS by the shift amount. 2973 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2974 N->getValueType(0), 2975 LHS->getOperand(1), N->getOperand(1)); 2976 2977 // Create the new shift. 2978 SDValue NewShift = DAG.getNode(N->getOpcode(), 2979 LHS->getOperand(0).getDebugLoc(), 2980 VT, LHS->getOperand(0), N->getOperand(1)); 2981 2982 // Create the new binop. 2983 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2984} 2985 2986SDValue DAGCombiner::visitSHL(SDNode *N) { 2987 SDValue N0 = N->getOperand(0); 2988 SDValue N1 = N->getOperand(1); 2989 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2990 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2991 EVT VT = N0.getValueType(); 2992 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2993 2994 // fold (shl c1, c2) -> c1<<c2 2995 if (N0C && N1C) 2996 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2997 // fold (shl 0, x) -> 0 2998 if (N0C && N0C->isNullValue()) 2999 return N0; 3000 // fold (shl x, c >= size(x)) -> undef 3001 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3002 return DAG.getUNDEF(VT); 3003 // fold (shl x, 0) -> x 3004 if (N1C && N1C->isNullValue()) 3005 return N0; 3006 // if (shl x, c) is known to be zero, return 0 3007 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3008 APInt::getAllOnesValue(OpSizeInBits))) 3009 return DAG.getConstant(0, VT); 3010 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3011 if (N1.getOpcode() == ISD::TRUNCATE && 3012 N1.getOperand(0).getOpcode() == ISD::AND && 3013 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3014 SDValue N101 = N1.getOperand(0).getOperand(1); 3015 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3016 EVT TruncVT = N1.getValueType(); 3017 SDValue N100 = N1.getOperand(0).getOperand(0); 3018 APInt TruncC = N101C->getAPIntValue(); 3019 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3020 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3021 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3022 DAG.getNode(ISD::TRUNCATE, 3023 N->getDebugLoc(), 3024 TruncVT, N100), 3025 DAG.getConstant(TruncC, TruncVT))); 3026 } 3027 } 3028 3029 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3030 return SDValue(N, 0); 3031 3032 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3033 if (N1C && N0.getOpcode() == ISD::SHL && 3034 N0.getOperand(1).getOpcode() == ISD::Constant) { 3035 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3036 uint64_t c2 = N1C->getZExtValue(); 3037 if (c1 + c2 >= OpSizeInBits) 3038 return DAG.getConstant(0, VT); 3039 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3040 DAG.getConstant(c1 + c2, N1.getValueType())); 3041 } 3042 3043 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3044 // For this to be valid, the second form must not preserve any of the bits 3045 // that are shifted out by the inner shift in the first form. This means 3046 // the outer shift size must be >= the number of bits added by the ext. 3047 // As a corollary, we don't care what kind of ext it is. 3048 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3049 N0.getOpcode() == ISD::ANY_EXTEND || 3050 N0.getOpcode() == ISD::SIGN_EXTEND) && 3051 N0.getOperand(0).getOpcode() == ISD::SHL && 3052 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3053 uint64_t c1 = 3054 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3055 uint64_t c2 = N1C->getZExtValue(); 3056 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3057 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3058 if (c2 >= OpSizeInBits - InnerShiftSize) { 3059 if (c1 + c2 >= OpSizeInBits) 3060 return DAG.getConstant(0, VT); 3061 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3062 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3063 N0.getOperand(0)->getOperand(0)), 3064 DAG.getConstant(c1 + c2, N1.getValueType())); 3065 } 3066 } 3067 3068 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 3069 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 3070 if (N1C && N0.getOpcode() == ISD::SRL && 3071 N0.getOperand(1).getOpcode() == ISD::Constant) { 3072 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3073 if (c1 < VT.getSizeInBits()) { 3074 uint64_t c2 = N1C->getZExtValue(); 3075 SDValue HiBitsMask = 3076 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3077 VT.getSizeInBits() - c1), 3078 VT); 3079 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 3080 N0.getOperand(0), 3081 HiBitsMask); 3082 if (c2 > c1) 3083 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 3084 DAG.getConstant(c2-c1, N1.getValueType())); 3085 else 3086 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 3087 DAG.getConstant(c1-c2, N1.getValueType())); 3088 } 3089 } 3090 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3091 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3092 SDValue HiBitsMask = 3093 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3094 VT.getSizeInBits() - 3095 N1C->getZExtValue()), 3096 VT); 3097 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3098 HiBitsMask); 3099 } 3100 3101 if (N1C) { 3102 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3103 if (NewSHL.getNode()) 3104 return NewSHL; 3105 } 3106 3107 return SDValue(); 3108} 3109 3110SDValue DAGCombiner::visitSRA(SDNode *N) { 3111 SDValue N0 = N->getOperand(0); 3112 SDValue N1 = N->getOperand(1); 3113 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3114 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3115 EVT VT = N0.getValueType(); 3116 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3117 3118 // fold (sra c1, c2) -> (sra c1, c2) 3119 if (N0C && N1C) 3120 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3121 // fold (sra 0, x) -> 0 3122 if (N0C && N0C->isNullValue()) 3123 return N0; 3124 // fold (sra -1, x) -> -1 3125 if (N0C && N0C->isAllOnesValue()) 3126 return N0; 3127 // fold (sra x, (setge c, size(x))) -> undef 3128 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3129 return DAG.getUNDEF(VT); 3130 // fold (sra x, 0) -> x 3131 if (N1C && N1C->isNullValue()) 3132 return N0; 3133 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3134 // sext_inreg. 3135 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3136 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3137 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3138 if (VT.isVector()) 3139 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3140 ExtVT, VT.getVectorNumElements()); 3141 if ((!LegalOperations || 3142 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3143 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3144 N0.getOperand(0), DAG.getValueType(ExtVT)); 3145 } 3146 3147 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3148 if (N1C && N0.getOpcode() == ISD::SRA) { 3149 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3150 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3151 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3152 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3153 DAG.getConstant(Sum, N1C->getValueType(0))); 3154 } 3155 } 3156 3157 // fold (sra (shl X, m), (sub result_size, n)) 3158 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3159 // result_size - n != m. 3160 // If truncate is free for the target sext(shl) is likely to result in better 3161 // code. 3162 if (N0.getOpcode() == ISD::SHL) { 3163 // Get the two constanst of the shifts, CN0 = m, CN = n. 3164 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3165 if (N01C && N1C) { 3166 // Determine what the truncate's result bitsize and type would be. 3167 EVT TruncVT = 3168 EVT::getIntegerVT(*DAG.getContext(), 3169 OpSizeInBits - N1C->getZExtValue()); 3170 // Determine the residual right-shift amount. 3171 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3172 3173 // If the shift is not a no-op (in which case this should be just a sign 3174 // extend already), the truncated to type is legal, sign_extend is legal 3175 // on that type, and the truncate to that type is both legal and free, 3176 // perform the transform. 3177 if ((ShiftAmt > 0) && 3178 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3179 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3180 TLI.isTruncateFree(VT, TruncVT)) { 3181 3182 SDValue Amt = DAG.getConstant(ShiftAmt, 3183 getShiftAmountTy(N0.getOperand(0).getValueType())); 3184 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3185 N0.getOperand(0), Amt); 3186 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3187 Shift); 3188 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3189 N->getValueType(0), Trunc); 3190 } 3191 } 3192 } 3193 3194 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3195 if (N1.getOpcode() == ISD::TRUNCATE && 3196 N1.getOperand(0).getOpcode() == ISD::AND && 3197 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3198 SDValue N101 = N1.getOperand(0).getOperand(1); 3199 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3200 EVT TruncVT = N1.getValueType(); 3201 SDValue N100 = N1.getOperand(0).getOperand(0); 3202 APInt TruncC = N101C->getAPIntValue(); 3203 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3204 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3205 DAG.getNode(ISD::AND, N->getDebugLoc(), 3206 TruncVT, 3207 DAG.getNode(ISD::TRUNCATE, 3208 N->getDebugLoc(), 3209 TruncVT, N100), 3210 DAG.getConstant(TruncC, TruncVT))); 3211 } 3212 } 3213 3214 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3215 // if c1 is equal to the number of bits the trunc removes 3216 if (N0.getOpcode() == ISD::TRUNCATE && 3217 (N0.getOperand(0).getOpcode() == ISD::SRL || 3218 N0.getOperand(0).getOpcode() == ISD::SRA) && 3219 N0.getOperand(0).hasOneUse() && 3220 N0.getOperand(0).getOperand(1).hasOneUse() && 3221 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3222 EVT LargeVT = N0.getOperand(0).getValueType(); 3223 ConstantSDNode *LargeShiftAmt = 3224 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3225 3226 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3227 LargeShiftAmt->getZExtValue()) { 3228 SDValue Amt = 3229 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3230 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3231 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3232 N0.getOperand(0).getOperand(0), Amt); 3233 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3234 } 3235 } 3236 3237 // Simplify, based on bits shifted out of the LHS. 3238 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3239 return SDValue(N, 0); 3240 3241 3242 // If the sign bit is known to be zero, switch this to a SRL. 3243 if (DAG.SignBitIsZero(N0)) 3244 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3245 3246 if (N1C) { 3247 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3248 if (NewSRA.getNode()) 3249 return NewSRA; 3250 } 3251 3252 return SDValue(); 3253} 3254 3255SDValue DAGCombiner::visitSRL(SDNode *N) { 3256 SDValue N0 = N->getOperand(0); 3257 SDValue N1 = N->getOperand(1); 3258 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3259 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3260 EVT VT = N0.getValueType(); 3261 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3262 3263 // fold (srl c1, c2) -> c1 >>u c2 3264 if (N0C && N1C) 3265 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3266 // fold (srl 0, x) -> 0 3267 if (N0C && N0C->isNullValue()) 3268 return N0; 3269 // fold (srl x, c >= size(x)) -> undef 3270 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3271 return DAG.getUNDEF(VT); 3272 // fold (srl x, 0) -> x 3273 if (N1C && N1C->isNullValue()) 3274 return N0; 3275 // if (srl x, c) is known to be zero, return 0 3276 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3277 APInt::getAllOnesValue(OpSizeInBits))) 3278 return DAG.getConstant(0, VT); 3279 3280 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3281 if (N1C && N0.getOpcode() == ISD::SRL && 3282 N0.getOperand(1).getOpcode() == ISD::Constant) { 3283 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3284 uint64_t c2 = N1C->getZExtValue(); 3285 if (c1 + c2 >= OpSizeInBits) 3286 return DAG.getConstant(0, VT); 3287 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3288 DAG.getConstant(c1 + c2, N1.getValueType())); 3289 } 3290 3291 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3292 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3293 N0.getOperand(0).getOpcode() == ISD::SRL && 3294 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3295 uint64_t c1 = 3296 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3297 uint64_t c2 = N1C->getZExtValue(); 3298 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3299 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3300 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3301 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3302 if (c1 + OpSizeInBits == InnerShiftSize) { 3303 if (c1 + c2 >= InnerShiftSize) 3304 return DAG.getConstant(0, VT); 3305 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3306 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3307 N0.getOperand(0)->getOperand(0), 3308 DAG.getConstant(c1 + c2, ShiftCountVT))); 3309 } 3310 } 3311 3312 // fold (srl (shl x, c), c) -> (and x, cst2) 3313 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3314 N0.getValueSizeInBits() <= 64) { 3315 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3316 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3317 DAG.getConstant(~0ULL >> ShAmt, VT)); 3318 } 3319 3320 3321 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3322 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3323 // Shifting in all undef bits? 3324 EVT SmallVT = N0.getOperand(0).getValueType(); 3325 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3326 return DAG.getUNDEF(VT); 3327 3328 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3329 uint64_t ShiftAmt = N1C->getZExtValue(); 3330 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3331 N0.getOperand(0), 3332 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3333 AddToWorkList(SmallShift.getNode()); 3334 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3335 } 3336 } 3337 3338 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3339 // bit, which is unmodified by sra. 3340 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3341 if (N0.getOpcode() == ISD::SRA) 3342 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3343 } 3344 3345 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3346 if (N1C && N0.getOpcode() == ISD::CTLZ && 3347 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3348 APInt KnownZero, KnownOne; 3349 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 3350 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 3351 3352 // If any of the input bits are KnownOne, then the input couldn't be all 3353 // zeros, thus the result of the srl will always be zero. 3354 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3355 3356 // If all of the bits input the to ctlz node are known to be zero, then 3357 // the result of the ctlz is "32" and the result of the shift is one. 3358 APInt UnknownBits = ~KnownZero & Mask; 3359 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3360 3361 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3362 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3363 // Okay, we know that only that the single bit specified by UnknownBits 3364 // could be set on input to the CTLZ node. If this bit is set, the SRL 3365 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3366 // to an SRL/XOR pair, which is likely to simplify more. 3367 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3368 SDValue Op = N0.getOperand(0); 3369 3370 if (ShAmt) { 3371 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3372 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3373 AddToWorkList(Op.getNode()); 3374 } 3375 3376 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3377 Op, DAG.getConstant(1, VT)); 3378 } 3379 } 3380 3381 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3382 if (N1.getOpcode() == ISD::TRUNCATE && 3383 N1.getOperand(0).getOpcode() == ISD::AND && 3384 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3385 SDValue N101 = N1.getOperand(0).getOperand(1); 3386 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3387 EVT TruncVT = N1.getValueType(); 3388 SDValue N100 = N1.getOperand(0).getOperand(0); 3389 APInt TruncC = N101C->getAPIntValue(); 3390 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3391 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3392 DAG.getNode(ISD::AND, N->getDebugLoc(), 3393 TruncVT, 3394 DAG.getNode(ISD::TRUNCATE, 3395 N->getDebugLoc(), 3396 TruncVT, N100), 3397 DAG.getConstant(TruncC, TruncVT))); 3398 } 3399 } 3400 3401 // fold operands of srl based on knowledge that the low bits are not 3402 // demanded. 3403 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3404 return SDValue(N, 0); 3405 3406 if (N1C) { 3407 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3408 if (NewSRL.getNode()) 3409 return NewSRL; 3410 } 3411 3412 // Attempt to convert a srl of a load into a narrower zero-extending load. 3413 SDValue NarrowLoad = ReduceLoadWidth(N); 3414 if (NarrowLoad.getNode()) 3415 return NarrowLoad; 3416 3417 // Here is a common situation. We want to optimize: 3418 // 3419 // %a = ... 3420 // %b = and i32 %a, 2 3421 // %c = srl i32 %b, 1 3422 // brcond i32 %c ... 3423 // 3424 // into 3425 // 3426 // %a = ... 3427 // %b = and %a, 2 3428 // %c = setcc eq %b, 0 3429 // brcond %c ... 3430 // 3431 // However when after the source operand of SRL is optimized into AND, the SRL 3432 // itself may not be optimized further. Look for it and add the BRCOND into 3433 // the worklist. 3434 if (N->hasOneUse()) { 3435 SDNode *Use = *N->use_begin(); 3436 if (Use->getOpcode() == ISD::BRCOND) 3437 AddToWorkList(Use); 3438 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3439 // Also look pass the truncate. 3440 Use = *Use->use_begin(); 3441 if (Use->getOpcode() == ISD::BRCOND) 3442 AddToWorkList(Use); 3443 } 3444 } 3445 3446 return SDValue(); 3447} 3448 3449SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3450 SDValue N0 = N->getOperand(0); 3451 EVT VT = N->getValueType(0); 3452 3453 // fold (ctlz c1) -> c2 3454 if (isa<ConstantSDNode>(N0)) 3455 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3456 return SDValue(); 3457} 3458 3459SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3460 SDValue N0 = N->getOperand(0); 3461 EVT VT = N->getValueType(0); 3462 3463 // fold (cttz c1) -> c2 3464 if (isa<ConstantSDNode>(N0)) 3465 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3466 return SDValue(); 3467} 3468 3469SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3470 SDValue N0 = N->getOperand(0); 3471 EVT VT = N->getValueType(0); 3472 3473 // fold (ctpop c1) -> c2 3474 if (isa<ConstantSDNode>(N0)) 3475 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3476 return SDValue(); 3477} 3478 3479SDValue DAGCombiner::visitSELECT(SDNode *N) { 3480 SDValue N0 = N->getOperand(0); 3481 SDValue N1 = N->getOperand(1); 3482 SDValue N2 = N->getOperand(2); 3483 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3484 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3485 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3486 EVT VT = N->getValueType(0); 3487 EVT VT0 = N0.getValueType(); 3488 3489 // fold (select C, X, X) -> X 3490 if (N1 == N2) 3491 return N1; 3492 // fold (select true, X, Y) -> X 3493 if (N0C && !N0C->isNullValue()) 3494 return N1; 3495 // fold (select false, X, Y) -> Y 3496 if (N0C && N0C->isNullValue()) 3497 return N2; 3498 // fold (select C, 1, X) -> (or C, X) 3499 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 3500 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3501 // fold (select C, 0, 1) -> (xor C, 1) 3502 if (VT.isInteger() && 3503 (VT0 == MVT::i1 || 3504 (VT0.isInteger() && 3505 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 3506 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 3507 SDValue XORNode; 3508 if (VT == VT0) 3509 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 3510 N0, DAG.getConstant(1, VT0)); 3511 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 3512 N0, DAG.getConstant(1, VT0)); 3513 AddToWorkList(XORNode.getNode()); 3514 if (VT.bitsGT(VT0)) 3515 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 3516 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 3517 } 3518 // fold (select C, 0, X) -> (and (not C), X) 3519 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 3520 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3521 AddToWorkList(NOTNode.getNode()); 3522 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 3523 } 3524 // fold (select C, X, 1) -> (or (not C), X) 3525 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 3526 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3527 AddToWorkList(NOTNode.getNode()); 3528 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 3529 } 3530 // fold (select C, X, 0) -> (and C, X) 3531 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 3532 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3533 // fold (select X, X, Y) -> (or X, Y) 3534 // fold (select X, 1, Y) -> (or X, Y) 3535 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 3536 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3537 // fold (select X, Y, X) -> (and X, Y) 3538 // fold (select X, Y, 0) -> (and X, Y) 3539 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 3540 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3541 3542 // If we can fold this based on the true/false value, do so. 3543 if (SimplifySelectOps(N, N1, N2)) 3544 return SDValue(N, 0); // Don't revisit N. 3545 3546 // fold selects based on a setcc into other things, such as min/max/abs 3547 if (N0.getOpcode() == ISD::SETCC) { 3548 // FIXME: 3549 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 3550 // having to say they don't support SELECT_CC on every type the DAG knows 3551 // about, since there is no way to mark an opcode illegal at all value types 3552 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 3553 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 3554 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 3555 N0.getOperand(0), N0.getOperand(1), 3556 N1, N2, N0.getOperand(2)); 3557 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 3558 } 3559 3560 return SDValue(); 3561} 3562 3563SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 3564 SDValue N0 = N->getOperand(0); 3565 SDValue N1 = N->getOperand(1); 3566 SDValue N2 = N->getOperand(2); 3567 SDValue N3 = N->getOperand(3); 3568 SDValue N4 = N->getOperand(4); 3569 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 3570 3571 // fold select_cc lhs, rhs, x, x, cc -> x 3572 if (N2 == N3) 3573 return N2; 3574 3575 // Determine if the condition we're dealing with is constant 3576 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 3577 N0, N1, CC, N->getDebugLoc(), false); 3578 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 3579 3580 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 3581 if (!SCCC->isNullValue()) 3582 return N2; // cond always true -> true val 3583 else 3584 return N3; // cond always false -> false val 3585 } 3586 3587 // Fold to a simpler select_cc 3588 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 3589 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 3590 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 3591 SCC.getOperand(2)); 3592 3593 // If we can fold this based on the true/false value, do so. 3594 if (SimplifySelectOps(N, N2, N3)) 3595 return SDValue(N, 0); // Don't revisit N. 3596 3597 // fold select_cc into other things, such as min/max/abs 3598 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3599} 3600 3601SDValue DAGCombiner::visitSETCC(SDNode *N) { 3602 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3603 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3604 N->getDebugLoc()); 3605} 3606 3607// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3608// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3609// transformation. Returns true if extension are possible and the above 3610// mentioned transformation is profitable. 3611static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3612 unsigned ExtOpc, 3613 SmallVector<SDNode*, 4> &ExtendNodes, 3614 const TargetLowering &TLI) { 3615 bool HasCopyToRegUses = false; 3616 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3617 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3618 UE = N0.getNode()->use_end(); 3619 UI != UE; ++UI) { 3620 SDNode *User = *UI; 3621 if (User == N) 3622 continue; 3623 if (UI.getUse().getResNo() != N0.getResNo()) 3624 continue; 3625 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3626 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3627 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3628 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3629 // Sign bits will be lost after a zext. 3630 return false; 3631 bool Add = false; 3632 for (unsigned i = 0; i != 2; ++i) { 3633 SDValue UseOp = User->getOperand(i); 3634 if (UseOp == N0) 3635 continue; 3636 if (!isa<ConstantSDNode>(UseOp)) 3637 return false; 3638 Add = true; 3639 } 3640 if (Add) 3641 ExtendNodes.push_back(User); 3642 continue; 3643 } 3644 // If truncates aren't free and there are users we can't 3645 // extend, it isn't worthwhile. 3646 if (!isTruncFree) 3647 return false; 3648 // Remember if this value is live-out. 3649 if (User->getOpcode() == ISD::CopyToReg) 3650 HasCopyToRegUses = true; 3651 } 3652 3653 if (HasCopyToRegUses) { 3654 bool BothLiveOut = false; 3655 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3656 UI != UE; ++UI) { 3657 SDUse &Use = UI.getUse(); 3658 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3659 BothLiveOut = true; 3660 break; 3661 } 3662 } 3663 if (BothLiveOut) 3664 // Both unextended and extended values are live out. There had better be 3665 // a good reason for the transformation. 3666 return ExtendNodes.size(); 3667 } 3668 return true; 3669} 3670 3671SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3672 SDValue N0 = N->getOperand(0); 3673 EVT VT = N->getValueType(0); 3674 3675 // fold (sext c1) -> c1 3676 if (isa<ConstantSDNode>(N0)) 3677 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3678 3679 // fold (sext (sext x)) -> (sext x) 3680 // fold (sext (aext x)) -> (sext x) 3681 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3682 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3683 N0.getOperand(0)); 3684 3685 if (N0.getOpcode() == ISD::TRUNCATE) { 3686 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3687 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3688 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3689 if (NarrowLoad.getNode()) { 3690 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3691 if (NarrowLoad.getNode() != N0.getNode()) { 3692 CombineTo(N0.getNode(), NarrowLoad); 3693 // CombineTo deleted the truncate, if needed, but not what's under it. 3694 AddToWorkList(oye); 3695 } 3696 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3697 } 3698 3699 // See if the value being truncated is already sign extended. If so, just 3700 // eliminate the trunc/sext pair. 3701 SDValue Op = N0.getOperand(0); 3702 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3703 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3704 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3705 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3706 3707 if (OpBits == DestBits) { 3708 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3709 // bits, it is already ready. 3710 if (NumSignBits > DestBits-MidBits) 3711 return Op; 3712 } else if (OpBits < DestBits) { 3713 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3714 // bits, just sext from i32. 3715 if (NumSignBits > OpBits-MidBits) 3716 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3717 } else { 3718 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3719 // bits, just truncate to i32. 3720 if (NumSignBits > OpBits-MidBits) 3721 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3722 } 3723 3724 // fold (sext (truncate x)) -> (sextinreg x). 3725 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3726 N0.getValueType())) { 3727 if (OpBits < DestBits) 3728 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3729 else if (OpBits > DestBits) 3730 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3731 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3732 DAG.getValueType(N0.getValueType())); 3733 } 3734 } 3735 3736 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3737 // None of the supported targets knows how to perform load and sign extend 3738 // on vectors in one instruction. We only perform this transformation on 3739 // scalars. 3740 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 3741 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3742 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3743 bool DoXform = true; 3744 SmallVector<SDNode*, 4> SetCCs; 3745 if (!N0.hasOneUse()) 3746 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3747 if (DoXform) { 3748 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3749 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3750 LN0->getChain(), 3751 LN0->getBasePtr(), LN0->getPointerInfo(), 3752 N0.getValueType(), 3753 LN0->isVolatile(), LN0->isNonTemporal(), 3754 LN0->getAlignment()); 3755 CombineTo(N, ExtLoad); 3756 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3757 N0.getValueType(), ExtLoad); 3758 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3759 3760 // Extend SetCC uses if necessary. 3761 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3762 SDNode *SetCC = SetCCs[i]; 3763 SmallVector<SDValue, 4> Ops; 3764 3765 for (unsigned j = 0; j != 2; ++j) { 3766 SDValue SOp = SetCC->getOperand(j); 3767 if (SOp == Trunc) 3768 Ops.push_back(ExtLoad); 3769 else 3770 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3771 N->getDebugLoc(), VT, SOp)); 3772 } 3773 3774 Ops.push_back(SetCC->getOperand(2)); 3775 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3776 SetCC->getValueType(0), 3777 &Ops[0], Ops.size())); 3778 } 3779 3780 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3781 } 3782 } 3783 3784 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3785 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3786 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3787 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3788 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3789 EVT MemVT = LN0->getMemoryVT(); 3790 if ((!LegalOperations && !LN0->isVolatile()) || 3791 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3792 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3793 LN0->getChain(), 3794 LN0->getBasePtr(), LN0->getPointerInfo(), 3795 MemVT, 3796 LN0->isVolatile(), LN0->isNonTemporal(), 3797 LN0->getAlignment()); 3798 CombineTo(N, ExtLoad); 3799 CombineTo(N0.getNode(), 3800 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3801 N0.getValueType(), ExtLoad), 3802 ExtLoad.getValue(1)); 3803 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3804 } 3805 } 3806 3807 if (N0.getOpcode() == ISD::SETCC) { 3808 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3809 // Only do this before legalize for now. 3810 if (VT.isVector() && !LegalOperations) { 3811 EVT N0VT = N0.getOperand(0).getValueType(); 3812 // We know that the # elements of the results is the same as the 3813 // # elements of the compare (and the # elements of the compare result 3814 // for that matter). Check to see that they are the same size. If so, 3815 // we know that the element size of the sext'd result matches the 3816 // element size of the compare operands. 3817 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 3818 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3819 N0.getOperand(1), 3820 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3821 // If the desired elements are smaller or larger than the source 3822 // elements we can use a matching integer vector type and then 3823 // truncate/sign extend 3824 else { 3825 EVT MatchingElementType = 3826 EVT::getIntegerVT(*DAG.getContext(), 3827 N0VT.getScalarType().getSizeInBits()); 3828 EVT MatchingVectorType = 3829 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3830 N0VT.getVectorNumElements()); 3831 SDValue VsetCC = 3832 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3833 N0.getOperand(1), 3834 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3835 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 3836 } 3837 } 3838 3839 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3840 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 3841 SDValue NegOne = 3842 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 3843 SDValue SCC = 3844 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3845 NegOne, DAG.getConstant(0, VT), 3846 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3847 if (SCC.getNode()) return SCC; 3848 if (!LegalOperations || 3849 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 3850 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 3851 DAG.getSetCC(N->getDebugLoc(), 3852 TLI.getSetCCResultType(VT), 3853 N0.getOperand(0), N0.getOperand(1), 3854 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3855 NegOne, DAG.getConstant(0, VT)); 3856 } 3857 3858 // fold (sext x) -> (zext x) if the sign bit is known zero. 3859 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3860 DAG.SignBitIsZero(N0)) 3861 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3862 3863 return SDValue(); 3864} 3865 3866SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3867 SDValue N0 = N->getOperand(0); 3868 EVT VT = N->getValueType(0); 3869 3870 // fold (zext c1) -> c1 3871 if (isa<ConstantSDNode>(N0)) 3872 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3873 // fold (zext (zext x)) -> (zext x) 3874 // fold (zext (aext x)) -> (zext x) 3875 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3876 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3877 N0.getOperand(0)); 3878 3879 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3880 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3881 if (N0.getOpcode() == ISD::TRUNCATE) { 3882 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3883 if (NarrowLoad.getNode()) { 3884 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3885 if (NarrowLoad.getNode() != N0.getNode()) { 3886 CombineTo(N0.getNode(), NarrowLoad); 3887 // CombineTo deleted the truncate, if needed, but not what's under it. 3888 AddToWorkList(oye); 3889 } 3890 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3891 } 3892 } 3893 3894 // fold (zext (truncate x)) -> (and x, mask) 3895 if (N0.getOpcode() == ISD::TRUNCATE && 3896 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3897 3898 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3899 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 3900 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3901 if (NarrowLoad.getNode()) { 3902 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3903 if (NarrowLoad.getNode() != N0.getNode()) { 3904 CombineTo(N0.getNode(), NarrowLoad); 3905 // CombineTo deleted the truncate, if needed, but not what's under it. 3906 AddToWorkList(oye); 3907 } 3908 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3909 } 3910 3911 SDValue Op = N0.getOperand(0); 3912 if (Op.getValueType().bitsLT(VT)) { 3913 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3914 } else if (Op.getValueType().bitsGT(VT)) { 3915 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3916 } 3917 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3918 N0.getValueType().getScalarType()); 3919 } 3920 3921 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3922 // if either of the casts is not free. 3923 if (N0.getOpcode() == ISD::AND && 3924 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3925 N0.getOperand(1).getOpcode() == ISD::Constant && 3926 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3927 N0.getValueType()) || 3928 !TLI.isZExtFree(N0.getValueType(), VT))) { 3929 SDValue X = N0.getOperand(0).getOperand(0); 3930 if (X.getValueType().bitsLT(VT)) { 3931 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3932 } else if (X.getValueType().bitsGT(VT)) { 3933 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3934 } 3935 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3936 Mask = Mask.zext(VT.getSizeInBits()); 3937 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3938 X, DAG.getConstant(Mask, VT)); 3939 } 3940 3941 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3942 // None of the supported targets knows how to perform load and vector_zext 3943 // on vectors in one instruction. We only perform this transformation on 3944 // scalars. 3945 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 3946 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3947 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3948 bool DoXform = true; 3949 SmallVector<SDNode*, 4> SetCCs; 3950 if (!N0.hasOneUse()) 3951 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3952 if (DoXform) { 3953 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3954 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3955 LN0->getChain(), 3956 LN0->getBasePtr(), LN0->getPointerInfo(), 3957 N0.getValueType(), 3958 LN0->isVolatile(), LN0->isNonTemporal(), 3959 LN0->getAlignment()); 3960 CombineTo(N, ExtLoad); 3961 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3962 N0.getValueType(), ExtLoad); 3963 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3964 3965 // Extend SetCC uses if necessary. 3966 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3967 SDNode *SetCC = SetCCs[i]; 3968 SmallVector<SDValue, 4> Ops; 3969 3970 for (unsigned j = 0; j != 2; ++j) { 3971 SDValue SOp = SetCC->getOperand(j); 3972 if (SOp == Trunc) 3973 Ops.push_back(ExtLoad); 3974 else 3975 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3976 N->getDebugLoc(), VT, SOp)); 3977 } 3978 3979 Ops.push_back(SetCC->getOperand(2)); 3980 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3981 SetCC->getValueType(0), 3982 &Ops[0], Ops.size())); 3983 } 3984 3985 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3986 } 3987 } 3988 3989 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3990 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3991 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3992 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3993 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3994 EVT MemVT = LN0->getMemoryVT(); 3995 if ((!LegalOperations && !LN0->isVolatile()) || 3996 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3997 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3998 LN0->getChain(), 3999 LN0->getBasePtr(), LN0->getPointerInfo(), 4000 MemVT, 4001 LN0->isVolatile(), LN0->isNonTemporal(), 4002 LN0->getAlignment()); 4003 CombineTo(N, ExtLoad); 4004 CombineTo(N0.getNode(), 4005 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4006 ExtLoad), 4007 ExtLoad.getValue(1)); 4008 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4009 } 4010 } 4011 4012 if (N0.getOpcode() == ISD::SETCC) { 4013 if (!LegalOperations && VT.isVector()) { 4014 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4015 // Only do this before legalize for now. 4016 EVT N0VT = N0.getOperand(0).getValueType(); 4017 EVT EltVT = VT.getVectorElementType(); 4018 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4019 DAG.getConstant(1, EltVT)); 4020 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4021 // We know that the # elements of the results is the same as the 4022 // # elements of the compare (and the # elements of the compare result 4023 // for that matter). Check to see that they are the same size. If so, 4024 // we know that the element size of the sext'd result matches the 4025 // element size of the compare operands. 4026 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4027 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4028 N0.getOperand(1), 4029 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4030 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4031 &OneOps[0], OneOps.size())); 4032 4033 // If the desired elements are smaller or larger than the source 4034 // elements we can use a matching integer vector type and then 4035 // truncate/sign extend 4036 EVT MatchingElementType = 4037 EVT::getIntegerVT(*DAG.getContext(), 4038 N0VT.getScalarType().getSizeInBits()); 4039 EVT MatchingVectorType = 4040 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4041 N0VT.getVectorNumElements()); 4042 SDValue VsetCC = 4043 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4044 N0.getOperand(1), 4045 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4046 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4047 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4048 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4049 &OneOps[0], OneOps.size())); 4050 } 4051 4052 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4053 SDValue SCC = 4054 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4055 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4056 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4057 if (SCC.getNode()) return SCC; 4058 } 4059 4060 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4061 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4062 isa<ConstantSDNode>(N0.getOperand(1)) && 4063 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4064 N0.hasOneUse()) { 4065 SDValue ShAmt = N0.getOperand(1); 4066 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4067 if (N0.getOpcode() == ISD::SHL) { 4068 SDValue InnerZExt = N0.getOperand(0); 4069 // If the original shl may be shifting out bits, do not perform this 4070 // transformation. 4071 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4072 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4073 if (ShAmtVal > KnownZeroBits) 4074 return SDValue(); 4075 } 4076 4077 DebugLoc DL = N->getDebugLoc(); 4078 4079 // Ensure that the shift amount is wide enough for the shifted value. 4080 if (VT.getSizeInBits() >= 256) 4081 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4082 4083 return DAG.getNode(N0.getOpcode(), DL, VT, 4084 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4085 ShAmt); 4086 } 4087 4088 return SDValue(); 4089} 4090 4091SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4092 SDValue N0 = N->getOperand(0); 4093 EVT VT = N->getValueType(0); 4094 4095 // fold (aext c1) -> c1 4096 if (isa<ConstantSDNode>(N0)) 4097 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4098 // fold (aext (aext x)) -> (aext x) 4099 // fold (aext (zext x)) -> (zext x) 4100 // fold (aext (sext x)) -> (sext x) 4101 if (N0.getOpcode() == ISD::ANY_EXTEND || 4102 N0.getOpcode() == ISD::ZERO_EXTEND || 4103 N0.getOpcode() == ISD::SIGN_EXTEND) 4104 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4105 4106 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4107 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4108 if (N0.getOpcode() == ISD::TRUNCATE) { 4109 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4110 if (NarrowLoad.getNode()) { 4111 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4112 if (NarrowLoad.getNode() != N0.getNode()) { 4113 CombineTo(N0.getNode(), NarrowLoad); 4114 // CombineTo deleted the truncate, if needed, but not what's under it. 4115 AddToWorkList(oye); 4116 } 4117 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4118 } 4119 } 4120 4121 // fold (aext (truncate x)) 4122 if (N0.getOpcode() == ISD::TRUNCATE) { 4123 SDValue TruncOp = N0.getOperand(0); 4124 if (TruncOp.getValueType() == VT) 4125 return TruncOp; // x iff x size == zext size. 4126 if (TruncOp.getValueType().bitsGT(VT)) 4127 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4128 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4129 } 4130 4131 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4132 // if the trunc is not free. 4133 if (N0.getOpcode() == ISD::AND && 4134 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4135 N0.getOperand(1).getOpcode() == ISD::Constant && 4136 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4137 N0.getValueType())) { 4138 SDValue X = N0.getOperand(0).getOperand(0); 4139 if (X.getValueType().bitsLT(VT)) { 4140 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4141 } else if (X.getValueType().bitsGT(VT)) { 4142 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4143 } 4144 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4145 Mask = Mask.zext(VT.getSizeInBits()); 4146 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4147 X, DAG.getConstant(Mask, VT)); 4148 } 4149 4150 // fold (aext (load x)) -> (aext (truncate (extload x))) 4151 // None of the supported targets knows how to perform load and any_ext 4152 // on vectors in one instruction. We only perform this transformation on 4153 // scalars. 4154 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4155 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4156 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4157 bool DoXform = true; 4158 SmallVector<SDNode*, 4> SetCCs; 4159 if (!N0.hasOneUse()) 4160 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4161 if (DoXform) { 4162 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4163 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4164 LN0->getChain(), 4165 LN0->getBasePtr(), LN0->getPointerInfo(), 4166 N0.getValueType(), 4167 LN0->isVolatile(), LN0->isNonTemporal(), 4168 LN0->getAlignment()); 4169 CombineTo(N, ExtLoad); 4170 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4171 N0.getValueType(), ExtLoad); 4172 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4173 4174 // Extend SetCC uses if necessary. 4175 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4176 SDNode *SetCC = SetCCs[i]; 4177 SmallVector<SDValue, 4> Ops; 4178 4179 for (unsigned j = 0; j != 2; ++j) { 4180 SDValue SOp = SetCC->getOperand(j); 4181 if (SOp == Trunc) 4182 Ops.push_back(ExtLoad); 4183 else 4184 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 4185 N->getDebugLoc(), VT, SOp)); 4186 } 4187 4188 Ops.push_back(SetCC->getOperand(2)); 4189 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 4190 SetCC->getValueType(0), 4191 &Ops[0], Ops.size())); 4192 } 4193 4194 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4195 } 4196 } 4197 4198 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4199 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4200 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4201 if (N0.getOpcode() == ISD::LOAD && 4202 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4203 N0.hasOneUse()) { 4204 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4205 EVT MemVT = LN0->getMemoryVT(); 4206 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4207 VT, LN0->getChain(), LN0->getBasePtr(), 4208 LN0->getPointerInfo(), MemVT, 4209 LN0->isVolatile(), LN0->isNonTemporal(), 4210 LN0->getAlignment()); 4211 CombineTo(N, ExtLoad); 4212 CombineTo(N0.getNode(), 4213 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4214 N0.getValueType(), ExtLoad), 4215 ExtLoad.getValue(1)); 4216 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4217 } 4218 4219 if (N0.getOpcode() == ISD::SETCC) { 4220 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4221 // Only do this before legalize for now. 4222 if (VT.isVector() && !LegalOperations) { 4223 EVT N0VT = N0.getOperand(0).getValueType(); 4224 // We know that the # elements of the results is the same as the 4225 // # elements of the compare (and the # elements of the compare result 4226 // for that matter). Check to see that they are the same size. If so, 4227 // we know that the element size of the sext'd result matches the 4228 // element size of the compare operands. 4229 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4230 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4231 N0.getOperand(1), 4232 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4233 // If the desired elements are smaller or larger than the source 4234 // elements we can use a matching integer vector type and then 4235 // truncate/sign extend 4236 else { 4237 EVT MatchingElementType = 4238 EVT::getIntegerVT(*DAG.getContext(), 4239 N0VT.getScalarType().getSizeInBits()); 4240 EVT MatchingVectorType = 4241 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4242 N0VT.getVectorNumElements()); 4243 SDValue VsetCC = 4244 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4245 N0.getOperand(1), 4246 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4247 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4248 } 4249 } 4250 4251 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4252 SDValue SCC = 4253 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4254 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4255 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4256 if (SCC.getNode()) 4257 return SCC; 4258 } 4259 4260 return SDValue(); 4261} 4262 4263/// GetDemandedBits - See if the specified operand can be simplified with the 4264/// knowledge that only the bits specified by Mask are used. If so, return the 4265/// simpler operand, otherwise return a null SDValue. 4266SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4267 switch (V.getOpcode()) { 4268 default: break; 4269 case ISD::OR: 4270 case ISD::XOR: 4271 // If the LHS or RHS don't contribute bits to the or, drop them. 4272 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4273 return V.getOperand(1); 4274 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4275 return V.getOperand(0); 4276 break; 4277 case ISD::SRL: 4278 // Only look at single-use SRLs. 4279 if (!V.getNode()->hasOneUse()) 4280 break; 4281 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4282 // See if we can recursively simplify the LHS. 4283 unsigned Amt = RHSC->getZExtValue(); 4284 4285 // Watch out for shift count overflow though. 4286 if (Amt >= Mask.getBitWidth()) break; 4287 APInt NewMask = Mask << Amt; 4288 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4289 if (SimplifyLHS.getNode()) 4290 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4291 SimplifyLHS, V.getOperand(1)); 4292 } 4293 } 4294 return SDValue(); 4295} 4296 4297/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4298/// bits and then truncated to a narrower type and where N is a multiple 4299/// of number of bits of the narrower type, transform it to a narrower load 4300/// from address + N / num of bits of new type. If the result is to be 4301/// extended, also fold the extension to form a extending load. 4302SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4303 unsigned Opc = N->getOpcode(); 4304 4305 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4306 SDValue N0 = N->getOperand(0); 4307 EVT VT = N->getValueType(0); 4308 EVT ExtVT = VT; 4309 4310 // This transformation isn't valid for vector loads. 4311 if (VT.isVector()) 4312 return SDValue(); 4313 4314 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4315 // extended to VT. 4316 if (Opc == ISD::SIGN_EXTEND_INREG) { 4317 ExtType = ISD::SEXTLOAD; 4318 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4319 } else if (Opc == ISD::SRL) { 4320 // Another special-case: SRL is basically zero-extending a narrower value. 4321 ExtType = ISD::ZEXTLOAD; 4322 N0 = SDValue(N, 0); 4323 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4324 if (!N01) return SDValue(); 4325 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4326 VT.getSizeInBits() - N01->getZExtValue()); 4327 } 4328 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 4329 return SDValue(); 4330 4331 unsigned EVTBits = ExtVT.getSizeInBits(); 4332 4333 // Do not generate loads of non-round integer types since these can 4334 // be expensive (and would be wrong if the type is not byte sized). 4335 if (!ExtVT.isRound()) 4336 return SDValue(); 4337 4338 unsigned ShAmt = 0; 4339 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 4340 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4341 ShAmt = N01->getZExtValue(); 4342 // Is the shift amount a multiple of size of VT? 4343 if ((ShAmt & (EVTBits-1)) == 0) { 4344 N0 = N0.getOperand(0); 4345 // Is the load width a multiple of size of VT? 4346 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4347 return SDValue(); 4348 } 4349 4350 // At this point, we must have a load or else we can't do the transform. 4351 if (!isa<LoadSDNode>(N0)) return SDValue(); 4352 4353 // If the shift amount is larger than the input type then we're not 4354 // accessing any of the loaded bytes. If the load was a zextload/extload 4355 // then the result of the shift+trunc is zero/undef (handled elsewhere). 4356 // If the load was a sextload then the result is a splat of the sign bit 4357 // of the extended byte. This is not worth optimizing for. 4358 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 4359 return SDValue(); 4360 } 4361 } 4362 4363 // If the load is shifted left (and the result isn't shifted back right), 4364 // we can fold the truncate through the shift. 4365 unsigned ShLeftAmt = 0; 4366 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 4367 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 4368 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4369 ShLeftAmt = N01->getZExtValue(); 4370 N0 = N0.getOperand(0); 4371 } 4372 } 4373 4374 // If we haven't found a load, we can't narrow it. Don't transform one with 4375 // multiple uses, this would require adding a new load. 4376 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 4377 // Don't change the width of a volatile load. 4378 cast<LoadSDNode>(N0)->isVolatile()) 4379 return SDValue(); 4380 4381 // Verify that we are actually reducing a load width here. 4382 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 4383 return SDValue(); 4384 4385 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4386 EVT PtrType = N0.getOperand(1).getValueType(); 4387 4388 // For big endian targets, we need to adjust the offset to the pointer to 4389 // load the correct bytes. 4390 if (TLI.isBigEndian()) { 4391 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4392 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4393 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4394 } 4395 4396 uint64_t PtrOff = ShAmt / 8; 4397 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4398 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4399 PtrType, LN0->getBasePtr(), 4400 DAG.getConstant(PtrOff, PtrType)); 4401 AddToWorkList(NewPtr.getNode()); 4402 4403 SDValue Load; 4404 if (ExtType == ISD::NON_EXTLOAD) 4405 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4406 LN0->getPointerInfo().getWithOffset(PtrOff), 4407 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign); 4408 else 4409 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 4410 LN0->getPointerInfo().getWithOffset(PtrOff), 4411 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4412 NewAlign); 4413 4414 // Replace the old load's chain with the new load's chain. 4415 WorkListRemover DeadNodes(*this); 4416 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 4417 &DeadNodes); 4418 4419 // Shift the result left, if we've swallowed a left shift. 4420 SDValue Result = Load; 4421 if (ShLeftAmt != 0) { 4422 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 4423 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 4424 ShImmTy = VT; 4425 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 4426 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 4427 } 4428 4429 // Return the new loaded value. 4430 return Result; 4431} 4432 4433SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 4434 SDValue N0 = N->getOperand(0); 4435 SDValue N1 = N->getOperand(1); 4436 EVT VT = N->getValueType(0); 4437 EVT EVT = cast<VTSDNode>(N1)->getVT(); 4438 unsigned VTBits = VT.getScalarType().getSizeInBits(); 4439 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 4440 4441 // fold (sext_in_reg c1) -> c1 4442 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 4443 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 4444 4445 // If the input is already sign extended, just drop the extension. 4446 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 4447 return N0; 4448 4449 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 4450 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 4451 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 4452 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4453 N0.getOperand(0), N1); 4454 } 4455 4456 // fold (sext_in_reg (sext x)) -> (sext x) 4457 // fold (sext_in_reg (aext x)) -> (sext x) 4458 // if x is small enough. 4459 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 4460 SDValue N00 = N0.getOperand(0); 4461 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 4462 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 4463 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 4464 } 4465 4466 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 4467 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 4468 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 4469 4470 // fold operands of sext_in_reg based on knowledge that the top bits are not 4471 // demanded. 4472 if (SimplifyDemandedBits(SDValue(N, 0))) 4473 return SDValue(N, 0); 4474 4475 // fold (sext_in_reg (load x)) -> (smaller sextload x) 4476 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 4477 SDValue NarrowLoad = ReduceLoadWidth(N); 4478 if (NarrowLoad.getNode()) 4479 return NarrowLoad; 4480 4481 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 4482 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 4483 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 4484 if (N0.getOpcode() == ISD::SRL) { 4485 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 4486 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 4487 // We can turn this into an SRA iff the input to the SRL is already sign 4488 // extended enough. 4489 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 4490 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 4491 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 4492 N0.getOperand(0), N0.getOperand(1)); 4493 } 4494 } 4495 4496 // fold (sext_inreg (extload x)) -> (sextload x) 4497 if (ISD::isEXTLoad(N0.getNode()) && 4498 ISD::isUNINDEXEDLoad(N0.getNode()) && 4499 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4500 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4501 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4502 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4503 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4504 LN0->getChain(), 4505 LN0->getBasePtr(), LN0->getPointerInfo(), 4506 EVT, 4507 LN0->isVolatile(), LN0->isNonTemporal(), 4508 LN0->getAlignment()); 4509 CombineTo(N, ExtLoad); 4510 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4511 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4512 } 4513 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 4514 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4515 N0.hasOneUse() && 4516 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4517 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4518 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4519 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4520 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4521 LN0->getChain(), 4522 LN0->getBasePtr(), LN0->getPointerInfo(), 4523 EVT, 4524 LN0->isVolatile(), LN0->isNonTemporal(), 4525 LN0->getAlignment()); 4526 CombineTo(N, ExtLoad); 4527 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4528 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4529 } 4530 return SDValue(); 4531} 4532 4533SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 4534 SDValue N0 = N->getOperand(0); 4535 EVT VT = N->getValueType(0); 4536 4537 // noop truncate 4538 if (N0.getValueType() == N->getValueType(0)) 4539 return N0; 4540 // fold (truncate c1) -> c1 4541 if (isa<ConstantSDNode>(N0)) 4542 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 4543 // fold (truncate (truncate x)) -> (truncate x) 4544 if (N0.getOpcode() == ISD::TRUNCATE) 4545 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4546 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 4547 if (N0.getOpcode() == ISD::ZERO_EXTEND || 4548 N0.getOpcode() == ISD::SIGN_EXTEND || 4549 N0.getOpcode() == ISD::ANY_EXTEND) { 4550 if (N0.getOperand(0).getValueType().bitsLT(VT)) 4551 // if the source is smaller than the dest, we still need an extend 4552 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4553 N0.getOperand(0)); 4554 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 4555 // if the source is larger than the dest, than we just need the truncate 4556 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4557 else 4558 // if the source and dest are the same type, we can drop both the extend 4559 // and the truncate. 4560 return N0.getOperand(0); 4561 } 4562 4563 // See if we can simplify the input to this truncate through knowledge that 4564 // only the low bits are being used. 4565 // For example "trunc (or (shl x, 8), y)" // -> trunc y 4566 // Currently we only perform this optimization on scalars because vectors 4567 // may have different active low bits. 4568 if (!VT.isVector()) { 4569 SDValue Shorter = 4570 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 4571 VT.getSizeInBits())); 4572 if (Shorter.getNode()) 4573 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 4574 } 4575 // fold (truncate (load x)) -> (smaller load x) 4576 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 4577 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 4578 SDValue Reduced = ReduceLoadWidth(N); 4579 if (Reduced.getNode()) 4580 return Reduced; 4581 } 4582 4583 // Simplify the operands using demanded-bits information. 4584 if (!VT.isVector() && 4585 SimplifyDemandedBits(SDValue(N, 0))) 4586 return SDValue(N, 0); 4587 4588 return SDValue(); 4589} 4590 4591static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 4592 SDValue Elt = N->getOperand(i); 4593 if (Elt.getOpcode() != ISD::MERGE_VALUES) 4594 return Elt.getNode(); 4595 return Elt.getOperand(Elt.getResNo()).getNode(); 4596} 4597 4598/// CombineConsecutiveLoads - build_pair (load, load) -> load 4599/// if load locations are consecutive. 4600SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 4601 assert(N->getOpcode() == ISD::BUILD_PAIR); 4602 4603 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 4604 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 4605 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 4606 LD1->getPointerInfo().getAddrSpace() != 4607 LD2->getPointerInfo().getAddrSpace()) 4608 return SDValue(); 4609 EVT LD1VT = LD1->getValueType(0); 4610 4611 if (ISD::isNON_EXTLoad(LD2) && 4612 LD2->hasOneUse() && 4613 // If both are volatile this would reduce the number of volatile loads. 4614 // If one is volatile it might be ok, but play conservative and bail out. 4615 !LD1->isVolatile() && 4616 !LD2->isVolatile() && 4617 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 4618 unsigned Align = LD1->getAlignment(); 4619 unsigned NewAlign = TLI.getTargetData()-> 4620 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4621 4622 if (NewAlign <= Align && 4623 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 4624 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 4625 LD1->getBasePtr(), LD1->getPointerInfo(), 4626 false, false, Align); 4627 } 4628 4629 return SDValue(); 4630} 4631 4632SDValue DAGCombiner::visitBITCAST(SDNode *N) { 4633 SDValue N0 = N->getOperand(0); 4634 EVT VT = N->getValueType(0); 4635 4636 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 4637 // Only do this before legalize, since afterward the target may be depending 4638 // on the bitconvert. 4639 // First check to see if this is all constant. 4640 if (!LegalTypes && 4641 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 4642 VT.isVector()) { 4643 bool isSimple = true; 4644 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 4645 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 4646 N0.getOperand(i).getOpcode() != ISD::Constant && 4647 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 4648 isSimple = false; 4649 break; 4650 } 4651 4652 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 4653 assert(!DestEltVT.isVector() && 4654 "Element type of vector ValueType must not be vector!"); 4655 if (isSimple) 4656 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 4657 } 4658 4659 // If the input is a constant, let getNode fold it. 4660 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 4661 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 4662 if (Res.getNode() != N) { 4663 if (!LegalOperations || 4664 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 4665 return Res; 4666 4667 // Folding it resulted in an illegal node, and it's too late to 4668 // do that. Clean up the old node and forego the transformation. 4669 // Ideally this won't happen very often, because instcombine 4670 // and the earlier dagcombine runs (where illegal nodes are 4671 // permitted) should have folded most of them already. 4672 DAG.DeleteNode(Res.getNode()); 4673 } 4674 } 4675 4676 // (conv (conv x, t1), t2) -> (conv x, t2) 4677 if (N0.getOpcode() == ISD::BITCAST) 4678 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 4679 N0.getOperand(0)); 4680 4681 // fold (conv (load x)) -> (load (conv*)x) 4682 // If the resultant load doesn't need a higher alignment than the original! 4683 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 4684 // Do not change the width of a volatile load. 4685 !cast<LoadSDNode>(N0)->isVolatile() && 4686 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 4687 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4688 unsigned Align = TLI.getTargetData()-> 4689 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4690 unsigned OrigAlign = LN0->getAlignment(); 4691 4692 if (Align <= OrigAlign) { 4693 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 4694 LN0->getBasePtr(), LN0->getPointerInfo(), 4695 LN0->isVolatile(), LN0->isNonTemporal(), 4696 OrigAlign); 4697 AddToWorkList(N); 4698 CombineTo(N0.getNode(), 4699 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4700 N0.getValueType(), Load), 4701 Load.getValue(1)); 4702 return Load; 4703 } 4704 } 4705 4706 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 4707 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 4708 // This often reduces constant pool loads. 4709 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 4710 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 4711 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 4712 N0.getOperand(0)); 4713 AddToWorkList(NewConv.getNode()); 4714 4715 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4716 if (N0.getOpcode() == ISD::FNEG) 4717 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 4718 NewConv, DAG.getConstant(SignBit, VT)); 4719 assert(N0.getOpcode() == ISD::FABS); 4720 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4721 NewConv, DAG.getConstant(~SignBit, VT)); 4722 } 4723 4724 // fold (bitconvert (fcopysign cst, x)) -> 4725 // (or (and (bitconvert x), sign), (and cst, (not sign))) 4726 // Note that we don't handle (copysign x, cst) because this can always be 4727 // folded to an fneg or fabs. 4728 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 4729 isa<ConstantFPSDNode>(N0.getOperand(0)) && 4730 VT.isInteger() && !VT.isVector()) { 4731 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 4732 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 4733 if (isTypeLegal(IntXVT)) { 4734 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4735 IntXVT, N0.getOperand(1)); 4736 AddToWorkList(X.getNode()); 4737 4738 // If X has a different width than the result/lhs, sext it or truncate it. 4739 unsigned VTWidth = VT.getSizeInBits(); 4740 if (OrigXWidth < VTWidth) { 4741 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 4742 AddToWorkList(X.getNode()); 4743 } else if (OrigXWidth > VTWidth) { 4744 // To get the sign bit in the right place, we have to shift it right 4745 // before truncating. 4746 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 4747 X.getValueType(), X, 4748 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 4749 AddToWorkList(X.getNode()); 4750 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4751 AddToWorkList(X.getNode()); 4752 } 4753 4754 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4755 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 4756 X, DAG.getConstant(SignBit, VT)); 4757 AddToWorkList(X.getNode()); 4758 4759 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4760 VT, N0.getOperand(0)); 4761 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 4762 Cst, DAG.getConstant(~SignBit, VT)); 4763 AddToWorkList(Cst.getNode()); 4764 4765 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 4766 } 4767 } 4768 4769 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 4770 if (N0.getOpcode() == ISD::BUILD_PAIR) { 4771 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 4772 if (CombineLD.getNode()) 4773 return CombineLD; 4774 } 4775 4776 return SDValue(); 4777} 4778 4779SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 4780 EVT VT = N->getValueType(0); 4781 return CombineConsecutiveLoads(N, VT); 4782} 4783 4784/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 4785/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 4786/// destination element value type. 4787SDValue DAGCombiner:: 4788ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 4789 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 4790 4791 // If this is already the right type, we're done. 4792 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 4793 4794 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 4795 unsigned DstBitSize = DstEltVT.getSizeInBits(); 4796 4797 // If this is a conversion of N elements of one type to N elements of another 4798 // type, convert each element. This handles FP<->INT cases. 4799 if (SrcBitSize == DstBitSize) { 4800 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4801 BV->getValueType(0).getVectorNumElements()); 4802 4803 // Due to the FP element handling below calling this routine recursively, 4804 // we can end up with a scalar-to-vector node here. 4805 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 4806 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4807 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 4808 DstEltVT, BV->getOperand(0))); 4809 4810 SmallVector<SDValue, 8> Ops; 4811 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4812 SDValue Op = BV->getOperand(i); 4813 // If the vector element type is not legal, the BUILD_VECTOR operands 4814 // are promoted and implicitly truncated. Make that explicit here. 4815 if (Op.getValueType() != SrcEltVT) 4816 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 4817 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 4818 DstEltVT, Op)); 4819 AddToWorkList(Ops.back().getNode()); 4820 } 4821 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4822 &Ops[0], Ops.size()); 4823 } 4824 4825 // Otherwise, we're growing or shrinking the elements. To avoid having to 4826 // handle annoying details of growing/shrinking FP values, we convert them to 4827 // int first. 4828 if (SrcEltVT.isFloatingPoint()) { 4829 // Convert the input float vector to a int vector where the elements are the 4830 // same sizes. 4831 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 4832 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 4833 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 4834 SrcEltVT = IntVT; 4835 } 4836 4837 // Now we know the input is an integer vector. If the output is a FP type, 4838 // convert to integer first, then to FP of the right size. 4839 if (DstEltVT.isFloatingPoint()) { 4840 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4841 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4842 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 4843 4844 // Next, convert to FP elements of the same size. 4845 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 4846 } 4847 4848 // Okay, we know the src/dst types are both integers of differing types. 4849 // Handling growing first. 4850 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4851 if (SrcBitSize < DstBitSize) { 4852 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4853 4854 SmallVector<SDValue, 8> Ops; 4855 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4856 i += NumInputsPerOutput) { 4857 bool isLE = TLI.isLittleEndian(); 4858 APInt NewBits = APInt(DstBitSize, 0); 4859 bool EltIsUndef = true; 4860 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4861 // Shift the previously computed bits over. 4862 NewBits <<= SrcBitSize; 4863 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4864 if (Op.getOpcode() == ISD::UNDEF) continue; 4865 EltIsUndef = false; 4866 4867 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 4868 zextOrTrunc(SrcBitSize).zext(DstBitSize); 4869 } 4870 4871 if (EltIsUndef) 4872 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4873 else 4874 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4875 } 4876 4877 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4878 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4879 &Ops[0], Ops.size()); 4880 } 4881 4882 // Finally, this must be the case where we are shrinking elements: each input 4883 // turns into multiple outputs. 4884 bool isS2V = ISD::isScalarToVector(BV); 4885 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4886 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4887 NumOutputsPerInput*BV->getNumOperands()); 4888 SmallVector<SDValue, 8> Ops; 4889 4890 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4891 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4892 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4893 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4894 continue; 4895 } 4896 4897 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 4898 getAPIntValue().zextOrTrunc(SrcBitSize); 4899 4900 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4901 APInt ThisVal = OpVal.trunc(DstBitSize); 4902 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4903 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 4904 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4905 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4906 Ops[0]); 4907 OpVal = OpVal.lshr(DstBitSize); 4908 } 4909 4910 // For big endian targets, swap the order of the pieces of each element. 4911 if (TLI.isBigEndian()) 4912 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4913 } 4914 4915 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4916 &Ops[0], Ops.size()); 4917} 4918 4919SDValue DAGCombiner::visitFADD(SDNode *N) { 4920 SDValue N0 = N->getOperand(0); 4921 SDValue N1 = N->getOperand(1); 4922 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4923 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4924 EVT VT = N->getValueType(0); 4925 4926 // fold vector ops 4927 if (VT.isVector()) { 4928 SDValue FoldedVOp = SimplifyVBinOp(N); 4929 if (FoldedVOp.getNode()) return FoldedVOp; 4930 } 4931 4932 // fold (fadd c1, c2) -> (fadd c1, c2) 4933 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4934 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4935 // canonicalize constant to RHS 4936 if (N0CFP && !N1CFP) 4937 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4938 // fold (fadd A, 0) -> A 4939 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4940 return N0; 4941 // fold (fadd A, (fneg B)) -> (fsub A, B) 4942 if (isNegatibleForFree(N1, LegalOperations) == 2) 4943 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4944 GetNegatedExpression(N1, DAG, LegalOperations)); 4945 // fold (fadd (fneg A), B) -> (fsub B, A) 4946 if (isNegatibleForFree(N0, LegalOperations) == 2) 4947 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4948 GetNegatedExpression(N0, DAG, LegalOperations)); 4949 4950 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4951 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4952 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4953 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4954 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4955 N0.getOperand(1), N1)); 4956 4957 return SDValue(); 4958} 4959 4960SDValue DAGCombiner::visitFSUB(SDNode *N) { 4961 SDValue N0 = N->getOperand(0); 4962 SDValue N1 = N->getOperand(1); 4963 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4964 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4965 EVT VT = N->getValueType(0); 4966 4967 // fold vector ops 4968 if (VT.isVector()) { 4969 SDValue FoldedVOp = SimplifyVBinOp(N); 4970 if (FoldedVOp.getNode()) return FoldedVOp; 4971 } 4972 4973 // fold (fsub c1, c2) -> c1-c2 4974 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4975 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4976 // fold (fsub A, 0) -> A 4977 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4978 return N0; 4979 // fold (fsub 0, B) -> -B 4980 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4981 if (isNegatibleForFree(N1, LegalOperations)) 4982 return GetNegatedExpression(N1, DAG, LegalOperations); 4983 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4984 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4985 } 4986 // fold (fsub A, (fneg B)) -> (fadd A, B) 4987 if (isNegatibleForFree(N1, LegalOperations)) 4988 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4989 GetNegatedExpression(N1, DAG, LegalOperations)); 4990 4991 return SDValue(); 4992} 4993 4994SDValue DAGCombiner::visitFMUL(SDNode *N) { 4995 SDValue N0 = N->getOperand(0); 4996 SDValue N1 = N->getOperand(1); 4997 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4998 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4999 EVT VT = N->getValueType(0); 5000 5001 // fold vector ops 5002 if (VT.isVector()) { 5003 SDValue FoldedVOp = SimplifyVBinOp(N); 5004 if (FoldedVOp.getNode()) return FoldedVOp; 5005 } 5006 5007 // fold (fmul c1, c2) -> c1*c2 5008 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5009 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 5010 // canonicalize constant to RHS 5011 if (N0CFP && !N1CFP) 5012 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 5013 // fold (fmul A, 0) -> 0 5014 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 5015 return N1; 5016 // fold (fmul A, 0) -> 0, vector edition. 5017 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 5018 return N1; 5019 // fold (fmul X, 2.0) -> (fadd X, X) 5020 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 5021 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 5022 // fold (fmul X, -1.0) -> (fneg X) 5023 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 5024 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5025 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 5026 5027 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 5028 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 5029 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 5030 // Both can be negated for free, check to see if at least one is cheaper 5031 // negated. 5032 if (LHSNeg == 2 || RHSNeg == 2) 5033 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5034 GetNegatedExpression(N0, DAG, LegalOperations), 5035 GetNegatedExpression(N1, DAG, LegalOperations)); 5036 } 5037 } 5038 5039 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 5040 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 5041 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5042 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 5043 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5044 N0.getOperand(1), N1)); 5045 5046 return SDValue(); 5047} 5048 5049SDValue DAGCombiner::visitFDIV(SDNode *N) { 5050 SDValue N0 = N->getOperand(0); 5051 SDValue N1 = N->getOperand(1); 5052 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5053 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5054 EVT VT = N->getValueType(0); 5055 5056 // fold vector ops 5057 if (VT.isVector()) { 5058 SDValue FoldedVOp = SimplifyVBinOp(N); 5059 if (FoldedVOp.getNode()) return FoldedVOp; 5060 } 5061 5062 // fold (fdiv c1, c2) -> c1/c2 5063 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5064 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 5065 5066 5067 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 5068 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 5069 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 5070 // Both can be negated for free, check to see if at least one is cheaper 5071 // negated. 5072 if (LHSNeg == 2 || RHSNeg == 2) 5073 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 5074 GetNegatedExpression(N0, DAG, LegalOperations), 5075 GetNegatedExpression(N1, DAG, LegalOperations)); 5076 } 5077 } 5078 5079 return SDValue(); 5080} 5081 5082SDValue DAGCombiner::visitFREM(SDNode *N) { 5083 SDValue N0 = N->getOperand(0); 5084 SDValue N1 = N->getOperand(1); 5085 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5086 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5087 EVT VT = N->getValueType(0); 5088 5089 // fold (frem c1, c2) -> fmod(c1,c2) 5090 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5091 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 5092 5093 return SDValue(); 5094} 5095 5096SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 5097 SDValue N0 = N->getOperand(0); 5098 SDValue N1 = N->getOperand(1); 5099 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5100 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5101 EVT VT = N->getValueType(0); 5102 5103 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 5104 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 5105 5106 if (N1CFP) { 5107 const APFloat& V = N1CFP->getValueAPF(); 5108 // copysign(x, c1) -> fabs(x) iff ispos(c1) 5109 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 5110 if (!V.isNegative()) { 5111 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 5112 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5113 } else { 5114 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5115 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 5116 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 5117 } 5118 } 5119 5120 // copysign(fabs(x), y) -> copysign(x, y) 5121 // copysign(fneg(x), y) -> copysign(x, y) 5122 // copysign(copysign(x,z), y) -> copysign(x, y) 5123 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 5124 N0.getOpcode() == ISD::FCOPYSIGN) 5125 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5126 N0.getOperand(0), N1); 5127 5128 // copysign(x, abs(y)) -> abs(x) 5129 if (N1.getOpcode() == ISD::FABS) 5130 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5131 5132 // copysign(x, copysign(y,z)) -> copysign(x, z) 5133 if (N1.getOpcode() == ISD::FCOPYSIGN) 5134 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5135 N0, N1.getOperand(1)); 5136 5137 // copysign(x, fp_extend(y)) -> copysign(x, y) 5138 // copysign(x, fp_round(y)) -> copysign(x, y) 5139 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 5140 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5141 N0, N1.getOperand(0)); 5142 5143 return SDValue(); 5144} 5145 5146SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 5147 SDValue N0 = N->getOperand(0); 5148 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5149 EVT VT = N->getValueType(0); 5150 EVT OpVT = N0.getValueType(); 5151 5152 // fold (sint_to_fp c1) -> c1fp 5153 if (N0C && OpVT != MVT::ppcf128 && 5154 // ...but only if the target supports immediate floating-point values 5155 (Level == llvm::Unrestricted || TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5156 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5157 5158 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 5159 // but UINT_TO_FP is legal on this target, try to convert. 5160 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 5161 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 5162 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 5163 if (DAG.SignBitIsZero(N0)) 5164 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5165 } 5166 5167 return SDValue(); 5168} 5169 5170SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 5171 SDValue N0 = N->getOperand(0); 5172 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5173 EVT VT = N->getValueType(0); 5174 EVT OpVT = N0.getValueType(); 5175 5176 // fold (uint_to_fp c1) -> c1fp 5177 if (N0C && OpVT != MVT::ppcf128 && 5178 // ...but only if the target supports immediate floating-point values 5179 (Level == llvm::Unrestricted || TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5180 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5181 5182 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 5183 // but SINT_TO_FP is legal on this target, try to convert. 5184 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 5185 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 5186 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 5187 if (DAG.SignBitIsZero(N0)) 5188 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5189 } 5190 5191 return SDValue(); 5192} 5193 5194SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 5195 SDValue N0 = N->getOperand(0); 5196 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5197 EVT VT = N->getValueType(0); 5198 5199 // fold (fp_to_sint c1fp) -> c1 5200 if (N0CFP) 5201 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 5202 5203 return SDValue(); 5204} 5205 5206SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 5207 SDValue N0 = N->getOperand(0); 5208 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5209 EVT VT = N->getValueType(0); 5210 5211 // fold (fp_to_uint c1fp) -> c1 5212 if (N0CFP && VT != MVT::ppcf128) 5213 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 5214 5215 return SDValue(); 5216} 5217 5218SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 5219 SDValue N0 = N->getOperand(0); 5220 SDValue N1 = N->getOperand(1); 5221 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5222 EVT VT = N->getValueType(0); 5223 5224 // fold (fp_round c1fp) -> c1fp 5225 if (N0CFP && N0.getValueType() != MVT::ppcf128) 5226 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 5227 5228 // fold (fp_round (fp_extend x)) -> x 5229 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 5230 return N0.getOperand(0); 5231 5232 // fold (fp_round (fp_round x)) -> (fp_round x) 5233 if (N0.getOpcode() == ISD::FP_ROUND) { 5234 // This is a value preserving truncation if both round's are. 5235 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 5236 N0.getNode()->getConstantOperandVal(1) == 1; 5237 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 5238 DAG.getIntPtrConstant(IsTrunc)); 5239 } 5240 5241 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 5242 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 5243 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 5244 N0.getOperand(0), N1); 5245 AddToWorkList(Tmp.getNode()); 5246 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5247 Tmp, N0.getOperand(1)); 5248 } 5249 5250 return SDValue(); 5251} 5252 5253SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 5254 SDValue N0 = N->getOperand(0); 5255 EVT VT = N->getValueType(0); 5256 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5257 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5258 5259 // fold (fp_round_inreg c1fp) -> c1fp 5260 if (N0CFP && isTypeLegal(EVT)) { 5261 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 5262 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 5263 } 5264 5265 return SDValue(); 5266} 5267 5268SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 5269 SDValue N0 = N->getOperand(0); 5270 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5271 EVT VT = N->getValueType(0); 5272 5273 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 5274 if (N->hasOneUse() && 5275 N->use_begin()->getOpcode() == ISD::FP_ROUND) 5276 return SDValue(); 5277 5278 // fold (fp_extend c1fp) -> c1fp 5279 if (N0CFP && VT != MVT::ppcf128) 5280 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 5281 5282 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 5283 // value of X. 5284 if (N0.getOpcode() == ISD::FP_ROUND 5285 && N0.getNode()->getConstantOperandVal(1) == 1) { 5286 SDValue In = N0.getOperand(0); 5287 if (In.getValueType() == VT) return In; 5288 if (VT.bitsLT(In.getValueType())) 5289 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 5290 In, N0.getOperand(1)); 5291 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 5292 } 5293 5294 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 5295 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 5296 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5297 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 5298 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5299 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 5300 LN0->getChain(), 5301 LN0->getBasePtr(), LN0->getPointerInfo(), 5302 N0.getValueType(), 5303 LN0->isVolatile(), LN0->isNonTemporal(), 5304 LN0->getAlignment()); 5305 CombineTo(N, ExtLoad); 5306 CombineTo(N0.getNode(), 5307 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 5308 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 5309 ExtLoad.getValue(1)); 5310 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5311 } 5312 5313 return SDValue(); 5314} 5315 5316SDValue DAGCombiner::visitFNEG(SDNode *N) { 5317 SDValue N0 = N->getOperand(0); 5318 EVT VT = N->getValueType(0); 5319 5320 if (isNegatibleForFree(N0, LegalOperations)) 5321 return GetNegatedExpression(N0, DAG, LegalOperations); 5322 5323 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 5324 // constant pool values. 5325 if (N0.getOpcode() == ISD::BITCAST && 5326 !VT.isVector() && 5327 N0.getNode()->hasOneUse() && 5328 N0.getOperand(0).getValueType().isInteger()) { 5329 SDValue Int = N0.getOperand(0); 5330 EVT IntVT = Int.getValueType(); 5331 if (IntVT.isInteger() && !IntVT.isVector()) { 5332 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 5333 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5334 AddToWorkList(Int.getNode()); 5335 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5336 VT, Int); 5337 } 5338 } 5339 5340 return SDValue(); 5341} 5342 5343SDValue DAGCombiner::visitFABS(SDNode *N) { 5344 SDValue N0 = N->getOperand(0); 5345 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5346 EVT VT = N->getValueType(0); 5347 5348 // fold (fabs c1) -> fabs(c1) 5349 if (N0CFP && VT != MVT::ppcf128) 5350 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5351 // fold (fabs (fabs x)) -> (fabs x) 5352 if (N0.getOpcode() == ISD::FABS) 5353 return N->getOperand(0); 5354 // fold (fabs (fneg x)) -> (fabs x) 5355 // fold (fabs (fcopysign x, y)) -> (fabs x) 5356 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 5357 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 5358 5359 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 5360 // constant pool values. 5361 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 5362 N0.getOperand(0).getValueType().isInteger() && 5363 !N0.getOperand(0).getValueType().isVector()) { 5364 SDValue Int = N0.getOperand(0); 5365 EVT IntVT = Int.getValueType(); 5366 if (IntVT.isInteger() && !IntVT.isVector()) { 5367 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 5368 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5369 AddToWorkList(Int.getNode()); 5370 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5371 N->getValueType(0), Int); 5372 } 5373 } 5374 5375 return SDValue(); 5376} 5377 5378SDValue DAGCombiner::visitBRCOND(SDNode *N) { 5379 SDValue Chain = N->getOperand(0); 5380 SDValue N1 = N->getOperand(1); 5381 SDValue N2 = N->getOperand(2); 5382 5383 // If N is a constant we could fold this into a fallthrough or unconditional 5384 // branch. However that doesn't happen very often in normal code, because 5385 // Instcombine/SimplifyCFG should have handled the available opportunities. 5386 // If we did this folding here, it would be necessary to update the 5387 // MachineBasicBlock CFG, which is awkward. 5388 5389 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 5390 // on the target. 5391 if (N1.getOpcode() == ISD::SETCC && 5392 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 5393 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5394 Chain, N1.getOperand(2), 5395 N1.getOperand(0), N1.getOperand(1), N2); 5396 } 5397 5398 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 5399 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 5400 (N1.getOperand(0).hasOneUse() && 5401 N1.getOperand(0).getOpcode() == ISD::SRL))) { 5402 SDNode *Trunc = 0; 5403 if (N1.getOpcode() == ISD::TRUNCATE) { 5404 // Look pass the truncate. 5405 Trunc = N1.getNode(); 5406 N1 = N1.getOperand(0); 5407 } 5408 5409 // Match this pattern so that we can generate simpler code: 5410 // 5411 // %a = ... 5412 // %b = and i32 %a, 2 5413 // %c = srl i32 %b, 1 5414 // brcond i32 %c ... 5415 // 5416 // into 5417 // 5418 // %a = ... 5419 // %b = and i32 %a, 2 5420 // %c = setcc eq %b, 0 5421 // brcond %c ... 5422 // 5423 // This applies only when the AND constant value has one bit set and the 5424 // SRL constant is equal to the log2 of the AND constant. The back-end is 5425 // smart enough to convert the result into a TEST/JMP sequence. 5426 SDValue Op0 = N1.getOperand(0); 5427 SDValue Op1 = N1.getOperand(1); 5428 5429 if (Op0.getOpcode() == ISD::AND && 5430 Op1.getOpcode() == ISD::Constant) { 5431 SDValue AndOp1 = Op0.getOperand(1); 5432 5433 if (AndOp1.getOpcode() == ISD::Constant) { 5434 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 5435 5436 if (AndConst.isPowerOf2() && 5437 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 5438 SDValue SetCC = 5439 DAG.getSetCC(N->getDebugLoc(), 5440 TLI.getSetCCResultType(Op0.getValueType()), 5441 Op0, DAG.getConstant(0, Op0.getValueType()), 5442 ISD::SETNE); 5443 5444 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5445 MVT::Other, Chain, SetCC, N2); 5446 // Don't add the new BRCond into the worklist or else SimplifySelectCC 5447 // will convert it back to (X & C1) >> C2. 5448 CombineTo(N, NewBRCond, false); 5449 // Truncate is dead. 5450 if (Trunc) { 5451 removeFromWorkList(Trunc); 5452 DAG.DeleteNode(Trunc); 5453 } 5454 // Replace the uses of SRL with SETCC 5455 WorkListRemover DeadNodes(*this); 5456 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5457 removeFromWorkList(N1.getNode()); 5458 DAG.DeleteNode(N1.getNode()); 5459 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5460 } 5461 } 5462 } 5463 5464 if (Trunc) 5465 // Restore N1 if the above transformation doesn't match. 5466 N1 = N->getOperand(1); 5467 } 5468 5469 // Transform br(xor(x, y)) -> br(x != y) 5470 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 5471 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 5472 SDNode *TheXor = N1.getNode(); 5473 SDValue Op0 = TheXor->getOperand(0); 5474 SDValue Op1 = TheXor->getOperand(1); 5475 if (Op0.getOpcode() == Op1.getOpcode()) { 5476 // Avoid missing important xor optimizations. 5477 SDValue Tmp = visitXOR(TheXor); 5478 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 5479 DEBUG(dbgs() << "\nReplacing.8 "; 5480 TheXor->dump(&DAG); 5481 dbgs() << "\nWith: "; 5482 Tmp.getNode()->dump(&DAG); 5483 dbgs() << '\n'); 5484 WorkListRemover DeadNodes(*this); 5485 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 5486 removeFromWorkList(TheXor); 5487 DAG.DeleteNode(TheXor); 5488 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5489 MVT::Other, Chain, Tmp, N2); 5490 } 5491 } 5492 5493 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 5494 bool Equal = false; 5495 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 5496 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 5497 Op0.getOpcode() == ISD::XOR) { 5498 TheXor = Op0.getNode(); 5499 Equal = true; 5500 } 5501 5502 EVT SetCCVT = N1.getValueType(); 5503 if (LegalTypes) 5504 SetCCVT = TLI.getSetCCResultType(SetCCVT); 5505 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 5506 SetCCVT, 5507 Op0, Op1, 5508 Equal ? ISD::SETEQ : ISD::SETNE); 5509 // Replace the uses of XOR with SETCC 5510 WorkListRemover DeadNodes(*this); 5511 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5512 removeFromWorkList(N1.getNode()); 5513 DAG.DeleteNode(N1.getNode()); 5514 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5515 MVT::Other, Chain, SetCC, N2); 5516 } 5517 } 5518 5519 return SDValue(); 5520} 5521 5522// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 5523// 5524SDValue DAGCombiner::visitBR_CC(SDNode *N) { 5525 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 5526 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 5527 5528 // If N is a constant we could fold this into a fallthrough or unconditional 5529 // branch. However that doesn't happen very often in normal code, because 5530 // Instcombine/SimplifyCFG should have handled the available opportunities. 5531 // If we did this folding here, it would be necessary to update the 5532 // MachineBasicBlock CFG, which is awkward. 5533 5534 // Use SimplifySetCC to simplify SETCC's. 5535 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 5536 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 5537 false); 5538 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 5539 5540 // fold to a simpler setcc 5541 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 5542 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5543 N->getOperand(0), Simp.getOperand(2), 5544 Simp.getOperand(0), Simp.getOperand(1), 5545 N->getOperand(4)); 5546 5547 return SDValue(); 5548} 5549 5550/// CombineToPreIndexedLoadStore - Try turning a load / store into a 5551/// pre-indexed load / store when the base pointer is an add or subtract 5552/// and it has other uses besides the load / store. After the 5553/// transformation, the new indexed load / store has effectively folded 5554/// the add / subtract in and all of its other uses are redirected to the 5555/// new load / store. 5556bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 5557 if (!LegalOperations) 5558 return false; 5559 5560 bool isLoad = true; 5561 SDValue Ptr; 5562 EVT VT; 5563 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5564 if (LD->isIndexed()) 5565 return false; 5566 VT = LD->getMemoryVT(); 5567 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 5568 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 5569 return false; 5570 Ptr = LD->getBasePtr(); 5571 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5572 if (ST->isIndexed()) 5573 return false; 5574 VT = ST->getMemoryVT(); 5575 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 5576 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 5577 return false; 5578 Ptr = ST->getBasePtr(); 5579 isLoad = false; 5580 } else { 5581 return false; 5582 } 5583 5584 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 5585 // out. There is no reason to make this a preinc/predec. 5586 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 5587 Ptr.getNode()->hasOneUse()) 5588 return false; 5589 5590 // Ask the target to do addressing mode selection. 5591 SDValue BasePtr; 5592 SDValue Offset; 5593 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5594 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 5595 return false; 5596 // Don't create a indexed load / store with zero offset. 5597 if (isa<ConstantSDNode>(Offset) && 5598 cast<ConstantSDNode>(Offset)->isNullValue()) 5599 return false; 5600 5601 // Try turning it into a pre-indexed load / store except when: 5602 // 1) The new base ptr is a frame index. 5603 // 2) If N is a store and the new base ptr is either the same as or is a 5604 // predecessor of the value being stored. 5605 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 5606 // that would create a cycle. 5607 // 4) All uses are load / store ops that use it as old base ptr. 5608 5609 // Check #1. Preinc'ing a frame index would require copying the stack pointer 5610 // (plus the implicit offset) to a register to preinc anyway. 5611 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5612 return false; 5613 5614 // Check #2. 5615 if (!isLoad) { 5616 SDValue Val = cast<StoreSDNode>(N)->getValue(); 5617 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 5618 return false; 5619 } 5620 5621 // Now check for #3 and #4. 5622 bool RealUse = false; 5623 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5624 E = Ptr.getNode()->use_end(); I != E; ++I) { 5625 SDNode *Use = *I; 5626 if (Use == N) 5627 continue; 5628 if (Use->isPredecessorOf(N)) 5629 return false; 5630 5631 if (!((Use->getOpcode() == ISD::LOAD && 5632 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 5633 (Use->getOpcode() == ISD::STORE && 5634 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 5635 RealUse = true; 5636 } 5637 5638 if (!RealUse) 5639 return false; 5640 5641 SDValue Result; 5642 if (isLoad) 5643 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5644 BasePtr, Offset, AM); 5645 else 5646 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5647 BasePtr, Offset, AM); 5648 ++PreIndexedNodes; 5649 ++NodesCombined; 5650 DEBUG(dbgs() << "\nReplacing.4 "; 5651 N->dump(&DAG); 5652 dbgs() << "\nWith: "; 5653 Result.getNode()->dump(&DAG); 5654 dbgs() << '\n'); 5655 WorkListRemover DeadNodes(*this); 5656 if (isLoad) { 5657 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5658 &DeadNodes); 5659 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5660 &DeadNodes); 5661 } else { 5662 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5663 &DeadNodes); 5664 } 5665 5666 // Finally, since the node is now dead, remove it from the graph. 5667 DAG.DeleteNode(N); 5668 5669 // Replace the uses of Ptr with uses of the updated base value. 5670 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 5671 &DeadNodes); 5672 removeFromWorkList(Ptr.getNode()); 5673 DAG.DeleteNode(Ptr.getNode()); 5674 5675 return true; 5676} 5677 5678/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 5679/// add / sub of the base pointer node into a post-indexed load / store. 5680/// The transformation folded the add / subtract into the new indexed 5681/// load / store effectively and all of its uses are redirected to the 5682/// new load / store. 5683bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 5684 if (!LegalOperations) 5685 return false; 5686 5687 bool isLoad = true; 5688 SDValue Ptr; 5689 EVT VT; 5690 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5691 if (LD->isIndexed()) 5692 return false; 5693 VT = LD->getMemoryVT(); 5694 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 5695 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 5696 return false; 5697 Ptr = LD->getBasePtr(); 5698 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5699 if (ST->isIndexed()) 5700 return false; 5701 VT = ST->getMemoryVT(); 5702 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 5703 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 5704 return false; 5705 Ptr = ST->getBasePtr(); 5706 isLoad = false; 5707 } else { 5708 return false; 5709 } 5710 5711 if (Ptr.getNode()->hasOneUse()) 5712 return false; 5713 5714 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5715 E = Ptr.getNode()->use_end(); I != E; ++I) { 5716 SDNode *Op = *I; 5717 if (Op == N || 5718 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 5719 continue; 5720 5721 SDValue BasePtr; 5722 SDValue Offset; 5723 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5724 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 5725 // Don't create a indexed load / store with zero offset. 5726 if (isa<ConstantSDNode>(Offset) && 5727 cast<ConstantSDNode>(Offset)->isNullValue()) 5728 continue; 5729 5730 // Try turning it into a post-indexed load / store except when 5731 // 1) All uses are load / store ops that use it as base ptr. 5732 // 2) Op must be independent of N, i.e. Op is neither a predecessor 5733 // nor a successor of N. Otherwise, if Op is folded that would 5734 // create a cycle. 5735 5736 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5737 continue; 5738 5739 // Check for #1. 5740 bool TryNext = false; 5741 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 5742 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 5743 SDNode *Use = *II; 5744 if (Use == Ptr.getNode()) 5745 continue; 5746 5747 // If all the uses are load / store addresses, then don't do the 5748 // transformation. 5749 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 5750 bool RealUse = false; 5751 for (SDNode::use_iterator III = Use->use_begin(), 5752 EEE = Use->use_end(); III != EEE; ++III) { 5753 SDNode *UseUse = *III; 5754 if (!((UseUse->getOpcode() == ISD::LOAD && 5755 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 5756 (UseUse->getOpcode() == ISD::STORE && 5757 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 5758 RealUse = true; 5759 } 5760 5761 if (!RealUse) { 5762 TryNext = true; 5763 break; 5764 } 5765 } 5766 } 5767 5768 if (TryNext) 5769 continue; 5770 5771 // Check for #2 5772 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 5773 SDValue Result = isLoad 5774 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5775 BasePtr, Offset, AM) 5776 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5777 BasePtr, Offset, AM); 5778 ++PostIndexedNodes; 5779 ++NodesCombined; 5780 DEBUG(dbgs() << "\nReplacing.5 "; 5781 N->dump(&DAG); 5782 dbgs() << "\nWith: "; 5783 Result.getNode()->dump(&DAG); 5784 dbgs() << '\n'); 5785 WorkListRemover DeadNodes(*this); 5786 if (isLoad) { 5787 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5788 &DeadNodes); 5789 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5790 &DeadNodes); 5791 } else { 5792 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5793 &DeadNodes); 5794 } 5795 5796 // Finally, since the node is now dead, remove it from the graph. 5797 DAG.DeleteNode(N); 5798 5799 // Replace the uses of Use with uses of the updated base value. 5800 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 5801 Result.getValue(isLoad ? 1 : 0), 5802 &DeadNodes); 5803 removeFromWorkList(Op); 5804 DAG.DeleteNode(Op); 5805 return true; 5806 } 5807 } 5808 } 5809 5810 return false; 5811} 5812 5813SDValue DAGCombiner::visitLOAD(SDNode *N) { 5814 LoadSDNode *LD = cast<LoadSDNode>(N); 5815 SDValue Chain = LD->getChain(); 5816 SDValue Ptr = LD->getBasePtr(); 5817 5818 // If load is not volatile and there are no uses of the loaded value (and 5819 // the updated indexed value in case of indexed loads), change uses of the 5820 // chain value into uses of the chain input (i.e. delete the dead load). 5821 if (!LD->isVolatile()) { 5822 if (N->getValueType(1) == MVT::Other) { 5823 // Unindexed loads. 5824 if (N->hasNUsesOfValue(0, 0)) { 5825 // It's not safe to use the two value CombineTo variant here. e.g. 5826 // v1, chain2 = load chain1, loc 5827 // v2, chain3 = load chain2, loc 5828 // v3 = add v2, c 5829 // Now we replace use of chain2 with chain1. This makes the second load 5830 // isomorphic to the one we are deleting, and thus makes this load live. 5831 DEBUG(dbgs() << "\nReplacing.6 "; 5832 N->dump(&DAG); 5833 dbgs() << "\nWith chain: "; 5834 Chain.getNode()->dump(&DAG); 5835 dbgs() << "\n"); 5836 WorkListRemover DeadNodes(*this); 5837 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 5838 5839 if (N->use_empty()) { 5840 removeFromWorkList(N); 5841 DAG.DeleteNode(N); 5842 } 5843 5844 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5845 } 5846 } else { 5847 // Indexed loads. 5848 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 5849 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 5850 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 5851 DEBUG(dbgs() << "\nReplacing.7 "; 5852 N->dump(&DAG); 5853 dbgs() << "\nWith: "; 5854 Undef.getNode()->dump(&DAG); 5855 dbgs() << " and 2 other values\n"); 5856 WorkListRemover DeadNodes(*this); 5857 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 5858 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 5859 DAG.getUNDEF(N->getValueType(1)), 5860 &DeadNodes); 5861 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 5862 removeFromWorkList(N); 5863 DAG.DeleteNode(N); 5864 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5865 } 5866 } 5867 } 5868 5869 // If this load is directly stored, replace the load value with the stored 5870 // value. 5871 // TODO: Handle store large -> read small portion. 5872 // TODO: Handle TRUNCSTORE/LOADEXT 5873 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 5874 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 5875 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 5876 if (PrevST->getBasePtr() == Ptr && 5877 PrevST->getValue().getValueType() == N->getValueType(0)) 5878 return CombineTo(N, Chain.getOperand(1), Chain); 5879 } 5880 } 5881 5882 // Try to infer better alignment information than the load already has. 5883 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 5884 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5885 if (Align > LD->getAlignment()) 5886 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 5887 LD->getValueType(0), 5888 Chain, Ptr, LD->getPointerInfo(), 5889 LD->getMemoryVT(), 5890 LD->isVolatile(), LD->isNonTemporal(), Align); 5891 } 5892 } 5893 5894 if (CombinerAA) { 5895 // Walk up chain skipping non-aliasing memory nodes. 5896 SDValue BetterChain = FindBetterChain(N, Chain); 5897 5898 // If there is a better chain. 5899 if (Chain != BetterChain) { 5900 SDValue ReplLoad; 5901 5902 // Replace the chain to void dependency. 5903 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5904 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5905 BetterChain, Ptr, LD->getPointerInfo(), 5906 LD->isVolatile(), LD->isNonTemporal(), 5907 LD->getAlignment()); 5908 } else { 5909 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 5910 LD->getValueType(0), 5911 BetterChain, Ptr, LD->getPointerInfo(), 5912 LD->getMemoryVT(), 5913 LD->isVolatile(), 5914 LD->isNonTemporal(), 5915 LD->getAlignment()); 5916 } 5917 5918 // Create token factor to keep old chain connected. 5919 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5920 MVT::Other, Chain, ReplLoad.getValue(1)); 5921 5922 // Make sure the new and old chains are cleaned up. 5923 AddToWorkList(Token.getNode()); 5924 5925 // Replace uses with load result and token factor. Don't add users 5926 // to work list. 5927 return CombineTo(N, ReplLoad.getValue(0), Token, false); 5928 } 5929 } 5930 5931 // Try transforming N to an indexed load. 5932 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5933 return SDValue(N, 0); 5934 5935 return SDValue(); 5936} 5937 5938/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 5939/// load is having specific bytes cleared out. If so, return the byte size 5940/// being masked out and the shift amount. 5941static std::pair<unsigned, unsigned> 5942CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 5943 std::pair<unsigned, unsigned> Result(0, 0); 5944 5945 // Check for the structure we're looking for. 5946 if (V->getOpcode() != ISD::AND || 5947 !isa<ConstantSDNode>(V->getOperand(1)) || 5948 !ISD::isNormalLoad(V->getOperand(0).getNode())) 5949 return Result; 5950 5951 // Check the chain and pointer. 5952 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 5953 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 5954 5955 // The store should be chained directly to the load or be an operand of a 5956 // tokenfactor. 5957 if (LD == Chain.getNode()) 5958 ; // ok. 5959 else if (Chain->getOpcode() != ISD::TokenFactor) 5960 return Result; // Fail. 5961 else { 5962 bool isOk = false; 5963 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 5964 if (Chain->getOperand(i).getNode() == LD) { 5965 isOk = true; 5966 break; 5967 } 5968 if (!isOk) return Result; 5969 } 5970 5971 // This only handles simple types. 5972 if (V.getValueType() != MVT::i16 && 5973 V.getValueType() != MVT::i32 && 5974 V.getValueType() != MVT::i64) 5975 return Result; 5976 5977 // Check the constant mask. Invert it so that the bits being masked out are 5978 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 5979 // follow the sign bit for uniformity. 5980 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 5981 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 5982 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 5983 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 5984 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 5985 if (NotMaskLZ == 64) return Result; // All zero mask. 5986 5987 // See if we have a continuous run of bits. If so, we have 0*1+0* 5988 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 5989 return Result; 5990 5991 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 5992 if (V.getValueType() != MVT::i64 && NotMaskLZ) 5993 NotMaskLZ -= 64-V.getValueSizeInBits(); 5994 5995 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 5996 switch (MaskedBytes) { 5997 case 1: 5998 case 2: 5999 case 4: break; 6000 default: return Result; // All one mask, or 5-byte mask. 6001 } 6002 6003 // Verify that the first bit starts at a multiple of mask so that the access 6004 // is aligned the same as the access width. 6005 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 6006 6007 Result.first = MaskedBytes; 6008 Result.second = NotMaskTZ/8; 6009 return Result; 6010} 6011 6012 6013/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 6014/// provides a value as specified by MaskInfo. If so, replace the specified 6015/// store with a narrower store of truncated IVal. 6016static SDNode * 6017ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 6018 SDValue IVal, StoreSDNode *St, 6019 DAGCombiner *DC) { 6020 unsigned NumBytes = MaskInfo.first; 6021 unsigned ByteShift = MaskInfo.second; 6022 SelectionDAG &DAG = DC->getDAG(); 6023 6024 // Check to see if IVal is all zeros in the part being masked in by the 'or' 6025 // that uses this. If not, this is not a replacement. 6026 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 6027 ByteShift*8, (ByteShift+NumBytes)*8); 6028 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 6029 6030 // Check that it is legal on the target to do this. It is legal if the new 6031 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 6032 // legalization. 6033 MVT VT = MVT::getIntegerVT(NumBytes*8); 6034 if (!DC->isTypeLegal(VT)) 6035 return 0; 6036 6037 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 6038 // shifted by ByteShift and truncated down to NumBytes. 6039 if (ByteShift) 6040 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 6041 DAG.getConstant(ByteShift*8, 6042 DC->getShiftAmountTy(IVal.getValueType()))); 6043 6044 // Figure out the offset for the store and the alignment of the access. 6045 unsigned StOffset; 6046 unsigned NewAlign = St->getAlignment(); 6047 6048 if (DAG.getTargetLoweringInfo().isLittleEndian()) 6049 StOffset = ByteShift; 6050 else 6051 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 6052 6053 SDValue Ptr = St->getBasePtr(); 6054 if (StOffset) { 6055 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 6056 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 6057 NewAlign = MinAlign(NewAlign, StOffset); 6058 } 6059 6060 // Truncate down to the new size. 6061 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 6062 6063 ++OpsNarrowed; 6064 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 6065 St->getPointerInfo().getWithOffset(StOffset), 6066 false, false, NewAlign).getNode(); 6067} 6068 6069 6070/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 6071/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 6072/// of the loaded bits, try narrowing the load and store if it would end up 6073/// being a win for performance or code size. 6074SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 6075 StoreSDNode *ST = cast<StoreSDNode>(N); 6076 if (ST->isVolatile()) 6077 return SDValue(); 6078 6079 SDValue Chain = ST->getChain(); 6080 SDValue Value = ST->getValue(); 6081 SDValue Ptr = ST->getBasePtr(); 6082 EVT VT = Value.getValueType(); 6083 6084 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 6085 return SDValue(); 6086 6087 unsigned Opc = Value.getOpcode(); 6088 6089 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 6090 // is a byte mask indicating a consecutive number of bytes, check to see if 6091 // Y is known to provide just those bytes. If so, we try to replace the 6092 // load + replace + store sequence with a single (narrower) store, which makes 6093 // the load dead. 6094 if (Opc == ISD::OR) { 6095 std::pair<unsigned, unsigned> MaskedLoad; 6096 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 6097 if (MaskedLoad.first) 6098 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6099 Value.getOperand(1), ST,this)) 6100 return SDValue(NewST, 0); 6101 6102 // Or is commutative, so try swapping X and Y. 6103 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 6104 if (MaskedLoad.first) 6105 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6106 Value.getOperand(0), ST,this)) 6107 return SDValue(NewST, 0); 6108 } 6109 6110 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 6111 Value.getOperand(1).getOpcode() != ISD::Constant) 6112 return SDValue(); 6113 6114 SDValue N0 = Value.getOperand(0); 6115 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6116 Chain == SDValue(N0.getNode(), 1)) { 6117 LoadSDNode *LD = cast<LoadSDNode>(N0); 6118 if (LD->getBasePtr() != Ptr || 6119 LD->getPointerInfo().getAddrSpace() != 6120 ST->getPointerInfo().getAddrSpace()) 6121 return SDValue(); 6122 6123 // Find the type to narrow it the load / op / store to. 6124 SDValue N1 = Value.getOperand(1); 6125 unsigned BitWidth = N1.getValueSizeInBits(); 6126 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 6127 if (Opc == ISD::AND) 6128 Imm ^= APInt::getAllOnesValue(BitWidth); 6129 if (Imm == 0 || Imm.isAllOnesValue()) 6130 return SDValue(); 6131 unsigned ShAmt = Imm.countTrailingZeros(); 6132 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 6133 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 6134 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6135 while (NewBW < BitWidth && 6136 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 6137 TLI.isNarrowingProfitable(VT, NewVT))) { 6138 NewBW = NextPowerOf2(NewBW); 6139 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6140 } 6141 if (NewBW >= BitWidth) 6142 return SDValue(); 6143 6144 // If the lsb changed does not start at the type bitwidth boundary, 6145 // start at the previous one. 6146 if (ShAmt % NewBW) 6147 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 6148 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 6149 if ((Imm & Mask) == Imm) { 6150 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 6151 if (Opc == ISD::AND) 6152 NewImm ^= APInt::getAllOnesValue(NewBW); 6153 uint64_t PtrOff = ShAmt / 8; 6154 // For big endian targets, we need to adjust the offset to the pointer to 6155 // load the correct bytes. 6156 if (TLI.isBigEndian()) 6157 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 6158 6159 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 6160 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 6161 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 6162 return SDValue(); 6163 6164 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 6165 Ptr.getValueType(), Ptr, 6166 DAG.getConstant(PtrOff, Ptr.getValueType())); 6167 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 6168 LD->getChain(), NewPtr, 6169 LD->getPointerInfo().getWithOffset(PtrOff), 6170 LD->isVolatile(), LD->isNonTemporal(), 6171 NewAlign); 6172 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 6173 DAG.getConstant(NewImm, NewVT)); 6174 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 6175 NewVal, NewPtr, 6176 ST->getPointerInfo().getWithOffset(PtrOff), 6177 false, false, NewAlign); 6178 6179 AddToWorkList(NewPtr.getNode()); 6180 AddToWorkList(NewLD.getNode()); 6181 AddToWorkList(NewVal.getNode()); 6182 WorkListRemover DeadNodes(*this); 6183 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 6184 &DeadNodes); 6185 ++OpsNarrowed; 6186 return NewST; 6187 } 6188 } 6189 6190 return SDValue(); 6191} 6192 6193/// TransformFPLoadStorePair - For a given floating point load / store pair, 6194/// if the load value isn't used by any other operations, then consider 6195/// transforming the pair to integer load / store operations if the target 6196/// deems the transformation profitable. 6197SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 6198 StoreSDNode *ST = cast<StoreSDNode>(N); 6199 SDValue Chain = ST->getChain(); 6200 SDValue Value = ST->getValue(); 6201 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 6202 Value.hasOneUse() && 6203 Chain == SDValue(Value.getNode(), 1)) { 6204 LoadSDNode *LD = cast<LoadSDNode>(Value); 6205 EVT VT = LD->getMemoryVT(); 6206 if (!VT.isFloatingPoint() || 6207 VT != ST->getMemoryVT() || 6208 LD->isNonTemporal() || 6209 ST->isNonTemporal() || 6210 LD->getPointerInfo().getAddrSpace() != 0 || 6211 ST->getPointerInfo().getAddrSpace() != 0) 6212 return SDValue(); 6213 6214 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 6215 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 6216 !TLI.isOperationLegal(ISD::STORE, IntVT) || 6217 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 6218 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 6219 return SDValue(); 6220 6221 unsigned LDAlign = LD->getAlignment(); 6222 unsigned STAlign = ST->getAlignment(); 6223 const Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 6224 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy); 6225 if (LDAlign < ABIAlign || STAlign < ABIAlign) 6226 return SDValue(); 6227 6228 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 6229 LD->getChain(), LD->getBasePtr(), 6230 LD->getPointerInfo(), 6231 false, false, LDAlign); 6232 6233 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 6234 NewLD, ST->getBasePtr(), 6235 ST->getPointerInfo(), 6236 false, false, STAlign); 6237 6238 AddToWorkList(NewLD.getNode()); 6239 AddToWorkList(NewST.getNode()); 6240 WorkListRemover DeadNodes(*this); 6241 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1), 6242 &DeadNodes); 6243 ++LdStFP2Int; 6244 return NewST; 6245 } 6246 6247 return SDValue(); 6248} 6249 6250SDValue DAGCombiner::visitSTORE(SDNode *N) { 6251 StoreSDNode *ST = cast<StoreSDNode>(N); 6252 SDValue Chain = ST->getChain(); 6253 SDValue Value = ST->getValue(); 6254 SDValue Ptr = ST->getBasePtr(); 6255 6256 // If this is a store of a bit convert, store the input value if the 6257 // resultant store does not need a higher alignment than the original. 6258 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 6259 ST->isUnindexed()) { 6260 unsigned OrigAlign = ST->getAlignment(); 6261 EVT SVT = Value.getOperand(0).getValueType(); 6262 unsigned Align = TLI.getTargetData()-> 6263 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 6264 if (Align <= OrigAlign && 6265 ((!LegalOperations && !ST->isVolatile()) || 6266 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 6267 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6268 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6269 ST->isNonTemporal(), OrigAlign); 6270 } 6271 6272 // Turn 'store undef, Ptr' -> nothing. 6273 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 6274 return Chain; 6275 6276 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 6277 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 6278 // NOTE: If the original store is volatile, this transform must not increase 6279 // the number of stores. For example, on x86-32 an f64 can be stored in one 6280 // processor operation but an i64 (which is not legal) requires two. So the 6281 // transform should not be done in this case. 6282 if (Value.getOpcode() != ISD::TargetConstantFP) { 6283 SDValue Tmp; 6284 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 6285 default: llvm_unreachable("Unknown FP type"); 6286 case MVT::f80: // We don't do this for these yet. 6287 case MVT::f128: 6288 case MVT::ppcf128: 6289 break; 6290 case MVT::f32: 6291 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 6292 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6293 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 6294 bitcastToAPInt().getZExtValue(), MVT::i32); 6295 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6296 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6297 ST->isNonTemporal(), ST->getAlignment()); 6298 } 6299 break; 6300 case MVT::f64: 6301 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 6302 !ST->isVolatile()) || 6303 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 6304 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 6305 getZExtValue(), MVT::i64); 6306 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6307 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6308 ST->isNonTemporal(), ST->getAlignment()); 6309 } 6310 6311 if (!ST->isVolatile() && 6312 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6313 // Many FP stores are not made apparent until after legalize, e.g. for 6314 // argument passing. Since this is so common, custom legalize the 6315 // 64-bit integer store into two 32-bit stores. 6316 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 6317 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 6318 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 6319 if (TLI.isBigEndian()) std::swap(Lo, Hi); 6320 6321 unsigned Alignment = ST->getAlignment(); 6322 bool isVolatile = ST->isVolatile(); 6323 bool isNonTemporal = ST->isNonTemporal(); 6324 6325 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 6326 Ptr, ST->getPointerInfo(), 6327 isVolatile, isNonTemporal, 6328 ST->getAlignment()); 6329 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 6330 DAG.getConstant(4, Ptr.getValueType())); 6331 Alignment = MinAlign(Alignment, 4U); 6332 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 6333 Ptr, ST->getPointerInfo().getWithOffset(4), 6334 isVolatile, isNonTemporal, 6335 Alignment); 6336 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6337 St0, St1); 6338 } 6339 6340 break; 6341 } 6342 } 6343 } 6344 6345 // Try to infer better alignment information than the store already has. 6346 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 6347 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6348 if (Align > ST->getAlignment()) 6349 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 6350 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6351 ST->isVolatile(), ST->isNonTemporal(), Align); 6352 } 6353 } 6354 6355 // Try transforming a pair floating point load / store ops to integer 6356 // load / store ops. 6357 SDValue NewST = TransformFPLoadStorePair(N); 6358 if (NewST.getNode()) 6359 return NewST; 6360 6361 if (CombinerAA) { 6362 // Walk up chain skipping non-aliasing memory nodes. 6363 SDValue BetterChain = FindBetterChain(N, Chain); 6364 6365 // If there is a better chain. 6366 if (Chain != BetterChain) { 6367 SDValue ReplStore; 6368 6369 // Replace the chain to avoid dependency. 6370 if (ST->isTruncatingStore()) { 6371 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6372 ST->getPointerInfo(), 6373 ST->getMemoryVT(), ST->isVolatile(), 6374 ST->isNonTemporal(), ST->getAlignment()); 6375 } else { 6376 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6377 ST->getPointerInfo(), 6378 ST->isVolatile(), ST->isNonTemporal(), 6379 ST->getAlignment()); 6380 } 6381 6382 // Create token to keep both nodes around. 6383 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6384 MVT::Other, Chain, ReplStore); 6385 6386 // Make sure the new and old chains are cleaned up. 6387 AddToWorkList(Token.getNode()); 6388 6389 // Don't add users to work list. 6390 return CombineTo(N, Token, false); 6391 } 6392 } 6393 6394 // Try transforming N to an indexed store. 6395 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6396 return SDValue(N, 0); 6397 6398 // FIXME: is there such a thing as a truncating indexed store? 6399 if (ST->isTruncatingStore() && ST->isUnindexed() && 6400 Value.getValueType().isInteger()) { 6401 // See if we can simplify the input to this truncstore with knowledge that 6402 // only the low bits are being used. For example: 6403 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 6404 SDValue Shorter = 6405 GetDemandedBits(Value, 6406 APInt::getLowBitsSet(Value.getValueSizeInBits(), 6407 ST->getMemoryVT().getSizeInBits())); 6408 AddToWorkList(Value.getNode()); 6409 if (Shorter.getNode()) 6410 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 6411 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6412 ST->isVolatile(), ST->isNonTemporal(), 6413 ST->getAlignment()); 6414 6415 // Otherwise, see if we can simplify the operation with 6416 // SimplifyDemandedBits, which only works if the value has a single use. 6417 if (SimplifyDemandedBits(Value, 6418 APInt::getLowBitsSet( 6419 Value.getValueType().getScalarType().getSizeInBits(), 6420 ST->getMemoryVT().getScalarType().getSizeInBits()))) 6421 return SDValue(N, 0); 6422 } 6423 6424 // If this is a load followed by a store to the same location, then the store 6425 // is dead/noop. 6426 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 6427 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 6428 ST->isUnindexed() && !ST->isVolatile() && 6429 // There can't be any side effects between the load and store, such as 6430 // a call or store. 6431 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 6432 // The store is dead, remove it. 6433 return Chain; 6434 } 6435 } 6436 6437 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 6438 // truncating store. We can do this even if this is already a truncstore. 6439 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 6440 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 6441 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 6442 ST->getMemoryVT())) { 6443 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6444 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6445 ST->isVolatile(), ST->isNonTemporal(), 6446 ST->getAlignment()); 6447 } 6448 6449 return ReduceLoadOpStoreWidth(N); 6450} 6451 6452SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 6453 SDValue InVec = N->getOperand(0); 6454 SDValue InVal = N->getOperand(1); 6455 SDValue EltNo = N->getOperand(2); 6456 6457 // If the inserted element is an UNDEF, just use the input vector. 6458 if (InVal.getOpcode() == ISD::UNDEF) 6459 return InVec; 6460 6461 EVT VT = InVec.getValueType(); 6462 6463 // If we can't generate a legal BUILD_VECTOR, exit 6464 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 6465 return SDValue(); 6466 6467 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 6468 // vector with the inserted element. 6469 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 6470 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6471 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 6472 InVec.getNode()->op_end()); 6473 if (Elt < Ops.size()) 6474 Ops[Elt] = InVal; 6475 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6476 VT, &Ops[0], Ops.size()); 6477 } 6478 // If the invec is an UNDEF and if EltNo is a constant, create a new 6479 // BUILD_VECTOR with undef elements and the inserted element. 6480 if (InVec.getOpcode() == ISD::UNDEF && 6481 isa<ConstantSDNode>(EltNo)) { 6482 EVT EltVT = VT.getVectorElementType(); 6483 unsigned NElts = VT.getVectorNumElements(); 6484 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 6485 6486 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6487 if (Elt < Ops.size()) 6488 Ops[Elt] = InVal; 6489 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6490 VT, &Ops[0], Ops.size()); 6491 } 6492 return SDValue(); 6493} 6494 6495SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 6496 // (vextract (scalar_to_vector val, 0) -> val 6497 SDValue InVec = N->getOperand(0); 6498 6499 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 6500 // Check if the result type doesn't match the inserted element type. A 6501 // SCALAR_TO_VECTOR may truncate the inserted element and the 6502 // EXTRACT_VECTOR_ELT may widen the extracted vector. 6503 SDValue InOp = InVec.getOperand(0); 6504 EVT NVT = N->getValueType(0); 6505 if (InOp.getValueType() != NVT) { 6506 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 6507 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 6508 } 6509 return InOp; 6510 } 6511 6512 // Perform only after legalization to ensure build_vector / vector_shuffle 6513 // optimizations have already been done. 6514 if (!LegalOperations) return SDValue(); 6515 6516 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 6517 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 6518 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 6519 SDValue EltNo = N->getOperand(1); 6520 6521 if (isa<ConstantSDNode>(EltNo)) { 6522 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6523 bool NewLoad = false; 6524 bool BCNumEltsChanged = false; 6525 EVT VT = InVec.getValueType(); 6526 EVT ExtVT = VT.getVectorElementType(); 6527 EVT LVT = ExtVT; 6528 6529 if (InVec.getOpcode() == ISD::BITCAST) { 6530 EVT BCVT = InVec.getOperand(0).getValueType(); 6531 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 6532 return SDValue(); 6533 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 6534 BCNumEltsChanged = true; 6535 InVec = InVec.getOperand(0); 6536 ExtVT = BCVT.getVectorElementType(); 6537 NewLoad = true; 6538 } 6539 6540 LoadSDNode *LN0 = NULL; 6541 const ShuffleVectorSDNode *SVN = NULL; 6542 if (ISD::isNormalLoad(InVec.getNode())) { 6543 LN0 = cast<LoadSDNode>(InVec); 6544 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 6545 InVec.getOperand(0).getValueType() == ExtVT && 6546 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 6547 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 6548 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 6549 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 6550 // => 6551 // (load $addr+1*size) 6552 6553 // If the bit convert changed the number of elements, it is unsafe 6554 // to examine the mask. 6555 if (BCNumEltsChanged) 6556 return SDValue(); 6557 6558 // Select the input vector, guarding against out of range extract vector. 6559 unsigned NumElems = VT.getVectorNumElements(); 6560 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 6561 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 6562 6563 if (InVec.getOpcode() == ISD::BITCAST) 6564 InVec = InVec.getOperand(0); 6565 if (ISD::isNormalLoad(InVec.getNode())) { 6566 LN0 = cast<LoadSDNode>(InVec); 6567 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 6568 } 6569 } 6570 6571 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 6572 return SDValue(); 6573 6574 // If Idx was -1 above, Elt is going to be -1, so just return undef. 6575 if (Elt == -1) 6576 return DAG.getUNDEF(LN0->getBasePtr().getValueType()); 6577 6578 unsigned Align = LN0->getAlignment(); 6579 if (NewLoad) { 6580 // Check the resultant load doesn't need a higher alignment than the 6581 // original load. 6582 unsigned NewAlign = 6583 TLI.getTargetData() 6584 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 6585 6586 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 6587 return SDValue(); 6588 6589 Align = NewAlign; 6590 } 6591 6592 SDValue NewPtr = LN0->getBasePtr(); 6593 unsigned PtrOff = 0; 6594 6595 if (Elt) { 6596 PtrOff = LVT.getSizeInBits() * Elt / 8; 6597 EVT PtrType = NewPtr.getValueType(); 6598 if (TLI.isBigEndian()) 6599 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 6600 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 6601 DAG.getConstant(PtrOff, PtrType)); 6602 } 6603 6604 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 6605 LN0->getPointerInfo().getWithOffset(PtrOff), 6606 LN0->isVolatile(), LN0->isNonTemporal(), Align); 6607 } 6608 6609 return SDValue(); 6610} 6611 6612SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 6613 unsigned NumInScalars = N->getNumOperands(); 6614 EVT VT = N->getValueType(0); 6615 6616 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 6617 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 6618 // at most two distinct vectors, turn this into a shuffle node. 6619 SDValue VecIn1, VecIn2; 6620 for (unsigned i = 0; i != NumInScalars; ++i) { 6621 // Ignore undef inputs. 6622 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 6623 6624 // If this input is something other than a EXTRACT_VECTOR_ELT with a 6625 // constant index, bail out. 6626 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 6627 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 6628 VecIn1 = VecIn2 = SDValue(0, 0); 6629 break; 6630 } 6631 6632 // If the input vector type disagrees with the result of the build_vector, 6633 // we can't make a shuffle. 6634 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 6635 if (ExtractedFromVec.getValueType() != VT) { 6636 VecIn1 = VecIn2 = SDValue(0, 0); 6637 break; 6638 } 6639 6640 // Otherwise, remember this. We allow up to two distinct input vectors. 6641 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 6642 continue; 6643 6644 if (VecIn1.getNode() == 0) { 6645 VecIn1 = ExtractedFromVec; 6646 } else if (VecIn2.getNode() == 0) { 6647 VecIn2 = ExtractedFromVec; 6648 } else { 6649 // Too many inputs. 6650 VecIn1 = VecIn2 = SDValue(0, 0); 6651 break; 6652 } 6653 } 6654 6655 // If everything is good, we can make a shuffle operation. 6656 if (VecIn1.getNode()) { 6657 SmallVector<int, 8> Mask; 6658 for (unsigned i = 0; i != NumInScalars; ++i) { 6659 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 6660 Mask.push_back(-1); 6661 continue; 6662 } 6663 6664 // If extracting from the first vector, just use the index directly. 6665 SDValue Extract = N->getOperand(i); 6666 SDValue ExtVal = Extract.getOperand(1); 6667 if (Extract.getOperand(0) == VecIn1) { 6668 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6669 if (ExtIndex > VT.getVectorNumElements()) 6670 return SDValue(); 6671 6672 Mask.push_back(ExtIndex); 6673 continue; 6674 } 6675 6676 // Otherwise, use InIdx + VecSize 6677 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6678 Mask.push_back(Idx+NumInScalars); 6679 } 6680 6681 // Add count and size info. 6682 if (!isTypeLegal(VT)) 6683 return SDValue(); 6684 6685 // Return the new VECTOR_SHUFFLE node. 6686 SDValue Ops[2]; 6687 Ops[0] = VecIn1; 6688 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 6689 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 6690 } 6691 6692 return SDValue(); 6693} 6694 6695SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 6696 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 6697 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 6698 // inputs come from at most two distinct vectors, turn this into a shuffle 6699 // node. 6700 6701 // If we only have one input vector, we don't need to do any concatenation. 6702 if (N->getNumOperands() == 1) 6703 return N->getOperand(0); 6704 6705 return SDValue(); 6706} 6707 6708SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 6709 EVT VT = N->getValueType(0); 6710 unsigned NumElts = VT.getVectorNumElements(); 6711 6712 SDValue N0 = N->getOperand(0); 6713 6714 assert(N0.getValueType().getVectorNumElements() == NumElts && 6715 "Vector shuffle must be normalized in DAG"); 6716 6717 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 6718 6719 // If it is a splat, check if the argument vector is another splat or a 6720 // build_vector with all scalar elements the same. 6721 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 6722 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 6723 SDNode *V = N0.getNode(); 6724 6725 // If this is a bit convert that changes the element type of the vector but 6726 // not the number of vector elements, look through it. Be careful not to 6727 // look though conversions that change things like v4f32 to v2f64. 6728 if (V->getOpcode() == ISD::BITCAST) { 6729 SDValue ConvInput = V->getOperand(0); 6730 if (ConvInput.getValueType().isVector() && 6731 ConvInput.getValueType().getVectorNumElements() == NumElts) 6732 V = ConvInput.getNode(); 6733 } 6734 6735 if (V->getOpcode() == ISD::BUILD_VECTOR) { 6736 assert(V->getNumOperands() == NumElts && 6737 "BUILD_VECTOR has wrong number of operands"); 6738 SDValue Base; 6739 bool AllSame = true; 6740 for (unsigned i = 0; i != NumElts; ++i) { 6741 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 6742 Base = V->getOperand(i); 6743 break; 6744 } 6745 } 6746 // Splat of <u, u, u, u>, return <u, u, u, u> 6747 if (!Base.getNode()) 6748 return N0; 6749 for (unsigned i = 0; i != NumElts; ++i) { 6750 if (V->getOperand(i) != Base) { 6751 AllSame = false; 6752 break; 6753 } 6754 } 6755 // Splat of <x, x, x, x>, return <x, x, x, x> 6756 if (AllSame) 6757 return N0; 6758 } 6759 } 6760 return SDValue(); 6761} 6762 6763SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 6764 if (!TLI.getShouldFoldAtomicFences()) 6765 return SDValue(); 6766 6767 SDValue atomic = N->getOperand(0); 6768 switch (atomic.getOpcode()) { 6769 case ISD::ATOMIC_CMP_SWAP: 6770 case ISD::ATOMIC_SWAP: 6771 case ISD::ATOMIC_LOAD_ADD: 6772 case ISD::ATOMIC_LOAD_SUB: 6773 case ISD::ATOMIC_LOAD_AND: 6774 case ISD::ATOMIC_LOAD_OR: 6775 case ISD::ATOMIC_LOAD_XOR: 6776 case ISD::ATOMIC_LOAD_NAND: 6777 case ISD::ATOMIC_LOAD_MIN: 6778 case ISD::ATOMIC_LOAD_MAX: 6779 case ISD::ATOMIC_LOAD_UMIN: 6780 case ISD::ATOMIC_LOAD_UMAX: 6781 break; 6782 default: 6783 return SDValue(); 6784 } 6785 6786 SDValue fence = atomic.getOperand(0); 6787 if (fence.getOpcode() != ISD::MEMBARRIER) 6788 return SDValue(); 6789 6790 switch (atomic.getOpcode()) { 6791 case ISD::ATOMIC_CMP_SWAP: 6792 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6793 fence.getOperand(0), 6794 atomic.getOperand(1), atomic.getOperand(2), 6795 atomic.getOperand(3)), atomic.getResNo()); 6796 case ISD::ATOMIC_SWAP: 6797 case ISD::ATOMIC_LOAD_ADD: 6798 case ISD::ATOMIC_LOAD_SUB: 6799 case ISD::ATOMIC_LOAD_AND: 6800 case ISD::ATOMIC_LOAD_OR: 6801 case ISD::ATOMIC_LOAD_XOR: 6802 case ISD::ATOMIC_LOAD_NAND: 6803 case ISD::ATOMIC_LOAD_MIN: 6804 case ISD::ATOMIC_LOAD_MAX: 6805 case ISD::ATOMIC_LOAD_UMIN: 6806 case ISD::ATOMIC_LOAD_UMAX: 6807 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6808 fence.getOperand(0), 6809 atomic.getOperand(1), atomic.getOperand(2)), 6810 atomic.getResNo()); 6811 default: 6812 return SDValue(); 6813 } 6814} 6815 6816/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 6817/// an AND to a vector_shuffle with the destination vector and a zero vector. 6818/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 6819/// vector_shuffle V, Zero, <0, 4, 2, 4> 6820SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 6821 EVT VT = N->getValueType(0); 6822 DebugLoc dl = N->getDebugLoc(); 6823 SDValue LHS = N->getOperand(0); 6824 SDValue RHS = N->getOperand(1); 6825 if (N->getOpcode() == ISD::AND) { 6826 if (RHS.getOpcode() == ISD::BITCAST) 6827 RHS = RHS.getOperand(0); 6828 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 6829 SmallVector<int, 8> Indices; 6830 unsigned NumElts = RHS.getNumOperands(); 6831 for (unsigned i = 0; i != NumElts; ++i) { 6832 SDValue Elt = RHS.getOperand(i); 6833 if (!isa<ConstantSDNode>(Elt)) 6834 return SDValue(); 6835 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 6836 Indices.push_back(i); 6837 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 6838 Indices.push_back(NumElts); 6839 else 6840 return SDValue(); 6841 } 6842 6843 // Let's see if the target supports this vector_shuffle. 6844 EVT RVT = RHS.getValueType(); 6845 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 6846 return SDValue(); 6847 6848 // Return the new VECTOR_SHUFFLE node. 6849 EVT EltVT = RVT.getVectorElementType(); 6850 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 6851 DAG.getConstant(0, EltVT)); 6852 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6853 RVT, &ZeroOps[0], ZeroOps.size()); 6854 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 6855 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 6856 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 6857 } 6858 } 6859 6860 return SDValue(); 6861} 6862 6863/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 6864SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 6865 // After legalize, the target may be depending on adds and other 6866 // binary ops to provide legal ways to construct constants or other 6867 // things. Simplifying them may result in a loss of legality. 6868 if (LegalOperations) return SDValue(); 6869 6870 assert(N->getValueType(0).isVector() && 6871 "SimplifyVBinOp only works on vectors!"); 6872 6873 SDValue LHS = N->getOperand(0); 6874 SDValue RHS = N->getOperand(1); 6875 SDValue Shuffle = XformToShuffleWithZero(N); 6876 if (Shuffle.getNode()) return Shuffle; 6877 6878 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 6879 // this operation. 6880 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 6881 RHS.getOpcode() == ISD::BUILD_VECTOR) { 6882 SmallVector<SDValue, 8> Ops; 6883 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 6884 SDValue LHSOp = LHS.getOperand(i); 6885 SDValue RHSOp = RHS.getOperand(i); 6886 // If these two elements can't be folded, bail out. 6887 if ((LHSOp.getOpcode() != ISD::UNDEF && 6888 LHSOp.getOpcode() != ISD::Constant && 6889 LHSOp.getOpcode() != ISD::ConstantFP) || 6890 (RHSOp.getOpcode() != ISD::UNDEF && 6891 RHSOp.getOpcode() != ISD::Constant && 6892 RHSOp.getOpcode() != ISD::ConstantFP)) 6893 break; 6894 6895 // Can't fold divide by zero. 6896 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 6897 N->getOpcode() == ISD::FDIV) { 6898 if ((RHSOp.getOpcode() == ISD::Constant && 6899 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 6900 (RHSOp.getOpcode() == ISD::ConstantFP && 6901 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 6902 break; 6903 } 6904 6905 EVT VT = LHSOp.getValueType(); 6906 assert(RHSOp.getValueType() == VT && 6907 "SimplifyVBinOp with different BUILD_VECTOR element types"); 6908 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 6909 LHSOp, RHSOp); 6910 if (FoldOp.getOpcode() != ISD::UNDEF && 6911 FoldOp.getOpcode() != ISD::Constant && 6912 FoldOp.getOpcode() != ISD::ConstantFP) 6913 break; 6914 Ops.push_back(FoldOp); 6915 AddToWorkList(FoldOp.getNode()); 6916 } 6917 6918 if (Ops.size() == LHS.getNumOperands()) 6919 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6920 LHS.getValueType(), &Ops[0], Ops.size()); 6921 } 6922 6923 return SDValue(); 6924} 6925 6926SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 6927 SDValue N1, SDValue N2){ 6928 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 6929 6930 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 6931 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 6932 6933 // If we got a simplified select_cc node back from SimplifySelectCC, then 6934 // break it down into a new SETCC node, and a new SELECT node, and then return 6935 // the SELECT node, since we were called with a SELECT node. 6936 if (SCC.getNode()) { 6937 // Check to see if we got a select_cc back (to turn into setcc/select). 6938 // Otherwise, just return whatever node we got back, like fabs. 6939 if (SCC.getOpcode() == ISD::SELECT_CC) { 6940 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 6941 N0.getValueType(), 6942 SCC.getOperand(0), SCC.getOperand(1), 6943 SCC.getOperand(4)); 6944 AddToWorkList(SETCC.getNode()); 6945 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 6946 SCC.getOperand(2), SCC.getOperand(3), SETCC); 6947 } 6948 6949 return SCC; 6950 } 6951 return SDValue(); 6952} 6953 6954/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 6955/// are the two values being selected between, see if we can simplify the 6956/// select. Callers of this should assume that TheSelect is deleted if this 6957/// returns true. As such, they should return the appropriate thing (e.g. the 6958/// node) back to the top-level of the DAG combiner loop to avoid it being 6959/// looked at. 6960bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 6961 SDValue RHS) { 6962 6963 // Cannot simplify select with vector condition 6964 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 6965 6966 // If this is a select from two identical things, try to pull the operation 6967 // through the select. 6968 if (LHS.getOpcode() != RHS.getOpcode() || 6969 !LHS.hasOneUse() || !RHS.hasOneUse()) 6970 return false; 6971 6972 // If this is a load and the token chain is identical, replace the select 6973 // of two loads with a load through a select of the address to load from. 6974 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 6975 // constants have been dropped into the constant pool. 6976 if (LHS.getOpcode() == ISD::LOAD) { 6977 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 6978 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 6979 6980 // Token chains must be identical. 6981 if (LHS.getOperand(0) != RHS.getOperand(0) || 6982 // Do not let this transformation reduce the number of volatile loads. 6983 LLD->isVolatile() || RLD->isVolatile() || 6984 // If this is an EXTLOAD, the VT's must match. 6985 LLD->getMemoryVT() != RLD->getMemoryVT() || 6986 // If this is an EXTLOAD, the kind of extension must match. 6987 (LLD->getExtensionType() != RLD->getExtensionType() && 6988 // The only exception is if one of the extensions is anyext. 6989 LLD->getExtensionType() != ISD::EXTLOAD && 6990 RLD->getExtensionType() != ISD::EXTLOAD) || 6991 // FIXME: this discards src value information. This is 6992 // over-conservative. It would be beneficial to be able to remember 6993 // both potential memory locations. Since we are discarding 6994 // src value info, don't do the transformation if the memory 6995 // locations are not in the default address space. 6996 LLD->getPointerInfo().getAddrSpace() != 0 || 6997 RLD->getPointerInfo().getAddrSpace() != 0) 6998 return false; 6999 7000 // Check that the select condition doesn't reach either load. If so, 7001 // folding this will induce a cycle into the DAG. If not, this is safe to 7002 // xform, so create a select of the addresses. 7003 SDValue Addr; 7004 if (TheSelect->getOpcode() == ISD::SELECT) { 7005 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 7006 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 7007 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 7008 return false; 7009 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 7010 LLD->getBasePtr().getValueType(), 7011 TheSelect->getOperand(0), LLD->getBasePtr(), 7012 RLD->getBasePtr()); 7013 } else { // Otherwise SELECT_CC 7014 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 7015 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 7016 7017 if ((LLD->hasAnyUseOfValue(1) && 7018 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 7019 (LLD->hasAnyUseOfValue(1) && 7020 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS)))) 7021 return false; 7022 7023 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 7024 LLD->getBasePtr().getValueType(), 7025 TheSelect->getOperand(0), 7026 TheSelect->getOperand(1), 7027 LLD->getBasePtr(), RLD->getBasePtr(), 7028 TheSelect->getOperand(4)); 7029 } 7030 7031 SDValue Load; 7032 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 7033 Load = DAG.getLoad(TheSelect->getValueType(0), 7034 TheSelect->getDebugLoc(), 7035 // FIXME: Discards pointer info. 7036 LLD->getChain(), Addr, MachinePointerInfo(), 7037 LLD->isVolatile(), LLD->isNonTemporal(), 7038 LLD->getAlignment()); 7039 } else { 7040 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 7041 RLD->getExtensionType() : LLD->getExtensionType(), 7042 TheSelect->getDebugLoc(), 7043 TheSelect->getValueType(0), 7044 // FIXME: Discards pointer info. 7045 LLD->getChain(), Addr, MachinePointerInfo(), 7046 LLD->getMemoryVT(), LLD->isVolatile(), 7047 LLD->isNonTemporal(), LLD->getAlignment()); 7048 } 7049 7050 // Users of the select now use the result of the load. 7051 CombineTo(TheSelect, Load); 7052 7053 // Users of the old loads now use the new load's chain. We know the 7054 // old-load value is dead now. 7055 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 7056 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 7057 return true; 7058 } 7059 7060 return false; 7061} 7062 7063/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 7064/// where 'cond' is the comparison specified by CC. 7065SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 7066 SDValue N2, SDValue N3, 7067 ISD::CondCode CC, bool NotExtCompare) { 7068 // (x ? y : y) -> y. 7069 if (N2 == N3) return N2; 7070 7071 EVT VT = N2.getValueType(); 7072 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 7073 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 7074 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 7075 7076 // Determine if the condition we're dealing with is constant 7077 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 7078 N0, N1, CC, DL, false); 7079 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 7080 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 7081 7082 // fold select_cc true, x, y -> x 7083 if (SCCC && !SCCC->isNullValue()) 7084 return N2; 7085 // fold select_cc false, x, y -> y 7086 if (SCCC && SCCC->isNullValue()) 7087 return N3; 7088 7089 // Check to see if we can simplify the select into an fabs node 7090 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 7091 // Allow either -0.0 or 0.0 7092 if (CFP->getValueAPF().isZero()) { 7093 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 7094 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 7095 N0 == N2 && N3.getOpcode() == ISD::FNEG && 7096 N2 == N3.getOperand(0)) 7097 return DAG.getNode(ISD::FABS, DL, VT, N0); 7098 7099 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 7100 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 7101 N0 == N3 && N2.getOpcode() == ISD::FNEG && 7102 N2.getOperand(0) == N3) 7103 return DAG.getNode(ISD::FABS, DL, VT, N3); 7104 } 7105 } 7106 7107 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 7108 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 7109 // in it. This is a win when the constant is not otherwise available because 7110 // it replaces two constant pool loads with one. We only do this if the FP 7111 // type is known to be legal, because if it isn't, then we are before legalize 7112 // types an we want the other legalization to happen first (e.g. to avoid 7113 // messing with soft float) and if the ConstantFP is not legal, because if 7114 // it is legal, we may not need to store the FP constant in a constant pool. 7115 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 7116 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 7117 if (TLI.isTypeLegal(N2.getValueType()) && 7118 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 7119 TargetLowering::Legal) && 7120 // If both constants have multiple uses, then we won't need to do an 7121 // extra load, they are likely around in registers for other users. 7122 (TV->hasOneUse() || FV->hasOneUse())) { 7123 Constant *Elts[] = { 7124 const_cast<ConstantFP*>(FV->getConstantFPValue()), 7125 const_cast<ConstantFP*>(TV->getConstantFPValue()) 7126 }; 7127 const Type *FPTy = Elts[0]->getType(); 7128 const TargetData &TD = *TLI.getTargetData(); 7129 7130 // Create a ConstantArray of the two constants. 7131 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 7132 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 7133 TD.getPrefTypeAlignment(FPTy)); 7134 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 7135 7136 // Get the offsets to the 0 and 1 element of the array so that we can 7137 // select between them. 7138 SDValue Zero = DAG.getIntPtrConstant(0); 7139 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 7140 SDValue One = DAG.getIntPtrConstant(EltSize); 7141 7142 SDValue Cond = DAG.getSetCC(DL, 7143 TLI.getSetCCResultType(N0.getValueType()), 7144 N0, N1, CC); 7145 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 7146 Cond, One, Zero); 7147 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 7148 CstOffset); 7149 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 7150 MachinePointerInfo::getConstantPool(), false, 7151 false, Alignment); 7152 7153 } 7154 } 7155 7156 // Check to see if we can perform the "gzip trick", transforming 7157 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 7158 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 7159 N0.getValueType().isInteger() && 7160 N2.getValueType().isInteger() && 7161 (N1C->isNullValue() || // (a < 0) ? b : 0 7162 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 7163 EVT XType = N0.getValueType(); 7164 EVT AType = N2.getValueType(); 7165 if (XType.bitsGE(AType)) { 7166 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 7167 // single-bit constant. 7168 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 7169 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 7170 ShCtV = XType.getSizeInBits()-ShCtV-1; 7171 SDValue ShCt = DAG.getConstant(ShCtV, 7172 getShiftAmountTy(N0.getValueType())); 7173 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 7174 XType, N0, ShCt); 7175 AddToWorkList(Shift.getNode()); 7176 7177 if (XType.bitsGT(AType)) { 7178 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 7179 AddToWorkList(Shift.getNode()); 7180 } 7181 7182 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 7183 } 7184 7185 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 7186 XType, N0, 7187 DAG.getConstant(XType.getSizeInBits()-1, 7188 getShiftAmountTy(N0.getValueType()))); 7189 AddToWorkList(Shift.getNode()); 7190 7191 if (XType.bitsGT(AType)) { 7192 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 7193 AddToWorkList(Shift.getNode()); 7194 } 7195 7196 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 7197 } 7198 } 7199 7200 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 7201 // where y is has a single bit set. 7202 // A plaintext description would be, we can turn the SELECT_CC into an AND 7203 // when the condition can be materialized as an all-ones register. Any 7204 // single bit-test can be materialized as an all-ones register with 7205 // shift-left and shift-right-arith. 7206 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 7207 N0->getValueType(0) == VT && 7208 N1C && N1C->isNullValue() && 7209 N2C && N2C->isNullValue()) { 7210 SDValue AndLHS = N0->getOperand(0); 7211 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 7212 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 7213 // Shift the tested bit over the sign bit. 7214 APInt AndMask = ConstAndRHS->getAPIntValue(); 7215 SDValue ShlAmt = 7216 DAG.getConstant(AndMask.countLeadingZeros(), 7217 getShiftAmountTy(AndLHS.getValueType())); 7218 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 7219 7220 // Now arithmetic right shift it all the way over, so the result is either 7221 // all-ones, or zero. 7222 SDValue ShrAmt = 7223 DAG.getConstant(AndMask.getBitWidth()-1, 7224 getShiftAmountTy(Shl.getValueType())); 7225 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 7226 7227 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 7228 } 7229 } 7230 7231 // fold select C, 16, 0 -> shl C, 4 7232 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 7233 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 7234 7235 // If the caller doesn't want us to simplify this into a zext of a compare, 7236 // don't do it. 7237 if (NotExtCompare && N2C->getAPIntValue() == 1) 7238 return SDValue(); 7239 7240 // Get a SetCC of the condition 7241 // FIXME: Should probably make sure that setcc is legal if we ever have a 7242 // target where it isn't. 7243 SDValue Temp, SCC; 7244 // cast from setcc result type to select result type 7245 if (LegalTypes) { 7246 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 7247 N0, N1, CC); 7248 if (N2.getValueType().bitsLT(SCC.getValueType())) 7249 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 7250 else 7251 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7252 N2.getValueType(), SCC); 7253 } else { 7254 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 7255 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7256 N2.getValueType(), SCC); 7257 } 7258 7259 AddToWorkList(SCC.getNode()); 7260 AddToWorkList(Temp.getNode()); 7261 7262 if (N2C->getAPIntValue() == 1) 7263 return Temp; 7264 7265 // shl setcc result by log2 n2c 7266 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 7267 DAG.getConstant(N2C->getAPIntValue().logBase2(), 7268 getShiftAmountTy(Temp.getValueType()))); 7269 } 7270 7271 // Check to see if this is the equivalent of setcc 7272 // FIXME: Turn all of these into setcc if setcc if setcc is legal 7273 // otherwise, go ahead with the folds. 7274 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 7275 EVT XType = N0.getValueType(); 7276 if (!LegalOperations || 7277 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 7278 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 7279 if (Res.getValueType() != VT) 7280 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 7281 return Res; 7282 } 7283 7284 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 7285 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 7286 (!LegalOperations || 7287 TLI.isOperationLegal(ISD::CTLZ, XType))) { 7288 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 7289 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 7290 DAG.getConstant(Log2_32(XType.getSizeInBits()), 7291 getShiftAmountTy(Ctlz.getValueType()))); 7292 } 7293 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 7294 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 7295 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 7296 XType, DAG.getConstant(0, XType), N0); 7297 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 7298 return DAG.getNode(ISD::SRL, DL, XType, 7299 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 7300 DAG.getConstant(XType.getSizeInBits()-1, 7301 getShiftAmountTy(XType))); 7302 } 7303 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 7304 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 7305 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 7306 DAG.getConstant(XType.getSizeInBits()-1, 7307 getShiftAmountTy(N0.getValueType()))); 7308 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 7309 } 7310 } 7311 7312 // Check to see if this is an integer abs. 7313 // select_cc setg[te] X, 0, X, -X -> 7314 // select_cc setgt X, -1, X, -X -> 7315 // select_cc setl[te] X, 0, -X, X -> 7316 // select_cc setlt X, 1, -X, X -> 7317 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 7318 if (N1C) { 7319 ConstantSDNode *SubC = NULL; 7320 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 7321 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 7322 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 7323 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 7324 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 7325 (N1C->isOne() && CC == ISD::SETLT)) && 7326 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 7327 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 7328 7329 EVT XType = N0.getValueType(); 7330 if (SubC && SubC->isNullValue() && XType.isInteger()) { 7331 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 7332 N0, 7333 DAG.getConstant(XType.getSizeInBits()-1, 7334 getShiftAmountTy(N0.getValueType()))); 7335 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 7336 XType, N0, Shift); 7337 AddToWorkList(Shift.getNode()); 7338 AddToWorkList(Add.getNode()); 7339 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 7340 } 7341 } 7342 7343 return SDValue(); 7344} 7345 7346/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 7347SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 7348 SDValue N1, ISD::CondCode Cond, 7349 DebugLoc DL, bool foldBooleans) { 7350 TargetLowering::DAGCombinerInfo 7351 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 7352 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 7353} 7354 7355/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 7356/// return a DAG expression to select that will generate the same value by 7357/// multiplying by a magic number. See: 7358/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7359SDValue DAGCombiner::BuildSDIV(SDNode *N) { 7360 std::vector<SDNode*> Built; 7361 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 7362 7363 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7364 ii != ee; ++ii) 7365 AddToWorkList(*ii); 7366 return S; 7367} 7368 7369/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 7370/// return a DAG expression to select that will generate the same value by 7371/// multiplying by a magic number. See: 7372/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7373SDValue DAGCombiner::BuildUDIV(SDNode *N) { 7374 std::vector<SDNode*> Built; 7375 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 7376 7377 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7378 ii != ee; ++ii) 7379 AddToWorkList(*ii); 7380 return S; 7381} 7382 7383/// FindBaseOffset - Return true if base is a frame index, which is known not 7384// to alias with anything but itself. Provides base object and offset as 7385// results. 7386static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 7387 const GlobalValue *&GV, void *&CV) { 7388 // Assume it is a primitive operation. 7389 Base = Ptr; Offset = 0; GV = 0; CV = 0; 7390 7391 // If it's an adding a simple constant then integrate the offset. 7392 if (Base.getOpcode() == ISD::ADD) { 7393 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 7394 Base = Base.getOperand(0); 7395 Offset += C->getZExtValue(); 7396 } 7397 } 7398 7399 // Return the underlying GlobalValue, and update the Offset. Return false 7400 // for GlobalAddressSDNode since the same GlobalAddress may be represented 7401 // by multiple nodes with different offsets. 7402 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 7403 GV = G->getGlobal(); 7404 Offset += G->getOffset(); 7405 return false; 7406 } 7407 7408 // Return the underlying Constant value, and update the Offset. Return false 7409 // for ConstantSDNodes since the same constant pool entry may be represented 7410 // by multiple nodes with different offsets. 7411 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 7412 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 7413 : (void *)C->getConstVal(); 7414 Offset += C->getOffset(); 7415 return false; 7416 } 7417 // If it's any of the following then it can't alias with anything but itself. 7418 return isa<FrameIndexSDNode>(Base); 7419} 7420 7421/// isAlias - Return true if there is any possibility that the two addresses 7422/// overlap. 7423bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 7424 const Value *SrcValue1, int SrcValueOffset1, 7425 unsigned SrcValueAlign1, 7426 const MDNode *TBAAInfo1, 7427 SDValue Ptr2, int64_t Size2, 7428 const Value *SrcValue2, int SrcValueOffset2, 7429 unsigned SrcValueAlign2, 7430 const MDNode *TBAAInfo2) const { 7431 // If they are the same then they must be aliases. 7432 if (Ptr1 == Ptr2) return true; 7433 7434 // Gather base node and offset information. 7435 SDValue Base1, Base2; 7436 int64_t Offset1, Offset2; 7437 const GlobalValue *GV1, *GV2; 7438 void *CV1, *CV2; 7439 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 7440 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 7441 7442 // If they have a same base address then check to see if they overlap. 7443 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 7444 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7445 7446 // It is possible for different frame indices to alias each other, mostly 7447 // when tail call optimization reuses return address slots for arguments. 7448 // To catch this case, look up the actual index of frame indices to compute 7449 // the real alias relationship. 7450 if (isFrameIndex1 && isFrameIndex2) { 7451 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7452 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 7453 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 7454 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7455 } 7456 7457 // Otherwise, if we know what the bases are, and they aren't identical, then 7458 // we know they cannot alias. 7459 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 7460 return false; 7461 7462 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 7463 // compared to the size and offset of the access, we may be able to prove they 7464 // do not alias. This check is conservative for now to catch cases created by 7465 // splitting vector types. 7466 if ((SrcValueAlign1 == SrcValueAlign2) && 7467 (SrcValueOffset1 != SrcValueOffset2) && 7468 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 7469 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 7470 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 7471 7472 // There is no overlap between these relatively aligned accesses of similar 7473 // size, return no alias. 7474 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 7475 return false; 7476 } 7477 7478 if (CombinerGlobalAA) { 7479 // Use alias analysis information. 7480 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 7481 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 7482 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 7483 AliasAnalysis::AliasResult AAResult = 7484 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 7485 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 7486 if (AAResult == AliasAnalysis::NoAlias) 7487 return false; 7488 } 7489 7490 // Otherwise we have to assume they alias. 7491 return true; 7492} 7493 7494/// FindAliasInfo - Extracts the relevant alias information from the memory 7495/// node. Returns true if the operand was a load. 7496bool DAGCombiner::FindAliasInfo(SDNode *N, 7497 SDValue &Ptr, int64_t &Size, 7498 const Value *&SrcValue, 7499 int &SrcValueOffset, 7500 unsigned &SrcValueAlign, 7501 const MDNode *&TBAAInfo) const { 7502 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7503 Ptr = LD->getBasePtr(); 7504 Size = LD->getMemoryVT().getSizeInBits() >> 3; 7505 SrcValue = LD->getSrcValue(); 7506 SrcValueOffset = LD->getSrcValueOffset(); 7507 SrcValueAlign = LD->getOriginalAlignment(); 7508 TBAAInfo = LD->getTBAAInfo(); 7509 return true; 7510 } 7511 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7512 Ptr = ST->getBasePtr(); 7513 Size = ST->getMemoryVT().getSizeInBits() >> 3; 7514 SrcValue = ST->getSrcValue(); 7515 SrcValueOffset = ST->getSrcValueOffset(); 7516 SrcValueAlign = ST->getOriginalAlignment(); 7517 TBAAInfo = ST->getTBAAInfo(); 7518 return false; 7519 } 7520 llvm_unreachable("FindAliasInfo expected a memory operand"); 7521} 7522 7523/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 7524/// looking for aliasing nodes and adding them to the Aliases vector. 7525void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 7526 SmallVector<SDValue, 8> &Aliases) { 7527 SmallVector<SDValue, 8> Chains; // List of chains to visit. 7528 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 7529 7530 // Get alias information for node. 7531 SDValue Ptr; 7532 int64_t Size; 7533 const Value *SrcValue; 7534 int SrcValueOffset; 7535 unsigned SrcValueAlign; 7536 const MDNode *SrcTBAAInfo; 7537 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 7538 SrcValueAlign, SrcTBAAInfo); 7539 7540 // Starting off. 7541 Chains.push_back(OriginalChain); 7542 unsigned Depth = 0; 7543 7544 // Look at each chain and determine if it is an alias. If so, add it to the 7545 // aliases list. If not, then continue up the chain looking for the next 7546 // candidate. 7547 while (!Chains.empty()) { 7548 SDValue Chain = Chains.back(); 7549 Chains.pop_back(); 7550 7551 // For TokenFactor nodes, look at each operand and only continue up the 7552 // chain until we find two aliases. If we've seen two aliases, assume we'll 7553 // find more and revert to original chain since the xform is unlikely to be 7554 // profitable. 7555 // 7556 // FIXME: The depth check could be made to return the last non-aliasing 7557 // chain we found before we hit a tokenfactor rather than the original 7558 // chain. 7559 if (Depth > 6 || Aliases.size() == 2) { 7560 Aliases.clear(); 7561 Aliases.push_back(OriginalChain); 7562 break; 7563 } 7564 7565 // Don't bother if we've been before. 7566 if (!Visited.insert(Chain.getNode())) 7567 continue; 7568 7569 switch (Chain.getOpcode()) { 7570 case ISD::EntryToken: 7571 // Entry token is ideal chain operand, but handled in FindBetterChain. 7572 break; 7573 7574 case ISD::LOAD: 7575 case ISD::STORE: { 7576 // Get alias information for Chain. 7577 SDValue OpPtr; 7578 int64_t OpSize; 7579 const Value *OpSrcValue; 7580 int OpSrcValueOffset; 7581 unsigned OpSrcValueAlign; 7582 const MDNode *OpSrcTBAAInfo; 7583 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 7584 OpSrcValue, OpSrcValueOffset, 7585 OpSrcValueAlign, 7586 OpSrcTBAAInfo); 7587 7588 // If chain is alias then stop here. 7589 if (!(IsLoad && IsOpLoad) && 7590 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 7591 SrcTBAAInfo, 7592 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 7593 OpSrcValueAlign, OpSrcTBAAInfo)) { 7594 Aliases.push_back(Chain); 7595 } else { 7596 // Look further up the chain. 7597 Chains.push_back(Chain.getOperand(0)); 7598 ++Depth; 7599 } 7600 break; 7601 } 7602 7603 case ISD::TokenFactor: 7604 // We have to check each of the operands of the token factor for "small" 7605 // token factors, so we queue them up. Adding the operands to the queue 7606 // (stack) in reverse order maintains the original order and increases the 7607 // likelihood that getNode will find a matching token factor (CSE.) 7608 if (Chain.getNumOperands() > 16) { 7609 Aliases.push_back(Chain); 7610 break; 7611 } 7612 for (unsigned n = Chain.getNumOperands(); n;) 7613 Chains.push_back(Chain.getOperand(--n)); 7614 ++Depth; 7615 break; 7616 7617 default: 7618 // For all other instructions we will just have to take what we can get. 7619 Aliases.push_back(Chain); 7620 break; 7621 } 7622 } 7623} 7624 7625/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 7626/// for a better chain (aliasing node.) 7627SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 7628 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 7629 7630 // Accumulate all the aliases to this node. 7631 GatherAllAliases(N, OldChain, Aliases); 7632 7633 // If no operands then chain to entry token. 7634 if (Aliases.size() == 0) 7635 return DAG.getEntryNode(); 7636 7637 // If a single operand then chain to it. We don't need to revisit it. 7638 if (Aliases.size() == 1) 7639 return Aliases[0]; 7640 7641 // Construct a custom tailored token factor. 7642 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7643 &Aliases[0], Aliases.size()); 7644} 7645 7646// SelectionDAG::Combine - This is the entry point for the file. 7647// 7648void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 7649 CodeGenOpt::Level OptLevel) { 7650 /// run - This is the main entry point to this class. 7651 /// 7652 DAGCombiner(*this, AA, OptLevel).Run(Level); 7653} 7654