DAGCombiner.cpp revision 83060c544bde0e2e9798829516040c76c5dd5013
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: divide by zero is currently left unfolded. do we want to turn this 26// into an undef? 27// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "dagcombine" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/Analysis/AliasAnalysis.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Target/TargetLowering.h" 38#include "llvm/Target/TargetOptions.h" 39#include "llvm/Support/Compiler.h" 40#include "llvm/Support/CommandLine.h" 41#include <algorithm> 42using namespace llvm; 43 44STATISTIC(NodesCombined , "Number of dag nodes combined"); 45STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 46STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 47 48namespace { 49#ifndef NDEBUG 50 static cl::opt<bool> 51 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 52 cl::desc("Pop up a window to show dags before the first " 53 "dag combine pass")); 54 static cl::opt<bool> 55 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 56 cl::desc("Pop up a window to show dags before the second " 57 "dag combine pass")); 58#else 59 static const bool ViewDAGCombine1 = false; 60 static const bool ViewDAGCombine2 = false; 61#endif 62 63 static cl::opt<bool> 64 CombinerAA("combiner-alias-analysis", cl::Hidden, 65 cl::desc("Turn on alias analysis during testing")); 66 67 static cl::opt<bool> 68 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 69 cl::desc("Include global information in alias analysis")); 70 71//------------------------------ DAGCombiner ---------------------------------// 72 73 class VISIBILITY_HIDDEN DAGCombiner { 74 SelectionDAG &DAG; 75 TargetLowering &TLI; 76 bool AfterLegalize; 77 78 // Worklist of all of the nodes that need to be simplified. 79 std::vector<SDNode*> WorkList; 80 81 // AA - Used for DAG load/store alias analysis. 82 AliasAnalysis &AA; 83 84 /// AddUsersToWorkList - When an instruction is simplified, add all users of 85 /// the instruction to the work lists because they might get more simplified 86 /// now. 87 /// 88 void AddUsersToWorkList(SDNode *N) { 89 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 90 UI != UE; ++UI) 91 AddToWorkList(*UI); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 public: 102 /// AddToWorkList - Add to the work list making sure it's instance is at the 103 /// the back (next to be processed.) 104 void AddToWorkList(SDNode *N) { 105 removeFromWorkList(N); 106 WorkList.push_back(N); 107 } 108 109 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 110 bool AddTo = true) { 111 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 112 ++NodesCombined; 113 DOUT << "\nReplacing.1 "; DEBUG(N->dump()); 114 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 115 DOUT << " and " << NumTo-1 << " other values\n"; 116 std::vector<SDNode*> NowDead; 117 DAG.ReplaceAllUsesWith(N, To, &NowDead); 118 119 if (AddTo) { 120 // Push the new nodes and any users onto the worklist 121 for (unsigned i = 0, e = NumTo; i != e; ++i) { 122 AddToWorkList(To[i].Val); 123 AddUsersToWorkList(To[i].Val); 124 } 125 } 126 127 // Nodes can be reintroduced into the worklist. Make sure we do not 128 // process a node that has been replaced. 129 removeFromWorkList(N); 130 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 131 removeFromWorkList(NowDead[i]); 132 133 // Finally, since the node is now dead, remove it from the graph. 134 DAG.DeleteNode(N); 135 return SDOperand(N, 0); 136 } 137 138 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 139 return CombineTo(N, &Res, 1, AddTo); 140 } 141 142 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 143 bool AddTo = true) { 144 SDOperand To[] = { Res0, Res1 }; 145 return CombineTo(N, To, 2, AddTo); 146 } 147 private: 148 149 /// SimplifyDemandedBits - Check the specified integer node value to see if 150 /// it can be simplified or if things it uses can be simplified by bit 151 /// propagation. If so, return true. 152 bool SimplifyDemandedBits(SDOperand Op) { 153 TargetLowering::TargetLoweringOpt TLO(DAG); 154 uint64_t KnownZero, KnownOne; 155 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 156 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 157 return false; 158 159 // Revisit the node. 160 AddToWorkList(Op.Val); 161 162 // Replace the old value with the new one. 163 ++NodesCombined; 164 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump()); 165 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 166 DOUT << '\n'; 167 168 std::vector<SDNode*> NowDead; 169 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 170 171 // Push the new node and any (possibly new) users onto the worklist. 172 AddToWorkList(TLO.New.Val); 173 AddUsersToWorkList(TLO.New.Val); 174 175 // Nodes can end up on the worklist more than once. Make sure we do 176 // not process a node that has been replaced. 177 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 178 removeFromWorkList(NowDead[i]); 179 180 // Finally, if the node is now dead, remove it from the graph. The node 181 // may not be dead if the replacement process recursively simplified to 182 // something else needing this node. 183 if (TLO.Old.Val->use_empty()) { 184 removeFromWorkList(TLO.Old.Val); 185 DAG.DeleteNode(TLO.Old.Val); 186 } 187 return true; 188 } 189 190 bool CombineToPreIndexedLoadStore(SDNode *N); 191 bool CombineToPostIndexedLoadStore(SDNode *N); 192 193 194 /// visit - call the node-specific routine that knows how to fold each 195 /// particular type of node. 196 SDOperand visit(SDNode *N); 197 198 // Visitation implementation - Implement dag node combining for different 199 // node types. The semantics are as follows: 200 // Return Value: 201 // SDOperand.Val == 0 - No change was made 202 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 203 // otherwise - N should be replaced by the returned Operand. 204 // 205 SDOperand visitTokenFactor(SDNode *N); 206 SDOperand visitADD(SDNode *N); 207 SDOperand visitSUB(SDNode *N); 208 SDOperand visitADDC(SDNode *N); 209 SDOperand visitADDE(SDNode *N); 210 SDOperand visitMUL(SDNode *N); 211 SDOperand visitSDIV(SDNode *N); 212 SDOperand visitUDIV(SDNode *N); 213 SDOperand visitSREM(SDNode *N); 214 SDOperand visitUREM(SDNode *N); 215 SDOperand visitMULHU(SDNode *N); 216 SDOperand visitMULHS(SDNode *N); 217 SDOperand visitAND(SDNode *N); 218 SDOperand visitOR(SDNode *N); 219 SDOperand visitXOR(SDNode *N); 220 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp); 221 SDOperand visitSHL(SDNode *N); 222 SDOperand visitSRA(SDNode *N); 223 SDOperand visitSRL(SDNode *N); 224 SDOperand visitCTLZ(SDNode *N); 225 SDOperand visitCTTZ(SDNode *N); 226 SDOperand visitCTPOP(SDNode *N); 227 SDOperand visitSELECT(SDNode *N); 228 SDOperand visitSELECT_CC(SDNode *N); 229 SDOperand visitSETCC(SDNode *N); 230 SDOperand visitSIGN_EXTEND(SDNode *N); 231 SDOperand visitZERO_EXTEND(SDNode *N); 232 SDOperand visitANY_EXTEND(SDNode *N); 233 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 234 SDOperand visitTRUNCATE(SDNode *N); 235 SDOperand visitBIT_CONVERT(SDNode *N); 236 SDOperand visitVBIT_CONVERT(SDNode *N); 237 SDOperand visitFADD(SDNode *N); 238 SDOperand visitFSUB(SDNode *N); 239 SDOperand visitFMUL(SDNode *N); 240 SDOperand visitFDIV(SDNode *N); 241 SDOperand visitFREM(SDNode *N); 242 SDOperand visitFCOPYSIGN(SDNode *N); 243 SDOperand visitSINT_TO_FP(SDNode *N); 244 SDOperand visitUINT_TO_FP(SDNode *N); 245 SDOperand visitFP_TO_SINT(SDNode *N); 246 SDOperand visitFP_TO_UINT(SDNode *N); 247 SDOperand visitFP_ROUND(SDNode *N); 248 SDOperand visitFP_ROUND_INREG(SDNode *N); 249 SDOperand visitFP_EXTEND(SDNode *N); 250 SDOperand visitFNEG(SDNode *N); 251 SDOperand visitFABS(SDNode *N); 252 SDOperand visitBRCOND(SDNode *N); 253 SDOperand visitBR_CC(SDNode *N); 254 SDOperand visitLOAD(SDNode *N); 255 SDOperand visitSTORE(SDNode *N); 256 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 257 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N); 258 SDOperand visitVBUILD_VECTOR(SDNode *N); 259 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 260 SDOperand visitVVECTOR_SHUFFLE(SDNode *N); 261 262 SDOperand XformToShuffleWithZero(SDNode *N); 263 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 264 265 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 266 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 267 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 268 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 269 SDOperand N3, ISD::CondCode CC); 270 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 271 ISD::CondCode Cond, bool foldBooleans = true); 272 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType); 273 SDOperand BuildSDIV(SDNode *N); 274 SDOperand BuildUDIV(SDNode *N); 275 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 276 277 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 278 /// looking for aliasing nodes and adding them to the Aliases vector. 279 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 280 SmallVector<SDOperand, 8> &Aliases); 281 282 /// isAlias - Return true if there is any possibility that the two addresses 283 /// overlap. 284 bool isAlias(SDOperand Ptr1, int64_t Size1, 285 const Value *SrcValue1, int SrcValueOffset1, 286 SDOperand Ptr2, int64_t Size2, 287 const Value *SrcValue2, int SrcValueOffset2); 288 289 /// FindAliasInfo - Extracts the relevant alias information from the memory 290 /// node. Returns true if the operand was a load. 291 bool FindAliasInfo(SDNode *N, 292 SDOperand &Ptr, int64_t &Size, 293 const Value *&SrcValue, int &SrcValueOffset); 294 295 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 296 /// looking for a better chain (aliasing node.) 297 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 298 299public: 300 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 301 : DAG(D), 302 TLI(D.getTargetLoweringInfo()), 303 AfterLegalize(false), 304 AA(A) {} 305 306 /// Run - runs the dag combiner on all nodes in the work list 307 void Run(bool RunningAfterLegalize); 308 }; 309} 310 311//===----------------------------------------------------------------------===// 312// TargetLowering::DAGCombinerInfo implementation 313//===----------------------------------------------------------------------===// 314 315void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 316 ((DAGCombiner*)DC)->AddToWorkList(N); 317} 318 319SDOperand TargetLowering::DAGCombinerInfo:: 320CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 321 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 322} 323 324SDOperand TargetLowering::DAGCombinerInfo:: 325CombineTo(SDNode *N, SDOperand Res) { 326 return ((DAGCombiner*)DC)->CombineTo(N, Res); 327} 328 329 330SDOperand TargetLowering::DAGCombinerInfo:: 331CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 332 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 333} 334 335 336 337 338//===----------------------------------------------------------------------===// 339 340 341// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 342// that selects between the values 1 and 0, making it equivalent to a setcc. 343// Also, set the incoming LHS, RHS, and CC references to the appropriate 344// nodes based on the type of node we are checking. This simplifies life a 345// bit for the callers. 346static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 347 SDOperand &CC) { 348 if (N.getOpcode() == ISD::SETCC) { 349 LHS = N.getOperand(0); 350 RHS = N.getOperand(1); 351 CC = N.getOperand(2); 352 return true; 353 } 354 if (N.getOpcode() == ISD::SELECT_CC && 355 N.getOperand(2).getOpcode() == ISD::Constant && 356 N.getOperand(3).getOpcode() == ISD::Constant && 357 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 358 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 359 LHS = N.getOperand(0); 360 RHS = N.getOperand(1); 361 CC = N.getOperand(4); 362 return true; 363 } 364 return false; 365} 366 367// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 368// one use. If this is true, it allows the users to invert the operation for 369// free when it is profitable to do so. 370static bool isOneUseSetCC(SDOperand N) { 371 SDOperand N0, N1, N2; 372 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 373 return true; 374 return false; 375} 376 377SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 378 MVT::ValueType VT = N0.getValueType(); 379 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 380 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 381 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 382 if (isa<ConstantSDNode>(N1)) { 383 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 384 AddToWorkList(OpNode.Val); 385 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 386 } else if (N0.hasOneUse()) { 387 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 388 AddToWorkList(OpNode.Val); 389 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 390 } 391 } 392 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 393 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 394 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 395 if (isa<ConstantSDNode>(N0)) { 396 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 397 AddToWorkList(OpNode.Val); 398 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 399 } else if (N1.hasOneUse()) { 400 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 401 AddToWorkList(OpNode.Val); 402 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 403 } 404 } 405 return SDOperand(); 406} 407 408void DAGCombiner::Run(bool RunningAfterLegalize) { 409 // set the instance variable, so that the various visit routines may use it. 410 AfterLegalize = RunningAfterLegalize; 411 412 // Add all the dag nodes to the worklist. 413 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 414 E = DAG.allnodes_end(); I != E; ++I) 415 WorkList.push_back(I); 416 417 // Create a dummy node (which is not added to allnodes), that adds a reference 418 // to the root node, preventing it from being deleted, and tracking any 419 // changes of the root. 420 HandleSDNode Dummy(DAG.getRoot()); 421 422 // The root of the dag may dangle to deleted nodes until the dag combiner is 423 // done. Set it to null to avoid confusion. 424 DAG.setRoot(SDOperand()); 425 426 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 427 TargetLowering::DAGCombinerInfo 428 DagCombineInfo(DAG, !RunningAfterLegalize, false, this); 429 430 // while the worklist isn't empty, inspect the node on the end of it and 431 // try and combine it. 432 while (!WorkList.empty()) { 433 SDNode *N = WorkList.back(); 434 WorkList.pop_back(); 435 436 // If N has no uses, it is dead. Make sure to revisit all N's operands once 437 // N is deleted from the DAG, since they too may now be dead or may have a 438 // reduced number of uses, allowing other xforms. 439 if (N->use_empty() && N != &Dummy) { 440 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 441 AddToWorkList(N->getOperand(i).Val); 442 443 DAG.DeleteNode(N); 444 continue; 445 } 446 447 SDOperand RV = visit(N); 448 449 // If nothing happened, try a target-specific DAG combine. 450 if (RV.Val == 0) { 451 assert(N->getOpcode() != ISD::DELETED_NODE && 452 "Node was deleted but visit returned NULL!"); 453 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 454 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 455 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 456 } 457 458 if (RV.Val) { 459 ++NodesCombined; 460 // If we get back the same node we passed in, rather than a new node or 461 // zero, we know that the node must have defined multiple values and 462 // CombineTo was used. Since CombineTo takes care of the worklist 463 // mechanics for us, we have no work to do in this case. 464 if (RV.Val != N) { 465 assert(N->getOpcode() != ISD::DELETED_NODE && 466 RV.Val->getOpcode() != ISD::DELETED_NODE && 467 "Node was deleted but visit returned new node!"); 468 469 DOUT << "\nReplacing.3 "; DEBUG(N->dump()); 470 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 471 DOUT << '\n'; 472 std::vector<SDNode*> NowDead; 473 if (N->getNumValues() == RV.Val->getNumValues()) 474 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead); 475 else { 476 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch"); 477 SDOperand OpV = RV; 478 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 479 } 480 481 // Push the new node and any users onto the worklist 482 AddToWorkList(RV.Val); 483 AddUsersToWorkList(RV.Val); 484 485 // Nodes can be reintroduced into the worklist. Make sure we do not 486 // process a node that has been replaced. 487 removeFromWorkList(N); 488 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 489 removeFromWorkList(NowDead[i]); 490 491 // Finally, since the node is now dead, remove it from the graph. 492 DAG.DeleteNode(N); 493 } 494 } 495 } 496 497 // If the root changed (e.g. it was a dead load, update the root). 498 DAG.setRoot(Dummy.getValue()); 499} 500 501SDOperand DAGCombiner::visit(SDNode *N) { 502 switch(N->getOpcode()) { 503 default: break; 504 case ISD::TokenFactor: return visitTokenFactor(N); 505 case ISD::ADD: return visitADD(N); 506 case ISD::SUB: return visitSUB(N); 507 case ISD::ADDC: return visitADDC(N); 508 case ISD::ADDE: return visitADDE(N); 509 case ISD::MUL: return visitMUL(N); 510 case ISD::SDIV: return visitSDIV(N); 511 case ISD::UDIV: return visitUDIV(N); 512 case ISD::SREM: return visitSREM(N); 513 case ISD::UREM: return visitUREM(N); 514 case ISD::MULHU: return visitMULHU(N); 515 case ISD::MULHS: return visitMULHS(N); 516 case ISD::AND: return visitAND(N); 517 case ISD::OR: return visitOR(N); 518 case ISD::XOR: return visitXOR(N); 519 case ISD::SHL: return visitSHL(N); 520 case ISD::SRA: return visitSRA(N); 521 case ISD::SRL: return visitSRL(N); 522 case ISD::CTLZ: return visitCTLZ(N); 523 case ISD::CTTZ: return visitCTTZ(N); 524 case ISD::CTPOP: return visitCTPOP(N); 525 case ISD::SELECT: return visitSELECT(N); 526 case ISD::SELECT_CC: return visitSELECT_CC(N); 527 case ISD::SETCC: return visitSETCC(N); 528 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 529 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 530 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 531 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 532 case ISD::TRUNCATE: return visitTRUNCATE(N); 533 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 534 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N); 535 case ISD::FADD: return visitFADD(N); 536 case ISD::FSUB: return visitFSUB(N); 537 case ISD::FMUL: return visitFMUL(N); 538 case ISD::FDIV: return visitFDIV(N); 539 case ISD::FREM: return visitFREM(N); 540 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 541 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 542 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 543 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 544 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 545 case ISD::FP_ROUND: return visitFP_ROUND(N); 546 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 547 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 548 case ISD::FNEG: return visitFNEG(N); 549 case ISD::FABS: return visitFABS(N); 550 case ISD::BRCOND: return visitBRCOND(N); 551 case ISD::BR_CC: return visitBR_CC(N); 552 case ISD::LOAD: return visitLOAD(N); 553 case ISD::STORE: return visitSTORE(N); 554 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 555 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N); 556 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N); 557 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 558 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N); 559 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD); 560 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB); 561 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL); 562 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV); 563 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV); 564 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND); 565 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR); 566 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR); 567 } 568 return SDOperand(); 569} 570 571/// getInputChainForNode - Given a node, return its input chain if it has one, 572/// otherwise return a null sd operand. 573static SDOperand getInputChainForNode(SDNode *N) { 574 if (unsigned NumOps = N->getNumOperands()) { 575 if (N->getOperand(0).getValueType() == MVT::Other) 576 return N->getOperand(0); 577 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 578 return N->getOperand(NumOps-1); 579 for (unsigned i = 1; i < NumOps-1; ++i) 580 if (N->getOperand(i).getValueType() == MVT::Other) 581 return N->getOperand(i); 582 } 583 return SDOperand(0, 0); 584} 585 586SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 587 // If N has two operands, where one has an input chain equal to the other, 588 // the 'other' chain is redundant. 589 if (N->getNumOperands() == 2) { 590 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 591 return N->getOperand(0); 592 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 593 return N->getOperand(1); 594 } 595 596 597 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 598 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 599 bool Changed = false; // If we should replace this token factor. 600 601 // Start out with this token factor. 602 TFs.push_back(N); 603 604 // Iterate through token factors. The TFs grows when new token factors are 605 // encountered. 606 for (unsigned i = 0; i < TFs.size(); ++i) { 607 SDNode *TF = TFs[i]; 608 609 // Check each of the operands. 610 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 611 SDOperand Op = TF->getOperand(i); 612 613 switch (Op.getOpcode()) { 614 case ISD::EntryToken: 615 // Entry tokens don't need to be added to the list. They are 616 // rededundant. 617 Changed = true; 618 break; 619 620 case ISD::TokenFactor: 621 if ((CombinerAA || Op.hasOneUse()) && 622 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 623 // Queue up for processing. 624 TFs.push_back(Op.Val); 625 // Clean up in case the token factor is removed. 626 AddToWorkList(Op.Val); 627 Changed = true; 628 break; 629 } 630 // Fall thru 631 632 default: 633 // Only add if not there prior. 634 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end()) 635 Ops.push_back(Op); 636 break; 637 } 638 } 639 } 640 641 SDOperand Result; 642 643 // If we've change things around then replace token factor. 644 if (Changed) { 645 if (Ops.size() == 0) { 646 // The entry token is the only possible outcome. 647 Result = DAG.getEntryNode(); 648 } else { 649 // New and improved token factor. 650 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 651 } 652 653 // Don't add users to work list. 654 return CombineTo(N, Result, false); 655 } 656 657 return Result; 658} 659 660static 661SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 662 MVT::ValueType VT = N0.getValueType(); 663 SDOperand N00 = N0.getOperand(0); 664 SDOperand N01 = N0.getOperand(1); 665 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 666 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 667 isa<ConstantSDNode>(N00.getOperand(1))) { 668 N0 = DAG.getNode(ISD::ADD, VT, 669 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 670 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 671 return DAG.getNode(ISD::ADD, VT, N0, N1); 672 } 673 return SDOperand(); 674} 675 676SDOperand DAGCombiner::visitADD(SDNode *N) { 677 SDOperand N0 = N->getOperand(0); 678 SDOperand N1 = N->getOperand(1); 679 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 680 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 681 MVT::ValueType VT = N0.getValueType(); 682 683 // fold (add c1, c2) -> c1+c2 684 if (N0C && N1C) 685 return DAG.getNode(ISD::ADD, VT, N0, N1); 686 // canonicalize constant to RHS 687 if (N0C && !N1C) 688 return DAG.getNode(ISD::ADD, VT, N1, N0); 689 // fold (add x, 0) -> x 690 if (N1C && N1C->isNullValue()) 691 return N0; 692 // fold ((c1-A)+c2) -> (c1+c2)-A 693 if (N1C && N0.getOpcode() == ISD::SUB) 694 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 695 return DAG.getNode(ISD::SUB, VT, 696 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 697 N0.getOperand(1)); 698 // reassociate add 699 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 700 if (RADD.Val != 0) 701 return RADD; 702 // fold ((0-A) + B) -> B-A 703 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 704 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 705 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 706 // fold (A + (0-B)) -> A-B 707 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 708 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 709 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 710 // fold (A+(B-A)) -> B 711 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 712 return N1.getOperand(0); 713 714 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 715 return SDOperand(N, 0); 716 717 // fold (a+b) -> (a|b) iff a and b share no bits. 718 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 719 uint64_t LHSZero, LHSOne; 720 uint64_t RHSZero, RHSOne; 721 uint64_t Mask = MVT::getIntVTBitMask(VT); 722 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 723 if (LHSZero) { 724 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 725 726 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 727 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 728 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 729 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 730 return DAG.getNode(ISD::OR, VT, N0, N1); 731 } 732 } 733 734 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 735 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 736 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 737 if (Result.Val) return Result; 738 } 739 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 740 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 741 if (Result.Val) return Result; 742 } 743 744 return SDOperand(); 745} 746 747SDOperand DAGCombiner::visitADDC(SDNode *N) { 748 SDOperand N0 = N->getOperand(0); 749 SDOperand N1 = N->getOperand(1); 750 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 751 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 752 MVT::ValueType VT = N0.getValueType(); 753 754 // If the flag result is dead, turn this into an ADD. 755 if (N->hasNUsesOfValue(0, 1)) 756 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 757 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 758 759 // canonicalize constant to RHS. 760 if (N0C && !N1C) { 761 SDOperand Ops[] = { N1, N0 }; 762 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 763 } 764 765 // fold (addc x, 0) -> x + no carry out 766 if (N1C && N1C->isNullValue()) 767 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 768 769 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 770 uint64_t LHSZero, LHSOne; 771 uint64_t RHSZero, RHSOne; 772 uint64_t Mask = MVT::getIntVTBitMask(VT); 773 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 774 if (LHSZero) { 775 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 776 777 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 778 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 779 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 780 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 781 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 782 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 783 } 784 785 return SDOperand(); 786} 787 788SDOperand DAGCombiner::visitADDE(SDNode *N) { 789 SDOperand N0 = N->getOperand(0); 790 SDOperand N1 = N->getOperand(1); 791 SDOperand CarryIn = N->getOperand(2); 792 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 793 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 794 //MVT::ValueType VT = N0.getValueType(); 795 796 // canonicalize constant to RHS 797 if (N0C && !N1C) { 798 SDOperand Ops[] = { N1, N0, CarryIn }; 799 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 800 } 801 802 // fold (adde x, y, false) -> (addc x, y) 803 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 804 SDOperand Ops[] = { N1, N0 }; 805 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 806 } 807 808 return SDOperand(); 809} 810 811 812 813SDOperand DAGCombiner::visitSUB(SDNode *N) { 814 SDOperand N0 = N->getOperand(0); 815 SDOperand N1 = N->getOperand(1); 816 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 817 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 818 MVT::ValueType VT = N0.getValueType(); 819 820 // fold (sub x, x) -> 0 821 if (N0 == N1) 822 return DAG.getConstant(0, N->getValueType(0)); 823 // fold (sub c1, c2) -> c1-c2 824 if (N0C && N1C) 825 return DAG.getNode(ISD::SUB, VT, N0, N1); 826 // fold (sub x, c) -> (add x, -c) 827 if (N1C) 828 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 829 // fold (A+B)-A -> B 830 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 831 return N0.getOperand(1); 832 // fold (A+B)-B -> A 833 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 834 return N0.getOperand(0); 835 return SDOperand(); 836} 837 838SDOperand DAGCombiner::visitMUL(SDNode *N) { 839 SDOperand N0 = N->getOperand(0); 840 SDOperand N1 = N->getOperand(1); 841 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 842 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 843 MVT::ValueType VT = N0.getValueType(); 844 845 // fold (mul c1, c2) -> c1*c2 846 if (N0C && N1C) 847 return DAG.getNode(ISD::MUL, VT, N0, N1); 848 // canonicalize constant to RHS 849 if (N0C && !N1C) 850 return DAG.getNode(ISD::MUL, VT, N1, N0); 851 // fold (mul x, 0) -> 0 852 if (N1C && N1C->isNullValue()) 853 return N1; 854 // fold (mul x, -1) -> 0-x 855 if (N1C && N1C->isAllOnesValue()) 856 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 857 // fold (mul x, (1 << c)) -> x << c 858 if (N1C && isPowerOf2_64(N1C->getValue())) 859 return DAG.getNode(ISD::SHL, VT, N0, 860 DAG.getConstant(Log2_64(N1C->getValue()), 861 TLI.getShiftAmountTy())); 862 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 863 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 864 // FIXME: If the input is something that is easily negated (e.g. a 865 // single-use add), we should put the negate there. 866 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 867 DAG.getNode(ISD::SHL, VT, N0, 868 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 869 TLI.getShiftAmountTy()))); 870 } 871 872 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 873 if (N1C && N0.getOpcode() == ISD::SHL && 874 isa<ConstantSDNode>(N0.getOperand(1))) { 875 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 876 AddToWorkList(C3.Val); 877 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 878 } 879 880 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 881 // use. 882 { 883 SDOperand Sh(0,0), Y(0,0); 884 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 885 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 886 N0.Val->hasOneUse()) { 887 Sh = N0; Y = N1; 888 } else if (N1.getOpcode() == ISD::SHL && 889 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 890 Sh = N1; Y = N0; 891 } 892 if (Sh.Val) { 893 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 894 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 895 } 896 } 897 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 898 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 899 isa<ConstantSDNode>(N0.getOperand(1))) { 900 return DAG.getNode(ISD::ADD, VT, 901 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 902 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 903 } 904 905 // reassociate mul 906 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 907 if (RMUL.Val != 0) 908 return RMUL; 909 return SDOperand(); 910} 911 912SDOperand DAGCombiner::visitSDIV(SDNode *N) { 913 SDOperand N0 = N->getOperand(0); 914 SDOperand N1 = N->getOperand(1); 915 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 916 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 917 MVT::ValueType VT = N->getValueType(0); 918 919 // fold (sdiv c1, c2) -> c1/c2 920 if (N0C && N1C && !N1C->isNullValue()) 921 return DAG.getNode(ISD::SDIV, VT, N0, N1); 922 // fold (sdiv X, 1) -> X 923 if (N1C && N1C->getSignExtended() == 1LL) 924 return N0; 925 // fold (sdiv X, -1) -> 0-X 926 if (N1C && N1C->isAllOnesValue()) 927 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 928 // If we know the sign bits of both operands are zero, strength reduce to a 929 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 930 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 931 if (TLI.MaskedValueIsZero(N1, SignBit) && 932 TLI.MaskedValueIsZero(N0, SignBit)) 933 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 934 // fold (sdiv X, pow2) -> simple ops after legalize 935 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 936 (isPowerOf2_64(N1C->getSignExtended()) || 937 isPowerOf2_64(-N1C->getSignExtended()))) { 938 // If dividing by powers of two is cheap, then don't perform the following 939 // fold. 940 if (TLI.isPow2DivCheap()) 941 return SDOperand(); 942 int64_t pow2 = N1C->getSignExtended(); 943 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 944 unsigned lg2 = Log2_64(abs2); 945 // Splat the sign bit into the register 946 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 947 DAG.getConstant(MVT::getSizeInBits(VT)-1, 948 TLI.getShiftAmountTy())); 949 AddToWorkList(SGN.Val); 950 // Add (N0 < 0) ? abs2 - 1 : 0; 951 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 952 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 953 TLI.getShiftAmountTy())); 954 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 955 AddToWorkList(SRL.Val); 956 AddToWorkList(ADD.Val); // Divide by pow2 957 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 958 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 959 // If we're dividing by a positive value, we're done. Otherwise, we must 960 // negate the result. 961 if (pow2 > 0) 962 return SRA; 963 AddToWorkList(SRA.Val); 964 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 965 } 966 // if integer divide is expensive and we satisfy the requirements, emit an 967 // alternate sequence. 968 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 969 !TLI.isIntDivCheap()) { 970 SDOperand Op = BuildSDIV(N); 971 if (Op.Val) return Op; 972 } 973 return SDOperand(); 974} 975 976SDOperand DAGCombiner::visitUDIV(SDNode *N) { 977 SDOperand N0 = N->getOperand(0); 978 SDOperand N1 = N->getOperand(1); 979 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 980 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 981 MVT::ValueType VT = N->getValueType(0); 982 983 // fold (udiv c1, c2) -> c1/c2 984 if (N0C && N1C && !N1C->isNullValue()) 985 return DAG.getNode(ISD::UDIV, VT, N0, N1); 986 // fold (udiv x, (1 << c)) -> x >>u c 987 if (N1C && isPowerOf2_64(N1C->getValue())) 988 return DAG.getNode(ISD::SRL, VT, N0, 989 DAG.getConstant(Log2_64(N1C->getValue()), 990 TLI.getShiftAmountTy())); 991 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 992 if (N1.getOpcode() == ISD::SHL) { 993 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 994 if (isPowerOf2_64(SHC->getValue())) { 995 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 996 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 997 DAG.getConstant(Log2_64(SHC->getValue()), 998 ADDVT)); 999 AddToWorkList(Add.Val); 1000 return DAG.getNode(ISD::SRL, VT, N0, Add); 1001 } 1002 } 1003 } 1004 // fold (udiv x, c) -> alternate 1005 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1006 SDOperand Op = BuildUDIV(N); 1007 if (Op.Val) return Op; 1008 } 1009 return SDOperand(); 1010} 1011 1012SDOperand DAGCombiner::visitSREM(SDNode *N) { 1013 SDOperand N0 = N->getOperand(0); 1014 SDOperand N1 = N->getOperand(1); 1015 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1016 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1017 MVT::ValueType VT = N->getValueType(0); 1018 1019 // fold (srem c1, c2) -> c1%c2 1020 if (N0C && N1C && !N1C->isNullValue()) 1021 return DAG.getNode(ISD::SREM, VT, N0, N1); 1022 // If we know the sign bits of both operands are zero, strength reduce to a 1023 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1024 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1025 if (TLI.MaskedValueIsZero(N1, SignBit) && 1026 TLI.MaskedValueIsZero(N0, SignBit)) 1027 return DAG.getNode(ISD::UREM, VT, N0, N1); 1028 1029 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1030 // the remainder operation. 1031 if (N1C && !N1C->isNullValue()) { 1032 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1033 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1034 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1035 AddToWorkList(Div.Val); 1036 AddToWorkList(Mul.Val); 1037 return Sub; 1038 } 1039 1040 return SDOperand(); 1041} 1042 1043SDOperand DAGCombiner::visitUREM(SDNode *N) { 1044 SDOperand N0 = N->getOperand(0); 1045 SDOperand N1 = N->getOperand(1); 1046 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1047 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1048 MVT::ValueType VT = N->getValueType(0); 1049 1050 // fold (urem c1, c2) -> c1%c2 1051 if (N0C && N1C && !N1C->isNullValue()) 1052 return DAG.getNode(ISD::UREM, VT, N0, N1); 1053 // fold (urem x, pow2) -> (and x, pow2-1) 1054 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1055 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1056 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1057 if (N1.getOpcode() == ISD::SHL) { 1058 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1059 if (isPowerOf2_64(SHC->getValue())) { 1060 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1061 AddToWorkList(Add.Val); 1062 return DAG.getNode(ISD::AND, VT, N0, Add); 1063 } 1064 } 1065 } 1066 1067 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1068 // the remainder operation. 1069 if (N1C && !N1C->isNullValue()) { 1070 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1071 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1072 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1073 AddToWorkList(Div.Val); 1074 AddToWorkList(Mul.Val); 1075 return Sub; 1076 } 1077 1078 return SDOperand(); 1079} 1080 1081SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1082 SDOperand N0 = N->getOperand(0); 1083 SDOperand N1 = N->getOperand(1); 1084 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1085 1086 // fold (mulhs x, 0) -> 0 1087 if (N1C && N1C->isNullValue()) 1088 return N1; 1089 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1090 if (N1C && N1C->getValue() == 1) 1091 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1092 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1093 TLI.getShiftAmountTy())); 1094 return SDOperand(); 1095} 1096 1097SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1098 SDOperand N0 = N->getOperand(0); 1099 SDOperand N1 = N->getOperand(1); 1100 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1101 1102 // fold (mulhu x, 0) -> 0 1103 if (N1C && N1C->isNullValue()) 1104 return N1; 1105 // fold (mulhu x, 1) -> 0 1106 if (N1C && N1C->getValue() == 1) 1107 return DAG.getConstant(0, N0.getValueType()); 1108 return SDOperand(); 1109} 1110 1111/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1112/// two operands of the same opcode, try to simplify it. 1113SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1114 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1115 MVT::ValueType VT = N0.getValueType(); 1116 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1117 1118 // For each of OP in AND/OR/XOR: 1119 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1120 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1121 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1122 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1123 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1124 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1125 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1126 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1127 N0.getOperand(0).getValueType(), 1128 N0.getOperand(0), N1.getOperand(0)); 1129 AddToWorkList(ORNode.Val); 1130 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1131 } 1132 1133 // For each of OP in SHL/SRL/SRA/AND... 1134 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1135 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1136 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1137 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1138 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1139 N0.getOperand(1) == N1.getOperand(1)) { 1140 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1141 N0.getOperand(0).getValueType(), 1142 N0.getOperand(0), N1.getOperand(0)); 1143 AddToWorkList(ORNode.Val); 1144 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1145 } 1146 1147 return SDOperand(); 1148} 1149 1150SDOperand DAGCombiner::visitAND(SDNode *N) { 1151 SDOperand N0 = N->getOperand(0); 1152 SDOperand N1 = N->getOperand(1); 1153 SDOperand LL, LR, RL, RR, CC0, CC1; 1154 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1155 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1156 MVT::ValueType VT = N1.getValueType(); 1157 1158 // fold (and c1, c2) -> c1&c2 1159 if (N0C && N1C) 1160 return DAG.getNode(ISD::AND, VT, N0, N1); 1161 // canonicalize constant to RHS 1162 if (N0C && !N1C) 1163 return DAG.getNode(ISD::AND, VT, N1, N0); 1164 // fold (and x, -1) -> x 1165 if (N1C && N1C->isAllOnesValue()) 1166 return N0; 1167 // if (and x, c) is known to be zero, return 0 1168 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1169 return DAG.getConstant(0, VT); 1170 // reassociate and 1171 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1172 if (RAND.Val != 0) 1173 return RAND; 1174 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1175 if (N1C && N0.getOpcode() == ISD::OR) 1176 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1177 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1178 return N1; 1179 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1180 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1181 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1182 if (TLI.MaskedValueIsZero(N0.getOperand(0), 1183 ~N1C->getValue() & InMask)) { 1184 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1185 N0.getOperand(0)); 1186 1187 // Replace uses of the AND with uses of the Zero extend node. 1188 CombineTo(N, Zext); 1189 1190 // We actually want to replace all uses of the any_extend with the 1191 // zero_extend, to avoid duplicating things. This will later cause this 1192 // AND to be folded. 1193 CombineTo(N0.Val, Zext); 1194 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1195 } 1196 } 1197 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1198 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1199 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1200 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1201 1202 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1203 MVT::isInteger(LL.getValueType())) { 1204 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1205 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1206 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1207 AddToWorkList(ORNode.Val); 1208 return DAG.getSetCC(VT, ORNode, LR, Op1); 1209 } 1210 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1211 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1212 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1213 AddToWorkList(ANDNode.Val); 1214 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1215 } 1216 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1217 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1218 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1219 AddToWorkList(ORNode.Val); 1220 return DAG.getSetCC(VT, ORNode, LR, Op1); 1221 } 1222 } 1223 // canonicalize equivalent to ll == rl 1224 if (LL == RR && LR == RL) { 1225 Op1 = ISD::getSetCCSwappedOperands(Op1); 1226 std::swap(RL, RR); 1227 } 1228 if (LL == RL && LR == RR) { 1229 bool isInteger = MVT::isInteger(LL.getValueType()); 1230 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1231 if (Result != ISD::SETCC_INVALID) 1232 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1233 } 1234 } 1235 1236 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1237 if (N0.getOpcode() == N1.getOpcode()) { 1238 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1239 if (Tmp.Val) return Tmp; 1240 } 1241 1242 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1243 // fold (and (sra)) -> (and (srl)) when possible. 1244 if (!MVT::isVector(VT) && 1245 SimplifyDemandedBits(SDOperand(N, 0))) 1246 return SDOperand(N, 0); 1247 // fold (zext_inreg (extload x)) -> (zextload x) 1248 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1249 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1250 MVT::ValueType EVT = LN0->getLoadedVT(); 1251 // If we zero all the possible extended bits, then we can turn this into 1252 // a zextload if we are running before legalize or the operation is legal. 1253 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1254 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1255 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1256 LN0->getBasePtr(), LN0->getSrcValue(), 1257 LN0->getSrcValueOffset(), EVT); 1258 AddToWorkList(N); 1259 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1260 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1261 } 1262 } 1263 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1264 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1265 N0.hasOneUse()) { 1266 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1267 MVT::ValueType EVT = LN0->getLoadedVT(); 1268 // If we zero all the possible extended bits, then we can turn this into 1269 // a zextload if we are running before legalize or the operation is legal. 1270 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1271 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1272 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1273 LN0->getBasePtr(), LN0->getSrcValue(), 1274 LN0->getSrcValueOffset(), EVT); 1275 AddToWorkList(N); 1276 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1277 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1278 } 1279 } 1280 1281 // fold (and (load x), 255) -> (zextload x, i8) 1282 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1283 if (N1C && N0.getOpcode() == ISD::LOAD) { 1284 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1285 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1286 LN0->getAddressingMode() == ISD::UNINDEXED && 1287 N0.hasOneUse()) { 1288 MVT::ValueType EVT, LoadedVT; 1289 if (N1C->getValue() == 255) 1290 EVT = MVT::i8; 1291 else if (N1C->getValue() == 65535) 1292 EVT = MVT::i16; 1293 else if (N1C->getValue() == ~0U) 1294 EVT = MVT::i32; 1295 else 1296 EVT = MVT::Other; 1297 1298 LoadedVT = LN0->getLoadedVT(); 1299 if (EVT != MVT::Other && LoadedVT > EVT && 1300 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1301 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1302 // For big endian targets, we need to add an offset to the pointer to 1303 // load the correct bytes. For little endian systems, we merely need to 1304 // read fewer bytes from the same pointer. 1305 unsigned PtrOff = 1306 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1307 SDOperand NewPtr = LN0->getBasePtr(); 1308 if (!TLI.isLittleEndian()) 1309 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1310 DAG.getConstant(PtrOff, PtrType)); 1311 AddToWorkList(NewPtr.Val); 1312 SDOperand Load = 1313 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1314 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT); 1315 AddToWorkList(N); 1316 CombineTo(N0.Val, Load, Load.getValue(1)); 1317 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1318 } 1319 } 1320 } 1321 1322 return SDOperand(); 1323} 1324 1325SDOperand DAGCombiner::visitOR(SDNode *N) { 1326 SDOperand N0 = N->getOperand(0); 1327 SDOperand N1 = N->getOperand(1); 1328 SDOperand LL, LR, RL, RR, CC0, CC1; 1329 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1330 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1331 MVT::ValueType VT = N1.getValueType(); 1332 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1333 1334 // fold (or c1, c2) -> c1|c2 1335 if (N0C && N1C) 1336 return DAG.getNode(ISD::OR, VT, N0, N1); 1337 // canonicalize constant to RHS 1338 if (N0C && !N1C) 1339 return DAG.getNode(ISD::OR, VT, N1, N0); 1340 // fold (or x, 0) -> x 1341 if (N1C && N1C->isNullValue()) 1342 return N0; 1343 // fold (or x, -1) -> -1 1344 if (N1C && N1C->isAllOnesValue()) 1345 return N1; 1346 // fold (or x, c) -> c iff (x & ~c) == 0 1347 if (N1C && 1348 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1349 return N1; 1350 // reassociate or 1351 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1352 if (ROR.Val != 0) 1353 return ROR; 1354 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1355 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1356 isa<ConstantSDNode>(N0.getOperand(1))) { 1357 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1358 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1359 N1), 1360 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1361 } 1362 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1363 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1364 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1365 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1366 1367 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1368 MVT::isInteger(LL.getValueType())) { 1369 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1370 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1371 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1372 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1373 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1374 AddToWorkList(ORNode.Val); 1375 return DAG.getSetCC(VT, ORNode, LR, Op1); 1376 } 1377 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1378 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1379 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1380 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1381 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1382 AddToWorkList(ANDNode.Val); 1383 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1384 } 1385 } 1386 // canonicalize equivalent to ll == rl 1387 if (LL == RR && LR == RL) { 1388 Op1 = ISD::getSetCCSwappedOperands(Op1); 1389 std::swap(RL, RR); 1390 } 1391 if (LL == RL && LR == RR) { 1392 bool isInteger = MVT::isInteger(LL.getValueType()); 1393 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1394 if (Result != ISD::SETCC_INVALID) 1395 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1396 } 1397 } 1398 1399 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1400 if (N0.getOpcode() == N1.getOpcode()) { 1401 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1402 if (Tmp.Val) return Tmp; 1403 } 1404 1405 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1406 if (N0.getOpcode() == ISD::AND && 1407 N1.getOpcode() == ISD::AND && 1408 N0.getOperand(1).getOpcode() == ISD::Constant && 1409 N1.getOperand(1).getOpcode() == ISD::Constant && 1410 // Don't increase # computations. 1411 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1412 // We can only do this xform if we know that bits from X that are set in C2 1413 // but not in C1 are already zero. Likewise for Y. 1414 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1415 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1416 1417 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1418 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1419 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1420 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1421 } 1422 } 1423 1424 1425 // See if this is some rotate idiom. 1426 if (SDNode *Rot = MatchRotate(N0, N1)) 1427 return SDOperand(Rot, 0); 1428 1429 return SDOperand(); 1430} 1431 1432 1433/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1434static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1435 if (Op.getOpcode() == ISD::AND) { 1436 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1437 Mask = Op.getOperand(1); 1438 Op = Op.getOperand(0); 1439 } else { 1440 return false; 1441 } 1442 } 1443 1444 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1445 Shift = Op; 1446 return true; 1447 } 1448 return false; 1449} 1450 1451 1452// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1453// idioms for rotate, and if the target supports rotation instructions, generate 1454// a rot[lr]. 1455SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1456 // Must be a legal type. Expanded an promoted things won't work with rotates. 1457 MVT::ValueType VT = LHS.getValueType(); 1458 if (!TLI.isTypeLegal(VT)) return 0; 1459 1460 // The target must have at least one rotate flavor. 1461 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1462 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1463 if (!HasROTL && !HasROTR) return 0; 1464 1465 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1466 SDOperand LHSShift; // The shift. 1467 SDOperand LHSMask; // AND value if any. 1468 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1469 return 0; // Not part of a rotate. 1470 1471 SDOperand RHSShift; // The shift. 1472 SDOperand RHSMask; // AND value if any. 1473 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1474 return 0; // Not part of a rotate. 1475 1476 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1477 return 0; // Not shifting the same value. 1478 1479 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1480 return 0; // Shifts must disagree. 1481 1482 // Canonicalize shl to left side in a shl/srl pair. 1483 if (RHSShift.getOpcode() == ISD::SHL) { 1484 std::swap(LHS, RHS); 1485 std::swap(LHSShift, RHSShift); 1486 std::swap(LHSMask , RHSMask ); 1487 } 1488 1489 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1490 1491 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1492 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1493 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant && 1494 RHSShift.getOperand(1).getOpcode() == ISD::Constant) { 1495 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue(); 1496 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue(); 1497 if ((LShVal + RShVal) != OpSizeInBits) 1498 return 0; 1499 1500 SDOperand Rot; 1501 if (HasROTL) 1502 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0), 1503 LHSShift.getOperand(1)); 1504 else 1505 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0), 1506 RHSShift.getOperand(1)); 1507 1508 // If there is an AND of either shifted operand, apply it to the result. 1509 if (LHSMask.Val || RHSMask.Val) { 1510 uint64_t Mask = MVT::getIntVTBitMask(VT); 1511 1512 if (LHSMask.Val) { 1513 uint64_t RHSBits = (1ULL << LShVal)-1; 1514 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1515 } 1516 if (RHSMask.Val) { 1517 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1518 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1519 } 1520 1521 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1522 } 1523 1524 return Rot.Val; 1525 } 1526 1527 // If there is a mask here, and we have a variable shift, we can't be sure 1528 // that we're masking out the right stuff. 1529 if (LHSMask.Val || RHSMask.Val) 1530 return 0; 1531 1532 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1533 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1534 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB && 1535 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) { 1536 if (ConstantSDNode *SUBC = 1537 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) { 1538 if (SUBC->getValue() == OpSizeInBits) 1539 if (HasROTL) 1540 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0), 1541 LHSShift.getOperand(1)).Val; 1542 else 1543 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0), 1544 LHSShift.getOperand(1)).Val; 1545 } 1546 } 1547 1548 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1549 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1550 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB && 1551 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) { 1552 if (ConstantSDNode *SUBC = 1553 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) { 1554 if (SUBC->getValue() == OpSizeInBits) 1555 if (HasROTL) 1556 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0), 1557 LHSShift.getOperand(1)).Val; 1558 else 1559 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0), 1560 RHSShift.getOperand(1)).Val; 1561 } 1562 } 1563 1564 return 0; 1565} 1566 1567 1568SDOperand DAGCombiner::visitXOR(SDNode *N) { 1569 SDOperand N0 = N->getOperand(0); 1570 SDOperand N1 = N->getOperand(1); 1571 SDOperand LHS, RHS, CC; 1572 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1573 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1574 MVT::ValueType VT = N0.getValueType(); 1575 1576 // fold (xor c1, c2) -> c1^c2 1577 if (N0C && N1C) 1578 return DAG.getNode(ISD::XOR, VT, N0, N1); 1579 // canonicalize constant to RHS 1580 if (N0C && !N1C) 1581 return DAG.getNode(ISD::XOR, VT, N1, N0); 1582 // fold (xor x, 0) -> x 1583 if (N1C && N1C->isNullValue()) 1584 return N0; 1585 // reassociate xor 1586 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1587 if (RXOR.Val != 0) 1588 return RXOR; 1589 // fold !(x cc y) -> (x !cc y) 1590 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1591 bool isInt = MVT::isInteger(LHS.getValueType()); 1592 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1593 isInt); 1594 if (N0.getOpcode() == ISD::SETCC) 1595 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1596 if (N0.getOpcode() == ISD::SELECT_CC) 1597 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1598 assert(0 && "Unhandled SetCC Equivalent!"); 1599 abort(); 1600 } 1601 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1602 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 1603 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1604 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1605 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1606 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1607 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1608 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1609 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1610 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1611 } 1612 } 1613 // fold !(x or y) -> (!x and !y) iff x or y are constants 1614 if (N1C && N1C->isAllOnesValue() && 1615 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1616 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1617 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1618 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1619 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1620 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1621 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1622 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1623 } 1624 } 1625 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1626 if (N1C && N0.getOpcode() == ISD::XOR) { 1627 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1628 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1629 if (N00C) 1630 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1631 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1632 if (N01C) 1633 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1634 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1635 } 1636 // fold (xor x, x) -> 0 1637 if (N0 == N1) { 1638 if (!MVT::isVector(VT)) { 1639 return DAG.getConstant(0, VT); 1640 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1641 // Produce a vector of zeros. 1642 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT)); 1643 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 1644 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1645 } 1646 } 1647 1648 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 1649 if (N0.getOpcode() == N1.getOpcode()) { 1650 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1651 if (Tmp.Val) return Tmp; 1652 } 1653 1654 // Simplify the expression using non-local knowledge. 1655 if (!MVT::isVector(VT) && 1656 SimplifyDemandedBits(SDOperand(N, 0))) 1657 return SDOperand(N, 0); 1658 1659 return SDOperand(); 1660} 1661 1662SDOperand DAGCombiner::visitSHL(SDNode *N) { 1663 SDOperand N0 = N->getOperand(0); 1664 SDOperand N1 = N->getOperand(1); 1665 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1666 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1667 MVT::ValueType VT = N0.getValueType(); 1668 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1669 1670 // fold (shl c1, c2) -> c1<<c2 1671 if (N0C && N1C) 1672 return DAG.getNode(ISD::SHL, VT, N0, N1); 1673 // fold (shl 0, x) -> 0 1674 if (N0C && N0C->isNullValue()) 1675 return N0; 1676 // fold (shl x, c >= size(x)) -> undef 1677 if (N1C && N1C->getValue() >= OpSizeInBits) 1678 return DAG.getNode(ISD::UNDEF, VT); 1679 // fold (shl x, 0) -> x 1680 if (N1C && N1C->isNullValue()) 1681 return N0; 1682 // if (shl x, c) is known to be zero, return 0 1683 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1684 return DAG.getConstant(0, VT); 1685 if (SimplifyDemandedBits(SDOperand(N, 0))) 1686 return SDOperand(N, 0); 1687 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1688 if (N1C && N0.getOpcode() == ISD::SHL && 1689 N0.getOperand(1).getOpcode() == ISD::Constant) { 1690 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1691 uint64_t c2 = N1C->getValue(); 1692 if (c1 + c2 > OpSizeInBits) 1693 return DAG.getConstant(0, VT); 1694 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1695 DAG.getConstant(c1 + c2, N1.getValueType())); 1696 } 1697 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1698 // (srl (and x, -1 << c1), c1-c2) 1699 if (N1C && N0.getOpcode() == ISD::SRL && 1700 N0.getOperand(1).getOpcode() == ISD::Constant) { 1701 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1702 uint64_t c2 = N1C->getValue(); 1703 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1704 DAG.getConstant(~0ULL << c1, VT)); 1705 if (c2 > c1) 1706 return DAG.getNode(ISD::SHL, VT, Mask, 1707 DAG.getConstant(c2-c1, N1.getValueType())); 1708 else 1709 return DAG.getNode(ISD::SRL, VT, Mask, 1710 DAG.getConstant(c1-c2, N1.getValueType())); 1711 } 1712 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1713 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1714 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1715 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1716 return SDOperand(); 1717} 1718 1719SDOperand DAGCombiner::visitSRA(SDNode *N) { 1720 SDOperand N0 = N->getOperand(0); 1721 SDOperand N1 = N->getOperand(1); 1722 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1723 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1724 MVT::ValueType VT = N0.getValueType(); 1725 1726 // fold (sra c1, c2) -> c1>>c2 1727 if (N0C && N1C) 1728 return DAG.getNode(ISD::SRA, VT, N0, N1); 1729 // fold (sra 0, x) -> 0 1730 if (N0C && N0C->isNullValue()) 1731 return N0; 1732 // fold (sra -1, x) -> -1 1733 if (N0C && N0C->isAllOnesValue()) 1734 return N0; 1735 // fold (sra x, c >= size(x)) -> undef 1736 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 1737 return DAG.getNode(ISD::UNDEF, VT); 1738 // fold (sra x, 0) -> x 1739 if (N1C && N1C->isNullValue()) 1740 return N0; 1741 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 1742 // sext_inreg. 1743 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 1744 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 1745 MVT::ValueType EVT; 1746 switch (LowBits) { 1747 default: EVT = MVT::Other; break; 1748 case 1: EVT = MVT::i1; break; 1749 case 8: EVT = MVT::i8; break; 1750 case 16: EVT = MVT::i16; break; 1751 case 32: EVT = MVT::i32; break; 1752 } 1753 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 1754 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1755 DAG.getValueType(EVT)); 1756 } 1757 1758 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 1759 if (N1C && N0.getOpcode() == ISD::SRA) { 1760 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1761 unsigned Sum = N1C->getValue() + C1->getValue(); 1762 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 1763 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 1764 DAG.getConstant(Sum, N1C->getValueType(0))); 1765 } 1766 } 1767 1768 // Simplify, based on bits shifted out of the LHS. 1769 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 1770 return SDOperand(N, 0); 1771 1772 1773 // If the sign bit is known to be zero, switch this to a SRL. 1774 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 1775 return DAG.getNode(ISD::SRL, VT, N0, N1); 1776 return SDOperand(); 1777} 1778 1779SDOperand DAGCombiner::visitSRL(SDNode *N) { 1780 SDOperand N0 = N->getOperand(0); 1781 SDOperand N1 = N->getOperand(1); 1782 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1783 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1784 MVT::ValueType VT = N0.getValueType(); 1785 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1786 1787 // fold (srl c1, c2) -> c1 >>u c2 1788 if (N0C && N1C) 1789 return DAG.getNode(ISD::SRL, VT, N0, N1); 1790 // fold (srl 0, x) -> 0 1791 if (N0C && N0C->isNullValue()) 1792 return N0; 1793 // fold (srl x, c >= size(x)) -> undef 1794 if (N1C && N1C->getValue() >= OpSizeInBits) 1795 return DAG.getNode(ISD::UNDEF, VT); 1796 // fold (srl x, 0) -> x 1797 if (N1C && N1C->isNullValue()) 1798 return N0; 1799 // if (srl x, c) is known to be zero, return 0 1800 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1801 return DAG.getConstant(0, VT); 1802 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1803 if (N1C && N0.getOpcode() == ISD::SRL && 1804 N0.getOperand(1).getOpcode() == ISD::Constant) { 1805 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1806 uint64_t c2 = N1C->getValue(); 1807 if (c1 + c2 > OpSizeInBits) 1808 return DAG.getConstant(0, VT); 1809 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1810 DAG.getConstant(c1 + c2, N1.getValueType())); 1811 } 1812 1813 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 1814 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1815 // Shifting in all undef bits? 1816 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 1817 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 1818 return DAG.getNode(ISD::UNDEF, VT); 1819 1820 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 1821 AddToWorkList(SmallShift.Val); 1822 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 1823 } 1824 1825 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 1826 // bit, which is unmodified by sra. 1827 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 1828 if (N0.getOpcode() == ISD::SRA) 1829 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 1830 } 1831 1832 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 1833 if (N1C && N0.getOpcode() == ISD::CTLZ && 1834 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 1835 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 1836 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 1837 1838 // If any of the input bits are KnownOne, then the input couldn't be all 1839 // zeros, thus the result of the srl will always be zero. 1840 if (KnownOne) return DAG.getConstant(0, VT); 1841 1842 // If all of the bits input the to ctlz node are known to be zero, then 1843 // the result of the ctlz is "32" and the result of the shift is one. 1844 uint64_t UnknownBits = ~KnownZero & Mask; 1845 if (UnknownBits == 0) return DAG.getConstant(1, VT); 1846 1847 // Otherwise, check to see if there is exactly one bit input to the ctlz. 1848 if ((UnknownBits & (UnknownBits-1)) == 0) { 1849 // Okay, we know that only that the single bit specified by UnknownBits 1850 // could be set on input to the CTLZ node. If this bit is set, the SRL 1851 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 1852 // to an SRL,XOR pair, which is likely to simplify more. 1853 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 1854 SDOperand Op = N0.getOperand(0); 1855 if (ShAmt) { 1856 Op = DAG.getNode(ISD::SRL, VT, Op, 1857 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 1858 AddToWorkList(Op.Val); 1859 } 1860 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 1861 } 1862 } 1863 1864 return SDOperand(); 1865} 1866 1867SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1868 SDOperand N0 = N->getOperand(0); 1869 MVT::ValueType VT = N->getValueType(0); 1870 1871 // fold (ctlz c1) -> c2 1872 if (isa<ConstantSDNode>(N0)) 1873 return DAG.getNode(ISD::CTLZ, VT, N0); 1874 return SDOperand(); 1875} 1876 1877SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1878 SDOperand N0 = N->getOperand(0); 1879 MVT::ValueType VT = N->getValueType(0); 1880 1881 // fold (cttz c1) -> c2 1882 if (isa<ConstantSDNode>(N0)) 1883 return DAG.getNode(ISD::CTTZ, VT, N0); 1884 return SDOperand(); 1885} 1886 1887SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1888 SDOperand N0 = N->getOperand(0); 1889 MVT::ValueType VT = N->getValueType(0); 1890 1891 // fold (ctpop c1) -> c2 1892 if (isa<ConstantSDNode>(N0)) 1893 return DAG.getNode(ISD::CTPOP, VT, N0); 1894 return SDOperand(); 1895} 1896 1897SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1898 SDOperand N0 = N->getOperand(0); 1899 SDOperand N1 = N->getOperand(1); 1900 SDOperand N2 = N->getOperand(2); 1901 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1902 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1903 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1904 MVT::ValueType VT = N->getValueType(0); 1905 1906 // fold select C, X, X -> X 1907 if (N1 == N2) 1908 return N1; 1909 // fold select true, X, Y -> X 1910 if (N0C && !N0C->isNullValue()) 1911 return N1; 1912 // fold select false, X, Y -> Y 1913 if (N0C && N0C->isNullValue()) 1914 return N2; 1915 // fold select C, 1, X -> C | X 1916 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1917 return DAG.getNode(ISD::OR, VT, N0, N2); 1918 // fold select C, 0, X -> ~C & X 1919 // FIXME: this should check for C type == X type, not i1? 1920 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1921 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1922 AddToWorkList(XORNode.Val); 1923 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1924 } 1925 // fold select C, X, 1 -> ~C | X 1926 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1927 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1928 AddToWorkList(XORNode.Val); 1929 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1930 } 1931 // fold select C, X, 0 -> C & X 1932 // FIXME: this should check for C type == X type, not i1? 1933 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1934 return DAG.getNode(ISD::AND, VT, N0, N1); 1935 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1936 if (MVT::i1 == VT && N0 == N1) 1937 return DAG.getNode(ISD::OR, VT, N0, N2); 1938 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1939 if (MVT::i1 == VT && N0 == N2) 1940 return DAG.getNode(ISD::AND, VT, N0, N1); 1941 1942 // If we can fold this based on the true/false value, do so. 1943 if (SimplifySelectOps(N, N1, N2)) 1944 return SDOperand(N, 0); // Don't revisit N. 1945 1946 // fold selects based on a setcc into other things, such as min/max/abs 1947 if (N0.getOpcode() == ISD::SETCC) 1948 // FIXME: 1949 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 1950 // having to say they don't support SELECT_CC on every type the DAG knows 1951 // about, since there is no way to mark an opcode illegal at all value types 1952 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 1953 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 1954 N1, N2, N0.getOperand(2)); 1955 else 1956 return SimplifySelect(N0, N1, N2); 1957 return SDOperand(); 1958} 1959 1960SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1961 SDOperand N0 = N->getOperand(0); 1962 SDOperand N1 = N->getOperand(1); 1963 SDOperand N2 = N->getOperand(2); 1964 SDOperand N3 = N->getOperand(3); 1965 SDOperand N4 = N->getOperand(4); 1966 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1967 1968 // fold select_cc lhs, rhs, x, x, cc -> x 1969 if (N2 == N3) 1970 return N2; 1971 1972 // Determine if the condition we're dealing with is constant 1973 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1974 if (SCC.Val) AddToWorkList(SCC.Val); 1975 1976 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 1977 if (SCCC->getValue()) 1978 return N2; // cond always true -> true val 1979 else 1980 return N3; // cond always false -> false val 1981 } 1982 1983 // Fold to a simpler select_cc 1984 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 1985 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 1986 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 1987 SCC.getOperand(2)); 1988 1989 // If we can fold this based on the true/false value, do so. 1990 if (SimplifySelectOps(N, N2, N3)) 1991 return SDOperand(N, 0); // Don't revisit N. 1992 1993 // fold select_cc into other things, such as min/max/abs 1994 return SimplifySelectCC(N0, N1, N2, N3, CC); 1995} 1996 1997SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1998 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1999 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2000} 2001 2002SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2003 SDOperand N0 = N->getOperand(0); 2004 MVT::ValueType VT = N->getValueType(0); 2005 2006 // fold (sext c1) -> c1 2007 if (isa<ConstantSDNode>(N0)) 2008 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2009 2010 // fold (sext (sext x)) -> (sext x) 2011 // fold (sext (aext x)) -> (sext x) 2012 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2013 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2014 2015 if (N0.getOpcode() == ISD::TRUNCATE) { 2016 // See if the value being truncated is already sign extended. If so, just 2017 // eliminate the trunc/sext pair. 2018 SDOperand Op = N0.getOperand(0); 2019 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2020 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2021 unsigned DestBits = MVT::getSizeInBits(VT); 2022 unsigned NumSignBits = TLI.ComputeNumSignBits(Op); 2023 2024 if (OpBits == DestBits) { 2025 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2026 // bits, it is already ready. 2027 if (NumSignBits > DestBits-MidBits) 2028 return Op; 2029 } else if (OpBits < DestBits) { 2030 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2031 // bits, just sext from i32. 2032 if (NumSignBits > OpBits-MidBits) 2033 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2034 } else { 2035 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2036 // bits, just truncate to i32. 2037 if (NumSignBits > OpBits-MidBits) 2038 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2039 } 2040 2041 // fold (sext (truncate x)) -> (sextinreg x). 2042 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2043 N0.getValueType())) { 2044 if (Op.getValueType() < VT) 2045 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2046 else if (Op.getValueType() > VT) 2047 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2048 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2049 DAG.getValueType(N0.getValueType())); 2050 } 2051 } 2052 2053 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2054 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2055 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2056 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2057 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2058 LN0->getBasePtr(), LN0->getSrcValue(), 2059 LN0->getSrcValueOffset(), 2060 N0.getValueType()); 2061 CombineTo(N, ExtLoad); 2062 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2063 ExtLoad.getValue(1)); 2064 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2065 } 2066 2067 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2068 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2069 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2070 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2071 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2072 MVT::ValueType EVT = LN0->getLoadedVT(); 2073 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2074 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2075 LN0->getBasePtr(), LN0->getSrcValue(), 2076 LN0->getSrcValueOffset(), EVT); 2077 CombineTo(N, ExtLoad); 2078 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2079 ExtLoad.getValue(1)); 2080 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2081 } 2082 } 2083 2084 return SDOperand(); 2085} 2086 2087SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2088 SDOperand N0 = N->getOperand(0); 2089 MVT::ValueType VT = N->getValueType(0); 2090 2091 // fold (zext c1) -> c1 2092 if (isa<ConstantSDNode>(N0)) 2093 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2094 // fold (zext (zext x)) -> (zext x) 2095 // fold (zext (aext x)) -> (zext x) 2096 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2097 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2098 2099 // fold (zext (truncate x)) -> (and x, mask) 2100 if (N0.getOpcode() == ISD::TRUNCATE && 2101 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2102 SDOperand Op = N0.getOperand(0); 2103 if (Op.getValueType() < VT) { 2104 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2105 } else if (Op.getValueType() > VT) { 2106 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2107 } 2108 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2109 } 2110 2111 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2112 if (N0.getOpcode() == ISD::AND && 2113 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2114 N0.getOperand(1).getOpcode() == ISD::Constant) { 2115 SDOperand X = N0.getOperand(0).getOperand(0); 2116 if (X.getValueType() < VT) { 2117 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2118 } else if (X.getValueType() > VT) { 2119 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2120 } 2121 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2122 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2123 } 2124 2125 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2126 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2127 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2128 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2129 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2130 LN0->getBasePtr(), LN0->getSrcValue(), 2131 LN0->getSrcValueOffset(), 2132 N0.getValueType()); 2133 CombineTo(N, ExtLoad); 2134 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2135 ExtLoad.getValue(1)); 2136 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2137 } 2138 2139 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2140 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2141 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2142 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2143 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2144 MVT::ValueType EVT = LN0->getLoadedVT(); 2145 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2146 LN0->getBasePtr(), LN0->getSrcValue(), 2147 LN0->getSrcValueOffset(), EVT); 2148 CombineTo(N, ExtLoad); 2149 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2150 ExtLoad.getValue(1)); 2151 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2152 } 2153 return SDOperand(); 2154} 2155 2156SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2157 SDOperand N0 = N->getOperand(0); 2158 MVT::ValueType VT = N->getValueType(0); 2159 2160 // fold (aext c1) -> c1 2161 if (isa<ConstantSDNode>(N0)) 2162 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2163 // fold (aext (aext x)) -> (aext x) 2164 // fold (aext (zext x)) -> (zext x) 2165 // fold (aext (sext x)) -> (sext x) 2166 if (N0.getOpcode() == ISD::ANY_EXTEND || 2167 N0.getOpcode() == ISD::ZERO_EXTEND || 2168 N0.getOpcode() == ISD::SIGN_EXTEND) 2169 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2170 2171 // fold (aext (truncate x)) 2172 if (N0.getOpcode() == ISD::TRUNCATE) { 2173 SDOperand TruncOp = N0.getOperand(0); 2174 if (TruncOp.getValueType() == VT) 2175 return TruncOp; // x iff x size == zext size. 2176 if (TruncOp.getValueType() > VT) 2177 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2178 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2179 } 2180 2181 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2182 if (N0.getOpcode() == ISD::AND && 2183 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2184 N0.getOperand(1).getOpcode() == ISD::Constant) { 2185 SDOperand X = N0.getOperand(0).getOperand(0); 2186 if (X.getValueType() < VT) { 2187 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2188 } else if (X.getValueType() > VT) { 2189 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2190 } 2191 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2192 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2193 } 2194 2195 // fold (aext (load x)) -> (aext (truncate (extload x))) 2196 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2197 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2198 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2199 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2200 LN0->getBasePtr(), LN0->getSrcValue(), 2201 LN0->getSrcValueOffset(), 2202 N0.getValueType()); 2203 CombineTo(N, ExtLoad); 2204 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2205 ExtLoad.getValue(1)); 2206 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2207 } 2208 2209 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2210 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2211 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2212 if (N0.getOpcode() == ISD::LOAD && 2213 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2214 N0.hasOneUse()) { 2215 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2216 MVT::ValueType EVT = LN0->getLoadedVT(); 2217 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2218 LN0->getChain(), LN0->getBasePtr(), 2219 LN0->getSrcValue(), 2220 LN0->getSrcValueOffset(), EVT); 2221 CombineTo(N, ExtLoad); 2222 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2223 ExtLoad.getValue(1)); 2224 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2225 } 2226 return SDOperand(); 2227} 2228 2229 2230SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 2231 SDOperand N0 = N->getOperand(0); 2232 SDOperand N1 = N->getOperand(1); 2233 MVT::ValueType VT = N->getValueType(0); 2234 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 2235 unsigned EVTBits = MVT::getSizeInBits(EVT); 2236 2237 // fold (sext_in_reg c1) -> c1 2238 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 2239 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 2240 2241 // If the input is already sign extended, just drop the extension. 2242 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 2243 return N0; 2244 2245 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 2246 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2247 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 2248 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 2249 } 2250 2251 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 2252 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 2253 return DAG.getZeroExtendInReg(N0, EVT); 2254 2255 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 2256 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 2257 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 2258 if (N0.getOpcode() == ISD::SRL) { 2259 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2260 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 2261 // We can turn this into an SRA iff the input to the SRL is already sign 2262 // extended enough. 2263 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0)); 2264 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 2265 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 2266 } 2267 } 2268 2269 // fold (sext_inreg (extload x)) -> (sextload x) 2270 if (ISD::isEXTLoad(N0.Val) && 2271 ISD::isUNINDEXEDLoad(N0.Val) && 2272 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2273 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2274 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2275 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2276 LN0->getBasePtr(), LN0->getSrcValue(), 2277 LN0->getSrcValueOffset(), EVT); 2278 CombineTo(N, ExtLoad); 2279 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2280 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2281 } 2282 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 2283 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2284 N0.hasOneUse() && 2285 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2286 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2287 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2288 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2289 LN0->getBasePtr(), LN0->getSrcValue(), 2290 LN0->getSrcValueOffset(), EVT); 2291 CombineTo(N, ExtLoad); 2292 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2293 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2294 } 2295 return SDOperand(); 2296} 2297 2298SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 2299 SDOperand N0 = N->getOperand(0); 2300 MVT::ValueType VT = N->getValueType(0); 2301 2302 // noop truncate 2303 if (N0.getValueType() == N->getValueType(0)) 2304 return N0; 2305 // fold (truncate c1) -> c1 2306 if (isa<ConstantSDNode>(N0)) 2307 return DAG.getNode(ISD::TRUNCATE, VT, N0); 2308 // fold (truncate (truncate x)) -> (truncate x) 2309 if (N0.getOpcode() == ISD::TRUNCATE) 2310 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2311 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 2312 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 2313 N0.getOpcode() == ISD::ANY_EXTEND) { 2314 if (N0.getOperand(0).getValueType() < VT) 2315 // if the source is smaller than the dest, we still need an extend 2316 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2317 else if (N0.getOperand(0).getValueType() > VT) 2318 // if the source is larger than the dest, than we just need the truncate 2319 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2320 else 2321 // if the source and dest are the same type, we can drop both the extend 2322 // and the truncate 2323 return N0.getOperand(0); 2324 } 2325 // fold (truncate (load x)) -> (smaller load x) 2326 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2327 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 2328 // zero extended form: by shrinking the load, we lose track of the fact 2329 // that it is already zero extended. 2330 // FIXME: This should be reevaluated. 2331 VT != MVT::i1) { 2332 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 2333 "Cannot truncate to larger type!"); 2334 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2335 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 2336 // For big endian targets, we need to add an offset to the pointer to load 2337 // the correct bytes. For little endian systems, we merely need to read 2338 // fewer bytes from the same pointer. 2339 uint64_t PtrOff = 2340 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 2341 SDOperand NewPtr = TLI.isLittleEndian() ? LN0->getBasePtr() : 2342 DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 2343 DAG.getConstant(PtrOff, PtrType)); 2344 AddToWorkList(NewPtr.Val); 2345 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), NewPtr, 2346 LN0->getSrcValue(), LN0->getSrcValueOffset()); 2347 AddToWorkList(N); 2348 CombineTo(N0.Val, Load, Load.getValue(1)); 2349 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2350 } 2351 return SDOperand(); 2352} 2353 2354SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 2355 SDOperand N0 = N->getOperand(0); 2356 MVT::ValueType VT = N->getValueType(0); 2357 2358 // If the input is a constant, let getNode() fold it. 2359 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 2360 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 2361 if (Res.Val != N) return Res; 2362 } 2363 2364 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 2365 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 2366 2367 // fold (conv (load x)) -> (load (conv*)x) 2368 // FIXME: These xforms need to know that the resultant load doesn't need a 2369 // higher alignment than the original! 2370 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) { 2371 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2372 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 2373 LN0->getSrcValue(), LN0->getSrcValueOffset()); 2374 AddToWorkList(N); 2375 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 2376 Load.getValue(1)); 2377 return Load; 2378 } 2379 2380 return SDOperand(); 2381} 2382 2383SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) { 2384 SDOperand N0 = N->getOperand(0); 2385 MVT::ValueType VT = N->getValueType(0); 2386 2387 // If the input is a VBUILD_VECTOR with all constant elements, fold this now. 2388 // First check to see if this is all constant. 2389 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() && 2390 VT == MVT::Vector) { 2391 bool isSimple = true; 2392 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i) 2393 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 2394 N0.getOperand(i).getOpcode() != ISD::Constant && 2395 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 2396 isSimple = false; 2397 break; 2398 } 2399 2400 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT(); 2401 if (isSimple && !MVT::isVector(DestEltVT)) { 2402 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT); 2403 } 2404 } 2405 2406 return SDOperand(); 2407} 2408 2409/// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector 2410/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 2411/// destination element value type. 2412SDOperand DAGCombiner:: 2413ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 2414 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 2415 2416 // If this is already the right type, we're done. 2417 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 2418 2419 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 2420 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 2421 2422 // If this is a conversion of N elements of one type to N elements of another 2423 // type, convert each element. This handles FP<->INT cases. 2424 if (SrcBitSize == DstBitSize) { 2425 SmallVector<SDOperand, 8> Ops; 2426 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2427 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 2428 AddToWorkList(Ops.back().Val); 2429 } 2430 Ops.push_back(*(BV->op_end()-2)); // Add num elements. 2431 Ops.push_back(DAG.getValueType(DstEltVT)); 2432 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2433 } 2434 2435 // Otherwise, we're growing or shrinking the elements. To avoid having to 2436 // handle annoying details of growing/shrinking FP values, we convert them to 2437 // int first. 2438 if (MVT::isFloatingPoint(SrcEltVT)) { 2439 // Convert the input float vector to a int vector where the elements are the 2440 // same sizes. 2441 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 2442 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2443 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val; 2444 SrcEltVT = IntVT; 2445 } 2446 2447 // Now we know the input is an integer vector. If the output is a FP type, 2448 // convert to integer first, then to FP of the right size. 2449 if (MVT::isFloatingPoint(DstEltVT)) { 2450 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 2451 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2452 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val; 2453 2454 // Next, convert to FP elements of the same size. 2455 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT); 2456 } 2457 2458 // Okay, we know the src/dst types are both integers of differing types. 2459 // Handling growing first. 2460 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 2461 if (SrcBitSize < DstBitSize) { 2462 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 2463 2464 SmallVector<SDOperand, 8> Ops; 2465 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; 2466 i += NumInputsPerOutput) { 2467 bool isLE = TLI.isLittleEndian(); 2468 uint64_t NewBits = 0; 2469 bool EltIsUndef = true; 2470 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 2471 // Shift the previously computed bits over. 2472 NewBits <<= SrcBitSize; 2473 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 2474 if (Op.getOpcode() == ISD::UNDEF) continue; 2475 EltIsUndef = false; 2476 2477 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 2478 } 2479 2480 if (EltIsUndef) 2481 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2482 else 2483 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 2484 } 2485 2486 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2487 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2488 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2489 } 2490 2491 // Finally, this must be the case where we are shrinking elements: each input 2492 // turns into multiple outputs. 2493 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 2494 SmallVector<SDOperand, 8> Ops; 2495 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2496 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 2497 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 2498 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2499 continue; 2500 } 2501 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 2502 2503 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 2504 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 2505 OpVal >>= DstBitSize; 2506 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 2507 } 2508 2509 // For big endian targets, swap the order of the pieces of each element. 2510 if (!TLI.isLittleEndian()) 2511 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 2512 } 2513 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2514 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2515 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2516} 2517 2518 2519 2520SDOperand DAGCombiner::visitFADD(SDNode *N) { 2521 SDOperand N0 = N->getOperand(0); 2522 SDOperand N1 = N->getOperand(1); 2523 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2524 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2525 MVT::ValueType VT = N->getValueType(0); 2526 2527 // fold (fadd c1, c2) -> c1+c2 2528 if (N0CFP && N1CFP) 2529 return DAG.getNode(ISD::FADD, VT, N0, N1); 2530 // canonicalize constant to RHS 2531 if (N0CFP && !N1CFP) 2532 return DAG.getNode(ISD::FADD, VT, N1, N0); 2533 // fold (A + (-B)) -> A-B 2534 if (N1.getOpcode() == ISD::FNEG) 2535 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 2536 // fold ((-A) + B) -> B-A 2537 if (N0.getOpcode() == ISD::FNEG) 2538 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 2539 2540 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 2541 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 2542 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 2543 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 2544 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 2545 2546 return SDOperand(); 2547} 2548 2549SDOperand DAGCombiner::visitFSUB(SDNode *N) { 2550 SDOperand N0 = N->getOperand(0); 2551 SDOperand N1 = N->getOperand(1); 2552 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2553 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2554 MVT::ValueType VT = N->getValueType(0); 2555 2556 // fold (fsub c1, c2) -> c1-c2 2557 if (N0CFP && N1CFP) 2558 return DAG.getNode(ISD::FSUB, VT, N0, N1); 2559 // fold (A-(-B)) -> A+B 2560 if (N1.getOpcode() == ISD::FNEG) 2561 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 2562 return SDOperand(); 2563} 2564 2565SDOperand DAGCombiner::visitFMUL(SDNode *N) { 2566 SDOperand N0 = N->getOperand(0); 2567 SDOperand N1 = N->getOperand(1); 2568 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2569 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2570 MVT::ValueType VT = N->getValueType(0); 2571 2572 // fold (fmul c1, c2) -> c1*c2 2573 if (N0CFP && N1CFP) 2574 return DAG.getNode(ISD::FMUL, VT, N0, N1); 2575 // canonicalize constant to RHS 2576 if (N0CFP && !N1CFP) 2577 return DAG.getNode(ISD::FMUL, VT, N1, N0); 2578 // fold (fmul X, 2.0) -> (fadd X, X) 2579 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 2580 return DAG.getNode(ISD::FADD, VT, N0, N0); 2581 2582 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 2583 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 2584 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 2585 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 2586 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 2587 2588 return SDOperand(); 2589} 2590 2591SDOperand DAGCombiner::visitFDIV(SDNode *N) { 2592 SDOperand N0 = N->getOperand(0); 2593 SDOperand N1 = N->getOperand(1); 2594 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2595 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2596 MVT::ValueType VT = N->getValueType(0); 2597 2598 // fold (fdiv c1, c2) -> c1/c2 2599 if (N0CFP && N1CFP) 2600 return DAG.getNode(ISD::FDIV, VT, N0, N1); 2601 return SDOperand(); 2602} 2603 2604SDOperand DAGCombiner::visitFREM(SDNode *N) { 2605 SDOperand N0 = N->getOperand(0); 2606 SDOperand N1 = N->getOperand(1); 2607 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2608 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2609 MVT::ValueType VT = N->getValueType(0); 2610 2611 // fold (frem c1, c2) -> fmod(c1,c2) 2612 if (N0CFP && N1CFP) 2613 return DAG.getNode(ISD::FREM, VT, N0, N1); 2614 return SDOperand(); 2615} 2616 2617SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 2618 SDOperand N0 = N->getOperand(0); 2619 SDOperand N1 = N->getOperand(1); 2620 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2621 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2622 MVT::ValueType VT = N->getValueType(0); 2623 2624 if (N0CFP && N1CFP) // Constant fold 2625 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 2626 2627 if (N1CFP) { 2628 // copysign(x, c1) -> fabs(x) iff ispos(c1) 2629 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 2630 union { 2631 double d; 2632 int64_t i; 2633 } u; 2634 u.d = N1CFP->getValue(); 2635 if (u.i >= 0) 2636 return DAG.getNode(ISD::FABS, VT, N0); 2637 else 2638 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 2639 } 2640 2641 // copysign(fabs(x), y) -> copysign(x, y) 2642 // copysign(fneg(x), y) -> copysign(x, y) 2643 // copysign(copysign(x,z), y) -> copysign(x, y) 2644 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 2645 N0.getOpcode() == ISD::FCOPYSIGN) 2646 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 2647 2648 // copysign(x, abs(y)) -> abs(x) 2649 if (N1.getOpcode() == ISD::FABS) 2650 return DAG.getNode(ISD::FABS, VT, N0); 2651 2652 // copysign(x, copysign(y,z)) -> copysign(x, z) 2653 if (N1.getOpcode() == ISD::FCOPYSIGN) 2654 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 2655 2656 // copysign(x, fp_extend(y)) -> copysign(x, y) 2657 // copysign(x, fp_round(y)) -> copysign(x, y) 2658 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 2659 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 2660 2661 return SDOperand(); 2662} 2663 2664 2665 2666SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 2667 SDOperand N0 = N->getOperand(0); 2668 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2669 MVT::ValueType VT = N->getValueType(0); 2670 2671 // fold (sint_to_fp c1) -> c1fp 2672 if (N0C) 2673 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 2674 return SDOperand(); 2675} 2676 2677SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 2678 SDOperand N0 = N->getOperand(0); 2679 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2680 MVT::ValueType VT = N->getValueType(0); 2681 2682 // fold (uint_to_fp c1) -> c1fp 2683 if (N0C) 2684 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 2685 return SDOperand(); 2686} 2687 2688SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 2689 SDOperand N0 = N->getOperand(0); 2690 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2691 MVT::ValueType VT = N->getValueType(0); 2692 2693 // fold (fp_to_sint c1fp) -> c1 2694 if (N0CFP) 2695 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 2696 return SDOperand(); 2697} 2698 2699SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 2700 SDOperand N0 = N->getOperand(0); 2701 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2702 MVT::ValueType VT = N->getValueType(0); 2703 2704 // fold (fp_to_uint c1fp) -> c1 2705 if (N0CFP) 2706 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 2707 return SDOperand(); 2708} 2709 2710SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 2711 SDOperand N0 = N->getOperand(0); 2712 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2713 MVT::ValueType VT = N->getValueType(0); 2714 2715 // fold (fp_round c1fp) -> c1fp 2716 if (N0CFP) 2717 return DAG.getNode(ISD::FP_ROUND, VT, N0); 2718 2719 // fold (fp_round (fp_extend x)) -> x 2720 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 2721 return N0.getOperand(0); 2722 2723 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 2724 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 2725 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 2726 AddToWorkList(Tmp.Val); 2727 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 2728 } 2729 2730 return SDOperand(); 2731} 2732 2733SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 2734 SDOperand N0 = N->getOperand(0); 2735 MVT::ValueType VT = N->getValueType(0); 2736 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2737 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2738 2739 // fold (fp_round_inreg c1fp) -> c1fp 2740 if (N0CFP) { 2741 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 2742 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 2743 } 2744 return SDOperand(); 2745} 2746 2747SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 2748 SDOperand N0 = N->getOperand(0); 2749 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2750 MVT::ValueType VT = N->getValueType(0); 2751 2752 // fold (fp_extend c1fp) -> c1fp 2753 if (N0CFP) 2754 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 2755 2756 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 2757 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2758 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2759 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2760 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2761 LN0->getBasePtr(), LN0->getSrcValue(), 2762 LN0->getSrcValueOffset(), 2763 N0.getValueType()); 2764 CombineTo(N, ExtLoad); 2765 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 2766 ExtLoad.getValue(1)); 2767 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2768 } 2769 2770 2771 return SDOperand(); 2772} 2773 2774SDOperand DAGCombiner::visitFNEG(SDNode *N) { 2775 SDOperand N0 = N->getOperand(0); 2776 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2777 MVT::ValueType VT = N->getValueType(0); 2778 2779 // fold (fneg c1) -> -c1 2780 if (N0CFP) 2781 return DAG.getNode(ISD::FNEG, VT, N0); 2782 // fold (fneg (sub x, y)) -> (sub y, x) 2783 if (N0.getOpcode() == ISD::SUB) 2784 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0)); 2785 // fold (fneg (fneg x)) -> x 2786 if (N0.getOpcode() == ISD::FNEG) 2787 return N0.getOperand(0); 2788 return SDOperand(); 2789} 2790 2791SDOperand DAGCombiner::visitFABS(SDNode *N) { 2792 SDOperand N0 = N->getOperand(0); 2793 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2794 MVT::ValueType VT = N->getValueType(0); 2795 2796 // fold (fabs c1) -> fabs(c1) 2797 if (N0CFP) 2798 return DAG.getNode(ISD::FABS, VT, N0); 2799 // fold (fabs (fabs x)) -> (fabs x) 2800 if (N0.getOpcode() == ISD::FABS) 2801 return N->getOperand(0); 2802 // fold (fabs (fneg x)) -> (fabs x) 2803 // fold (fabs (fcopysign x, y)) -> (fabs x) 2804 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 2805 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 2806 2807 return SDOperand(); 2808} 2809 2810SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 2811 SDOperand Chain = N->getOperand(0); 2812 SDOperand N1 = N->getOperand(1); 2813 SDOperand N2 = N->getOperand(2); 2814 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2815 2816 // never taken branch, fold to chain 2817 if (N1C && N1C->isNullValue()) 2818 return Chain; 2819 // unconditional branch 2820 if (N1C && N1C->getValue() == 1) 2821 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2822 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 2823 // on the target. 2824 if (N1.getOpcode() == ISD::SETCC && 2825 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 2826 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 2827 N1.getOperand(0), N1.getOperand(1), N2); 2828 } 2829 return SDOperand(); 2830} 2831 2832// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 2833// 2834SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 2835 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 2836 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 2837 2838 // Use SimplifySetCC to simplify SETCC's. 2839 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 2840 if (Simp.Val) AddToWorkList(Simp.Val); 2841 2842 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 2843 2844 // fold br_cc true, dest -> br dest (unconditional branch) 2845 if (SCCC && SCCC->getValue()) 2846 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 2847 N->getOperand(4)); 2848 // fold br_cc false, dest -> unconditional fall through 2849 if (SCCC && SCCC->isNullValue()) 2850 return N->getOperand(0); 2851 2852 // fold to a simpler setcc 2853 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 2854 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 2855 Simp.getOperand(2), Simp.getOperand(0), 2856 Simp.getOperand(1), N->getOperand(4)); 2857 return SDOperand(); 2858} 2859 2860 2861/// CombineToPreIndexedLoadStore - Try turning a load / store and a 2862/// pre-indexed load / store when the base pointer is a add or subtract 2863/// and it has other uses besides the load / store. After the 2864/// transformation, the new indexed load / store has effectively folded 2865/// the add / subtract in and all of its other uses are redirected to the 2866/// new load / store. 2867bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 2868 if (!AfterLegalize) 2869 return false; 2870 2871 bool isLoad = true; 2872 SDOperand Ptr; 2873 MVT::ValueType VT; 2874 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 2875 if (LD->getAddressingMode() != ISD::UNINDEXED) 2876 return false; 2877 VT = LD->getLoadedVT(); 2878 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 2879 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 2880 return false; 2881 Ptr = LD->getBasePtr(); 2882 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 2883 if (ST->getAddressingMode() != ISD::UNINDEXED) 2884 return false; 2885 VT = ST->getStoredVT(); 2886 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 2887 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 2888 return false; 2889 Ptr = ST->getBasePtr(); 2890 isLoad = false; 2891 } else 2892 return false; 2893 2894 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 2895 // out. There is no reason to make this a preinc/predec. 2896 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 2897 Ptr.Val->hasOneUse()) 2898 return false; 2899 2900 // Ask the target to do addressing mode selection. 2901 SDOperand BasePtr; 2902 SDOperand Offset; 2903 ISD::MemIndexedMode AM = ISD::UNINDEXED; 2904 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 2905 return false; 2906 2907 // Try turning it into a pre-indexed load / store except when: 2908 // 1) The base is a frame index. 2909 // 2) If N is a store and the ptr is either the same as or is a 2910 // predecessor of the value being stored. 2911 // 3) Another use of base ptr is a predecessor of N. If ptr is folded 2912 // that would create a cycle. 2913 // 4) All uses are load / store ops that use it as base ptr. 2914 2915 // Check #1. Preinc'ing a frame index would require copying the stack pointer 2916 // (plus the implicit offset) to a register to preinc anyway. 2917 if (isa<FrameIndexSDNode>(BasePtr)) 2918 return false; 2919 2920 // Check #2. 2921 if (!isLoad) { 2922 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 2923 if (Val == Ptr || Ptr.Val->isPredecessor(Val.Val)) 2924 return false; 2925 } 2926 2927 // Now check for #2 and #3. 2928 bool RealUse = false; 2929 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 2930 E = Ptr.Val->use_end(); I != E; ++I) { 2931 SDNode *Use = *I; 2932 if (Use == N) 2933 continue; 2934 if (Use->isPredecessor(N)) 2935 return false; 2936 2937 if (!((Use->getOpcode() == ISD::LOAD && 2938 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 2939 (Use->getOpcode() == ISD::STORE) && 2940 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 2941 RealUse = true; 2942 } 2943 if (!RealUse) 2944 return false; 2945 2946 SDOperand Result; 2947 if (isLoad) 2948 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 2949 else 2950 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 2951 ++PreIndexedNodes; 2952 ++NodesCombined; 2953 DOUT << "\nReplacing.4 "; DEBUG(N->dump()); 2954 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 2955 DOUT << '\n'; 2956 std::vector<SDNode*> NowDead; 2957 if (isLoad) { 2958 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 2959 NowDead); 2960 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 2961 NowDead); 2962 } else { 2963 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 2964 NowDead); 2965 } 2966 2967 // Nodes can end up on the worklist more than once. Make sure we do 2968 // not process a node that has been replaced. 2969 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 2970 removeFromWorkList(NowDead[i]); 2971 // Finally, since the node is now dead, remove it from the graph. 2972 DAG.DeleteNode(N); 2973 2974 // Replace the uses of Ptr with uses of the updated base value. 2975 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 2976 NowDead); 2977 removeFromWorkList(Ptr.Val); 2978 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 2979 removeFromWorkList(NowDead[i]); 2980 DAG.DeleteNode(Ptr.Val); 2981 2982 return true; 2983} 2984 2985/// CombineToPostIndexedLoadStore - Try combine a load / store with a 2986/// add / sub of the base pointer node into a post-indexed load / store. 2987/// The transformation folded the add / subtract into the new indexed 2988/// load / store effectively and all of its uses are redirected to the 2989/// new load / store. 2990bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 2991 if (!AfterLegalize) 2992 return false; 2993 2994 bool isLoad = true; 2995 SDOperand Ptr; 2996 MVT::ValueType VT; 2997 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 2998 if (LD->getAddressingMode() != ISD::UNINDEXED) 2999 return false; 3000 VT = LD->getLoadedVT(); 3001 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 3002 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 3003 return false; 3004 Ptr = LD->getBasePtr(); 3005 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3006 if (ST->getAddressingMode() != ISD::UNINDEXED) 3007 return false; 3008 VT = ST->getStoredVT(); 3009 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 3010 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 3011 return false; 3012 Ptr = ST->getBasePtr(); 3013 isLoad = false; 3014 } else 3015 return false; 3016 3017 if (Ptr.Val->hasOneUse()) 3018 return false; 3019 3020 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3021 E = Ptr.Val->use_end(); I != E; ++I) { 3022 SDNode *Op = *I; 3023 if (Op == N || 3024 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 3025 continue; 3026 3027 SDOperand BasePtr; 3028 SDOperand Offset; 3029 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3030 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 3031 if (Ptr == Offset) 3032 std::swap(BasePtr, Offset); 3033 if (Ptr != BasePtr) 3034 continue; 3035 3036 // Try turning it into a post-indexed load / store except when 3037 // 1) All uses are load / store ops that use it as base ptr. 3038 // 2) Op must be independent of N, i.e. Op is neither a predecessor 3039 // nor a successor of N. Otherwise, if Op is folded that would 3040 // create a cycle. 3041 3042 // Check for #1. 3043 bool TryNext = false; 3044 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 3045 EE = BasePtr.Val->use_end(); II != EE; ++II) { 3046 SDNode *Use = *II; 3047 if (Use == Ptr.Val) 3048 continue; 3049 3050 // If all the uses are load / store addresses, then don't do the 3051 // transformation. 3052 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 3053 bool RealUse = false; 3054 for (SDNode::use_iterator III = Use->use_begin(), 3055 EEE = Use->use_end(); III != EEE; ++III) { 3056 SDNode *UseUse = *III; 3057 if (!((UseUse->getOpcode() == ISD::LOAD && 3058 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 3059 (UseUse->getOpcode() == ISD::STORE) && 3060 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 3061 RealUse = true; 3062 } 3063 3064 if (!RealUse) { 3065 TryNext = true; 3066 break; 3067 } 3068 } 3069 } 3070 if (TryNext) 3071 continue; 3072 3073 // Check for #2 3074 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 3075 SDOperand Result = isLoad 3076 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 3077 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3078 ++PostIndexedNodes; 3079 ++NodesCombined; 3080 DOUT << "\nReplacing.5 "; DEBUG(N->dump()); 3081 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3082 DOUT << '\n'; 3083 std::vector<SDNode*> NowDead; 3084 if (isLoad) { 3085 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3086 NowDead); 3087 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3088 NowDead); 3089 } else { 3090 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3091 NowDead); 3092 } 3093 3094 // Nodes can end up on the worklist more than once. Make sure we do 3095 // not process a node that has been replaced. 3096 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3097 removeFromWorkList(NowDead[i]); 3098 // Finally, since the node is now dead, remove it from the graph. 3099 DAG.DeleteNode(N); 3100 3101 // Replace the uses of Use with uses of the updated base value. 3102 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 3103 Result.getValue(isLoad ? 1 : 0), 3104 NowDead); 3105 removeFromWorkList(Op); 3106 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3107 removeFromWorkList(NowDead[i]); 3108 DAG.DeleteNode(Op); 3109 3110 return true; 3111 } 3112 } 3113 } 3114 return false; 3115} 3116 3117 3118SDOperand DAGCombiner::visitLOAD(SDNode *N) { 3119 LoadSDNode *LD = cast<LoadSDNode>(N); 3120 SDOperand Chain = LD->getChain(); 3121 SDOperand Ptr = LD->getBasePtr(); 3122 3123 // If there are no uses of the loaded value, change uses of the chain value 3124 // into uses of the chain input (i.e. delete the dead load). 3125 if (N->hasNUsesOfValue(0, 0)) 3126 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 3127 3128 // If this load is directly stored, replace the load value with the stored 3129 // value. 3130 // TODO: Handle store large -> read small portion. 3131 // TODO: Handle TRUNCSTORE/LOADEXT 3132 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3133 if (ISD::isNON_TRUNCStore(Chain.Val)) { 3134 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 3135 if (PrevST->getBasePtr() == Ptr && 3136 PrevST->getValue().getValueType() == N->getValueType(0)) 3137 return CombineTo(N, Chain.getOperand(1), Chain); 3138 } 3139 } 3140 3141 if (CombinerAA) { 3142 // Walk up chain skipping non-aliasing memory nodes. 3143 SDOperand BetterChain = FindBetterChain(N, Chain); 3144 3145 // If there is a better chain. 3146 if (Chain != BetterChain) { 3147 SDOperand ReplLoad; 3148 3149 // Replace the chain to void dependency. 3150 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3151 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 3152 LD->getSrcValue(), LD->getSrcValueOffset()); 3153 } else { 3154 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 3155 LD->getValueType(0), 3156 BetterChain, Ptr, LD->getSrcValue(), 3157 LD->getSrcValueOffset(), 3158 LD->getLoadedVT()); 3159 } 3160 3161 // Create token factor to keep old chain connected. 3162 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 3163 Chain, ReplLoad.getValue(1)); 3164 3165 // Replace uses with load result and token factor. Don't add users 3166 // to work list. 3167 return CombineTo(N, ReplLoad.getValue(0), Token, false); 3168 } 3169 } 3170 3171 // Try transforming N to an indexed load. 3172 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3173 return SDOperand(N, 0); 3174 3175 return SDOperand(); 3176} 3177 3178SDOperand DAGCombiner::visitSTORE(SDNode *N) { 3179 StoreSDNode *ST = cast<StoreSDNode>(N); 3180 SDOperand Chain = ST->getChain(); 3181 SDOperand Value = ST->getValue(); 3182 SDOperand Ptr = ST->getBasePtr(); 3183 3184 // If this is a store of a bit convert, store the input value. 3185 // FIXME: This needs to know that the resultant store does not need a 3186 // higher alignment than the original. 3187 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) { 3188 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 3189 ST->getSrcValueOffset()); 3190 } 3191 3192 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 3193 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 3194 if (Value.getOpcode() != ISD::TargetConstantFP) { 3195 SDOperand Tmp; 3196 switch (CFP->getValueType(0)) { 3197 default: assert(0 && "Unknown FP type"); 3198 case MVT::f32: 3199 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 3200 Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 3201 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3202 ST->getSrcValueOffset()); 3203 } 3204 break; 3205 case MVT::f64: 3206 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 3207 Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 3208 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3209 ST->getSrcValueOffset()); 3210 } else if (TLI.isTypeLegal(MVT::i32)) { 3211 // Many FP stores are not make apparent until after legalize, e.g. for 3212 // argument passing. Since this is so common, custom legalize the 3213 // 64-bit integer store into two 32-bit stores. 3214 uint64_t Val = DoubleToBits(CFP->getValue()); 3215 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 3216 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 3217 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 3218 3219 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 3220 ST->getSrcValueOffset()); 3221 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3222 DAG.getConstant(4, Ptr.getValueType())); 3223 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 3224 ST->getSrcValueOffset()+4); 3225 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 3226 } 3227 break; 3228 } 3229 } 3230 } 3231 3232 if (CombinerAA) { 3233 // Walk up chain skipping non-aliasing memory nodes. 3234 SDOperand BetterChain = FindBetterChain(N, Chain); 3235 3236 // If there is a better chain. 3237 if (Chain != BetterChain) { 3238 // Replace the chain to avoid dependency. 3239 SDOperand ReplStore; 3240 if (ST->isTruncatingStore()) { 3241 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 3242 ST->getSrcValue(),ST->getSrcValueOffset(), ST->getStoredVT()); 3243 } else { 3244 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 3245 ST->getSrcValue(), ST->getSrcValueOffset()); 3246 } 3247 3248 // Create token to keep both nodes around. 3249 SDOperand Token = 3250 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 3251 3252 // Don't add users to work list. 3253 return CombineTo(N, Token, false); 3254 } 3255 } 3256 3257 // Try transforming N to an indexed store. 3258 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3259 return SDOperand(N, 0); 3260 3261 return SDOperand(); 3262} 3263 3264SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 3265 SDOperand InVec = N->getOperand(0); 3266 SDOperand InVal = N->getOperand(1); 3267 SDOperand EltNo = N->getOperand(2); 3268 3269 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 3270 // vector with the inserted element. 3271 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 3272 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 3273 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 3274 if (Elt < Ops.size()) 3275 Ops[Elt] = InVal; 3276 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 3277 &Ops[0], Ops.size()); 3278 } 3279 3280 return SDOperand(); 3281} 3282 3283SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) { 3284 SDOperand InVec = N->getOperand(0); 3285 SDOperand InVal = N->getOperand(1); 3286 SDOperand EltNo = N->getOperand(2); 3287 SDOperand NumElts = N->getOperand(3); 3288 SDOperand EltType = N->getOperand(4); 3289 3290 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new 3291 // vector with the inserted element. 3292 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 3293 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 3294 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 3295 if (Elt < Ops.size()-2) 3296 Ops[Elt] = InVal; 3297 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), 3298 &Ops[0], Ops.size()); 3299 } 3300 3301 return SDOperand(); 3302} 3303 3304SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) { 3305 unsigned NumInScalars = N->getNumOperands()-2; 3306 SDOperand NumElts = N->getOperand(NumInScalars); 3307 SDOperand EltType = N->getOperand(NumInScalars+1); 3308 3309 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT 3310 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most 3311 // two distinct vectors, turn this into a shuffle node. 3312 SDOperand VecIn1, VecIn2; 3313 for (unsigned i = 0; i != NumInScalars; ++i) { 3314 // Ignore undef inputs. 3315 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 3316 3317 // If this input is something other than a VEXTRACT_VECTOR_ELT with a 3318 // constant index, bail out. 3319 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT || 3320 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 3321 VecIn1 = VecIn2 = SDOperand(0, 0); 3322 break; 3323 } 3324 3325 // If the input vector type disagrees with the result of the vbuild_vector, 3326 // we can't make a shuffle. 3327 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 3328 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts || 3329 *(ExtractedFromVec.Val->op_end()-1) != EltType) { 3330 VecIn1 = VecIn2 = SDOperand(0, 0); 3331 break; 3332 } 3333 3334 // Otherwise, remember this. We allow up to two distinct input vectors. 3335 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 3336 continue; 3337 3338 if (VecIn1.Val == 0) { 3339 VecIn1 = ExtractedFromVec; 3340 } else if (VecIn2.Val == 0) { 3341 VecIn2 = ExtractedFromVec; 3342 } else { 3343 // Too many inputs. 3344 VecIn1 = VecIn2 = SDOperand(0, 0); 3345 break; 3346 } 3347 } 3348 3349 // If everything is good, we can make a shuffle operation. 3350 if (VecIn1.Val) { 3351 SmallVector<SDOperand, 8> BuildVecIndices; 3352 for (unsigned i = 0; i != NumInScalars; ++i) { 3353 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 3354 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 3355 continue; 3356 } 3357 3358 SDOperand Extract = N->getOperand(i); 3359 3360 // If extracting from the first vector, just use the index directly. 3361 if (Extract.getOperand(0) == VecIn1) { 3362 BuildVecIndices.push_back(Extract.getOperand(1)); 3363 continue; 3364 } 3365 3366 // Otherwise, use InIdx + VecSize 3367 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 3368 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, 3369 TLI.getPointerTy())); 3370 } 3371 3372 // Add count and size info. 3373 BuildVecIndices.push_back(NumElts); 3374 BuildVecIndices.push_back(DAG.getValueType(TLI.getPointerTy())); 3375 3376 // Return the new VVECTOR_SHUFFLE node. 3377 SDOperand Ops[5]; 3378 Ops[0] = VecIn1; 3379 if (VecIn2.Val) { 3380 Ops[1] = VecIn2; 3381 } else { 3382 // Use an undef vbuild_vector as input for the second operand. 3383 std::vector<SDOperand> UnOps(NumInScalars, 3384 DAG.getNode(ISD::UNDEF, 3385 cast<VTSDNode>(EltType)->getVT())); 3386 UnOps.push_back(NumElts); 3387 UnOps.push_back(EltType); 3388 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3389 &UnOps[0], UnOps.size()); 3390 AddToWorkList(Ops[1].Val); 3391 } 3392 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3393 &BuildVecIndices[0], BuildVecIndices.size()); 3394 Ops[3] = NumElts; 3395 Ops[4] = EltType; 3396 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5); 3397 } 3398 3399 return SDOperand(); 3400} 3401 3402SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 3403 SDOperand ShufMask = N->getOperand(2); 3404 unsigned NumElts = ShufMask.getNumOperands(); 3405 3406 // If the shuffle mask is an identity operation on the LHS, return the LHS. 3407 bool isIdentity = true; 3408 for (unsigned i = 0; i != NumElts; ++i) { 3409 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3410 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 3411 isIdentity = false; 3412 break; 3413 } 3414 } 3415 if (isIdentity) return N->getOperand(0); 3416 3417 // If the shuffle mask is an identity operation on the RHS, return the RHS. 3418 isIdentity = true; 3419 for (unsigned i = 0; i != NumElts; ++i) { 3420 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3421 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 3422 isIdentity = false; 3423 break; 3424 } 3425 } 3426 if (isIdentity) return N->getOperand(1); 3427 3428 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 3429 // needed at all. 3430 bool isUnary = true; 3431 bool isSplat = true; 3432 int VecNum = -1; 3433 unsigned BaseIdx = 0; 3434 for (unsigned i = 0; i != NumElts; ++i) 3435 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 3436 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 3437 int V = (Idx < NumElts) ? 0 : 1; 3438 if (VecNum == -1) { 3439 VecNum = V; 3440 BaseIdx = Idx; 3441 } else { 3442 if (BaseIdx != Idx) 3443 isSplat = false; 3444 if (VecNum != V) { 3445 isUnary = false; 3446 break; 3447 } 3448 } 3449 } 3450 3451 SDOperand N0 = N->getOperand(0); 3452 SDOperand N1 = N->getOperand(1); 3453 // Normalize unary shuffle so the RHS is undef. 3454 if (isUnary && VecNum == 1) 3455 std::swap(N0, N1); 3456 3457 // If it is a splat, check if the argument vector is a build_vector with 3458 // all scalar elements the same. 3459 if (isSplat) { 3460 SDNode *V = N0.Val; 3461 if (V->getOpcode() == ISD::BIT_CONVERT) 3462 V = V->getOperand(0).Val; 3463 if (V->getOpcode() == ISD::BUILD_VECTOR) { 3464 unsigned NumElems = V->getNumOperands()-2; 3465 if (NumElems > BaseIdx) { 3466 SDOperand Base; 3467 bool AllSame = true; 3468 for (unsigned i = 0; i != NumElems; ++i) { 3469 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 3470 Base = V->getOperand(i); 3471 break; 3472 } 3473 } 3474 // Splat of <u, u, u, u>, return <u, u, u, u> 3475 if (!Base.Val) 3476 return N0; 3477 for (unsigned i = 0; i != NumElems; ++i) { 3478 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 3479 V->getOperand(i) != Base) { 3480 AllSame = false; 3481 break; 3482 } 3483 } 3484 // Splat of <x, x, x, x>, return <x, x, x, x> 3485 if (AllSame) 3486 return N0; 3487 } 3488 } 3489 } 3490 3491 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 3492 // into an undef. 3493 if (isUnary || N0 == N1) { 3494 if (N0.getOpcode() == ISD::UNDEF) 3495 return DAG.getNode(ISD::UNDEF, N->getValueType(0)); 3496 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 3497 // first operand. 3498 SmallVector<SDOperand, 8> MappedOps; 3499 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) { 3500 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 3501 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 3502 MappedOps.push_back(ShufMask.getOperand(i)); 3503 } else { 3504 unsigned NewIdx = 3505 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 3506 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 3507 } 3508 } 3509 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 3510 &MappedOps[0], MappedOps.size()); 3511 AddToWorkList(ShufMask.Val); 3512 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 3513 N0, 3514 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 3515 ShufMask); 3516 } 3517 3518 return SDOperand(); 3519} 3520 3521SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) { 3522 SDOperand ShufMask = N->getOperand(2); 3523 unsigned NumElts = ShufMask.getNumOperands()-2; 3524 3525 // If the shuffle mask is an identity operation on the LHS, return the LHS. 3526 bool isIdentity = true; 3527 for (unsigned i = 0; i != NumElts; ++i) { 3528 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3529 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 3530 isIdentity = false; 3531 break; 3532 } 3533 } 3534 if (isIdentity) return N->getOperand(0); 3535 3536 // If the shuffle mask is an identity operation on the RHS, return the RHS. 3537 isIdentity = true; 3538 for (unsigned i = 0; i != NumElts; ++i) { 3539 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3540 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 3541 isIdentity = false; 3542 break; 3543 } 3544 } 3545 if (isIdentity) return N->getOperand(1); 3546 3547 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 3548 // needed at all. 3549 bool isUnary = true; 3550 bool isSplat = true; 3551 int VecNum = -1; 3552 unsigned BaseIdx = 0; 3553 for (unsigned i = 0; i != NumElts; ++i) 3554 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 3555 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 3556 int V = (Idx < NumElts) ? 0 : 1; 3557 if (VecNum == -1) { 3558 VecNum = V; 3559 BaseIdx = Idx; 3560 } else { 3561 if (BaseIdx != Idx) 3562 isSplat = false; 3563 if (VecNum != V) { 3564 isUnary = false; 3565 break; 3566 } 3567 } 3568 } 3569 3570 SDOperand N0 = N->getOperand(0); 3571 SDOperand N1 = N->getOperand(1); 3572 // Normalize unary shuffle so the RHS is undef. 3573 if (isUnary && VecNum == 1) 3574 std::swap(N0, N1); 3575 3576 // If it is a splat, check if the argument vector is a build_vector with 3577 // all scalar elements the same. 3578 if (isSplat) { 3579 SDNode *V = N0.Val; 3580 3581 // If this is a vbit convert that changes the element type of the vector but 3582 // not the number of vector elements, look through it. Be careful not to 3583 // look though conversions that change things like v4f32 to v2f64. 3584 if (V->getOpcode() == ISD::VBIT_CONVERT) { 3585 SDOperand ConvInput = V->getOperand(0); 3586 if (ConvInput.getValueType() == MVT::Vector && 3587 NumElts == 3588 ConvInput.getConstantOperandVal(ConvInput.getNumOperands()-2)) 3589 V = ConvInput.Val; 3590 } 3591 3592 if (V->getOpcode() == ISD::VBUILD_VECTOR) { 3593 unsigned NumElems = V->getNumOperands()-2; 3594 if (NumElems > BaseIdx) { 3595 SDOperand Base; 3596 bool AllSame = true; 3597 for (unsigned i = 0; i != NumElems; ++i) { 3598 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 3599 Base = V->getOperand(i); 3600 break; 3601 } 3602 } 3603 // Splat of <u, u, u, u>, return <u, u, u, u> 3604 if (!Base.Val) 3605 return N0; 3606 for (unsigned i = 0; i != NumElems; ++i) { 3607 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 3608 V->getOperand(i) != Base) { 3609 AllSame = false; 3610 break; 3611 } 3612 } 3613 // Splat of <x, x, x, x>, return <x, x, x, x> 3614 if (AllSame) 3615 return N0; 3616 } 3617 } 3618 } 3619 3620 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 3621 // into an undef. 3622 if (isUnary || N0 == N1) { 3623 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 3624 // first operand. 3625 SmallVector<SDOperand, 8> MappedOps; 3626 for (unsigned i = 0; i != NumElts; ++i) { 3627 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 3628 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 3629 MappedOps.push_back(ShufMask.getOperand(i)); 3630 } else { 3631 unsigned NewIdx = 3632 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 3633 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 3634 } 3635 } 3636 // Add the type/#elts values. 3637 MappedOps.push_back(ShufMask.getOperand(NumElts)); 3638 MappedOps.push_back(ShufMask.getOperand(NumElts+1)); 3639 3640 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(), 3641 &MappedOps[0], MappedOps.size()); 3642 AddToWorkList(ShufMask.Val); 3643 3644 // Build the undef vector. 3645 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType()); 3646 for (unsigned i = 0; i != NumElts; ++i) 3647 MappedOps[i] = UDVal; 3648 MappedOps[NumElts ] = *(N0.Val->op_end()-2); 3649 MappedOps[NumElts+1] = *(N0.Val->op_end()-1); 3650 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3651 &MappedOps[0], MappedOps.size()); 3652 3653 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 3654 N0, UDVal, ShufMask, 3655 MappedOps[NumElts], MappedOps[NumElts+1]); 3656 } 3657 3658 return SDOperand(); 3659} 3660 3661/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 3662/// a VAND to a vector_shuffle with the destination vector and a zero vector. 3663/// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 3664/// vector_shuffle V, Zero, <0, 4, 2, 4> 3665SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 3666 SDOperand LHS = N->getOperand(0); 3667 SDOperand RHS = N->getOperand(1); 3668 if (N->getOpcode() == ISD::VAND) { 3669 SDOperand DstVecSize = *(LHS.Val->op_end()-2); 3670 SDOperand DstVecEVT = *(LHS.Val->op_end()-1); 3671 if (RHS.getOpcode() == ISD::VBIT_CONVERT) 3672 RHS = RHS.getOperand(0); 3673 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) { 3674 std::vector<SDOperand> IdxOps; 3675 unsigned NumOps = RHS.getNumOperands(); 3676 unsigned NumElts = NumOps-2; 3677 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT(); 3678 for (unsigned i = 0; i != NumElts; ++i) { 3679 SDOperand Elt = RHS.getOperand(i); 3680 if (!isa<ConstantSDNode>(Elt)) 3681 return SDOperand(); 3682 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 3683 IdxOps.push_back(DAG.getConstant(i, EVT)); 3684 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 3685 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 3686 else 3687 return SDOperand(); 3688 } 3689 3690 // Let's see if the target supports this vector_shuffle. 3691 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 3692 return SDOperand(); 3693 3694 // Return the new VVECTOR_SHUFFLE node. 3695 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32); 3696 SDOperand EVTNode = DAG.getValueType(EVT); 3697 std::vector<SDOperand> Ops; 3698 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode, 3699 EVTNode); 3700 Ops.push_back(LHS); 3701 AddToWorkList(LHS.Val); 3702 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 3703 ZeroOps.push_back(NumEltsNode); 3704 ZeroOps.push_back(EVTNode); 3705 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3706 &ZeroOps[0], ZeroOps.size())); 3707 IdxOps.push_back(NumEltsNode); 3708 IdxOps.push_back(EVTNode); 3709 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3710 &IdxOps[0], IdxOps.size())); 3711 Ops.push_back(NumEltsNode); 3712 Ops.push_back(EVTNode); 3713 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 3714 &Ops[0], Ops.size()); 3715 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) { 3716 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 3717 DstVecSize, DstVecEVT); 3718 } 3719 return Result; 3720 } 3721 } 3722 return SDOperand(); 3723} 3724 3725/// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates 3726/// the scalar operation of the vop if it is operating on an integer vector 3727/// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD). 3728SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp, 3729 ISD::NodeType FPOp) { 3730 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT(); 3731 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp; 3732 SDOperand LHS = N->getOperand(0); 3733 SDOperand RHS = N->getOperand(1); 3734 SDOperand Shuffle = XformToShuffleWithZero(N); 3735 if (Shuffle.Val) return Shuffle; 3736 3737 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold 3738 // this operation. 3739 if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 3740 RHS.getOpcode() == ISD::VBUILD_VECTOR) { 3741 SmallVector<SDOperand, 8> Ops; 3742 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) { 3743 SDOperand LHSOp = LHS.getOperand(i); 3744 SDOperand RHSOp = RHS.getOperand(i); 3745 // If these two elements can't be folded, bail out. 3746 if ((LHSOp.getOpcode() != ISD::UNDEF && 3747 LHSOp.getOpcode() != ISD::Constant && 3748 LHSOp.getOpcode() != ISD::ConstantFP) || 3749 (RHSOp.getOpcode() != ISD::UNDEF && 3750 RHSOp.getOpcode() != ISD::Constant && 3751 RHSOp.getOpcode() != ISD::ConstantFP)) 3752 break; 3753 // Can't fold divide by zero. 3754 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) { 3755 if ((RHSOp.getOpcode() == ISD::Constant && 3756 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 3757 (RHSOp.getOpcode() == ISD::ConstantFP && 3758 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue())) 3759 break; 3760 } 3761 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp)); 3762 AddToWorkList(Ops.back().Val); 3763 assert((Ops.back().getOpcode() == ISD::UNDEF || 3764 Ops.back().getOpcode() == ISD::Constant || 3765 Ops.back().getOpcode() == ISD::ConstantFP) && 3766 "Scalar binop didn't fold!"); 3767 } 3768 3769 if (Ops.size() == LHS.getNumOperands()-2) { 3770 Ops.push_back(*(LHS.Val->op_end()-2)); 3771 Ops.push_back(*(LHS.Val->op_end()-1)); 3772 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 3773 } 3774 } 3775 3776 return SDOperand(); 3777} 3778 3779SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 3780 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 3781 3782 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 3783 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3784 // If we got a simplified select_cc node back from SimplifySelectCC, then 3785 // break it down into a new SETCC node, and a new SELECT node, and then return 3786 // the SELECT node, since we were called with a SELECT node. 3787 if (SCC.Val) { 3788 // Check to see if we got a select_cc back (to turn into setcc/select). 3789 // Otherwise, just return whatever node we got back, like fabs. 3790 if (SCC.getOpcode() == ISD::SELECT_CC) { 3791 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 3792 SCC.getOperand(0), SCC.getOperand(1), 3793 SCC.getOperand(4)); 3794 AddToWorkList(SETCC.Val); 3795 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 3796 SCC.getOperand(3), SETCC); 3797 } 3798 return SCC; 3799 } 3800 return SDOperand(); 3801} 3802 3803/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 3804/// are the two values being selected between, see if we can simplify the 3805/// select. Callers of this should assume that TheSelect is deleted if this 3806/// returns true. As such, they should return the appropriate thing (e.g. the 3807/// node) back to the top-level of the DAG combiner loop to avoid it being 3808/// looked at. 3809/// 3810bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 3811 SDOperand RHS) { 3812 3813 // If this is a select from two identical things, try to pull the operation 3814 // through the select. 3815 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 3816 // If this is a load and the token chain is identical, replace the select 3817 // of two loads with a load through a select of the address to load from. 3818 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 3819 // constants have been dropped into the constant pool. 3820 if (LHS.getOpcode() == ISD::LOAD && 3821 // Token chains must be identical. 3822 LHS.getOperand(0) == RHS.getOperand(0)) { 3823 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 3824 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 3825 3826 // If this is an EXTLOAD, the VT's must match. 3827 if (LLD->getLoadedVT() == RLD->getLoadedVT()) { 3828 // FIXME: this conflates two src values, discarding one. This is not 3829 // the right thing to do, but nothing uses srcvalues now. When they do, 3830 // turn SrcValue into a list of locations. 3831 SDOperand Addr; 3832 if (TheSelect->getOpcode() == ISD::SELECT) { 3833 // Check that the condition doesn't reach either load. If so, folding 3834 // this will induce a cycle into the DAG. 3835 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 3836 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 3837 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 3838 TheSelect->getOperand(0), LLD->getBasePtr(), 3839 RLD->getBasePtr()); 3840 } 3841 } else { 3842 // Check that the condition doesn't reach either load. If so, folding 3843 // this will induce a cycle into the DAG. 3844 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 3845 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 3846 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 3847 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 3848 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 3849 TheSelect->getOperand(0), 3850 TheSelect->getOperand(1), 3851 LLD->getBasePtr(), RLD->getBasePtr(), 3852 TheSelect->getOperand(4)); 3853 } 3854 } 3855 3856 if (Addr.Val) { 3857 SDOperand Load; 3858 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 3859 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 3860 Addr,LLD->getSrcValue(), 3861 LLD->getSrcValueOffset()); 3862 else { 3863 Load = DAG.getExtLoad(LLD->getExtensionType(), 3864 TheSelect->getValueType(0), 3865 LLD->getChain(), Addr, LLD->getSrcValue(), 3866 LLD->getSrcValueOffset(), 3867 LLD->getLoadedVT()); 3868 } 3869 // Users of the select now use the result of the load. 3870 CombineTo(TheSelect, Load); 3871 3872 // Users of the old loads now use the new load's chain. We know the 3873 // old-load value is dead now. 3874 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 3875 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 3876 return true; 3877 } 3878 } 3879 } 3880 } 3881 3882 return false; 3883} 3884 3885SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 3886 SDOperand N2, SDOperand N3, 3887 ISD::CondCode CC) { 3888 3889 MVT::ValueType VT = N2.getValueType(); 3890 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 3891 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 3892 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 3893 3894 // Determine if the condition we're dealing with is constant 3895 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 3896 if (SCC.Val) AddToWorkList(SCC.Val); 3897 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 3898 3899 // fold select_cc true, x, y -> x 3900 if (SCCC && SCCC->getValue()) 3901 return N2; 3902 // fold select_cc false, x, y -> y 3903 if (SCCC && SCCC->getValue() == 0) 3904 return N3; 3905 3906 // Check to see if we can simplify the select into an fabs node 3907 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 3908 // Allow either -0.0 or 0.0 3909 if (CFP->getValue() == 0.0) { 3910 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 3911 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 3912 N0 == N2 && N3.getOpcode() == ISD::FNEG && 3913 N2 == N3.getOperand(0)) 3914 return DAG.getNode(ISD::FABS, VT, N0); 3915 3916 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 3917 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 3918 N0 == N3 && N2.getOpcode() == ISD::FNEG && 3919 N2.getOperand(0) == N3) 3920 return DAG.getNode(ISD::FABS, VT, N3); 3921 } 3922 } 3923 3924 // Check to see if we can perform the "gzip trick", transforming 3925 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 3926 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 3927 MVT::isInteger(N0.getValueType()) && 3928 MVT::isInteger(N2.getValueType()) && 3929 (N1C->isNullValue() || // (a < 0) ? b : 0 3930 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 3931 MVT::ValueType XType = N0.getValueType(); 3932 MVT::ValueType AType = N2.getValueType(); 3933 if (XType >= AType) { 3934 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 3935 // single-bit constant. 3936 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 3937 unsigned ShCtV = Log2_64(N2C->getValue()); 3938 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 3939 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 3940 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 3941 AddToWorkList(Shift.Val); 3942 if (XType > AType) { 3943 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 3944 AddToWorkList(Shift.Val); 3945 } 3946 return DAG.getNode(ISD::AND, AType, Shift, N2); 3947 } 3948 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 3949 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3950 TLI.getShiftAmountTy())); 3951 AddToWorkList(Shift.Val); 3952 if (XType > AType) { 3953 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 3954 AddToWorkList(Shift.Val); 3955 } 3956 return DAG.getNode(ISD::AND, AType, Shift, N2); 3957 } 3958 } 3959 3960 // fold select C, 16, 0 -> shl C, 4 3961 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 3962 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 3963 // Get a SetCC of the condition 3964 // FIXME: Should probably make sure that setcc is legal if we ever have a 3965 // target where it isn't. 3966 SDOperand Temp, SCC; 3967 // cast from setcc result type to select result type 3968 if (AfterLegalize) { 3969 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 3970 if (N2.getValueType() < SCC.getValueType()) 3971 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 3972 else 3973 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 3974 } else { 3975 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 3976 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 3977 } 3978 AddToWorkList(SCC.Val); 3979 AddToWorkList(Temp.Val); 3980 // shl setcc result by log2 n2c 3981 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 3982 DAG.getConstant(Log2_64(N2C->getValue()), 3983 TLI.getShiftAmountTy())); 3984 } 3985 3986 // Check to see if this is the equivalent of setcc 3987 // FIXME: Turn all of these into setcc if setcc if setcc is legal 3988 // otherwise, go ahead with the folds. 3989 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 3990 MVT::ValueType XType = N0.getValueType(); 3991 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 3992 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 3993 if (Res.getValueType() != VT) 3994 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 3995 return Res; 3996 } 3997 3998 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 3999 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 4000 TLI.isOperationLegal(ISD::CTLZ, XType)) { 4001 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 4002 return DAG.getNode(ISD::SRL, XType, Ctlz, 4003 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 4004 TLI.getShiftAmountTy())); 4005 } 4006 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 4007 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 4008 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 4009 N0); 4010 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 4011 DAG.getConstant(~0ULL, XType)); 4012 return DAG.getNode(ISD::SRL, XType, 4013 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 4014 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4015 TLI.getShiftAmountTy())); 4016 } 4017 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 4018 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 4019 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 4020 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4021 TLI.getShiftAmountTy())); 4022 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 4023 } 4024 } 4025 4026 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 4027 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4028 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 4029 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 4030 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 4031 MVT::ValueType XType = N0.getValueType(); 4032 if (SubC->isNullValue() && MVT::isInteger(XType)) { 4033 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4034 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4035 TLI.getShiftAmountTy())); 4036 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4037 AddToWorkList(Shift.Val); 4038 AddToWorkList(Add.Val); 4039 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4040 } 4041 } 4042 } 4043 4044 return SDOperand(); 4045} 4046 4047/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 4048SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 4049 SDOperand N1, ISD::CondCode Cond, 4050 bool foldBooleans) { 4051 TargetLowering::DAGCombinerInfo 4052 DagCombineInfo(DAG, !AfterLegalize, false, this); 4053 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 4054} 4055 4056/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 4057/// return a DAG expression to select that will generate the same value by 4058/// multiplying by a magic number. See: 4059/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4060SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 4061 std::vector<SDNode*> Built; 4062 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 4063 4064 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4065 ii != ee; ++ii) 4066 AddToWorkList(*ii); 4067 return S; 4068} 4069 4070/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 4071/// return a DAG expression to select that will generate the same value by 4072/// multiplying by a magic number. See: 4073/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4074SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 4075 std::vector<SDNode*> Built; 4076 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 4077 4078 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4079 ii != ee; ++ii) 4080 AddToWorkList(*ii); 4081 return S; 4082} 4083 4084/// FindBaseOffset - Return true if base is known not to alias with anything 4085/// but itself. Provides base object and offset as results. 4086static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 4087 // Assume it is a primitive operation. 4088 Base = Ptr; Offset = 0; 4089 4090 // If it's an adding a simple constant then integrate the offset. 4091 if (Base.getOpcode() == ISD::ADD) { 4092 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 4093 Base = Base.getOperand(0); 4094 Offset += C->getValue(); 4095 } 4096 } 4097 4098 // If it's any of the following then it can't alias with anything but itself. 4099 return isa<FrameIndexSDNode>(Base) || 4100 isa<ConstantPoolSDNode>(Base) || 4101 isa<GlobalAddressSDNode>(Base); 4102} 4103 4104/// isAlias - Return true if there is any possibility that the two addresses 4105/// overlap. 4106bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 4107 const Value *SrcValue1, int SrcValueOffset1, 4108 SDOperand Ptr2, int64_t Size2, 4109 const Value *SrcValue2, int SrcValueOffset2) 4110{ 4111 // If they are the same then they must be aliases. 4112 if (Ptr1 == Ptr2) return true; 4113 4114 // Gather base node and offset information. 4115 SDOperand Base1, Base2; 4116 int64_t Offset1, Offset2; 4117 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 4118 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 4119 4120 // If they have a same base address then... 4121 if (Base1 == Base2) { 4122 // Check to see if the addresses overlap. 4123 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 4124 } 4125 4126 // If we know both bases then they can't alias. 4127 if (KnownBase1 && KnownBase2) return false; 4128 4129 if (CombinerGlobalAA) { 4130 // Use alias analysis information. 4131 int Overlap1 = Size1 + SrcValueOffset1 + Offset1; 4132 int Overlap2 = Size2 + SrcValueOffset2 + Offset2; 4133 AliasAnalysis::AliasResult AAResult = 4134 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 4135 if (AAResult == AliasAnalysis::NoAlias) 4136 return false; 4137 } 4138 4139 // Otherwise we have to assume they alias. 4140 return true; 4141} 4142 4143/// FindAliasInfo - Extracts the relevant alias information from the memory 4144/// node. Returns true if the operand was a load. 4145bool DAGCombiner::FindAliasInfo(SDNode *N, 4146 SDOperand &Ptr, int64_t &Size, 4147 const Value *&SrcValue, int &SrcValueOffset) { 4148 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4149 Ptr = LD->getBasePtr(); 4150 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3; 4151 SrcValue = LD->getSrcValue(); 4152 SrcValueOffset = LD->getSrcValueOffset(); 4153 return true; 4154 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4155 Ptr = ST->getBasePtr(); 4156 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3; 4157 SrcValue = ST->getSrcValue(); 4158 SrcValueOffset = ST->getSrcValueOffset(); 4159 } else { 4160 assert(0 && "FindAliasInfo expected a memory operand"); 4161 } 4162 4163 return false; 4164} 4165 4166/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 4167/// looking for aliasing nodes and adding them to the Aliases vector. 4168void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 4169 SmallVector<SDOperand, 8> &Aliases) { 4170 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 4171 std::set<SDNode *> Visited; // Visited node set. 4172 4173 // Get alias information for node. 4174 SDOperand Ptr; 4175 int64_t Size; 4176 const Value *SrcValue; 4177 int SrcValueOffset; 4178 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 4179 4180 // Starting off. 4181 Chains.push_back(OriginalChain); 4182 4183 // Look at each chain and determine if it is an alias. If so, add it to the 4184 // aliases list. If not, then continue up the chain looking for the next 4185 // candidate. 4186 while (!Chains.empty()) { 4187 SDOperand Chain = Chains.back(); 4188 Chains.pop_back(); 4189 4190 // Don't bother if we've been before. 4191 if (Visited.find(Chain.Val) != Visited.end()) continue; 4192 Visited.insert(Chain.Val); 4193 4194 switch (Chain.getOpcode()) { 4195 case ISD::EntryToken: 4196 // Entry token is ideal chain operand, but handled in FindBetterChain. 4197 break; 4198 4199 case ISD::LOAD: 4200 case ISD::STORE: { 4201 // Get alias information for Chain. 4202 SDOperand OpPtr; 4203 int64_t OpSize; 4204 const Value *OpSrcValue; 4205 int OpSrcValueOffset; 4206 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 4207 OpSrcValue, OpSrcValueOffset); 4208 4209 // If chain is alias then stop here. 4210 if (!(IsLoad && IsOpLoad) && 4211 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 4212 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 4213 Aliases.push_back(Chain); 4214 } else { 4215 // Look further up the chain. 4216 Chains.push_back(Chain.getOperand(0)); 4217 // Clean up old chain. 4218 AddToWorkList(Chain.Val); 4219 } 4220 break; 4221 } 4222 4223 case ISD::TokenFactor: 4224 // We have to check each of the operands of the token factor, so we queue 4225 // then up. Adding the operands to the queue (stack) in reverse order 4226 // maintains the original order and increases the likelihood that getNode 4227 // will find a matching token factor (CSE.) 4228 for (unsigned n = Chain.getNumOperands(); n;) 4229 Chains.push_back(Chain.getOperand(--n)); 4230 // Eliminate the token factor if we can. 4231 AddToWorkList(Chain.Val); 4232 break; 4233 4234 default: 4235 // For all other instructions we will just have to take what we can get. 4236 Aliases.push_back(Chain); 4237 break; 4238 } 4239 } 4240} 4241 4242/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 4243/// for a better chain (aliasing node.) 4244SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 4245 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 4246 4247 // Accumulate all the aliases to this node. 4248 GatherAllAliases(N, OldChain, Aliases); 4249 4250 if (Aliases.size() == 0) { 4251 // If no operands then chain to entry token. 4252 return DAG.getEntryNode(); 4253 } else if (Aliases.size() == 1) { 4254 // If a single operand then chain to it. We don't need to revisit it. 4255 return Aliases[0]; 4256 } 4257 4258 // Construct a custom tailored token factor. 4259 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4260 &Aliases[0], Aliases.size()); 4261 4262 // Make sure the old chain gets cleaned up. 4263 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 4264 4265 return NewChain; 4266} 4267 4268// SelectionDAG::Combine - This is the entry point for the file. 4269// 4270void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 4271 if (!RunningAfterLegalize && ViewDAGCombine1) 4272 viewGraph(); 4273 if (RunningAfterLegalize && ViewDAGCombine2) 4274 viewGraph(); 4275 /// run - This is the main entry point to this class. 4276 /// 4277 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 4278} 4279