DAGCombiner.cpp revision 9176b0169c8650fa6fb1d0464256d7c3e8ecf115
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: make truncate see through SIGN_EXTEND and AND 26// FIXME: divide by zero is currently left unfolded. do we want to turn this 27// into an undef? 28// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 29// 30//===----------------------------------------------------------------------===// 31 32#define DEBUG_TYPE "dagcombine" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Target/TargetLowering.h" 38#include <algorithm> 39#include <cmath> 40#include <iostream> 41using namespace llvm; 42 43namespace { 44 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined"); 45 46 class DAGCombiner { 47 SelectionDAG &DAG; 48 TargetLowering &TLI; 49 bool AfterLegalize; 50 51 // Worklist of all of the nodes that need to be simplified. 52 std::vector<SDNode*> WorkList; 53 54 /// AddUsersToWorkList - When an instruction is simplified, add all users of 55 /// the instruction to the work lists because they might get more simplified 56 /// now. 57 /// 58 void AddUsersToWorkList(SDNode *N) { 59 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 60 UI != UE; ++UI) 61 WorkList.push_back(*UI); 62 } 63 64 /// removeFromWorkList - remove all instances of N from the worklist. 65 /// 66 void removeFromWorkList(SDNode *N) { 67 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 68 WorkList.end()); 69 } 70 71 public: 72 void AddToWorkList(SDNode *N) { 73 WorkList.push_back(N); 74 } 75 76 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 77 ++NodesCombined; 78 DEBUG(std::cerr << "\nReplacing "; N->dump(); 79 std::cerr << "\nWith: "; To[0].Val->dump(); 80 std::cerr << " and " << To.size()-1 << " other values\n"); 81 std::vector<SDNode*> NowDead; 82 DAG.ReplaceAllUsesWith(N, To, &NowDead); 83 84 // Push the new nodes and any users onto the worklist 85 for (unsigned i = 0, e = To.size(); i != e; ++i) { 86 WorkList.push_back(To[i].Val); 87 AddUsersToWorkList(To[i].Val); 88 } 89 90 // Nodes can end up on the worklist more than once. Make sure we do 91 // not process a node that has been replaced. 92 removeFromWorkList(N); 93 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 94 removeFromWorkList(NowDead[i]); 95 96 // Finally, since the node is now dead, remove it from the graph. 97 DAG.DeleteNode(N); 98 return SDOperand(N, 0); 99 } 100 101 SDOperand CombineTo(SDNode *N, SDOperand Res) { 102 std::vector<SDOperand> To; 103 To.push_back(Res); 104 return CombineTo(N, To); 105 } 106 107 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 108 std::vector<SDOperand> To; 109 To.push_back(Res0); 110 To.push_back(Res1); 111 return CombineTo(N, To); 112 } 113 private: 114 115 /// SimplifyDemandedBits - Check the specified integer node value to see if 116 /// it can be simplified or if things it uses can be simplified by bit 117 /// propagation. If so, return true. 118 bool SimplifyDemandedBits(SDOperand Op) { 119 TargetLowering::TargetLoweringOpt TLO(DAG); 120 uint64_t KnownZero, KnownOne; 121 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 122 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 123 return false; 124 125 // Revisit the node. 126 WorkList.push_back(Op.Val); 127 128 // Replace the old value with the new one. 129 ++NodesCombined; 130 DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump(); 131 std::cerr << "\nWith: "; TLO.New.Val->dump()); 132 133 std::vector<SDNode*> NowDead; 134 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 135 136 // Push the new node and any (possibly new) users onto the worklist. 137 WorkList.push_back(TLO.New.Val); 138 AddUsersToWorkList(TLO.New.Val); 139 140 // Nodes can end up on the worklist more than once. Make sure we do 141 // not process a node that has been replaced. 142 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 143 removeFromWorkList(NowDead[i]); 144 145 // Finally, if the node is now dead, remove it from the graph. The node 146 // may not be dead if the replacement process recursively simplified to 147 // something else needing this node. 148 if (TLO.Old.Val->use_empty()) { 149 removeFromWorkList(TLO.Old.Val); 150 DAG.DeleteNode(TLO.Old.Val); 151 } 152 return true; 153 } 154 155 /// visit - call the node-specific routine that knows how to fold each 156 /// particular type of node. 157 SDOperand visit(SDNode *N); 158 159 // Visitation implementation - Implement dag node combining for different 160 // node types. The semantics are as follows: 161 // Return Value: 162 // SDOperand.Val == 0 - No change was made 163 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 164 // otherwise - N should be replaced by the returned Operand. 165 // 166 SDOperand visitTokenFactor(SDNode *N); 167 SDOperand visitADD(SDNode *N); 168 SDOperand visitSUB(SDNode *N); 169 SDOperand visitMUL(SDNode *N); 170 SDOperand visitSDIV(SDNode *N); 171 SDOperand visitUDIV(SDNode *N); 172 SDOperand visitSREM(SDNode *N); 173 SDOperand visitUREM(SDNode *N); 174 SDOperand visitMULHU(SDNode *N); 175 SDOperand visitMULHS(SDNode *N); 176 SDOperand visitAND(SDNode *N); 177 SDOperand visitOR(SDNode *N); 178 SDOperand visitXOR(SDNode *N); 179 SDOperand visitSHL(SDNode *N); 180 SDOperand visitSRA(SDNode *N); 181 SDOperand visitSRL(SDNode *N); 182 SDOperand visitCTLZ(SDNode *N); 183 SDOperand visitCTTZ(SDNode *N); 184 SDOperand visitCTPOP(SDNode *N); 185 SDOperand visitSELECT(SDNode *N); 186 SDOperand visitSELECT_CC(SDNode *N); 187 SDOperand visitSETCC(SDNode *N); 188 SDOperand visitSIGN_EXTEND(SDNode *N); 189 SDOperand visitZERO_EXTEND(SDNode *N); 190 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 191 SDOperand visitTRUNCATE(SDNode *N); 192 SDOperand visitBIT_CONVERT(SDNode *N); 193 SDOperand visitFADD(SDNode *N); 194 SDOperand visitFSUB(SDNode *N); 195 SDOperand visitFMUL(SDNode *N); 196 SDOperand visitFDIV(SDNode *N); 197 SDOperand visitFREM(SDNode *N); 198 SDOperand visitFCOPYSIGN(SDNode *N); 199 SDOperand visitSINT_TO_FP(SDNode *N); 200 SDOperand visitUINT_TO_FP(SDNode *N); 201 SDOperand visitFP_TO_SINT(SDNode *N); 202 SDOperand visitFP_TO_UINT(SDNode *N); 203 SDOperand visitFP_ROUND(SDNode *N); 204 SDOperand visitFP_ROUND_INREG(SDNode *N); 205 SDOperand visitFP_EXTEND(SDNode *N); 206 SDOperand visitFNEG(SDNode *N); 207 SDOperand visitFABS(SDNode *N); 208 SDOperand visitBRCOND(SDNode *N); 209 SDOperand visitBRCONDTWOWAY(SDNode *N); 210 SDOperand visitBR_CC(SDNode *N); 211 SDOperand visitBRTWOWAY_CC(SDNode *N); 212 SDOperand visitLOAD(SDNode *N); 213 SDOperand visitSTORE(SDNode *N); 214 215 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 216 217 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 218 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 219 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 220 SDOperand N3, ISD::CondCode CC); 221 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 222 ISD::CondCode Cond, bool foldBooleans = true); 223 224 SDOperand BuildSDIV(SDNode *N); 225 SDOperand BuildUDIV(SDNode *N); 226public: 227 DAGCombiner(SelectionDAG &D) 228 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 229 230 /// Run - runs the dag combiner on all nodes in the work list 231 void Run(bool RunningAfterLegalize); 232 }; 233} 234 235//===----------------------------------------------------------------------===// 236// TargetLowering::DAGCombinerInfo implementation 237//===----------------------------------------------------------------------===// 238 239void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 240 ((DAGCombiner*)DC)->AddToWorkList(N); 241} 242 243SDOperand TargetLowering::DAGCombinerInfo:: 244CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 245 return ((DAGCombiner*)DC)->CombineTo(N, To); 246} 247 248SDOperand TargetLowering::DAGCombinerInfo:: 249CombineTo(SDNode *N, SDOperand Res) { 250 return ((DAGCombiner*)DC)->CombineTo(N, Res); 251} 252 253 254SDOperand TargetLowering::DAGCombinerInfo:: 255CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 256 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 257} 258 259 260 261 262//===----------------------------------------------------------------------===// 263 264 265struct ms { 266 int64_t m; // magic number 267 int64_t s; // shift amount 268}; 269 270struct mu { 271 uint64_t m; // magic number 272 int64_t a; // add indicator 273 int64_t s; // shift amount 274}; 275 276/// magic - calculate the magic numbers required to codegen an integer sdiv as 277/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 278/// or -1. 279static ms magic32(int32_t d) { 280 int32_t p; 281 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 282 const uint32_t two31 = 0x80000000U; 283 struct ms mag; 284 285 ad = abs(d); 286 t = two31 + ((uint32_t)d >> 31); 287 anc = t - 1 - t%ad; // absolute value of nc 288 p = 31; // initialize p 289 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 290 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 291 q2 = two31/ad; // initialize q2 = 2p/abs(d) 292 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 293 do { 294 p = p + 1; 295 q1 = 2*q1; // update q1 = 2p/abs(nc) 296 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 297 if (r1 >= anc) { // must be unsigned comparison 298 q1 = q1 + 1; 299 r1 = r1 - anc; 300 } 301 q2 = 2*q2; // update q2 = 2p/abs(d) 302 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 303 if (r2 >= ad) { // must be unsigned comparison 304 q2 = q2 + 1; 305 r2 = r2 - ad; 306 } 307 delta = ad - r2; 308 } while (q1 < delta || (q1 == delta && r1 == 0)); 309 310 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 311 if (d < 0) mag.m = -mag.m; // resulting magic number 312 mag.s = p - 32; // resulting shift 313 return mag; 314} 315 316/// magicu - calculate the magic numbers required to codegen an integer udiv as 317/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 318static mu magicu32(uint32_t d) { 319 int32_t p; 320 uint32_t nc, delta, q1, r1, q2, r2; 321 struct mu magu; 322 magu.a = 0; // initialize "add" indicator 323 nc = - 1 - (-d)%d; 324 p = 31; // initialize p 325 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 326 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 327 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 328 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 329 do { 330 p = p + 1; 331 if (r1 >= nc - r1 ) { 332 q1 = 2*q1 + 1; // update q1 333 r1 = 2*r1 - nc; // update r1 334 } 335 else { 336 q1 = 2*q1; // update q1 337 r1 = 2*r1; // update r1 338 } 339 if (r2 + 1 >= d - r2) { 340 if (q2 >= 0x7FFFFFFF) magu.a = 1; 341 q2 = 2*q2 + 1; // update q2 342 r2 = 2*r2 + 1 - d; // update r2 343 } 344 else { 345 if (q2 >= 0x80000000) magu.a = 1; 346 q2 = 2*q2; // update q2 347 r2 = 2*r2 + 1; // update r2 348 } 349 delta = d - 1 - r2; 350 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 351 magu.m = q2 + 1; // resulting magic number 352 magu.s = p - 32; // resulting shift 353 return magu; 354} 355 356/// magic - calculate the magic numbers required to codegen an integer sdiv as 357/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 358/// or -1. 359static ms magic64(int64_t d) { 360 int64_t p; 361 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 362 const uint64_t two63 = 9223372036854775808ULL; // 2^63 363 struct ms mag; 364 365 ad = d >= 0 ? d : -d; 366 t = two63 + ((uint64_t)d >> 63); 367 anc = t - 1 - t%ad; // absolute value of nc 368 p = 63; // initialize p 369 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 370 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 371 q2 = two63/ad; // initialize q2 = 2p/abs(d) 372 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 373 do { 374 p = p + 1; 375 q1 = 2*q1; // update q1 = 2p/abs(nc) 376 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 377 if (r1 >= anc) { // must be unsigned comparison 378 q1 = q1 + 1; 379 r1 = r1 - anc; 380 } 381 q2 = 2*q2; // update q2 = 2p/abs(d) 382 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 383 if (r2 >= ad) { // must be unsigned comparison 384 q2 = q2 + 1; 385 r2 = r2 - ad; 386 } 387 delta = ad - r2; 388 } while (q1 < delta || (q1 == delta && r1 == 0)); 389 390 mag.m = q2 + 1; 391 if (d < 0) mag.m = -mag.m; // resulting magic number 392 mag.s = p - 64; // resulting shift 393 return mag; 394} 395 396/// magicu - calculate the magic numbers required to codegen an integer udiv as 397/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 398static mu magicu64(uint64_t d) 399{ 400 int64_t p; 401 uint64_t nc, delta, q1, r1, q2, r2; 402 struct mu magu; 403 magu.a = 0; // initialize "add" indicator 404 nc = - 1 - (-d)%d; 405 p = 63; // initialize p 406 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 407 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 408 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 409 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 410 do { 411 p = p + 1; 412 if (r1 >= nc - r1 ) { 413 q1 = 2*q1 + 1; // update q1 414 r1 = 2*r1 - nc; // update r1 415 } 416 else { 417 q1 = 2*q1; // update q1 418 r1 = 2*r1; // update r1 419 } 420 if (r2 + 1 >= d - r2) { 421 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 422 q2 = 2*q2 + 1; // update q2 423 r2 = 2*r2 + 1 - d; // update r2 424 } 425 else { 426 if (q2 >= 0x8000000000000000ull) magu.a = 1; 427 q2 = 2*q2; // update q2 428 r2 = 2*r2 + 1; // update r2 429 } 430 delta = d - 1 - r2; 431 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 432 magu.m = q2 + 1; // resulting magic number 433 magu.s = p - 64; // resulting shift 434 return magu; 435} 436 437// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 438// that selects between the values 1 and 0, making it equivalent to a setcc. 439// Also, set the incoming LHS, RHS, and CC references to the appropriate 440// nodes based on the type of node we are checking. This simplifies life a 441// bit for the callers. 442static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 443 SDOperand &CC) { 444 if (N.getOpcode() == ISD::SETCC) { 445 LHS = N.getOperand(0); 446 RHS = N.getOperand(1); 447 CC = N.getOperand(2); 448 return true; 449 } 450 if (N.getOpcode() == ISD::SELECT_CC && 451 N.getOperand(2).getOpcode() == ISD::Constant && 452 N.getOperand(3).getOpcode() == ISD::Constant && 453 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 454 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 455 LHS = N.getOperand(0); 456 RHS = N.getOperand(1); 457 CC = N.getOperand(4); 458 return true; 459 } 460 return false; 461} 462 463// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 464// one use. If this is true, it allows the users to invert the operation for 465// free when it is profitable to do so. 466static bool isOneUseSetCC(SDOperand N) { 467 SDOperand N0, N1, N2; 468 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 469 return true; 470 return false; 471} 472 473// FIXME: This should probably go in the ISD class rather than being duplicated 474// in several files. 475static bool isCommutativeBinOp(unsigned Opcode) { 476 switch (Opcode) { 477 case ISD::ADD: 478 case ISD::MUL: 479 case ISD::AND: 480 case ISD::OR: 481 case ISD::XOR: return true; 482 default: return false; // FIXME: Need commutative info for user ops! 483 } 484} 485 486SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 487 MVT::ValueType VT = N0.getValueType(); 488 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 489 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 490 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 491 if (isa<ConstantSDNode>(N1)) { 492 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 493 AddToWorkList(OpNode.Val); 494 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 495 } else if (N0.hasOneUse()) { 496 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 497 AddToWorkList(OpNode.Val); 498 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 499 } 500 } 501 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 502 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 503 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 504 if (isa<ConstantSDNode>(N0)) { 505 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 506 AddToWorkList(OpNode.Val); 507 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 508 } else if (N1.hasOneUse()) { 509 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 510 AddToWorkList(OpNode.Val); 511 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 512 } 513 } 514 return SDOperand(); 515} 516 517void DAGCombiner::Run(bool RunningAfterLegalize) { 518 // set the instance variable, so that the various visit routines may use it. 519 AfterLegalize = RunningAfterLegalize; 520 521 // Add all the dag nodes to the worklist. 522 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 523 E = DAG.allnodes_end(); I != E; ++I) 524 WorkList.push_back(I); 525 526 // Create a dummy node (which is not added to allnodes), that adds a reference 527 // to the root node, preventing it from being deleted, and tracking any 528 // changes of the root. 529 HandleSDNode Dummy(DAG.getRoot()); 530 531 532 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 533 TargetLowering::DAGCombinerInfo 534 DagCombineInfo(DAG, !RunningAfterLegalize, this); 535 536 // while the worklist isn't empty, inspect the node on the end of it and 537 // try and combine it. 538 while (!WorkList.empty()) { 539 SDNode *N = WorkList.back(); 540 WorkList.pop_back(); 541 542 // If N has no uses, it is dead. Make sure to revisit all N's operands once 543 // N is deleted from the DAG, since they too may now be dead or may have a 544 // reduced number of uses, allowing other xforms. 545 if (N->use_empty() && N != &Dummy) { 546 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 547 WorkList.push_back(N->getOperand(i).Val); 548 549 removeFromWorkList(N); 550 DAG.DeleteNode(N); 551 continue; 552 } 553 554 SDOperand RV = visit(N); 555 556 // If nothing happened, try a target-specific DAG combine. 557 if (RV.Val == 0) { 558 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 559 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 560 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 561 } 562 563 if (RV.Val) { 564 ++NodesCombined; 565 // If we get back the same node we passed in, rather than a new node or 566 // zero, we know that the node must have defined multiple values and 567 // CombineTo was used. Since CombineTo takes care of the worklist 568 // mechanics for us, we have no work to do in this case. 569 if (RV.Val != N) { 570 DEBUG(std::cerr << "\nReplacing "; N->dump(); 571 std::cerr << "\nWith: "; RV.Val->dump(); 572 std::cerr << '\n'); 573 std::vector<SDNode*> NowDead; 574 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead); 575 576 // Push the new node and any users onto the worklist 577 WorkList.push_back(RV.Val); 578 AddUsersToWorkList(RV.Val); 579 580 // Nodes can end up on the worklist more than once. Make sure we do 581 // not process a node that has been replaced. 582 removeFromWorkList(N); 583 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 584 removeFromWorkList(NowDead[i]); 585 586 // Finally, since the node is now dead, remove it from the graph. 587 DAG.DeleteNode(N); 588 } 589 } 590 } 591 592 // If the root changed (e.g. it was a dead load, update the root). 593 DAG.setRoot(Dummy.getValue()); 594} 595 596SDOperand DAGCombiner::visit(SDNode *N) { 597 switch(N->getOpcode()) { 598 default: break; 599 case ISD::TokenFactor: return visitTokenFactor(N); 600 case ISD::ADD: return visitADD(N); 601 case ISD::SUB: return visitSUB(N); 602 case ISD::MUL: return visitMUL(N); 603 case ISD::SDIV: return visitSDIV(N); 604 case ISD::UDIV: return visitUDIV(N); 605 case ISD::SREM: return visitSREM(N); 606 case ISD::UREM: return visitUREM(N); 607 case ISD::MULHU: return visitMULHU(N); 608 case ISD::MULHS: return visitMULHS(N); 609 case ISD::AND: return visitAND(N); 610 case ISD::OR: return visitOR(N); 611 case ISD::XOR: return visitXOR(N); 612 case ISD::SHL: return visitSHL(N); 613 case ISD::SRA: return visitSRA(N); 614 case ISD::SRL: return visitSRL(N); 615 case ISD::CTLZ: return visitCTLZ(N); 616 case ISD::CTTZ: return visitCTTZ(N); 617 case ISD::CTPOP: return visitCTPOP(N); 618 case ISD::SELECT: return visitSELECT(N); 619 case ISD::SELECT_CC: return visitSELECT_CC(N); 620 case ISD::SETCC: return visitSETCC(N); 621 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 622 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 623 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 624 case ISD::TRUNCATE: return visitTRUNCATE(N); 625 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 626 case ISD::FADD: return visitFADD(N); 627 case ISD::FSUB: return visitFSUB(N); 628 case ISD::FMUL: return visitFMUL(N); 629 case ISD::FDIV: return visitFDIV(N); 630 case ISD::FREM: return visitFREM(N); 631 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 632 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 633 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 634 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 635 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 636 case ISD::FP_ROUND: return visitFP_ROUND(N); 637 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 638 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 639 case ISD::FNEG: return visitFNEG(N); 640 case ISD::FABS: return visitFABS(N); 641 case ISD::BRCOND: return visitBRCOND(N); 642 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N); 643 case ISD::BR_CC: return visitBR_CC(N); 644 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N); 645 case ISD::LOAD: return visitLOAD(N); 646 case ISD::STORE: return visitSTORE(N); 647 } 648 return SDOperand(); 649} 650 651SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 652 std::vector<SDOperand> Ops; 653 bool Changed = false; 654 655 // If the token factor has two operands and one is the entry token, replace 656 // the token factor with the other operand. 657 if (N->getNumOperands() == 2) { 658 if (N->getOperand(0).getOpcode() == ISD::EntryToken) 659 return N->getOperand(1); 660 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 661 return N->getOperand(0); 662 } 663 664 // fold (tokenfactor (tokenfactor)) -> tokenfactor 665 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 666 SDOperand Op = N->getOperand(i); 667 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 668 Changed = true; 669 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 670 Ops.push_back(Op.getOperand(j)); 671 } else { 672 Ops.push_back(Op); 673 } 674 } 675 if (Changed) 676 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 677 return SDOperand(); 678} 679 680SDOperand DAGCombiner::visitADD(SDNode *N) { 681 SDOperand N0 = N->getOperand(0); 682 SDOperand N1 = N->getOperand(1); 683 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 684 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 685 MVT::ValueType VT = N0.getValueType(); 686 687 // fold (add c1, c2) -> c1+c2 688 if (N0C && N1C) 689 return DAG.getNode(ISD::ADD, VT, N0, N1); 690 // canonicalize constant to RHS 691 if (N0C && !N1C) 692 return DAG.getNode(ISD::ADD, VT, N1, N0); 693 // fold (add x, 0) -> x 694 if (N1C && N1C->isNullValue()) 695 return N0; 696 // fold ((c1-A)+c2) -> (c1+c2)-A 697 if (N1C && N0.getOpcode() == ISD::SUB) 698 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 699 return DAG.getNode(ISD::SUB, VT, 700 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 701 N0.getOperand(1)); 702 // reassociate add 703 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 704 if (RADD.Val != 0) 705 return RADD; 706 // fold ((0-A) + B) -> B-A 707 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 708 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 709 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 710 // fold (A + (0-B)) -> A-B 711 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 712 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 713 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 714 // fold (A+(B-A)) -> B 715 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 716 return N1.getOperand(0); 717 // 718 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 719 return SDOperand(); 720 return SDOperand(); 721} 722 723SDOperand DAGCombiner::visitSUB(SDNode *N) { 724 SDOperand N0 = N->getOperand(0); 725 SDOperand N1 = N->getOperand(1); 726 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 727 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 728 MVT::ValueType VT = N0.getValueType(); 729 730 // fold (sub x, x) -> 0 731 if (N0 == N1) 732 return DAG.getConstant(0, N->getValueType(0)); 733 // fold (sub c1, c2) -> c1-c2 734 if (N0C && N1C) 735 return DAG.getNode(ISD::SUB, VT, N0, N1); 736 // fold (sub x, c) -> (add x, -c) 737 if (N1C) 738 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 739 // fold (A+B)-A -> B 740 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 741 return N0.getOperand(1); 742 // fold (A+B)-B -> A 743 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 744 return N0.getOperand(0); 745 return SDOperand(); 746} 747 748SDOperand DAGCombiner::visitMUL(SDNode *N) { 749 SDOperand N0 = N->getOperand(0); 750 SDOperand N1 = N->getOperand(1); 751 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 752 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 753 MVT::ValueType VT = N0.getValueType(); 754 755 // fold (mul c1, c2) -> c1*c2 756 if (N0C && N1C) 757 return DAG.getNode(ISD::MUL, VT, N0, N1); 758 // canonicalize constant to RHS 759 if (N0C && !N1C) 760 return DAG.getNode(ISD::MUL, VT, N1, N0); 761 // fold (mul x, 0) -> 0 762 if (N1C && N1C->isNullValue()) 763 return N1; 764 // fold (mul x, -1) -> 0-x 765 if (N1C && N1C->isAllOnesValue()) 766 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 767 // fold (mul x, (1 << c)) -> x << c 768 if (N1C && isPowerOf2_64(N1C->getValue())) 769 return DAG.getNode(ISD::SHL, VT, N0, 770 DAG.getConstant(Log2_64(N1C->getValue()), 771 TLI.getShiftAmountTy())); 772 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 773 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 774 // FIXME: If the input is something that is easily negated (e.g. a 775 // single-use add), we should put the negate there. 776 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 777 DAG.getNode(ISD::SHL, VT, N0, 778 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 779 TLI.getShiftAmountTy()))); 780 } 781 782 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 783 if (N1C && N0.getOpcode() == ISD::SHL && 784 isa<ConstantSDNode>(N0.getOperand(1))) { 785 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 786 AddToWorkList(C3.Val); 787 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 788 } 789 790 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 791 // use. 792 { 793 SDOperand Sh(0,0), Y(0,0); 794 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 795 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 796 N0.Val->hasOneUse()) { 797 Sh = N0; Y = N1; 798 } else if (N1.getOpcode() == ISD::SHL && 799 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 800 Sh = N1; Y = N0; 801 } 802 if (Sh.Val) { 803 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 804 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 805 } 806 } 807 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 808 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 809 isa<ConstantSDNode>(N0.getOperand(1))) { 810 return DAG.getNode(ISD::ADD, VT, 811 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 812 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 813 } 814 815 // reassociate mul 816 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 817 if (RMUL.Val != 0) 818 return RMUL; 819 return SDOperand(); 820} 821 822SDOperand DAGCombiner::visitSDIV(SDNode *N) { 823 SDOperand N0 = N->getOperand(0); 824 SDOperand N1 = N->getOperand(1); 825 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 826 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 827 MVT::ValueType VT = N->getValueType(0); 828 829 // fold (sdiv c1, c2) -> c1/c2 830 if (N0C && N1C && !N1C->isNullValue()) 831 return DAG.getNode(ISD::SDIV, VT, N0, N1); 832 // fold (sdiv X, 1) -> X 833 if (N1C && N1C->getSignExtended() == 1LL) 834 return N0; 835 // fold (sdiv X, -1) -> 0-X 836 if (N1C && N1C->isAllOnesValue()) 837 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 838 // If we know the sign bits of both operands are zero, strength reduce to a 839 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 840 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 841 if (TLI.MaskedValueIsZero(N1, SignBit) && 842 TLI.MaskedValueIsZero(N0, SignBit)) 843 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 844 // fold (sdiv X, pow2) -> simple ops after legalize 845 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 846 (isPowerOf2_64(N1C->getSignExtended()) || 847 isPowerOf2_64(-N1C->getSignExtended()))) { 848 // If dividing by powers of two is cheap, then don't perform the following 849 // fold. 850 if (TLI.isPow2DivCheap()) 851 return SDOperand(); 852 int64_t pow2 = N1C->getSignExtended(); 853 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 854 unsigned lg2 = Log2_64(abs2); 855 // Splat the sign bit into the register 856 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 857 DAG.getConstant(MVT::getSizeInBits(VT)-1, 858 TLI.getShiftAmountTy())); 859 AddToWorkList(SGN.Val); 860 // Add (N0 < 0) ? abs2 - 1 : 0; 861 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 862 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 863 TLI.getShiftAmountTy())); 864 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 865 AddToWorkList(SRL.Val); 866 AddToWorkList(ADD.Val); // Divide by pow2 867 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 868 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 869 // If we're dividing by a positive value, we're done. Otherwise, we must 870 // negate the result. 871 if (pow2 > 0) 872 return SRA; 873 AddToWorkList(SRA.Val); 874 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 875 } 876 // if integer divide is expensive and we satisfy the requirements, emit an 877 // alternate sequence. 878 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 879 !TLI.isIntDivCheap()) { 880 SDOperand Op = BuildSDIV(N); 881 if (Op.Val) return Op; 882 } 883 return SDOperand(); 884} 885 886SDOperand DAGCombiner::visitUDIV(SDNode *N) { 887 SDOperand N0 = N->getOperand(0); 888 SDOperand N1 = N->getOperand(1); 889 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 890 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 891 MVT::ValueType VT = N->getValueType(0); 892 893 // fold (udiv c1, c2) -> c1/c2 894 if (N0C && N1C && !N1C->isNullValue()) 895 return DAG.getNode(ISD::UDIV, VT, N0, N1); 896 // fold (udiv x, (1 << c)) -> x >>u c 897 if (N1C && isPowerOf2_64(N1C->getValue())) 898 return DAG.getNode(ISD::SRL, VT, N0, 899 DAG.getConstant(Log2_64(N1C->getValue()), 900 TLI.getShiftAmountTy())); 901 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 902 if (N1.getOpcode() == ISD::SHL) { 903 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 904 if (isPowerOf2_64(SHC->getValue())) { 905 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 906 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 907 DAG.getConstant(Log2_64(SHC->getValue()), 908 ADDVT)); 909 AddToWorkList(Add.Val); 910 return DAG.getNode(ISD::SRL, VT, N0, Add); 911 } 912 } 913 } 914 // fold (udiv x, c) -> alternate 915 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 916 SDOperand Op = BuildUDIV(N); 917 if (Op.Val) return Op; 918 } 919 return SDOperand(); 920} 921 922SDOperand DAGCombiner::visitSREM(SDNode *N) { 923 SDOperand N0 = N->getOperand(0); 924 SDOperand N1 = N->getOperand(1); 925 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 926 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 927 MVT::ValueType VT = N->getValueType(0); 928 929 // fold (srem c1, c2) -> c1%c2 930 if (N0C && N1C && !N1C->isNullValue()) 931 return DAG.getNode(ISD::SREM, VT, N0, N1); 932 // If we know the sign bits of both operands are zero, strength reduce to a 933 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 934 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 935 if (TLI.MaskedValueIsZero(N1, SignBit) && 936 TLI.MaskedValueIsZero(N0, SignBit)) 937 return DAG.getNode(ISD::UREM, VT, N0, N1); 938 return SDOperand(); 939} 940 941SDOperand DAGCombiner::visitUREM(SDNode *N) { 942 SDOperand N0 = N->getOperand(0); 943 SDOperand N1 = N->getOperand(1); 944 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 945 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 946 MVT::ValueType VT = N->getValueType(0); 947 948 // fold (urem c1, c2) -> c1%c2 949 if (N0C && N1C && !N1C->isNullValue()) 950 return DAG.getNode(ISD::UREM, VT, N0, N1); 951 // fold (urem x, pow2) -> (and x, pow2-1) 952 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 953 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 954 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 955 if (N1.getOpcode() == ISD::SHL) { 956 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 957 if (isPowerOf2_64(SHC->getValue())) { 958 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 959 AddToWorkList(Add.Val); 960 return DAG.getNode(ISD::AND, VT, N0, Add); 961 } 962 } 963 } 964 return SDOperand(); 965} 966 967SDOperand DAGCombiner::visitMULHS(SDNode *N) { 968 SDOperand N0 = N->getOperand(0); 969 SDOperand N1 = N->getOperand(1); 970 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 971 972 // fold (mulhs x, 0) -> 0 973 if (N1C && N1C->isNullValue()) 974 return N1; 975 // fold (mulhs x, 1) -> (sra x, size(x)-1) 976 if (N1C && N1C->getValue() == 1) 977 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 978 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 979 TLI.getShiftAmountTy())); 980 return SDOperand(); 981} 982 983SDOperand DAGCombiner::visitMULHU(SDNode *N) { 984 SDOperand N0 = N->getOperand(0); 985 SDOperand N1 = N->getOperand(1); 986 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 987 988 // fold (mulhu x, 0) -> 0 989 if (N1C && N1C->isNullValue()) 990 return N1; 991 // fold (mulhu x, 1) -> 0 992 if (N1C && N1C->getValue() == 1) 993 return DAG.getConstant(0, N0.getValueType()); 994 return SDOperand(); 995} 996 997SDOperand DAGCombiner::visitAND(SDNode *N) { 998 SDOperand N0 = N->getOperand(0); 999 SDOperand N1 = N->getOperand(1); 1000 SDOperand LL, LR, RL, RR, CC0, CC1; 1001 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1002 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1003 MVT::ValueType VT = N1.getValueType(); 1004 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1005 1006 // fold (and c1, c2) -> c1&c2 1007 if (N0C && N1C) 1008 return DAG.getNode(ISD::AND, VT, N0, N1); 1009 // canonicalize constant to RHS 1010 if (N0C && !N1C) 1011 return DAG.getNode(ISD::AND, VT, N1, N0); 1012 // fold (and x, -1) -> x 1013 if (N1C && N1C->isAllOnesValue()) 1014 return N0; 1015 // if (and x, c) is known to be zero, return 0 1016 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1017 return DAG.getConstant(0, VT); 1018 // reassociate and 1019 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1020 if (RAND.Val != 0) 1021 return RAND; 1022 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1023 if (N1C && N0.getOpcode() == ISD::OR) 1024 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1025 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1026 return N1; 1027 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1028 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1029 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1030 if (TLI.MaskedValueIsZero(N0.getOperand(0), 1031 ~N1C->getValue() & InMask)) { 1032 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1033 N0.getOperand(0)); 1034 1035 // Replace uses of the AND with uses of the Zero extend node. 1036 CombineTo(N, Zext); 1037 1038 // We actually want to replace all uses of the any_extend with the 1039 // zero_extend, to avoid duplicating things. This will later cause this 1040 // AND to be folded. 1041 CombineTo(N0.Val, Zext); 1042 return SDOperand(); 1043 } 1044 } 1045 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1046 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1047 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1048 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1049 1050 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1051 MVT::isInteger(LL.getValueType())) { 1052 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1053 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1054 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1055 AddToWorkList(ORNode.Val); 1056 return DAG.getSetCC(VT, ORNode, LR, Op1); 1057 } 1058 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1059 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1060 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1061 AddToWorkList(ANDNode.Val); 1062 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1063 } 1064 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1065 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1066 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1067 AddToWorkList(ORNode.Val); 1068 return DAG.getSetCC(VT, ORNode, LR, Op1); 1069 } 1070 } 1071 // canonicalize equivalent to ll == rl 1072 if (LL == RR && LR == RL) { 1073 Op1 = ISD::getSetCCSwappedOperands(Op1); 1074 std::swap(RL, RR); 1075 } 1076 if (LL == RL && LR == RR) { 1077 bool isInteger = MVT::isInteger(LL.getValueType()); 1078 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1079 if (Result != ISD::SETCC_INVALID) 1080 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1081 } 1082 } 1083 // fold (and (zext x), (zext y)) -> (zext (and x, y)) 1084 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1085 N1.getOpcode() == ISD::ZERO_EXTEND && 1086 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1087 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 1088 N0.getOperand(0), N1.getOperand(0)); 1089 AddToWorkList(ANDNode.Val); 1090 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode); 1091 } 1092 // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y)) 1093 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1094 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1095 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1096 N0.getOperand(1) == N1.getOperand(1)) { 1097 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 1098 N0.getOperand(0), N1.getOperand(0)); 1099 AddToWorkList(ANDNode.Val); 1100 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1)); 1101 } 1102 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1103 // fold (and (sra)) -> (and (srl)) when possible. 1104 if (SimplifyDemandedBits(SDOperand(N, 0))) 1105 return SDOperand(); 1106 // fold (zext_inreg (extload x)) -> (zextload x) 1107 if (N0.getOpcode() == ISD::EXTLOAD) { 1108 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1109 // If we zero all the possible extended bits, then we can turn this into 1110 // a zextload if we are running before legalize or the operation is legal. 1111 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1112 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1113 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1114 N0.getOperand(1), N0.getOperand(2), 1115 EVT); 1116 AddToWorkList(N); 1117 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1118 return SDOperand(); 1119 } 1120 } 1121 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1122 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) { 1123 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1124 // If we zero all the possible extended bits, then we can turn this into 1125 // a zextload if we are running before legalize or the operation is legal. 1126 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1127 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1128 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1129 N0.getOperand(1), N0.getOperand(2), 1130 EVT); 1131 AddToWorkList(N); 1132 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1133 return SDOperand(); 1134 } 1135 } 1136 1137 // fold (and (load x), 255) -> (zextload x, i8) 1138 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1139 if (N1C && 1140 (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD || 1141 N0.getOpcode() == ISD::ZEXTLOAD) && 1142 N0.hasOneUse()) { 1143 MVT::ValueType EVT, LoadedVT; 1144 if (N1C->getValue() == 255) 1145 EVT = MVT::i8; 1146 else if (N1C->getValue() == 65535) 1147 EVT = MVT::i16; 1148 else if (N1C->getValue() == ~0U) 1149 EVT = MVT::i32; 1150 else 1151 EVT = MVT::Other; 1152 1153 LoadedVT = N0.getOpcode() == ISD::LOAD ? VT : 1154 cast<VTSDNode>(N0.getOperand(3))->getVT(); 1155 if (EVT != MVT::Other && LoadedVT > EVT) { 1156 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1157 // For big endian targets, we need to add an offset to the pointer to load 1158 // the correct bytes. For little endian systems, we merely need to read 1159 // fewer bytes from the same pointer. 1160 unsigned PtrOff = 1161 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1162 SDOperand NewPtr = N0.getOperand(1); 1163 if (!TLI.isLittleEndian()) 1164 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1165 DAG.getConstant(PtrOff, PtrType)); 1166 AddToWorkList(NewPtr.Val); 1167 SDOperand Load = 1168 DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr, 1169 N0.getOperand(2), EVT); 1170 AddToWorkList(N); 1171 CombineTo(N0.Val, Load, Load.getValue(1)); 1172 return SDOperand(); 1173 } 1174 } 1175 1176 return SDOperand(); 1177} 1178 1179SDOperand DAGCombiner::visitOR(SDNode *N) { 1180 SDOperand N0 = N->getOperand(0); 1181 SDOperand N1 = N->getOperand(1); 1182 SDOperand LL, LR, RL, RR, CC0, CC1; 1183 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1184 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1185 MVT::ValueType VT = N1.getValueType(); 1186 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1187 1188 // fold (or c1, c2) -> c1|c2 1189 if (N0C && N1C) 1190 return DAG.getNode(ISD::OR, VT, N0, N1); 1191 // canonicalize constant to RHS 1192 if (N0C && !N1C) 1193 return DAG.getNode(ISD::OR, VT, N1, N0); 1194 // fold (or x, 0) -> x 1195 if (N1C && N1C->isNullValue()) 1196 return N0; 1197 // fold (or x, -1) -> -1 1198 if (N1C && N1C->isAllOnesValue()) 1199 return N1; 1200 // fold (or x, c) -> c iff (x & ~c) == 0 1201 if (N1C && 1202 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1203 return N1; 1204 // reassociate or 1205 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1206 if (ROR.Val != 0) 1207 return ROR; 1208 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1209 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1210 isa<ConstantSDNode>(N0.getOperand(1))) { 1211 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1212 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1213 N1), 1214 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1215 } 1216 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1217 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1218 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1219 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1220 1221 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1222 MVT::isInteger(LL.getValueType())) { 1223 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1224 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1225 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1226 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1227 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1228 AddToWorkList(ORNode.Val); 1229 return DAG.getSetCC(VT, ORNode, LR, Op1); 1230 } 1231 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1232 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1233 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1234 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1235 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1236 AddToWorkList(ANDNode.Val); 1237 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1238 } 1239 } 1240 // canonicalize equivalent to ll == rl 1241 if (LL == RR && LR == RL) { 1242 Op1 = ISD::getSetCCSwappedOperands(Op1); 1243 std::swap(RL, RR); 1244 } 1245 if (LL == RL && LR == RR) { 1246 bool isInteger = MVT::isInteger(LL.getValueType()); 1247 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1248 if (Result != ISD::SETCC_INVALID) 1249 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1250 } 1251 } 1252 // fold (or (zext x), (zext y)) -> (zext (or x, y)) 1253 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1254 N1.getOpcode() == ISD::ZERO_EXTEND && 1255 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1256 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 1257 N0.getOperand(0), N1.getOperand(0)); 1258 AddToWorkList(ORNode.Val); 1259 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode); 1260 } 1261 // fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y)) 1262 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1263 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1264 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1265 N0.getOperand(1) == N1.getOperand(1)) { 1266 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 1267 N0.getOperand(0), N1.getOperand(0)); 1268 AddToWorkList(ORNode.Val); 1269 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1270 } 1271 // canonicalize shl to left side in a shl/srl pair, to match rotate 1272 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 1273 std::swap(N0, N1); 1274 // check for rotl, rotr 1275 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL && 1276 N0.getOperand(0) == N1.getOperand(0) && 1277 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) { 1278 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1279 if (N0.getOperand(1).getOpcode() == ISD::Constant && 1280 N1.getOperand(1).getOpcode() == ISD::Constant) { 1281 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1282 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1283 if ((c1val + c2val) == OpSizeInBits) 1284 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1285 } 1286 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1287 if (N1.getOperand(1).getOpcode() == ISD::SUB && 1288 N0.getOperand(1) == N1.getOperand(1).getOperand(1)) 1289 if (ConstantSDNode *SUBC = 1290 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0))) 1291 if (SUBC->getValue() == OpSizeInBits) 1292 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1293 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1294 if (N0.getOperand(1).getOpcode() == ISD::SUB && 1295 N1.getOperand(1) == N0.getOperand(1).getOperand(1)) 1296 if (ConstantSDNode *SUBC = 1297 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0))) 1298 if (SUBC->getValue() == OpSizeInBits) { 1299 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT)) 1300 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0), 1301 N1.getOperand(1)); 1302 else 1303 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), 1304 N0.getOperand(1)); 1305 } 1306 } 1307 return SDOperand(); 1308} 1309 1310SDOperand DAGCombiner::visitXOR(SDNode *N) { 1311 SDOperand N0 = N->getOperand(0); 1312 SDOperand N1 = N->getOperand(1); 1313 SDOperand LHS, RHS, CC; 1314 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1315 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1316 MVT::ValueType VT = N0.getValueType(); 1317 1318 // fold (xor c1, c2) -> c1^c2 1319 if (N0C && N1C) 1320 return DAG.getNode(ISD::XOR, VT, N0, N1); 1321 // canonicalize constant to RHS 1322 if (N0C && !N1C) 1323 return DAG.getNode(ISD::XOR, VT, N1, N0); 1324 // fold (xor x, 0) -> x 1325 if (N1C && N1C->isNullValue()) 1326 return N0; 1327 // reassociate xor 1328 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1329 if (RXOR.Val != 0) 1330 return RXOR; 1331 // fold !(x cc y) -> (x !cc y) 1332 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1333 bool isInt = MVT::isInteger(LHS.getValueType()); 1334 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1335 isInt); 1336 if (N0.getOpcode() == ISD::SETCC) 1337 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1338 if (N0.getOpcode() == ISD::SELECT_CC) 1339 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1340 assert(0 && "Unhandled SetCC Equivalent!"); 1341 abort(); 1342 } 1343 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1344 if (N1C && N1C->getValue() == 1 && 1345 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1346 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1347 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1348 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1349 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1350 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1351 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1352 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1353 } 1354 } 1355 // fold !(x or y) -> (!x and !y) iff x or y are constants 1356 if (N1C && N1C->isAllOnesValue() && 1357 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1358 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1359 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1360 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1361 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1362 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1363 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1364 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1365 } 1366 } 1367 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1368 if (N1C && N0.getOpcode() == ISD::XOR) { 1369 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1370 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1371 if (N00C) 1372 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1373 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1374 if (N01C) 1375 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1376 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1377 } 1378 // fold (xor x, x) -> 0 1379 if (N0 == N1) 1380 return DAG.getConstant(0, VT); 1381 // fold (xor (zext x), (zext y)) -> (zext (xor x, y)) 1382 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1383 N1.getOpcode() == ISD::ZERO_EXTEND && 1384 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1385 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 1386 N0.getOperand(0), N1.getOperand(0)); 1387 AddToWorkList(XORNode.Val); 1388 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 1389 } 1390 // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y)) 1391 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1392 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1393 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1394 N0.getOperand(1) == N1.getOperand(1)) { 1395 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 1396 N0.getOperand(0), N1.getOperand(0)); 1397 AddToWorkList(XORNode.Val); 1398 return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1)); 1399 } 1400 return SDOperand(); 1401} 1402 1403SDOperand DAGCombiner::visitSHL(SDNode *N) { 1404 SDOperand N0 = N->getOperand(0); 1405 SDOperand N1 = N->getOperand(1); 1406 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1407 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1408 MVT::ValueType VT = N0.getValueType(); 1409 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1410 1411 // fold (shl c1, c2) -> c1<<c2 1412 if (N0C && N1C) 1413 return DAG.getNode(ISD::SHL, VT, N0, N1); 1414 // fold (shl 0, x) -> 0 1415 if (N0C && N0C->isNullValue()) 1416 return N0; 1417 // fold (shl x, c >= size(x)) -> undef 1418 if (N1C && N1C->getValue() >= OpSizeInBits) 1419 return DAG.getNode(ISD::UNDEF, VT); 1420 // fold (shl x, 0) -> x 1421 if (N1C && N1C->isNullValue()) 1422 return N0; 1423 // if (shl x, c) is known to be zero, return 0 1424 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1425 return DAG.getConstant(0, VT); 1426 if (SimplifyDemandedBits(SDOperand(N, 0))) 1427 return SDOperand(); 1428 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1429 if (N1C && N0.getOpcode() == ISD::SHL && 1430 N0.getOperand(1).getOpcode() == ISD::Constant) { 1431 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1432 uint64_t c2 = N1C->getValue(); 1433 if (c1 + c2 > OpSizeInBits) 1434 return DAG.getConstant(0, VT); 1435 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1436 DAG.getConstant(c1 + c2, N1.getValueType())); 1437 } 1438 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1439 // (srl (and x, -1 << c1), c1-c2) 1440 if (N1C && N0.getOpcode() == ISD::SRL && 1441 N0.getOperand(1).getOpcode() == ISD::Constant) { 1442 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1443 uint64_t c2 = N1C->getValue(); 1444 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1445 DAG.getConstant(~0ULL << c1, VT)); 1446 if (c2 > c1) 1447 return DAG.getNode(ISD::SHL, VT, Mask, 1448 DAG.getConstant(c2-c1, N1.getValueType())); 1449 else 1450 return DAG.getNode(ISD::SRL, VT, Mask, 1451 DAG.getConstant(c1-c2, N1.getValueType())); 1452 } 1453 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1454 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1455 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1456 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1457 return SDOperand(); 1458} 1459 1460SDOperand DAGCombiner::visitSRA(SDNode *N) { 1461 SDOperand N0 = N->getOperand(0); 1462 SDOperand N1 = N->getOperand(1); 1463 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1464 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1465 MVT::ValueType VT = N0.getValueType(); 1466 1467 // fold (sra c1, c2) -> c1>>c2 1468 if (N0C && N1C) 1469 return DAG.getNode(ISD::SRA, VT, N0, N1); 1470 // fold (sra 0, x) -> 0 1471 if (N0C && N0C->isNullValue()) 1472 return N0; 1473 // fold (sra -1, x) -> -1 1474 if (N0C && N0C->isAllOnesValue()) 1475 return N0; 1476 // fold (sra x, c >= size(x)) -> undef 1477 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 1478 return DAG.getNode(ISD::UNDEF, VT); 1479 // fold (sra x, 0) -> x 1480 if (N1C && N1C->isNullValue()) 1481 return N0; 1482 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 1483 // sext_inreg. 1484 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 1485 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 1486 MVT::ValueType EVT; 1487 switch (LowBits) { 1488 default: EVT = MVT::Other; break; 1489 case 1: EVT = MVT::i1; break; 1490 case 8: EVT = MVT::i8; break; 1491 case 16: EVT = MVT::i16; break; 1492 case 32: EVT = MVT::i32; break; 1493 } 1494 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 1495 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1496 DAG.getValueType(EVT)); 1497 } 1498 1499 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 1500 if (N1C && N0.getOpcode() == ISD::SRA) { 1501 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1502 unsigned Sum = N1C->getValue() + C1->getValue(); 1503 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 1504 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 1505 DAG.getConstant(Sum, N1C->getValueType(0))); 1506 } 1507 } 1508 1509 // If the sign bit is known to be zero, switch this to a SRL. 1510 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 1511 return DAG.getNode(ISD::SRL, VT, N0, N1); 1512 return SDOperand(); 1513} 1514 1515SDOperand DAGCombiner::visitSRL(SDNode *N) { 1516 SDOperand N0 = N->getOperand(0); 1517 SDOperand N1 = N->getOperand(1); 1518 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1519 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1520 MVT::ValueType VT = N0.getValueType(); 1521 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1522 1523 // fold (srl c1, c2) -> c1 >>u c2 1524 if (N0C && N1C) 1525 return DAG.getNode(ISD::SRL, VT, N0, N1); 1526 // fold (srl 0, x) -> 0 1527 if (N0C && N0C->isNullValue()) 1528 return N0; 1529 // fold (srl x, c >= size(x)) -> undef 1530 if (N1C && N1C->getValue() >= OpSizeInBits) 1531 return DAG.getNode(ISD::UNDEF, VT); 1532 // fold (srl x, 0) -> x 1533 if (N1C && N1C->isNullValue()) 1534 return N0; 1535 // if (srl x, c) is known to be zero, return 0 1536 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1537 return DAG.getConstant(0, VT); 1538 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1539 if (N1C && N0.getOpcode() == ISD::SRL && 1540 N0.getOperand(1).getOpcode() == ISD::Constant) { 1541 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1542 uint64_t c2 = N1C->getValue(); 1543 if (c1 + c2 > OpSizeInBits) 1544 return DAG.getConstant(0, VT); 1545 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1546 DAG.getConstant(c1 + c2, N1.getValueType())); 1547 } 1548 return SDOperand(); 1549} 1550 1551SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1552 SDOperand N0 = N->getOperand(0); 1553 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1554 MVT::ValueType VT = N->getValueType(0); 1555 1556 // fold (ctlz c1) -> c2 1557 if (N0C) 1558 return DAG.getNode(ISD::CTLZ, VT, N0); 1559 return SDOperand(); 1560} 1561 1562SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1563 SDOperand N0 = N->getOperand(0); 1564 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1565 MVT::ValueType VT = N->getValueType(0); 1566 1567 // fold (cttz c1) -> c2 1568 if (N0C) 1569 return DAG.getNode(ISD::CTTZ, VT, N0); 1570 return SDOperand(); 1571} 1572 1573SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1574 SDOperand N0 = N->getOperand(0); 1575 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1576 MVT::ValueType VT = N->getValueType(0); 1577 1578 // fold (ctpop c1) -> c2 1579 if (N0C) 1580 return DAG.getNode(ISD::CTPOP, VT, N0); 1581 return SDOperand(); 1582} 1583 1584SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1585 SDOperand N0 = N->getOperand(0); 1586 SDOperand N1 = N->getOperand(1); 1587 SDOperand N2 = N->getOperand(2); 1588 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1589 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1590 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1591 MVT::ValueType VT = N->getValueType(0); 1592 1593 // fold select C, X, X -> X 1594 if (N1 == N2) 1595 return N1; 1596 // fold select true, X, Y -> X 1597 if (N0C && !N0C->isNullValue()) 1598 return N1; 1599 // fold select false, X, Y -> Y 1600 if (N0C && N0C->isNullValue()) 1601 return N2; 1602 // fold select C, 1, X -> C | X 1603 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1604 return DAG.getNode(ISD::OR, VT, N0, N2); 1605 // fold select C, 0, X -> ~C & X 1606 // FIXME: this should check for C type == X type, not i1? 1607 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1608 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1609 AddToWorkList(XORNode.Val); 1610 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1611 } 1612 // fold select C, X, 1 -> ~C | X 1613 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1614 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1615 AddToWorkList(XORNode.Val); 1616 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1617 } 1618 // fold select C, X, 0 -> C & X 1619 // FIXME: this should check for C type == X type, not i1? 1620 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1621 return DAG.getNode(ISD::AND, VT, N0, N1); 1622 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1623 if (MVT::i1 == VT && N0 == N1) 1624 return DAG.getNode(ISD::OR, VT, N0, N2); 1625 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1626 if (MVT::i1 == VT && N0 == N2) 1627 return DAG.getNode(ISD::AND, VT, N0, N1); 1628 // If we can fold this based on the true/false value, do so. 1629 if (SimplifySelectOps(N, N1, N2)) 1630 return SDOperand(); 1631 // fold selects based on a setcc into other things, such as min/max/abs 1632 if (N0.getOpcode() == ISD::SETCC) 1633 // FIXME: 1634 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 1635 // having to say they don't support SELECT_CC on every type the DAG knows 1636 // about, since there is no way to mark an opcode illegal at all value types 1637 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 1638 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 1639 N1, N2, N0.getOperand(2)); 1640 else 1641 return SimplifySelect(N0, N1, N2); 1642 return SDOperand(); 1643} 1644 1645SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1646 SDOperand N0 = N->getOperand(0); 1647 SDOperand N1 = N->getOperand(1); 1648 SDOperand N2 = N->getOperand(2); 1649 SDOperand N3 = N->getOperand(3); 1650 SDOperand N4 = N->getOperand(4); 1651 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1652 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1653 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1654 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1655 1656 // Determine if the condition we're dealing with is constant 1657 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1658 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1659 1660 // fold select_cc lhs, rhs, x, x, cc -> x 1661 if (N2 == N3) 1662 return N2; 1663 1664 // If we can fold this based on the true/false value, do so. 1665 if (SimplifySelectOps(N, N2, N3)) 1666 return SDOperand(); 1667 1668 // fold select_cc into other things, such as min/max/abs 1669 return SimplifySelectCC(N0, N1, N2, N3, CC); 1670} 1671 1672SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1673 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1674 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1675} 1676 1677SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1678 SDOperand N0 = N->getOperand(0); 1679 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1680 MVT::ValueType VT = N->getValueType(0); 1681 1682 // fold (sext c1) -> c1 1683 if (N0C) 1684 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 1685 // fold (sext (sext x)) -> (sext x) 1686 if (N0.getOpcode() == ISD::SIGN_EXTEND) 1687 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1688 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size. 1689 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1690 (!AfterLegalize || 1691 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType()))) 1692 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1693 DAG.getValueType(N0.getValueType())); 1694 // fold (sext (load x)) -> (sext (truncate (sextload x))) 1695 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1696 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){ 1697 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1698 N0.getOperand(1), N0.getOperand(2), 1699 N0.getValueType()); 1700 CombineTo(N, ExtLoad); 1701 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1702 ExtLoad.getValue(1)); 1703 return SDOperand(); 1704 } 1705 1706 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 1707 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 1708 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1709 N0.hasOneUse()) { 1710 SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0), 1711 N0.getOperand(1), N0.getOperand(2), 1712 N0.getOperand(3)); 1713 CombineTo(N, ExtLoad); 1714 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1715 ExtLoad.getValue(1)); 1716 return SDOperand(); 1717 } 1718 1719 return SDOperand(); 1720} 1721 1722SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1723 SDOperand N0 = N->getOperand(0); 1724 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1725 MVT::ValueType VT = N->getValueType(0); 1726 1727 // fold (zext c1) -> c1 1728 if (N0C) 1729 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1730 // fold (zext (zext x)) -> (zext x) 1731 if (N0.getOpcode() == ISD::ZERO_EXTEND) 1732 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1733 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size. 1734 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1735 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType()))) 1736 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType()); 1737 // fold (zext (load x)) -> (zext (truncate (zextload x))) 1738 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1739 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){ 1740 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1741 N0.getOperand(1), N0.getOperand(2), 1742 N0.getValueType()); 1743 CombineTo(N, ExtLoad); 1744 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1745 ExtLoad.getValue(1)); 1746 return SDOperand(); 1747 } 1748 1749 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 1750 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 1751 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1752 N0.hasOneUse()) { 1753 SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1754 N0.getOperand(1), N0.getOperand(2), 1755 N0.getOperand(3)); 1756 CombineTo(N, ExtLoad); 1757 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1758 ExtLoad.getValue(1)); 1759 return SDOperand(); 1760 } 1761 return SDOperand(); 1762} 1763 1764SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1765 SDOperand N0 = N->getOperand(0); 1766 SDOperand N1 = N->getOperand(1); 1767 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1768 MVT::ValueType VT = N->getValueType(0); 1769 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1770 unsigned EVTBits = MVT::getSizeInBits(EVT); 1771 1772 // fold (sext_in_reg c1) -> c1 1773 if (N0C) { 1774 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT); 1775 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); 1776 } 1777 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 1778 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1779 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1780 return N0; 1781 } 1782 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1783 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1784 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1785 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1786 } 1787 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x) 1788 if (N0.getOpcode() == ISD::AssertSext && 1789 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1790 return N0; 1791 } 1792 // fold (sext_in_reg (sextload x)) -> (sextload x) 1793 if (N0.getOpcode() == ISD::SEXTLOAD && 1794 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) { 1795 return N0; 1796 } 1797 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1 1798 if (N0.getOpcode() == ISD::SETCC && 1799 TLI.getSetCCResultContents() == 1800 TargetLowering::ZeroOrNegativeOneSetCCResult) 1801 return N0; 1802 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1803 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 1804 return DAG.getZeroExtendInReg(N0, EVT); 1805 // fold (sext_in_reg (srl x)) -> sra x 1806 if (N0.getOpcode() == ISD::SRL && 1807 N0.getOperand(1).getOpcode() == ISD::Constant && 1808 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) { 1809 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0), 1810 N0.getOperand(1)); 1811 } 1812 // fold (sext_inreg (extload x)) -> (sextload x) 1813 if (N0.getOpcode() == ISD::EXTLOAD && 1814 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1815 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1816 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1817 N0.getOperand(1), N0.getOperand(2), 1818 EVT); 1819 CombineTo(N, ExtLoad); 1820 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1821 return SDOperand(); 1822 } 1823 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 1824 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() && 1825 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1826 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1827 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1828 N0.getOperand(1), N0.getOperand(2), 1829 EVT); 1830 CombineTo(N, ExtLoad); 1831 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1832 return SDOperand(); 1833 } 1834 return SDOperand(); 1835} 1836 1837SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 1838 SDOperand N0 = N->getOperand(0); 1839 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1840 MVT::ValueType VT = N->getValueType(0); 1841 1842 // noop truncate 1843 if (N0.getValueType() == N->getValueType(0)) 1844 return N0; 1845 // fold (truncate c1) -> c1 1846 if (N0C) 1847 return DAG.getNode(ISD::TRUNCATE, VT, N0); 1848 // fold (truncate (truncate x)) -> (truncate x) 1849 if (N0.getOpcode() == ISD::TRUNCATE) 1850 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1851 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 1852 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){ 1853 if (N0.getValueType() < VT) 1854 // if the source is smaller than the dest, we still need an extend 1855 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1856 else if (N0.getValueType() > VT) 1857 // if the source is larger than the dest, than we just need the truncate 1858 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1859 else 1860 // if the source and dest are the same type, we can drop both the extend 1861 // and the truncate 1862 return N0.getOperand(0); 1863 } 1864 // fold (truncate (load x)) -> (smaller load x) 1865 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1866 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 1867 "Cannot truncate to larger type!"); 1868 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1869 // For big endian targets, we need to add an offset to the pointer to load 1870 // the correct bytes. For little endian systems, we merely need to read 1871 // fewer bytes from the same pointer. 1872 uint64_t PtrOff = 1873 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 1874 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 1875 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 1876 DAG.getConstant(PtrOff, PtrType)); 1877 AddToWorkList(NewPtr.Val); 1878 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 1879 AddToWorkList(N); 1880 CombineTo(N0.Val, Load, Load.getValue(1)); 1881 return SDOperand(); 1882 } 1883 return SDOperand(); 1884} 1885 1886SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 1887 SDOperand N0 = N->getOperand(0); 1888 MVT::ValueType VT = N->getValueType(0); 1889 1890 // If the input is a constant, let getNode() fold it. 1891 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 1892 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 1893 if (Res.Val != N) return Res; 1894 } 1895 1896 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 1897 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 1898 1899 // fold (conv (load x)) -> (load (conv*)x) 1900 // FIXME: These xforms need to know that the resultant load doesn't need a 1901 // higher alignment than the original! 1902 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1903 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1), 1904 N0.getOperand(2)); 1905 AddToWorkList(N); 1906 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 1907 Load.getValue(1)); 1908 return Load; 1909 } 1910 1911 return SDOperand(); 1912} 1913 1914SDOperand DAGCombiner::visitFADD(SDNode *N) { 1915 SDOperand N0 = N->getOperand(0); 1916 SDOperand N1 = N->getOperand(1); 1917 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1918 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1919 MVT::ValueType VT = N->getValueType(0); 1920 1921 // fold (fadd c1, c2) -> c1+c2 1922 if (N0CFP && N1CFP) 1923 return DAG.getNode(ISD::FADD, VT, N0, N1); 1924 // canonicalize constant to RHS 1925 if (N0CFP && !N1CFP) 1926 return DAG.getNode(ISD::FADD, VT, N1, N0); 1927 // fold (A + (-B)) -> A-B 1928 if (N1.getOpcode() == ISD::FNEG) 1929 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 1930 // fold ((-A) + B) -> B-A 1931 if (N0.getOpcode() == ISD::FNEG) 1932 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 1933 return SDOperand(); 1934} 1935 1936SDOperand DAGCombiner::visitFSUB(SDNode *N) { 1937 SDOperand N0 = N->getOperand(0); 1938 SDOperand N1 = N->getOperand(1); 1939 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1940 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1941 MVT::ValueType VT = N->getValueType(0); 1942 1943 // fold (fsub c1, c2) -> c1-c2 1944 if (N0CFP && N1CFP) 1945 return DAG.getNode(ISD::FSUB, VT, N0, N1); 1946 // fold (A-(-B)) -> A+B 1947 if (N1.getOpcode() == ISD::FNEG) 1948 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 1949 return SDOperand(); 1950} 1951 1952SDOperand DAGCombiner::visitFMUL(SDNode *N) { 1953 SDOperand N0 = N->getOperand(0); 1954 SDOperand N1 = N->getOperand(1); 1955 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1956 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1957 MVT::ValueType VT = N->getValueType(0); 1958 1959 // fold (fmul c1, c2) -> c1*c2 1960 if (N0CFP && N1CFP) 1961 return DAG.getNode(ISD::FMUL, VT, N0, N1); 1962 // canonicalize constant to RHS 1963 if (N0CFP && !N1CFP) 1964 return DAG.getNode(ISD::FMUL, VT, N1, N0); 1965 // fold (fmul X, 2.0) -> (fadd X, X) 1966 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 1967 return DAG.getNode(ISD::FADD, VT, N0, N0); 1968 return SDOperand(); 1969} 1970 1971SDOperand DAGCombiner::visitFDIV(SDNode *N) { 1972 SDOperand N0 = N->getOperand(0); 1973 SDOperand N1 = N->getOperand(1); 1974 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1975 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1976 MVT::ValueType VT = N->getValueType(0); 1977 1978 // fold (fdiv c1, c2) -> c1/c2 1979 if (N0CFP && N1CFP) 1980 return DAG.getNode(ISD::FDIV, VT, N0, N1); 1981 return SDOperand(); 1982} 1983 1984SDOperand DAGCombiner::visitFREM(SDNode *N) { 1985 SDOperand N0 = N->getOperand(0); 1986 SDOperand N1 = N->getOperand(1); 1987 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1988 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1989 MVT::ValueType VT = N->getValueType(0); 1990 1991 // fold (frem c1, c2) -> fmod(c1,c2) 1992 if (N0CFP && N1CFP) 1993 return DAG.getNode(ISD::FREM, VT, N0, N1); 1994 return SDOperand(); 1995} 1996 1997SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 1998 SDOperand N0 = N->getOperand(0); 1999 SDOperand N1 = N->getOperand(1); 2000 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2001 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2002 MVT::ValueType VT = N->getValueType(0); 2003 2004 if (N0CFP && N1CFP) // Constant fold 2005 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 2006 2007 if (N1CFP) { 2008 // copysign(x, c1) -> fabs(x) iff ispos(c1) 2009 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 2010 union { 2011 double d; 2012 int64_t i; 2013 } u; 2014 u.d = N1CFP->getValue(); 2015 if (u.i >= 0) 2016 return DAG.getNode(ISD::FABS, VT, N0); 2017 else 2018 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 2019 } 2020 2021 // copysign(fabs(x), y) -> copysign(x, y) 2022 // copysign(fneg(x), y) -> copysign(x, y) 2023 // copysign(copysign(x,z), y) -> copysign(x, y) 2024 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 2025 N0.getOpcode() == ISD::FCOPYSIGN) 2026 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 2027 2028 // copysign(x, abs(y)) -> abs(x) 2029 if (N1.getOpcode() == ISD::FABS) 2030 return DAG.getNode(ISD::FABS, VT, N0); 2031 2032 // copysign(x, copysign(y,z)) -> copysign(x, z) 2033 if (N1.getOpcode() == ISD::FCOPYSIGN) 2034 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 2035 2036 // copysign(x, fp_extend(y)) -> copysign(x, y) 2037 // copysign(x, fp_round(y)) -> copysign(x, y) 2038 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 2039 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 2040 2041 return SDOperand(); 2042} 2043 2044 2045 2046SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 2047 SDOperand N0 = N->getOperand(0); 2048 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2049 MVT::ValueType VT = N->getValueType(0); 2050 2051 // fold (sint_to_fp c1) -> c1fp 2052 if (N0C) 2053 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 2054 return SDOperand(); 2055} 2056 2057SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 2058 SDOperand N0 = N->getOperand(0); 2059 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2060 MVT::ValueType VT = N->getValueType(0); 2061 2062 // fold (uint_to_fp c1) -> c1fp 2063 if (N0C) 2064 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 2065 return SDOperand(); 2066} 2067 2068SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 2069 SDOperand N0 = N->getOperand(0); 2070 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2071 MVT::ValueType VT = N->getValueType(0); 2072 2073 // fold (fp_to_sint c1fp) -> c1 2074 if (N0CFP) 2075 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 2076 return SDOperand(); 2077} 2078 2079SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 2080 SDOperand N0 = N->getOperand(0); 2081 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2082 MVT::ValueType VT = N->getValueType(0); 2083 2084 // fold (fp_to_uint c1fp) -> c1 2085 if (N0CFP) 2086 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 2087 return SDOperand(); 2088} 2089 2090SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 2091 SDOperand N0 = N->getOperand(0); 2092 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2093 MVT::ValueType VT = N->getValueType(0); 2094 2095 // fold (fp_round c1fp) -> c1fp 2096 if (N0CFP) 2097 return DAG.getNode(ISD::FP_ROUND, VT, N0); 2098 return SDOperand(); 2099} 2100 2101SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 2102 SDOperand N0 = N->getOperand(0); 2103 MVT::ValueType VT = N->getValueType(0); 2104 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2105 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2106 2107 // fold (fp_round_inreg c1fp) -> c1fp 2108 if (N0CFP) { 2109 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 2110 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 2111 } 2112 return SDOperand(); 2113} 2114 2115SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 2116 SDOperand N0 = N->getOperand(0); 2117 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2118 MVT::ValueType VT = N->getValueType(0); 2119 2120 // fold (fp_extend c1fp) -> c1fp 2121 if (N0CFP) 2122 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 2123 return SDOperand(); 2124} 2125 2126SDOperand DAGCombiner::visitFNEG(SDNode *N) { 2127 SDOperand N0 = N->getOperand(0); 2128 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2129 MVT::ValueType VT = N->getValueType(0); 2130 2131 // fold (fneg c1) -> -c1 2132 if (N0CFP) 2133 return DAG.getNode(ISD::FNEG, VT, N0); 2134 // fold (fneg (sub x, y)) -> (sub y, x) 2135 if (N0.getOpcode() == ISD::SUB) 2136 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0)); 2137 // fold (fneg (fneg x)) -> x 2138 if (N0.getOpcode() == ISD::FNEG) 2139 return N0.getOperand(0); 2140 return SDOperand(); 2141} 2142 2143SDOperand DAGCombiner::visitFABS(SDNode *N) { 2144 SDOperand N0 = N->getOperand(0); 2145 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2146 MVT::ValueType VT = N->getValueType(0); 2147 2148 // fold (fabs c1) -> fabs(c1) 2149 if (N0CFP) 2150 return DAG.getNode(ISD::FABS, VT, N0); 2151 // fold (fabs (fabs x)) -> (fabs x) 2152 if (N0.getOpcode() == ISD::FABS) 2153 return N->getOperand(0); 2154 // fold (fabs (fneg x)) -> (fabs x) 2155 // fold (fabs (fcopysign x, y)) -> (fabs x) 2156 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 2157 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 2158 2159 return SDOperand(); 2160} 2161 2162SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 2163 SDOperand Chain = N->getOperand(0); 2164 SDOperand N1 = N->getOperand(1); 2165 SDOperand N2 = N->getOperand(2); 2166 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2167 2168 // never taken branch, fold to chain 2169 if (N1C && N1C->isNullValue()) 2170 return Chain; 2171 // unconditional branch 2172 if (N1C && N1C->getValue() == 1) 2173 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2174 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 2175 // on the target. 2176 if (N1.getOpcode() == ISD::SETCC && 2177 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 2178 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 2179 N1.getOperand(0), N1.getOperand(1), N2); 2180 } 2181 return SDOperand(); 2182} 2183 2184SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) { 2185 SDOperand Chain = N->getOperand(0); 2186 SDOperand N1 = N->getOperand(1); 2187 SDOperand N2 = N->getOperand(2); 2188 SDOperand N3 = N->getOperand(3); 2189 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2190 2191 // unconditional branch to true mbb 2192 if (N1C && N1C->getValue() == 1) 2193 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2194 // unconditional branch to false mbb 2195 if (N1C && N1C->isNullValue()) 2196 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3); 2197 // fold a brcondtwoway with a setcc condition into a BRTWOWAY_CC node if 2198 // BRTWOWAY_CC is legal on the target. 2199 if (N1.getOpcode() == ISD::SETCC && 2200 TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 2201 std::vector<SDOperand> Ops; 2202 Ops.push_back(Chain); 2203 Ops.push_back(N1.getOperand(2)); 2204 Ops.push_back(N1.getOperand(0)); 2205 Ops.push_back(N1.getOperand(1)); 2206 Ops.push_back(N2); 2207 Ops.push_back(N3); 2208 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); 2209 } 2210 return SDOperand(); 2211} 2212 2213// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 2214// 2215SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 2216 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 2217 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 2218 2219 // Use SimplifySetCC to simplify SETCC's. 2220 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 2221 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 2222 2223 // fold br_cc true, dest -> br dest (unconditional branch) 2224 if (SCCC && SCCC->getValue()) 2225 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 2226 N->getOperand(4)); 2227 // fold br_cc false, dest -> unconditional fall through 2228 if (SCCC && SCCC->isNullValue()) 2229 return N->getOperand(0); 2230 // fold to a simpler setcc 2231 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 2232 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 2233 Simp.getOperand(2), Simp.getOperand(0), 2234 Simp.getOperand(1), N->getOperand(4)); 2235 return SDOperand(); 2236} 2237 2238SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) { 2239 SDOperand Chain = N->getOperand(0); 2240 SDOperand CCN = N->getOperand(1); 2241 SDOperand LHS = N->getOperand(2); 2242 SDOperand RHS = N->getOperand(3); 2243 SDOperand N4 = N->getOperand(4); 2244 SDOperand N5 = N->getOperand(5); 2245 2246 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS, 2247 cast<CondCodeSDNode>(CCN)->get(), false); 2248 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 2249 2250 // fold select_cc lhs, rhs, x, x, cc -> x 2251 if (N4 == N5) 2252 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 2253 // fold select_cc true, x, y -> x 2254 if (SCCC && SCCC->getValue()) 2255 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 2256 // fold select_cc false, x, y -> y 2257 if (SCCC && SCCC->isNullValue()) 2258 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5); 2259 // fold to a simpler setcc 2260 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) { 2261 std::vector<SDOperand> Ops; 2262 Ops.push_back(Chain); 2263 Ops.push_back(SCC.getOperand(2)); 2264 Ops.push_back(SCC.getOperand(0)); 2265 Ops.push_back(SCC.getOperand(1)); 2266 Ops.push_back(N4); 2267 Ops.push_back(N5); 2268 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); 2269 } 2270 return SDOperand(); 2271} 2272 2273SDOperand DAGCombiner::visitLOAD(SDNode *N) { 2274 SDOperand Chain = N->getOperand(0); 2275 SDOperand Ptr = N->getOperand(1); 2276 SDOperand SrcValue = N->getOperand(2); 2277 2278 // If this load is directly stored, replace the load value with the stored 2279 // value. 2280 // TODO: Handle store large -> read small portion. 2281 // TODO: Handle TRUNCSTORE/EXTLOAD 2282 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2283 Chain.getOperand(1).getValueType() == N->getValueType(0)) 2284 return CombineTo(N, Chain.getOperand(1), Chain); 2285 2286 return SDOperand(); 2287} 2288 2289SDOperand DAGCombiner::visitSTORE(SDNode *N) { 2290 SDOperand Chain = N->getOperand(0); 2291 SDOperand Value = N->getOperand(1); 2292 SDOperand Ptr = N->getOperand(2); 2293 SDOperand SrcValue = N->getOperand(3); 2294 2295 // If this is a store that kills a previous store, remove the previous store. 2296 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2297 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ && 2298 // Make sure that these stores are the same value type: 2299 // FIXME: we really care that the second store is >= size of the first. 2300 Value.getValueType() == Chain.getOperand(1).getValueType()) { 2301 // Create a new store of Value that replaces both stores. 2302 SDNode *PrevStore = Chain.Val; 2303 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 2304 return Chain; 2305 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 2306 PrevStore->getOperand(0), Value, Ptr, 2307 SrcValue); 2308 CombineTo(N, NewStore); // Nuke this store. 2309 CombineTo(PrevStore, NewStore); // Nuke the previous store. 2310 return SDOperand(N, 0); 2311 } 2312 2313 // If this is a store of a bit convert, store the input value. 2314 // FIXME: This needs to know that the resultant store does not need a 2315 // higher alignment than the original. 2316 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) 2317 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0), 2318 Ptr, SrcValue); 2319 2320 return SDOperand(); 2321} 2322 2323SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 2324 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 2325 2326 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 2327 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 2328 // If we got a simplified select_cc node back from SimplifySelectCC, then 2329 // break it down into a new SETCC node, and a new SELECT node, and then return 2330 // the SELECT node, since we were called with a SELECT node. 2331 if (SCC.Val) { 2332 // Check to see if we got a select_cc back (to turn into setcc/select). 2333 // Otherwise, just return whatever node we got back, like fabs. 2334 if (SCC.getOpcode() == ISD::SELECT_CC) { 2335 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 2336 SCC.getOperand(0), SCC.getOperand(1), 2337 SCC.getOperand(4)); 2338 AddToWorkList(SETCC.Val); 2339 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 2340 SCC.getOperand(3), SETCC); 2341 } 2342 return SCC; 2343 } 2344 return SDOperand(); 2345} 2346 2347/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 2348/// are the two values being selected between, see if we can simplify the 2349/// select. 2350/// 2351bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 2352 SDOperand RHS) { 2353 2354 // If this is a select from two identical things, try to pull the operation 2355 // through the select. 2356 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 2357#if 0 2358 std::cerr << "SELECT: ["; LHS.Val->dump(); 2359 std::cerr << "] ["; RHS.Val->dump(); 2360 std::cerr << "]\n"; 2361#endif 2362 2363 // If this is a load and the token chain is identical, replace the select 2364 // of two loads with a load through a select of the address to load from. 2365 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 2366 // constants have been dropped into the constant pool. 2367 if ((LHS.getOpcode() == ISD::LOAD || 2368 LHS.getOpcode() == ISD::EXTLOAD || 2369 LHS.getOpcode() == ISD::ZEXTLOAD || 2370 LHS.getOpcode() == ISD::SEXTLOAD) && 2371 // Token chains must be identical. 2372 LHS.getOperand(0) == RHS.getOperand(0) && 2373 // If this is an EXTLOAD, the VT's must match. 2374 (LHS.getOpcode() == ISD::LOAD || 2375 LHS.getOperand(3) == RHS.getOperand(3))) { 2376 // FIXME: this conflates two src values, discarding one. This is not 2377 // the right thing to do, but nothing uses srcvalues now. When they do, 2378 // turn SrcValue into a list of locations. 2379 SDOperand Addr; 2380 if (TheSelect->getOpcode() == ISD::SELECT) 2381 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(), 2382 TheSelect->getOperand(0), LHS.getOperand(1), 2383 RHS.getOperand(1)); 2384 else 2385 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(), 2386 TheSelect->getOperand(0), 2387 TheSelect->getOperand(1), 2388 LHS.getOperand(1), RHS.getOperand(1), 2389 TheSelect->getOperand(4)); 2390 2391 SDOperand Load; 2392 if (LHS.getOpcode() == ISD::LOAD) 2393 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0), 2394 Addr, LHS.getOperand(2)); 2395 else 2396 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0), 2397 LHS.getOperand(0), Addr, LHS.getOperand(2), 2398 cast<VTSDNode>(LHS.getOperand(3))->getVT()); 2399 // Users of the select now use the result of the load. 2400 CombineTo(TheSelect, Load); 2401 2402 // Users of the old loads now use the new load's chain. We know the 2403 // old-load value is dead now. 2404 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 2405 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 2406 return true; 2407 } 2408 } 2409 2410 return false; 2411} 2412 2413SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 2414 SDOperand N2, SDOperand N3, 2415 ISD::CondCode CC) { 2416 2417 MVT::ValueType VT = N2.getValueType(); 2418 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 2419 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 2420 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 2421 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 2422 2423 // Determine if the condition we're dealing with is constant 2424 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2425 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 2426 2427 // fold select_cc true, x, y -> x 2428 if (SCCC && SCCC->getValue()) 2429 return N2; 2430 // fold select_cc false, x, y -> y 2431 if (SCCC && SCCC->getValue() == 0) 2432 return N3; 2433 2434 // Check to see if we can simplify the select into an fabs node 2435 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 2436 // Allow either -0.0 or 0.0 2437 if (CFP->getValue() == 0.0) { 2438 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 2439 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 2440 N0 == N2 && N3.getOpcode() == ISD::FNEG && 2441 N2 == N3.getOperand(0)) 2442 return DAG.getNode(ISD::FABS, VT, N0); 2443 2444 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 2445 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 2446 N0 == N3 && N2.getOpcode() == ISD::FNEG && 2447 N2.getOperand(0) == N3) 2448 return DAG.getNode(ISD::FABS, VT, N3); 2449 } 2450 } 2451 2452 // Check to see if we can perform the "gzip trick", transforming 2453 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 2454 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 2455 MVT::isInteger(N0.getValueType()) && 2456 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 2457 MVT::ValueType XType = N0.getValueType(); 2458 MVT::ValueType AType = N2.getValueType(); 2459 if (XType >= AType) { 2460 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 2461 // single-bit constant. 2462 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 2463 unsigned ShCtV = Log2_64(N2C->getValue()); 2464 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 2465 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 2466 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 2467 AddToWorkList(Shift.Val); 2468 if (XType > AType) { 2469 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2470 AddToWorkList(Shift.Val); 2471 } 2472 return DAG.getNode(ISD::AND, AType, Shift, N2); 2473 } 2474 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2475 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2476 TLI.getShiftAmountTy())); 2477 AddToWorkList(Shift.Val); 2478 if (XType > AType) { 2479 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2480 AddToWorkList(Shift.Val); 2481 } 2482 return DAG.getNode(ISD::AND, AType, Shift, N2); 2483 } 2484 } 2485 2486 // fold select C, 16, 0 -> shl C, 4 2487 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 2488 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 2489 // Get a SetCC of the condition 2490 // FIXME: Should probably make sure that setcc is legal if we ever have a 2491 // target where it isn't. 2492 SDOperand Temp, SCC; 2493 // cast from setcc result type to select result type 2494 if (AfterLegalize) { 2495 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2496 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 2497 } else { 2498 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 2499 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 2500 } 2501 AddToWorkList(SCC.Val); 2502 AddToWorkList(Temp.Val); 2503 // shl setcc result by log2 n2c 2504 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 2505 DAG.getConstant(Log2_64(N2C->getValue()), 2506 TLI.getShiftAmountTy())); 2507 } 2508 2509 // Check to see if this is the equivalent of setcc 2510 // FIXME: Turn all of these into setcc if setcc if setcc is legal 2511 // otherwise, go ahead with the folds. 2512 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 2513 MVT::ValueType XType = N0.getValueType(); 2514 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 2515 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2516 if (Res.getValueType() != VT) 2517 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 2518 return Res; 2519 } 2520 2521 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 2522 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 2523 TLI.isOperationLegal(ISD::CTLZ, XType)) { 2524 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 2525 return DAG.getNode(ISD::SRL, XType, Ctlz, 2526 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 2527 TLI.getShiftAmountTy())); 2528 } 2529 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 2530 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 2531 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 2532 N0); 2533 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 2534 DAG.getConstant(~0ULL, XType)); 2535 return DAG.getNode(ISD::SRL, XType, 2536 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 2537 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2538 TLI.getShiftAmountTy())); 2539 } 2540 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 2541 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 2542 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 2543 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2544 TLI.getShiftAmountTy())); 2545 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 2546 } 2547 } 2548 2549 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 2550 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 2551 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 2552 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 2553 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 2554 MVT::ValueType XType = N0.getValueType(); 2555 if (SubC->isNullValue() && MVT::isInteger(XType)) { 2556 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2557 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2558 TLI.getShiftAmountTy())); 2559 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 2560 AddToWorkList(Shift.Val); 2561 AddToWorkList(Add.Val); 2562 return DAG.getNode(ISD::XOR, XType, Add, Shift); 2563 } 2564 } 2565 } 2566 2567 return SDOperand(); 2568} 2569 2570SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 2571 SDOperand N1, ISD::CondCode Cond, 2572 bool foldBooleans) { 2573 // These setcc operations always fold. 2574 switch (Cond) { 2575 default: break; 2576 case ISD::SETFALSE: 2577 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 2578 case ISD::SETTRUE: 2579 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 2580 } 2581 2582 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 2583 uint64_t C1 = N1C->getValue(); 2584 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 2585 uint64_t C0 = N0C->getValue(); 2586 2587 // Sign extend the operands if required 2588 if (ISD::isSignedIntSetCC(Cond)) { 2589 C0 = N0C->getSignExtended(); 2590 C1 = N1C->getSignExtended(); 2591 } 2592 2593 switch (Cond) { 2594 default: assert(0 && "Unknown integer setcc!"); 2595 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2596 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2597 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 2598 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 2599 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 2600 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 2601 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 2602 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 2603 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 2604 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 2605 } 2606 } else { 2607 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 2608 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 2609 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 2610 2611 // If the comparison constant has bits in the upper part, the 2612 // zero-extended value could never match. 2613 if (C1 & (~0ULL << InSize)) { 2614 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 2615 switch (Cond) { 2616 case ISD::SETUGT: 2617 case ISD::SETUGE: 2618 case ISD::SETEQ: return DAG.getConstant(0, VT); 2619 case ISD::SETULT: 2620 case ISD::SETULE: 2621 case ISD::SETNE: return DAG.getConstant(1, VT); 2622 case ISD::SETGT: 2623 case ISD::SETGE: 2624 // True if the sign bit of C1 is set. 2625 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 2626 case ISD::SETLT: 2627 case ISD::SETLE: 2628 // True if the sign bit of C1 isn't set. 2629 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 2630 default: 2631 break; 2632 } 2633 } 2634 2635 // Otherwise, we can perform the comparison with the low bits. 2636 switch (Cond) { 2637 case ISD::SETEQ: 2638 case ISD::SETNE: 2639 case ISD::SETUGT: 2640 case ISD::SETUGE: 2641 case ISD::SETULT: 2642 case ISD::SETULE: 2643 return DAG.getSetCC(VT, N0.getOperand(0), 2644 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 2645 Cond); 2646 default: 2647 break; // todo, be more careful with signed comparisons 2648 } 2649 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2650 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2651 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2652 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 2653 MVT::ValueType ExtDstTy = N0.getValueType(); 2654 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 2655 2656 // If the extended part has any inconsistent bits, it cannot ever 2657 // compare equal. In other words, they have to be all ones or all 2658 // zeros. 2659 uint64_t ExtBits = 2660 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 2661 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 2662 return DAG.getConstant(Cond == ISD::SETNE, VT); 2663 2664 SDOperand ZextOp; 2665 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 2666 if (Op0Ty == ExtSrcTy) { 2667 ZextOp = N0.getOperand(0); 2668 } else { 2669 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 2670 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 2671 DAG.getConstant(Imm, Op0Ty)); 2672 } 2673 AddToWorkList(ZextOp.Val); 2674 // Otherwise, make this a use of a zext. 2675 return DAG.getSetCC(VT, ZextOp, 2676 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 2677 ExtDstTy), 2678 Cond); 2679 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && 2680 (Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2681 (N0.getOpcode() == ISD::XOR || 2682 (N0.getOpcode() == ISD::AND && 2683 N0.getOperand(0).getOpcode() == ISD::XOR && 2684 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 2685 isa<ConstantSDNode>(N0.getOperand(1)) && 2686 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { 2687 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can 2688 // only do this if the top bits are known zero. 2689 if (TLI.MaskedValueIsZero(N1, 2690 MVT::getIntVTBitMask(N0.getValueType())-1)) { 2691 // Okay, get the un-inverted input value. 2692 SDOperand Val; 2693 if (N0.getOpcode() == ISD::XOR) 2694 Val = N0.getOperand(0); 2695 else { 2696 assert(N0.getOpcode() == ISD::AND && 2697 N0.getOperand(0).getOpcode() == ISD::XOR); 2698 // ((X^1)&1)^1 -> X & 1 2699 Val = DAG.getNode(ISD::AND, N0.getValueType(), 2700 N0.getOperand(0).getOperand(0), N0.getOperand(1)); 2701 } 2702 return DAG.getSetCC(VT, Val, N1, 2703 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2704 } 2705 } 2706 2707 uint64_t MinVal, MaxVal; 2708 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 2709 if (ISD::isSignedIntSetCC(Cond)) { 2710 MinVal = 1ULL << (OperandBitSize-1); 2711 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 2712 MaxVal = ~0ULL >> (65-OperandBitSize); 2713 else 2714 MaxVal = 0; 2715 } else { 2716 MinVal = 0; 2717 MaxVal = ~0ULL >> (64-OperandBitSize); 2718 } 2719 2720 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2721 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2722 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2723 --C1; // X >= C0 --> X > (C0-1) 2724 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2725 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2726 } 2727 2728 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2729 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2730 ++C1; // X <= C0 --> X < (C0+1) 2731 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2732 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2733 } 2734 2735 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2736 return DAG.getConstant(0, VT); // X < MIN --> false 2737 2738 // Canonicalize setgt X, Min --> setne X, Min 2739 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2740 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2741 // Canonicalize setlt X, Max --> setne X, Max 2742 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2743 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2744 2745 // If we have setult X, 1, turn it into seteq X, 0 2746 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2747 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 2748 ISD::SETEQ); 2749 // If we have setugt X, Max-1, turn it into seteq X, Max 2750 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2751 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 2752 ISD::SETEQ); 2753 2754 // If we have "setcc X, C0", check to see if we can shrink the immediate 2755 // by changing cc. 2756 2757 // SETUGT X, SINTMAX -> SETLT X, 0 2758 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 2759 C1 == (~0ULL >> (65-OperandBitSize))) 2760 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 2761 ISD::SETLT); 2762 2763 // FIXME: Implement the rest of these. 2764 2765 // Fold bit comparisons when we can. 2766 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2767 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 2768 if (ConstantSDNode *AndRHS = 2769 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2770 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2771 // Perform the xform if the AND RHS is a single bit. 2772 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 2773 return DAG.getNode(ISD::SRL, VT, N0, 2774 DAG.getConstant(Log2_64(AndRHS->getValue()), 2775 TLI.getShiftAmountTy())); 2776 } 2777 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 2778 // (X & 8) == 8 --> (X & 8) >> 3 2779 // Perform the xform if C1 is a single bit. 2780 if ((C1 & (C1-1)) == 0) { 2781 return DAG.getNode(ISD::SRL, VT, N0, 2782 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 2783 } 2784 } 2785 } 2786 } 2787 } else if (isa<ConstantSDNode>(N0.Val)) { 2788 // Ensure that the constant occurs on the RHS. 2789 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2790 } 2791 2792 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 2793 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 2794 double C0 = N0C->getValue(), C1 = N1C->getValue(); 2795 2796 switch (Cond) { 2797 default: break; // FIXME: Implement the rest of these! 2798 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2799 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2800 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 2801 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 2802 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 2803 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 2804 } 2805 } else { 2806 // Ensure that the constant occurs on the RHS. 2807 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2808 } 2809 2810 if (N0 == N1) { 2811 // We can always fold X == Y for integer setcc's. 2812 if (MVT::isInteger(N0.getValueType())) 2813 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2814 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2815 if (UOF == 2) // FP operators that are undefined on NaNs. 2816 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2817 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2818 return DAG.getConstant(UOF, VT); 2819 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2820 // if it is not already. 2821 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2822 if (NewCond != Cond) 2823 return DAG.getSetCC(VT, N0, N1, NewCond); 2824 } 2825 2826 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2827 MVT::isInteger(N0.getValueType())) { 2828 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2829 N0.getOpcode() == ISD::XOR) { 2830 // Simplify (X+Y) == (X+Z) --> Y == Z 2831 if (N0.getOpcode() == N1.getOpcode()) { 2832 if (N0.getOperand(0) == N1.getOperand(0)) 2833 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 2834 if (N0.getOperand(1) == N1.getOperand(1)) 2835 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 2836 if (isCommutativeBinOp(N0.getOpcode())) { 2837 // If X op Y == Y op X, try other combinations. 2838 if (N0.getOperand(0) == N1.getOperand(1)) 2839 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 2840 if (N0.getOperand(1) == N1.getOperand(0)) 2841 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 2842 } 2843 } 2844 2845 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2846 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2847 // Turn (X+C1) == C2 --> X == C2-C1 2848 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 2849 return DAG.getSetCC(VT, N0.getOperand(0), 2850 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 2851 N0.getValueType()), Cond); 2852 } 2853 2854 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2855 if (N0.getOpcode() == ISD::XOR) 2856 // If we know that all of the inverted bits are zero, don't bother 2857 // performing the inversion. 2858 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) 2859 return DAG.getSetCC(VT, N0.getOperand(0), 2860 DAG.getConstant(LHSR->getValue()^RHSC->getValue(), 2861 N0.getValueType()), Cond); 2862 } 2863 2864 // Turn (C1-X) == C2 --> X == C1-C2 2865 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2866 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 2867 return DAG.getSetCC(VT, N0.getOperand(1), 2868 DAG.getConstant(SUBC->getValue()-RHSC->getValue(), 2869 N0.getValueType()), Cond); 2870 } 2871 } 2872 } 2873 2874 // Simplify (X+Z) == X --> Z == 0 2875 if (N0.getOperand(0) == N1) 2876 return DAG.getSetCC(VT, N0.getOperand(1), 2877 DAG.getConstant(0, N0.getValueType()), Cond); 2878 if (N0.getOperand(1) == N1) { 2879 if (isCommutativeBinOp(N0.getOpcode())) 2880 return DAG.getSetCC(VT, N0.getOperand(0), 2881 DAG.getConstant(0, N0.getValueType()), Cond); 2882 else { 2883 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2884 // (Z-X) == X --> Z == X<<1 2885 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 2886 N1, 2887 DAG.getConstant(1,TLI.getShiftAmountTy())); 2888 AddToWorkList(SH.Val); 2889 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 2890 } 2891 } 2892 } 2893 2894 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2895 N1.getOpcode() == ISD::XOR) { 2896 // Simplify X == (X+Z) --> Z == 0 2897 if (N1.getOperand(0) == N0) { 2898 return DAG.getSetCC(VT, N1.getOperand(1), 2899 DAG.getConstant(0, N1.getValueType()), Cond); 2900 } else if (N1.getOperand(1) == N0) { 2901 if (isCommutativeBinOp(N1.getOpcode())) { 2902 return DAG.getSetCC(VT, N1.getOperand(0), 2903 DAG.getConstant(0, N1.getValueType()), Cond); 2904 } else { 2905 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2906 // X == (Z-X) --> X<<1 == Z 2907 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 2908 DAG.getConstant(1,TLI.getShiftAmountTy())); 2909 AddToWorkList(SH.Val); 2910 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 2911 } 2912 } 2913 } 2914 } 2915 2916 // Fold away ALL boolean setcc's. 2917 SDOperand Temp; 2918 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2919 switch (Cond) { 2920 default: assert(0 && "Unknown integer setcc!"); 2921 case ISD::SETEQ: // X == Y -> (X^Y)^1 2922 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2923 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 2924 AddToWorkList(Temp.Val); 2925 break; 2926 case ISD::SETNE: // X != Y --> (X^Y) 2927 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2928 break; 2929 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 2930 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 2931 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2932 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 2933 AddToWorkList(Temp.Val); 2934 break; 2935 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 2936 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 2937 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2938 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 2939 AddToWorkList(Temp.Val); 2940 break; 2941 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 2942 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 2943 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2944 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 2945 AddToWorkList(Temp.Val); 2946 break; 2947 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 2948 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 2949 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2950 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 2951 break; 2952 } 2953 if (VT != MVT::i1) { 2954 AddToWorkList(N0.Val); 2955 // FIXME: If running after legalize, we probably can't do this. 2956 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2957 } 2958 return N0; 2959 } 2960 2961 // Could not fold it. 2962 return SDOperand(); 2963} 2964 2965/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2966/// return a DAG expression to select that will generate the same value by 2967/// multiplying by a magic number. See: 2968/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2969SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 2970 MVT::ValueType VT = N->getValueType(0); 2971 2972 // Check to see if we can do this. 2973 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2974 return SDOperand(); // BuildSDIV only operates on i32 or i64 2975 if (!TLI.isOperationLegal(ISD::MULHS, VT)) 2976 return SDOperand(); // Make sure the target supports MULHS. 2977 2978 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 2979 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 2980 2981 // Multiply the numerator (operand 0) by the magic value 2982 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 2983 DAG.getConstant(magics.m, VT)); 2984 // If d > 0 and m < 0, add the numerator 2985 if (d > 0 && magics.m < 0) { 2986 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 2987 AddToWorkList(Q.Val); 2988 } 2989 // If d < 0 and m > 0, subtract the numerator. 2990 if (d < 0 && magics.m > 0) { 2991 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 2992 AddToWorkList(Q.Val); 2993 } 2994 // Shift right algebraic if shift value is nonzero 2995 if (magics.s > 0) { 2996 Q = DAG.getNode(ISD::SRA, VT, Q, 2997 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 2998 AddToWorkList(Q.Val); 2999 } 3000 // Extract the sign bit and add it to the quotient 3001 SDOperand T = 3002 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 3003 TLI.getShiftAmountTy())); 3004 AddToWorkList(T.Val); 3005 return DAG.getNode(ISD::ADD, VT, Q, T); 3006} 3007 3008/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3009/// return a DAG expression to select that will generate the same value by 3010/// multiplying by a magic number. See: 3011/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3012SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 3013 MVT::ValueType VT = N->getValueType(0); 3014 3015 // Check to see if we can do this. 3016 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 3017 return SDOperand(); // BuildUDIV only operates on i32 or i64 3018 if (!TLI.isOperationLegal(ISD::MULHU, VT)) 3019 return SDOperand(); // Make sure the target supports MULHU. 3020 3021 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 3022 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 3023 3024 // Multiply the numerator (operand 0) by the magic value 3025 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 3026 DAG.getConstant(magics.m, VT)); 3027 AddToWorkList(Q.Val); 3028 3029 if (magics.a == 0) { 3030 return DAG.getNode(ISD::SRL, VT, Q, 3031 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 3032 } else { 3033 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 3034 AddToWorkList(NPQ.Val); 3035 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 3036 DAG.getConstant(1, TLI.getShiftAmountTy())); 3037 AddToWorkList(NPQ.Val); 3038 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 3039 AddToWorkList(NPQ.Val); 3040 return DAG.getNode(ISD::SRL, VT, NPQ, 3041 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy())); 3042 } 3043} 3044 3045// SelectionDAG::Combine - This is the entry point for the file. 3046// 3047void SelectionDAG::Combine(bool RunningAfterLegalize) { 3048 /// run - This is the main entry point to this class. 3049 /// 3050 DAGCombiner(*this).Run(RunningAfterLegalize); 3051} 3052