DAGCombiner.cpp revision e7bec0dbb50235ec60f78f1f7b3f6d2f6bb5cd91
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: make truncate see through SIGN_EXTEND and AND 26// FIXME: divide by zero is currently left unfolded. do we want to turn this 27// into an undef? 28// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 29// 30//===----------------------------------------------------------------------===// 31 32#define DEBUG_TYPE "dagcombine" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Target/TargetLowering.h" 38#include "llvm/Support/Visibility.h" 39#include <algorithm> 40#include <cmath> 41#include <iostream> 42using namespace llvm; 43 44namespace { 45 static Statistic<> NodesCombined ("dagcombiner", 46 "Number of dag nodes combined"); 47 48 class VISIBILITY_HIDDEN DAGCombiner { 49 SelectionDAG &DAG; 50 TargetLowering &TLI; 51 bool AfterLegalize; 52 53 // Worklist of all of the nodes that need to be simplified. 54 std::vector<SDNode*> WorkList; 55 56 /// AddUsersToWorkList - When an instruction is simplified, add all users of 57 /// the instruction to the work lists because they might get more simplified 58 /// now. 59 /// 60 void AddUsersToWorkList(SDNode *N) { 61 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 62 UI != UE; ++UI) 63 WorkList.push_back(*UI); 64 } 65 66 /// removeFromWorkList - remove all instances of N from the worklist. 67 /// 68 void removeFromWorkList(SDNode *N) { 69 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 70 WorkList.end()); 71 } 72 73 public: 74 void AddToWorkList(SDNode *N) { 75 WorkList.push_back(N); 76 } 77 78 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 79 ++NodesCombined; 80 DEBUG(std::cerr << "\nReplacing "; N->dump(); 81 std::cerr << "\nWith: "; To[0].Val->dump(&DAG); 82 std::cerr << " and " << To.size()-1 << " other values\n"); 83 std::vector<SDNode*> NowDead; 84 DAG.ReplaceAllUsesWith(N, To, &NowDead); 85 86 // Push the new nodes and any users onto the worklist 87 for (unsigned i = 0, e = To.size(); i != e; ++i) { 88 WorkList.push_back(To[i].Val); 89 AddUsersToWorkList(To[i].Val); 90 } 91 92 // Nodes can end up on the worklist more than once. Make sure we do 93 // not process a node that has been replaced. 94 removeFromWorkList(N); 95 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 96 removeFromWorkList(NowDead[i]); 97 98 // Finally, since the node is now dead, remove it from the graph. 99 DAG.DeleteNode(N); 100 return SDOperand(N, 0); 101 } 102 103 SDOperand CombineTo(SDNode *N, SDOperand Res) { 104 std::vector<SDOperand> To; 105 To.push_back(Res); 106 return CombineTo(N, To); 107 } 108 109 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 110 std::vector<SDOperand> To; 111 To.push_back(Res0); 112 To.push_back(Res1); 113 return CombineTo(N, To); 114 } 115 private: 116 117 /// SimplifyDemandedBits - Check the specified integer node value to see if 118 /// it can be simplified or if things it uses can be simplified by bit 119 /// propagation. If so, return true. 120 bool SimplifyDemandedBits(SDOperand Op) { 121 TargetLowering::TargetLoweringOpt TLO(DAG); 122 uint64_t KnownZero, KnownOne; 123 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 124 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 125 return false; 126 127 // Revisit the node. 128 WorkList.push_back(Op.Val); 129 130 // Replace the old value with the new one. 131 ++NodesCombined; 132 DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump(); 133 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG)); 134 135 std::vector<SDNode*> NowDead; 136 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 137 138 // Push the new node and any (possibly new) users onto the worklist. 139 WorkList.push_back(TLO.New.Val); 140 AddUsersToWorkList(TLO.New.Val); 141 142 // Nodes can end up on the worklist more than once. Make sure we do 143 // not process a node that has been replaced. 144 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 145 removeFromWorkList(NowDead[i]); 146 147 // Finally, if the node is now dead, remove it from the graph. The node 148 // may not be dead if the replacement process recursively simplified to 149 // something else needing this node. 150 if (TLO.Old.Val->use_empty()) { 151 removeFromWorkList(TLO.Old.Val); 152 DAG.DeleteNode(TLO.Old.Val); 153 } 154 return true; 155 } 156 157 /// visit - call the node-specific routine that knows how to fold each 158 /// particular type of node. 159 SDOperand visit(SDNode *N); 160 161 // Visitation implementation - Implement dag node combining for different 162 // node types. The semantics are as follows: 163 // Return Value: 164 // SDOperand.Val == 0 - No change was made 165 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 166 // otherwise - N should be replaced by the returned Operand. 167 // 168 SDOperand visitTokenFactor(SDNode *N); 169 SDOperand visitADD(SDNode *N); 170 SDOperand visitSUB(SDNode *N); 171 SDOperand visitMUL(SDNode *N); 172 SDOperand visitSDIV(SDNode *N); 173 SDOperand visitUDIV(SDNode *N); 174 SDOperand visitSREM(SDNode *N); 175 SDOperand visitUREM(SDNode *N); 176 SDOperand visitMULHU(SDNode *N); 177 SDOperand visitMULHS(SDNode *N); 178 SDOperand visitAND(SDNode *N); 179 SDOperand visitOR(SDNode *N); 180 SDOperand visitXOR(SDNode *N); 181 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp); 182 SDOperand visitSHL(SDNode *N); 183 SDOperand visitSRA(SDNode *N); 184 SDOperand visitSRL(SDNode *N); 185 SDOperand visitCTLZ(SDNode *N); 186 SDOperand visitCTTZ(SDNode *N); 187 SDOperand visitCTPOP(SDNode *N); 188 SDOperand visitSELECT(SDNode *N); 189 SDOperand visitSELECT_CC(SDNode *N); 190 SDOperand visitSETCC(SDNode *N); 191 SDOperand visitSIGN_EXTEND(SDNode *N); 192 SDOperand visitZERO_EXTEND(SDNode *N); 193 SDOperand visitANY_EXTEND(SDNode *N); 194 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 195 SDOperand visitTRUNCATE(SDNode *N); 196 SDOperand visitBIT_CONVERT(SDNode *N); 197 SDOperand visitVBIT_CONVERT(SDNode *N); 198 SDOperand visitFADD(SDNode *N); 199 SDOperand visitFSUB(SDNode *N); 200 SDOperand visitFMUL(SDNode *N); 201 SDOperand visitFDIV(SDNode *N); 202 SDOperand visitFREM(SDNode *N); 203 SDOperand visitFCOPYSIGN(SDNode *N); 204 SDOperand visitSINT_TO_FP(SDNode *N); 205 SDOperand visitUINT_TO_FP(SDNode *N); 206 SDOperand visitFP_TO_SINT(SDNode *N); 207 SDOperand visitFP_TO_UINT(SDNode *N); 208 SDOperand visitFP_ROUND(SDNode *N); 209 SDOperand visitFP_ROUND_INREG(SDNode *N); 210 SDOperand visitFP_EXTEND(SDNode *N); 211 SDOperand visitFNEG(SDNode *N); 212 SDOperand visitFABS(SDNode *N); 213 SDOperand visitBRCOND(SDNode *N); 214 SDOperand visitBR_CC(SDNode *N); 215 SDOperand visitLOAD(SDNode *N); 216 SDOperand visitXEXTLOAD(SDNode *N); 217 SDOperand visitSTORE(SDNode *N); 218 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 219 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N); 220 SDOperand visitVBUILD_VECTOR(SDNode *N); 221 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 222 SDOperand visitVVECTOR_SHUFFLE(SDNode *N); 223 224 SDOperand XformToShuffleWithZero(SDNode *N); 225 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 226 227 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 228 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 229 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 230 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 231 SDOperand N3, ISD::CondCode CC); 232 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 233 ISD::CondCode Cond, bool foldBooleans = true); 234 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType); 235 SDOperand BuildSDIV(SDNode *N); 236 SDOperand BuildUDIV(SDNode *N); 237public: 238 DAGCombiner(SelectionDAG &D) 239 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 240 241 /// Run - runs the dag combiner on all nodes in the work list 242 void Run(bool RunningAfterLegalize); 243 }; 244} 245 246//===----------------------------------------------------------------------===// 247// TargetLowering::DAGCombinerInfo implementation 248//===----------------------------------------------------------------------===// 249 250void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 251 ((DAGCombiner*)DC)->AddToWorkList(N); 252} 253 254SDOperand TargetLowering::DAGCombinerInfo:: 255CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 256 return ((DAGCombiner*)DC)->CombineTo(N, To); 257} 258 259SDOperand TargetLowering::DAGCombinerInfo:: 260CombineTo(SDNode *N, SDOperand Res) { 261 return ((DAGCombiner*)DC)->CombineTo(N, Res); 262} 263 264 265SDOperand TargetLowering::DAGCombinerInfo:: 266CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 267 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 268} 269 270 271 272 273//===----------------------------------------------------------------------===// 274 275 276// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 277// that selects between the values 1 and 0, making it equivalent to a setcc. 278// Also, set the incoming LHS, RHS, and CC references to the appropriate 279// nodes based on the type of node we are checking. This simplifies life a 280// bit for the callers. 281static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 282 SDOperand &CC) { 283 if (N.getOpcode() == ISD::SETCC) { 284 LHS = N.getOperand(0); 285 RHS = N.getOperand(1); 286 CC = N.getOperand(2); 287 return true; 288 } 289 if (N.getOpcode() == ISD::SELECT_CC && 290 N.getOperand(2).getOpcode() == ISD::Constant && 291 N.getOperand(3).getOpcode() == ISD::Constant && 292 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 293 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 294 LHS = N.getOperand(0); 295 RHS = N.getOperand(1); 296 CC = N.getOperand(4); 297 return true; 298 } 299 return false; 300} 301 302// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 303// one use. If this is true, it allows the users to invert the operation for 304// free when it is profitable to do so. 305static bool isOneUseSetCC(SDOperand N) { 306 SDOperand N0, N1, N2; 307 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 308 return true; 309 return false; 310} 311 312// FIXME: This should probably go in the ISD class rather than being duplicated 313// in several files. 314static bool isCommutativeBinOp(unsigned Opcode) { 315 switch (Opcode) { 316 case ISD::ADD: 317 case ISD::MUL: 318 case ISD::AND: 319 case ISD::OR: 320 case ISD::XOR: return true; 321 default: return false; // FIXME: Need commutative info for user ops! 322 } 323} 324 325SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 326 MVT::ValueType VT = N0.getValueType(); 327 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 328 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 329 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 330 if (isa<ConstantSDNode>(N1)) { 331 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 332 AddToWorkList(OpNode.Val); 333 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 334 } else if (N0.hasOneUse()) { 335 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 336 AddToWorkList(OpNode.Val); 337 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 338 } 339 } 340 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 341 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 342 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 343 if (isa<ConstantSDNode>(N0)) { 344 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 345 AddToWorkList(OpNode.Val); 346 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 347 } else if (N1.hasOneUse()) { 348 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 349 AddToWorkList(OpNode.Val); 350 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 351 } 352 } 353 return SDOperand(); 354} 355 356void DAGCombiner::Run(bool RunningAfterLegalize) { 357 // set the instance variable, so that the various visit routines may use it. 358 AfterLegalize = RunningAfterLegalize; 359 360 // Add all the dag nodes to the worklist. 361 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 362 E = DAG.allnodes_end(); I != E; ++I) 363 WorkList.push_back(I); 364 365 // Create a dummy node (which is not added to allnodes), that adds a reference 366 // to the root node, preventing it from being deleted, and tracking any 367 // changes of the root. 368 HandleSDNode Dummy(DAG.getRoot()); 369 370 371 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 372 TargetLowering::DAGCombinerInfo 373 DagCombineInfo(DAG, !RunningAfterLegalize, this); 374 375 // while the worklist isn't empty, inspect the node on the end of it and 376 // try and combine it. 377 while (!WorkList.empty()) { 378 SDNode *N = WorkList.back(); 379 WorkList.pop_back(); 380 381 // If N has no uses, it is dead. Make sure to revisit all N's operands once 382 // N is deleted from the DAG, since they too may now be dead or may have a 383 // reduced number of uses, allowing other xforms. 384 if (N->use_empty() && N != &Dummy) { 385 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 386 WorkList.push_back(N->getOperand(i).Val); 387 388 removeFromWorkList(N); 389 DAG.DeleteNode(N); 390 continue; 391 } 392 393 SDOperand RV = visit(N); 394 395 // If nothing happened, try a target-specific DAG combine. 396 if (RV.Val == 0) { 397 assert(N->getOpcode() != ISD::DELETED_NODE && 398 "Node was deleted but visit returned NULL!"); 399 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 400 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 401 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 402 } 403 404 if (RV.Val) { 405 ++NodesCombined; 406 // If we get back the same node we passed in, rather than a new node or 407 // zero, we know that the node must have defined multiple values and 408 // CombineTo was used. Since CombineTo takes care of the worklist 409 // mechanics for us, we have no work to do in this case. 410 if (RV.Val != N) { 411 assert(N->getOpcode() != ISD::DELETED_NODE && 412 RV.Val->getOpcode() != ISD::DELETED_NODE && 413 "Node was deleted but visit returned new node!"); 414 415 DEBUG(std::cerr << "\nReplacing "; N->dump(); 416 std::cerr << "\nWith: "; RV.Val->dump(&DAG); 417 std::cerr << '\n'); 418 std::vector<SDNode*> NowDead; 419 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead); 420 421 // Push the new node and any users onto the worklist 422 WorkList.push_back(RV.Val); 423 AddUsersToWorkList(RV.Val); 424 425 // Nodes can end up on the worklist more than once. Make sure we do 426 // not process a node that has been replaced. 427 removeFromWorkList(N); 428 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 429 removeFromWorkList(NowDead[i]); 430 431 // Finally, since the node is now dead, remove it from the graph. 432 DAG.DeleteNode(N); 433 } 434 } 435 } 436 437 // If the root changed (e.g. it was a dead load, update the root). 438 DAG.setRoot(Dummy.getValue()); 439} 440 441SDOperand DAGCombiner::visit(SDNode *N) { 442 switch(N->getOpcode()) { 443 default: break; 444 case ISD::TokenFactor: return visitTokenFactor(N); 445 case ISD::ADD: return visitADD(N); 446 case ISD::SUB: return visitSUB(N); 447 case ISD::MUL: return visitMUL(N); 448 case ISD::SDIV: return visitSDIV(N); 449 case ISD::UDIV: return visitUDIV(N); 450 case ISD::SREM: return visitSREM(N); 451 case ISD::UREM: return visitUREM(N); 452 case ISD::MULHU: return visitMULHU(N); 453 case ISD::MULHS: return visitMULHS(N); 454 case ISD::AND: return visitAND(N); 455 case ISD::OR: return visitOR(N); 456 case ISD::XOR: return visitXOR(N); 457 case ISD::SHL: return visitSHL(N); 458 case ISD::SRA: return visitSRA(N); 459 case ISD::SRL: return visitSRL(N); 460 case ISD::CTLZ: return visitCTLZ(N); 461 case ISD::CTTZ: return visitCTTZ(N); 462 case ISD::CTPOP: return visitCTPOP(N); 463 case ISD::SELECT: return visitSELECT(N); 464 case ISD::SELECT_CC: return visitSELECT_CC(N); 465 case ISD::SETCC: return visitSETCC(N); 466 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 467 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 468 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 469 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 470 case ISD::TRUNCATE: return visitTRUNCATE(N); 471 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 472 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N); 473 case ISD::FADD: return visitFADD(N); 474 case ISD::FSUB: return visitFSUB(N); 475 case ISD::FMUL: return visitFMUL(N); 476 case ISD::FDIV: return visitFDIV(N); 477 case ISD::FREM: return visitFREM(N); 478 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 479 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 480 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 481 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 482 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 483 case ISD::FP_ROUND: return visitFP_ROUND(N); 484 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 485 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 486 case ISD::FNEG: return visitFNEG(N); 487 case ISD::FABS: return visitFABS(N); 488 case ISD::BRCOND: return visitBRCOND(N); 489 case ISD::BR_CC: return visitBR_CC(N); 490 case ISD::LOAD: return visitLOAD(N); 491 case ISD::EXTLOAD: 492 case ISD::SEXTLOAD: 493 case ISD::ZEXTLOAD: return visitXEXTLOAD(N); 494 case ISD::STORE: return visitSTORE(N); 495 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 496 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N); 497 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N); 498 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 499 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N); 500 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD); 501 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB); 502 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL); 503 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV); 504 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV); 505 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND); 506 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR); 507 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR); 508 } 509 return SDOperand(); 510} 511 512SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 513 std::vector<SDOperand> Ops; 514 bool Changed = false; 515 516 // If the token factor has two operands and one is the entry token, replace 517 // the token factor with the other operand. 518 if (N->getNumOperands() == 2) { 519 if (N->getOperand(0).getOpcode() == ISD::EntryToken || 520 N->getOperand(0) == N->getOperand(1)) 521 return N->getOperand(1); 522 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 523 return N->getOperand(0); 524 } 525 526 // fold (tokenfactor (tokenfactor)) -> tokenfactor 527 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 528 SDOperand Op = N->getOperand(i); 529 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 530 AddToWorkList(Op.Val); // Remove dead node. 531 Changed = true; 532 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 533 Ops.push_back(Op.getOperand(j)); 534 } else if (i == 0 || N->getOperand(i) != N->getOperand(i-1)) { 535 Ops.push_back(Op); 536 } else { 537 // Deleted an operand that was the same as the last one. 538 Changed = true; 539 } 540 } 541 if (Changed) 542 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 543 return SDOperand(); 544} 545 546SDOperand DAGCombiner::visitADD(SDNode *N) { 547 SDOperand N0 = N->getOperand(0); 548 SDOperand N1 = N->getOperand(1); 549 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 550 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 551 MVT::ValueType VT = N0.getValueType(); 552 553 // fold (add c1, c2) -> c1+c2 554 if (N0C && N1C) 555 return DAG.getNode(ISD::ADD, VT, N0, N1); 556 // canonicalize constant to RHS 557 if (N0C && !N1C) 558 return DAG.getNode(ISD::ADD, VT, N1, N0); 559 // fold (add x, 0) -> x 560 if (N1C && N1C->isNullValue()) 561 return N0; 562 // fold ((c1-A)+c2) -> (c1+c2)-A 563 if (N1C && N0.getOpcode() == ISD::SUB) 564 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 565 return DAG.getNode(ISD::SUB, VT, 566 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 567 N0.getOperand(1)); 568 // reassociate add 569 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 570 if (RADD.Val != 0) 571 return RADD; 572 // fold ((0-A) + B) -> B-A 573 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 574 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 575 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 576 // fold (A + (0-B)) -> A-B 577 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 578 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 579 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 580 // fold (A+(B-A)) -> B 581 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 582 return N1.getOperand(0); 583 584 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 585 return SDOperand(N, 0); 586 587 // fold (a+b) -> (a|b) iff a and b share no bits. 588 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 589 uint64_t LHSZero, LHSOne; 590 uint64_t RHSZero, RHSOne; 591 uint64_t Mask = MVT::getIntVTBitMask(VT); 592 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 593 if (LHSZero) { 594 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 595 596 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 597 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 598 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 599 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 600 return DAG.getNode(ISD::OR, VT, N0, N1); 601 } 602 } 603 604 return SDOperand(); 605} 606 607SDOperand DAGCombiner::visitSUB(SDNode *N) { 608 SDOperand N0 = N->getOperand(0); 609 SDOperand N1 = N->getOperand(1); 610 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 611 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 612 MVT::ValueType VT = N0.getValueType(); 613 614 // fold (sub x, x) -> 0 615 if (N0 == N1) 616 return DAG.getConstant(0, N->getValueType(0)); 617 // fold (sub c1, c2) -> c1-c2 618 if (N0C && N1C) 619 return DAG.getNode(ISD::SUB, VT, N0, N1); 620 // fold (sub x, c) -> (add x, -c) 621 if (N1C) 622 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 623 // fold (A+B)-A -> B 624 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 625 return N0.getOperand(1); 626 // fold (A+B)-B -> A 627 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 628 return N0.getOperand(0); 629 return SDOperand(); 630} 631 632SDOperand DAGCombiner::visitMUL(SDNode *N) { 633 SDOperand N0 = N->getOperand(0); 634 SDOperand N1 = N->getOperand(1); 635 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 636 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 637 MVT::ValueType VT = N0.getValueType(); 638 639 // fold (mul c1, c2) -> c1*c2 640 if (N0C && N1C) 641 return DAG.getNode(ISD::MUL, VT, N0, N1); 642 // canonicalize constant to RHS 643 if (N0C && !N1C) 644 return DAG.getNode(ISD::MUL, VT, N1, N0); 645 // fold (mul x, 0) -> 0 646 if (N1C && N1C->isNullValue()) 647 return N1; 648 // fold (mul x, -1) -> 0-x 649 if (N1C && N1C->isAllOnesValue()) 650 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 651 // fold (mul x, (1 << c)) -> x << c 652 if (N1C && isPowerOf2_64(N1C->getValue())) 653 return DAG.getNode(ISD::SHL, VT, N0, 654 DAG.getConstant(Log2_64(N1C->getValue()), 655 TLI.getShiftAmountTy())); 656 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 657 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 658 // FIXME: If the input is something that is easily negated (e.g. a 659 // single-use add), we should put the negate there. 660 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 661 DAG.getNode(ISD::SHL, VT, N0, 662 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 663 TLI.getShiftAmountTy()))); 664 } 665 666 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 667 if (N1C && N0.getOpcode() == ISD::SHL && 668 isa<ConstantSDNode>(N0.getOperand(1))) { 669 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 670 AddToWorkList(C3.Val); 671 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 672 } 673 674 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 675 // use. 676 { 677 SDOperand Sh(0,0), Y(0,0); 678 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 679 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 680 N0.Val->hasOneUse()) { 681 Sh = N0; Y = N1; 682 } else if (N1.getOpcode() == ISD::SHL && 683 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 684 Sh = N1; Y = N0; 685 } 686 if (Sh.Val) { 687 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 688 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 689 } 690 } 691 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 692 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 693 isa<ConstantSDNode>(N0.getOperand(1))) { 694 return DAG.getNode(ISD::ADD, VT, 695 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 696 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 697 } 698 699 // reassociate mul 700 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 701 if (RMUL.Val != 0) 702 return RMUL; 703 return SDOperand(); 704} 705 706SDOperand DAGCombiner::visitSDIV(SDNode *N) { 707 SDOperand N0 = N->getOperand(0); 708 SDOperand N1 = N->getOperand(1); 709 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 710 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 711 MVT::ValueType VT = N->getValueType(0); 712 713 // fold (sdiv c1, c2) -> c1/c2 714 if (N0C && N1C && !N1C->isNullValue()) 715 return DAG.getNode(ISD::SDIV, VT, N0, N1); 716 // fold (sdiv X, 1) -> X 717 if (N1C && N1C->getSignExtended() == 1LL) 718 return N0; 719 // fold (sdiv X, -1) -> 0-X 720 if (N1C && N1C->isAllOnesValue()) 721 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 722 // If we know the sign bits of both operands are zero, strength reduce to a 723 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 724 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 725 if (TLI.MaskedValueIsZero(N1, SignBit) && 726 TLI.MaskedValueIsZero(N0, SignBit)) 727 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 728 // fold (sdiv X, pow2) -> simple ops after legalize 729 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 730 (isPowerOf2_64(N1C->getSignExtended()) || 731 isPowerOf2_64(-N1C->getSignExtended()))) { 732 // If dividing by powers of two is cheap, then don't perform the following 733 // fold. 734 if (TLI.isPow2DivCheap()) 735 return SDOperand(); 736 int64_t pow2 = N1C->getSignExtended(); 737 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 738 unsigned lg2 = Log2_64(abs2); 739 // Splat the sign bit into the register 740 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 741 DAG.getConstant(MVT::getSizeInBits(VT)-1, 742 TLI.getShiftAmountTy())); 743 AddToWorkList(SGN.Val); 744 // Add (N0 < 0) ? abs2 - 1 : 0; 745 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 746 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 747 TLI.getShiftAmountTy())); 748 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 749 AddToWorkList(SRL.Val); 750 AddToWorkList(ADD.Val); // Divide by pow2 751 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 752 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 753 // If we're dividing by a positive value, we're done. Otherwise, we must 754 // negate the result. 755 if (pow2 > 0) 756 return SRA; 757 AddToWorkList(SRA.Val); 758 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 759 } 760 // if integer divide is expensive and we satisfy the requirements, emit an 761 // alternate sequence. 762 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 763 !TLI.isIntDivCheap()) { 764 SDOperand Op = BuildSDIV(N); 765 if (Op.Val) return Op; 766 } 767 return SDOperand(); 768} 769 770SDOperand DAGCombiner::visitUDIV(SDNode *N) { 771 SDOperand N0 = N->getOperand(0); 772 SDOperand N1 = N->getOperand(1); 773 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 774 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 775 MVT::ValueType VT = N->getValueType(0); 776 777 // fold (udiv c1, c2) -> c1/c2 778 if (N0C && N1C && !N1C->isNullValue()) 779 return DAG.getNode(ISD::UDIV, VT, N0, N1); 780 // fold (udiv x, (1 << c)) -> x >>u c 781 if (N1C && isPowerOf2_64(N1C->getValue())) 782 return DAG.getNode(ISD::SRL, VT, N0, 783 DAG.getConstant(Log2_64(N1C->getValue()), 784 TLI.getShiftAmountTy())); 785 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 786 if (N1.getOpcode() == ISD::SHL) { 787 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 788 if (isPowerOf2_64(SHC->getValue())) { 789 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 790 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 791 DAG.getConstant(Log2_64(SHC->getValue()), 792 ADDVT)); 793 AddToWorkList(Add.Val); 794 return DAG.getNode(ISD::SRL, VT, N0, Add); 795 } 796 } 797 } 798 // fold (udiv x, c) -> alternate 799 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 800 SDOperand Op = BuildUDIV(N); 801 if (Op.Val) return Op; 802 } 803 return SDOperand(); 804} 805 806SDOperand DAGCombiner::visitSREM(SDNode *N) { 807 SDOperand N0 = N->getOperand(0); 808 SDOperand N1 = N->getOperand(1); 809 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 810 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 811 MVT::ValueType VT = N->getValueType(0); 812 813 // fold (srem c1, c2) -> c1%c2 814 if (N0C && N1C && !N1C->isNullValue()) 815 return DAG.getNode(ISD::SREM, VT, N0, N1); 816 // If we know the sign bits of both operands are zero, strength reduce to a 817 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 818 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 819 if (TLI.MaskedValueIsZero(N1, SignBit) && 820 TLI.MaskedValueIsZero(N0, SignBit)) 821 return DAG.getNode(ISD::UREM, VT, N0, N1); 822 return SDOperand(); 823} 824 825SDOperand DAGCombiner::visitUREM(SDNode *N) { 826 SDOperand N0 = N->getOperand(0); 827 SDOperand N1 = N->getOperand(1); 828 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 829 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 830 MVT::ValueType VT = N->getValueType(0); 831 832 // fold (urem c1, c2) -> c1%c2 833 if (N0C && N1C && !N1C->isNullValue()) 834 return DAG.getNode(ISD::UREM, VT, N0, N1); 835 // fold (urem x, pow2) -> (and x, pow2-1) 836 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 837 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 838 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 839 if (N1.getOpcode() == ISD::SHL) { 840 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 841 if (isPowerOf2_64(SHC->getValue())) { 842 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 843 AddToWorkList(Add.Val); 844 return DAG.getNode(ISD::AND, VT, N0, Add); 845 } 846 } 847 } 848 return SDOperand(); 849} 850 851SDOperand DAGCombiner::visitMULHS(SDNode *N) { 852 SDOperand N0 = N->getOperand(0); 853 SDOperand N1 = N->getOperand(1); 854 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 855 856 // fold (mulhs x, 0) -> 0 857 if (N1C && N1C->isNullValue()) 858 return N1; 859 // fold (mulhs x, 1) -> (sra x, size(x)-1) 860 if (N1C && N1C->getValue() == 1) 861 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 862 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 863 TLI.getShiftAmountTy())); 864 return SDOperand(); 865} 866 867SDOperand DAGCombiner::visitMULHU(SDNode *N) { 868 SDOperand N0 = N->getOperand(0); 869 SDOperand N1 = N->getOperand(1); 870 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 871 872 // fold (mulhu x, 0) -> 0 873 if (N1C && N1C->isNullValue()) 874 return N1; 875 // fold (mulhu x, 1) -> 0 876 if (N1C && N1C->getValue() == 1) 877 return DAG.getConstant(0, N0.getValueType()); 878 return SDOperand(); 879} 880 881/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 882/// two operands of the same opcode, try to simplify it. 883SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 884 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 885 MVT::ValueType VT = N0.getValueType(); 886 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 887 888 // For each of OP in AND/OR/XOR: 889 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 890 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 891 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 892 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 893 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 894 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 895 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 896 SDOperand ORNode = DAG.getNode(N->getOpcode(), 897 N0.getOperand(0).getValueType(), 898 N0.getOperand(0), N1.getOperand(0)); 899 AddToWorkList(ORNode.Val); 900 return DAG.getNode(N0.getOpcode(), VT, ORNode); 901 } 902 903 // For each of OP in SHL/SRL/SRA/AND... 904 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 905 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 906 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 907 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 908 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 909 N0.getOperand(1) == N1.getOperand(1)) { 910 SDOperand ORNode = DAG.getNode(N->getOpcode(), 911 N0.getOperand(0).getValueType(), 912 N0.getOperand(0), N1.getOperand(0)); 913 AddToWorkList(ORNode.Val); 914 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 915 } 916 917 return SDOperand(); 918} 919 920SDOperand DAGCombiner::visitAND(SDNode *N) { 921 SDOperand N0 = N->getOperand(0); 922 SDOperand N1 = N->getOperand(1); 923 SDOperand LL, LR, RL, RR, CC0, CC1; 924 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 925 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 926 MVT::ValueType VT = N1.getValueType(); 927 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 928 929 // fold (and c1, c2) -> c1&c2 930 if (N0C && N1C) 931 return DAG.getNode(ISD::AND, VT, N0, N1); 932 // canonicalize constant to RHS 933 if (N0C && !N1C) 934 return DAG.getNode(ISD::AND, VT, N1, N0); 935 // fold (and x, -1) -> x 936 if (N1C && N1C->isAllOnesValue()) 937 return N0; 938 // if (and x, c) is known to be zero, return 0 939 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 940 return DAG.getConstant(0, VT); 941 // reassociate and 942 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 943 if (RAND.Val != 0) 944 return RAND; 945 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 946 if (N1C && N0.getOpcode() == ISD::OR) 947 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 948 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 949 return N1; 950 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 951 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 952 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 953 if (TLI.MaskedValueIsZero(N0.getOperand(0), 954 ~N1C->getValue() & InMask)) { 955 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 956 N0.getOperand(0)); 957 958 // Replace uses of the AND with uses of the Zero extend node. 959 CombineTo(N, Zext); 960 961 // We actually want to replace all uses of the any_extend with the 962 // zero_extend, to avoid duplicating things. This will later cause this 963 // AND to be folded. 964 CombineTo(N0.Val, Zext); 965 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 966 } 967 } 968 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 969 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 970 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 971 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 972 973 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 974 MVT::isInteger(LL.getValueType())) { 975 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 976 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 977 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 978 AddToWorkList(ORNode.Val); 979 return DAG.getSetCC(VT, ORNode, LR, Op1); 980 } 981 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 982 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 983 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 984 AddToWorkList(ANDNode.Val); 985 return DAG.getSetCC(VT, ANDNode, LR, Op1); 986 } 987 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 988 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 989 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 990 AddToWorkList(ORNode.Val); 991 return DAG.getSetCC(VT, ORNode, LR, Op1); 992 } 993 } 994 // canonicalize equivalent to ll == rl 995 if (LL == RR && LR == RL) { 996 Op1 = ISD::getSetCCSwappedOperands(Op1); 997 std::swap(RL, RR); 998 } 999 if (LL == RL && LR == RR) { 1000 bool isInteger = MVT::isInteger(LL.getValueType()); 1001 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1002 if (Result != ISD::SETCC_INVALID) 1003 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1004 } 1005 } 1006 1007 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1008 if (N0.getOpcode() == N1.getOpcode()) { 1009 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1010 if (Tmp.Val) return Tmp; 1011 } 1012 1013 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1014 // fold (and (sra)) -> (and (srl)) when possible. 1015 if (!MVT::isVector(VT) && 1016 SimplifyDemandedBits(SDOperand(N, 0))) 1017 return SDOperand(N, 0); 1018 // fold (zext_inreg (extload x)) -> (zextload x) 1019 if (N0.getOpcode() == ISD::EXTLOAD) { 1020 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1021 // If we zero all the possible extended bits, then we can turn this into 1022 // a zextload if we are running before legalize or the operation is legal. 1023 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1024 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1025 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1026 N0.getOperand(1), N0.getOperand(2), 1027 EVT); 1028 AddToWorkList(N); 1029 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1030 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1031 } 1032 } 1033 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1034 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) { 1035 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1036 // If we zero all the possible extended bits, then we can turn this into 1037 // a zextload if we are running before legalize or the operation is legal. 1038 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1039 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1040 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1041 N0.getOperand(1), N0.getOperand(2), 1042 EVT); 1043 AddToWorkList(N); 1044 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1045 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1046 } 1047 } 1048 1049 // fold (and (load x), 255) -> (zextload x, i8) 1050 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1051 if (N1C && 1052 (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD || 1053 N0.getOpcode() == ISD::ZEXTLOAD) && 1054 N0.hasOneUse()) { 1055 MVT::ValueType EVT, LoadedVT; 1056 if (N1C->getValue() == 255) 1057 EVT = MVT::i8; 1058 else if (N1C->getValue() == 65535) 1059 EVT = MVT::i16; 1060 else if (N1C->getValue() == ~0U) 1061 EVT = MVT::i32; 1062 else 1063 EVT = MVT::Other; 1064 1065 LoadedVT = N0.getOpcode() == ISD::LOAD ? VT : 1066 cast<VTSDNode>(N0.getOperand(3))->getVT(); 1067 if (EVT != MVT::Other && LoadedVT > EVT && 1068 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1069 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1070 // For big endian targets, we need to add an offset to the pointer to load 1071 // the correct bytes. For little endian systems, we merely need to read 1072 // fewer bytes from the same pointer. 1073 unsigned PtrOff = 1074 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1075 SDOperand NewPtr = N0.getOperand(1); 1076 if (!TLI.isLittleEndian()) 1077 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1078 DAG.getConstant(PtrOff, PtrType)); 1079 AddToWorkList(NewPtr.Val); 1080 SDOperand Load = 1081 DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr, 1082 N0.getOperand(2), EVT); 1083 AddToWorkList(N); 1084 CombineTo(N0.Val, Load, Load.getValue(1)); 1085 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1086 } 1087 } 1088 1089 return SDOperand(); 1090} 1091 1092SDOperand DAGCombiner::visitOR(SDNode *N) { 1093 SDOperand N0 = N->getOperand(0); 1094 SDOperand N1 = N->getOperand(1); 1095 SDOperand LL, LR, RL, RR, CC0, CC1; 1096 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1097 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1098 MVT::ValueType VT = N1.getValueType(); 1099 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1100 1101 // fold (or c1, c2) -> c1|c2 1102 if (N0C && N1C) 1103 return DAG.getNode(ISD::OR, VT, N0, N1); 1104 // canonicalize constant to RHS 1105 if (N0C && !N1C) 1106 return DAG.getNode(ISD::OR, VT, N1, N0); 1107 // fold (or x, 0) -> x 1108 if (N1C && N1C->isNullValue()) 1109 return N0; 1110 // fold (or x, -1) -> -1 1111 if (N1C && N1C->isAllOnesValue()) 1112 return N1; 1113 // fold (or x, c) -> c iff (x & ~c) == 0 1114 if (N1C && 1115 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1116 return N1; 1117 // reassociate or 1118 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1119 if (ROR.Val != 0) 1120 return ROR; 1121 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1122 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1123 isa<ConstantSDNode>(N0.getOperand(1))) { 1124 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1125 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1126 N1), 1127 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1128 } 1129 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1130 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1131 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1132 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1133 1134 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1135 MVT::isInteger(LL.getValueType())) { 1136 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1137 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1138 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1139 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1140 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1141 AddToWorkList(ORNode.Val); 1142 return DAG.getSetCC(VT, ORNode, LR, Op1); 1143 } 1144 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1145 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1146 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1147 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1148 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1149 AddToWorkList(ANDNode.Val); 1150 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1151 } 1152 } 1153 // canonicalize equivalent to ll == rl 1154 if (LL == RR && LR == RL) { 1155 Op1 = ISD::getSetCCSwappedOperands(Op1); 1156 std::swap(RL, RR); 1157 } 1158 if (LL == RL && LR == RR) { 1159 bool isInteger = MVT::isInteger(LL.getValueType()); 1160 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1161 if (Result != ISD::SETCC_INVALID) 1162 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1163 } 1164 } 1165 1166 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1167 if (N0.getOpcode() == N1.getOpcode()) { 1168 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1169 if (Tmp.Val) return Tmp; 1170 } 1171 1172 // canonicalize shl to left side in a shl/srl pair, to match rotate 1173 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 1174 std::swap(N0, N1); 1175 // check for rotl, rotr 1176 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL && 1177 N0.getOperand(0) == N1.getOperand(0) && 1178 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) { 1179 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1180 if (N0.getOperand(1).getOpcode() == ISD::Constant && 1181 N1.getOperand(1).getOpcode() == ISD::Constant) { 1182 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1183 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1184 if ((c1val + c2val) == OpSizeInBits) 1185 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1186 } 1187 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1188 if (N1.getOperand(1).getOpcode() == ISD::SUB && 1189 N0.getOperand(1) == N1.getOperand(1).getOperand(1)) 1190 if (ConstantSDNode *SUBC = 1191 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0))) 1192 if (SUBC->getValue() == OpSizeInBits) 1193 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1194 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1195 if (N0.getOperand(1).getOpcode() == ISD::SUB && 1196 N1.getOperand(1) == N0.getOperand(1).getOperand(1)) 1197 if (ConstantSDNode *SUBC = 1198 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0))) 1199 if (SUBC->getValue() == OpSizeInBits) { 1200 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT)) 1201 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0), 1202 N1.getOperand(1)); 1203 else 1204 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), 1205 N0.getOperand(1)); 1206 } 1207 } 1208 return SDOperand(); 1209} 1210 1211SDOperand DAGCombiner::visitXOR(SDNode *N) { 1212 SDOperand N0 = N->getOperand(0); 1213 SDOperand N1 = N->getOperand(1); 1214 SDOperand LHS, RHS, CC; 1215 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1216 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1217 MVT::ValueType VT = N0.getValueType(); 1218 1219 // fold (xor c1, c2) -> c1^c2 1220 if (N0C && N1C) 1221 return DAG.getNode(ISD::XOR, VT, N0, N1); 1222 // canonicalize constant to RHS 1223 if (N0C && !N1C) 1224 return DAG.getNode(ISD::XOR, VT, N1, N0); 1225 // fold (xor x, 0) -> x 1226 if (N1C && N1C->isNullValue()) 1227 return N0; 1228 // reassociate xor 1229 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1230 if (RXOR.Val != 0) 1231 return RXOR; 1232 // fold !(x cc y) -> (x !cc y) 1233 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1234 bool isInt = MVT::isInteger(LHS.getValueType()); 1235 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1236 isInt); 1237 if (N0.getOpcode() == ISD::SETCC) 1238 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1239 if (N0.getOpcode() == ISD::SELECT_CC) 1240 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1241 assert(0 && "Unhandled SetCC Equivalent!"); 1242 abort(); 1243 } 1244 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1245 if (N1C && N1C->getValue() == 1 && 1246 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1247 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1248 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1249 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1250 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1251 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1252 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1253 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1254 } 1255 } 1256 // fold !(x or y) -> (!x and !y) iff x or y are constants 1257 if (N1C && N1C->isAllOnesValue() && 1258 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1259 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1260 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1261 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1262 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1263 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1264 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1265 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1266 } 1267 } 1268 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1269 if (N1C && N0.getOpcode() == ISD::XOR) { 1270 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1271 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1272 if (N00C) 1273 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1274 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1275 if (N01C) 1276 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1277 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1278 } 1279 // fold (xor x, x) -> 0 1280 if (N0 == N1) { 1281 if (!MVT::isVector(VT)) { 1282 return DAG.getConstant(0, VT); 1283 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1284 // Produce a vector of zeros. 1285 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT)); 1286 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 1287 return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops); 1288 } 1289 } 1290 1291 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 1292 if (N0.getOpcode() == N1.getOpcode()) { 1293 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1294 if (Tmp.Val) return Tmp; 1295 } 1296 1297 // Simplify the expression using non-local knowledge. 1298 if (!MVT::isVector(VT) && 1299 SimplifyDemandedBits(SDOperand(N, 0))) 1300 return SDOperand(N, 0); 1301 1302 return SDOperand(); 1303} 1304 1305SDOperand DAGCombiner::visitSHL(SDNode *N) { 1306 SDOperand N0 = N->getOperand(0); 1307 SDOperand N1 = N->getOperand(1); 1308 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1309 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1310 MVT::ValueType VT = N0.getValueType(); 1311 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1312 1313 // fold (shl c1, c2) -> c1<<c2 1314 if (N0C && N1C) 1315 return DAG.getNode(ISD::SHL, VT, N0, N1); 1316 // fold (shl 0, x) -> 0 1317 if (N0C && N0C->isNullValue()) 1318 return N0; 1319 // fold (shl x, c >= size(x)) -> undef 1320 if (N1C && N1C->getValue() >= OpSizeInBits) 1321 return DAG.getNode(ISD::UNDEF, VT); 1322 // fold (shl x, 0) -> x 1323 if (N1C && N1C->isNullValue()) 1324 return N0; 1325 // if (shl x, c) is known to be zero, return 0 1326 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1327 return DAG.getConstant(0, VT); 1328 if (SimplifyDemandedBits(SDOperand(N, 0))) 1329 return SDOperand(N, 0); 1330 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1331 if (N1C && N0.getOpcode() == ISD::SHL && 1332 N0.getOperand(1).getOpcode() == ISD::Constant) { 1333 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1334 uint64_t c2 = N1C->getValue(); 1335 if (c1 + c2 > OpSizeInBits) 1336 return DAG.getConstant(0, VT); 1337 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1338 DAG.getConstant(c1 + c2, N1.getValueType())); 1339 } 1340 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1341 // (srl (and x, -1 << c1), c1-c2) 1342 if (N1C && N0.getOpcode() == ISD::SRL && 1343 N0.getOperand(1).getOpcode() == ISD::Constant) { 1344 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1345 uint64_t c2 = N1C->getValue(); 1346 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1347 DAG.getConstant(~0ULL << c1, VT)); 1348 if (c2 > c1) 1349 return DAG.getNode(ISD::SHL, VT, Mask, 1350 DAG.getConstant(c2-c1, N1.getValueType())); 1351 else 1352 return DAG.getNode(ISD::SRL, VT, Mask, 1353 DAG.getConstant(c1-c2, N1.getValueType())); 1354 } 1355 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1356 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1357 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1358 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1359 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) 1360 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1361 isa<ConstantSDNode>(N0.getOperand(1))) { 1362 return DAG.getNode(ISD::ADD, VT, 1363 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1), 1364 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1)); 1365 } 1366 return SDOperand(); 1367} 1368 1369SDOperand DAGCombiner::visitSRA(SDNode *N) { 1370 SDOperand N0 = N->getOperand(0); 1371 SDOperand N1 = N->getOperand(1); 1372 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1373 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1374 MVT::ValueType VT = N0.getValueType(); 1375 1376 // fold (sra c1, c2) -> c1>>c2 1377 if (N0C && N1C) 1378 return DAG.getNode(ISD::SRA, VT, N0, N1); 1379 // fold (sra 0, x) -> 0 1380 if (N0C && N0C->isNullValue()) 1381 return N0; 1382 // fold (sra -1, x) -> -1 1383 if (N0C && N0C->isAllOnesValue()) 1384 return N0; 1385 // fold (sra x, c >= size(x)) -> undef 1386 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 1387 return DAG.getNode(ISD::UNDEF, VT); 1388 // fold (sra x, 0) -> x 1389 if (N1C && N1C->isNullValue()) 1390 return N0; 1391 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 1392 // sext_inreg. 1393 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 1394 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 1395 MVT::ValueType EVT; 1396 switch (LowBits) { 1397 default: EVT = MVT::Other; break; 1398 case 1: EVT = MVT::i1; break; 1399 case 8: EVT = MVT::i8; break; 1400 case 16: EVT = MVT::i16; break; 1401 case 32: EVT = MVT::i32; break; 1402 } 1403 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 1404 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1405 DAG.getValueType(EVT)); 1406 } 1407 1408 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 1409 if (N1C && N0.getOpcode() == ISD::SRA) { 1410 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1411 unsigned Sum = N1C->getValue() + C1->getValue(); 1412 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 1413 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 1414 DAG.getConstant(Sum, N1C->getValueType(0))); 1415 } 1416 } 1417 1418 // Simplify, based on bits shifted out of the LHS. 1419 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 1420 return SDOperand(N, 0); 1421 1422 1423 // If the sign bit is known to be zero, switch this to a SRL. 1424 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 1425 return DAG.getNode(ISD::SRL, VT, N0, N1); 1426 return SDOperand(); 1427} 1428 1429SDOperand DAGCombiner::visitSRL(SDNode *N) { 1430 SDOperand N0 = N->getOperand(0); 1431 SDOperand N1 = N->getOperand(1); 1432 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1433 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1434 MVT::ValueType VT = N0.getValueType(); 1435 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1436 1437 // fold (srl c1, c2) -> c1 >>u c2 1438 if (N0C && N1C) 1439 return DAG.getNode(ISD::SRL, VT, N0, N1); 1440 // fold (srl 0, x) -> 0 1441 if (N0C && N0C->isNullValue()) 1442 return N0; 1443 // fold (srl x, c >= size(x)) -> undef 1444 if (N1C && N1C->getValue() >= OpSizeInBits) 1445 return DAG.getNode(ISD::UNDEF, VT); 1446 // fold (srl x, 0) -> x 1447 if (N1C && N1C->isNullValue()) 1448 return N0; 1449 // if (srl x, c) is known to be zero, return 0 1450 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1451 return DAG.getConstant(0, VT); 1452 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1453 if (N1C && N0.getOpcode() == ISD::SRL && 1454 N0.getOperand(1).getOpcode() == ISD::Constant) { 1455 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1456 uint64_t c2 = N1C->getValue(); 1457 if (c1 + c2 > OpSizeInBits) 1458 return DAG.getConstant(0, VT); 1459 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1460 DAG.getConstant(c1 + c2, N1.getValueType())); 1461 } 1462 1463 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 1464 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1465 // Shifting in all undef bits? 1466 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 1467 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 1468 return DAG.getNode(ISD::UNDEF, VT); 1469 1470 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 1471 AddToWorkList(SmallShift.Val); 1472 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 1473 } 1474 1475 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 1476 if (N1C && N0.getOpcode() == ISD::CTLZ && 1477 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 1478 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 1479 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 1480 1481 // If any of the input bits are KnownOne, then the input couldn't be all 1482 // zeros, thus the result of the srl will always be zero. 1483 if (KnownOne) return DAG.getConstant(0, VT); 1484 1485 // If all of the bits input the to ctlz node are known to be zero, then 1486 // the result of the ctlz is "32" and the result of the shift is one. 1487 uint64_t UnknownBits = ~KnownZero & Mask; 1488 if (UnknownBits == 0) return DAG.getConstant(1, VT); 1489 1490 // Otherwise, check to see if there is exactly one bit input to the ctlz. 1491 if ((UnknownBits & (UnknownBits-1)) == 0) { 1492 // Okay, we know that only that the single bit specified by UnknownBits 1493 // could be set on input to the CTLZ node. If this bit is set, the SRL 1494 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 1495 // to an SRL,XOR pair, which is likely to simplify more. 1496 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 1497 SDOperand Op = N0.getOperand(0); 1498 if (ShAmt) { 1499 Op = DAG.getNode(ISD::SRL, VT, Op, 1500 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 1501 AddToWorkList(Op.Val); 1502 } 1503 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 1504 } 1505 } 1506 1507 return SDOperand(); 1508} 1509 1510SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1511 SDOperand N0 = N->getOperand(0); 1512 MVT::ValueType VT = N->getValueType(0); 1513 1514 // fold (ctlz c1) -> c2 1515 if (isa<ConstantSDNode>(N0)) 1516 return DAG.getNode(ISD::CTLZ, VT, N0); 1517 return SDOperand(); 1518} 1519 1520SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1521 SDOperand N0 = N->getOperand(0); 1522 MVT::ValueType VT = N->getValueType(0); 1523 1524 // fold (cttz c1) -> c2 1525 if (isa<ConstantSDNode>(N0)) 1526 return DAG.getNode(ISD::CTTZ, VT, N0); 1527 return SDOperand(); 1528} 1529 1530SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1531 SDOperand N0 = N->getOperand(0); 1532 MVT::ValueType VT = N->getValueType(0); 1533 1534 // fold (ctpop c1) -> c2 1535 if (isa<ConstantSDNode>(N0)) 1536 return DAG.getNode(ISD::CTPOP, VT, N0); 1537 return SDOperand(); 1538} 1539 1540SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1541 SDOperand N0 = N->getOperand(0); 1542 SDOperand N1 = N->getOperand(1); 1543 SDOperand N2 = N->getOperand(2); 1544 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1545 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1546 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1547 MVT::ValueType VT = N->getValueType(0); 1548 1549 // fold select C, X, X -> X 1550 if (N1 == N2) 1551 return N1; 1552 // fold select true, X, Y -> X 1553 if (N0C && !N0C->isNullValue()) 1554 return N1; 1555 // fold select false, X, Y -> Y 1556 if (N0C && N0C->isNullValue()) 1557 return N2; 1558 // fold select C, 1, X -> C | X 1559 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1560 return DAG.getNode(ISD::OR, VT, N0, N2); 1561 // fold select C, 0, X -> ~C & X 1562 // FIXME: this should check for C type == X type, not i1? 1563 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1564 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1565 AddToWorkList(XORNode.Val); 1566 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1567 } 1568 // fold select C, X, 1 -> ~C | X 1569 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1570 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1571 AddToWorkList(XORNode.Val); 1572 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1573 } 1574 // fold select C, X, 0 -> C & X 1575 // FIXME: this should check for C type == X type, not i1? 1576 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1577 return DAG.getNode(ISD::AND, VT, N0, N1); 1578 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1579 if (MVT::i1 == VT && N0 == N1) 1580 return DAG.getNode(ISD::OR, VT, N0, N2); 1581 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1582 if (MVT::i1 == VT && N0 == N2) 1583 return DAG.getNode(ISD::AND, VT, N0, N1); 1584 1585 // If we can fold this based on the true/false value, do so. 1586 if (SimplifySelectOps(N, N1, N2)) 1587 return SDOperand(N, 0); // Don't revisit N. 1588 1589 // fold selects based on a setcc into other things, such as min/max/abs 1590 if (N0.getOpcode() == ISD::SETCC) 1591 // FIXME: 1592 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 1593 // having to say they don't support SELECT_CC on every type the DAG knows 1594 // about, since there is no way to mark an opcode illegal at all value types 1595 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 1596 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 1597 N1, N2, N0.getOperand(2)); 1598 else 1599 return SimplifySelect(N0, N1, N2); 1600 return SDOperand(); 1601} 1602 1603SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1604 SDOperand N0 = N->getOperand(0); 1605 SDOperand N1 = N->getOperand(1); 1606 SDOperand N2 = N->getOperand(2); 1607 SDOperand N3 = N->getOperand(3); 1608 SDOperand N4 = N->getOperand(4); 1609 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1610 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1611 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1612 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1613 1614 // Determine if the condition we're dealing with is constant 1615 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1616 //ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1617 1618 // fold select_cc lhs, rhs, x, x, cc -> x 1619 if (N2 == N3) 1620 return N2; 1621 1622 // If we can fold this based on the true/false value, do so. 1623 if (SimplifySelectOps(N, N2, N3)) 1624 return SDOperand(N, 0); // Don't revisit N. 1625 1626 // fold select_cc into other things, such as min/max/abs 1627 return SimplifySelectCC(N0, N1, N2, N3, CC); 1628} 1629 1630SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1631 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1632 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1633} 1634 1635SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1636 SDOperand N0 = N->getOperand(0); 1637 MVT::ValueType VT = N->getValueType(0); 1638 1639 // fold (sext c1) -> c1 1640 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0)) 1641 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 1642 1643 // fold (sext (sext x)) -> (sext x) 1644 // fold (sext (aext x)) -> (sext x) 1645 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 1646 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1647 1648 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size. 1649 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1650 (!AfterLegalize || 1651 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType()))) 1652 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1653 DAG.getValueType(N0.getValueType())); 1654 1655 // fold (sext (load x)) -> (sext (truncate (sextload x))) 1656 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1657 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){ 1658 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1659 N0.getOperand(1), N0.getOperand(2), 1660 N0.getValueType()); 1661 CombineTo(N, ExtLoad); 1662 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1663 ExtLoad.getValue(1)); 1664 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1665 } 1666 1667 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 1668 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 1669 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1670 N0.hasOneUse()) { 1671 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1672 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1673 N0.getOperand(1), N0.getOperand(2), EVT); 1674 CombineTo(N, ExtLoad); 1675 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1676 ExtLoad.getValue(1)); 1677 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1678 } 1679 1680 return SDOperand(); 1681} 1682 1683SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1684 SDOperand N0 = N->getOperand(0); 1685 MVT::ValueType VT = N->getValueType(0); 1686 1687 // fold (zext c1) -> c1 1688 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0)) 1689 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1690 // fold (zext (zext x)) -> (zext x) 1691 // fold (zext (aext x)) -> (zext x) 1692 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 1693 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1694 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size. 1695 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1696 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType()))) 1697 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType()); 1698 // fold (zext (load x)) -> (zext (truncate (zextload x))) 1699 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1700 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){ 1701 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1702 N0.getOperand(1), N0.getOperand(2), 1703 N0.getValueType()); 1704 CombineTo(N, ExtLoad); 1705 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1706 ExtLoad.getValue(1)); 1707 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1708 } 1709 1710 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 1711 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 1712 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1713 N0.hasOneUse()) { 1714 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1715 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1716 N0.getOperand(1), N0.getOperand(2), EVT); 1717 CombineTo(N, ExtLoad); 1718 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1719 ExtLoad.getValue(1)); 1720 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1721 } 1722 return SDOperand(); 1723} 1724 1725SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 1726 SDOperand N0 = N->getOperand(0); 1727 MVT::ValueType VT = N->getValueType(0); 1728 1729 // fold (aext c1) -> c1 1730 if (isa<ConstantSDNode>(N0)) 1731 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 1732 // fold (aext (aext x)) -> (aext x) 1733 // fold (aext (zext x)) -> (zext x) 1734 // fold (aext (sext x)) -> (sext x) 1735 if (N0.getOpcode() == ISD::ANY_EXTEND || 1736 N0.getOpcode() == ISD::ZERO_EXTEND || 1737 N0.getOpcode() == ISD::SIGN_EXTEND) 1738 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1739 1740 // fold (aext (truncate x)) -> x iff x size == zext size. 1741 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT) 1742 return N0.getOperand(0); 1743 // fold (aext (load x)) -> (aext (truncate (extload x))) 1744 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1745 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) { 1746 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0), 1747 N0.getOperand(1), N0.getOperand(2), 1748 N0.getValueType()); 1749 CombineTo(N, ExtLoad); 1750 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1751 ExtLoad.getValue(1)); 1752 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1753 } 1754 1755 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 1756 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 1757 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 1758 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD || 1759 N0.getOpcode() == ISD::SEXTLOAD) && 1760 N0.hasOneUse()) { 1761 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1762 SDOperand ExtLoad = DAG.getExtLoad(N0.getOpcode(), VT, N0.getOperand(0), 1763 N0.getOperand(1), N0.getOperand(2), EVT); 1764 CombineTo(N, ExtLoad); 1765 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1766 ExtLoad.getValue(1)); 1767 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1768 } 1769 return SDOperand(); 1770} 1771 1772 1773SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1774 SDOperand N0 = N->getOperand(0); 1775 SDOperand N1 = N->getOperand(1); 1776 MVT::ValueType VT = N->getValueType(0); 1777 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1778 unsigned EVTBits = MVT::getSizeInBits(EVT); 1779 1780 // fold (sext_in_reg c1) -> c1 1781 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 1782 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 1783 1784 // If the input is already sign extended, just drop the extension. 1785 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 1786 return N0; 1787 1788 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1789 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1790 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1791 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1792 } 1793 1794 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1795 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 1796 return DAG.getZeroExtendInReg(N0, EVT); 1797 1798 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 1799 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 1800 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 1801 if (N0.getOpcode() == ISD::SRL) { 1802 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1803 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 1804 // We can turn this into an SRA iff the input to the SRL is already sign 1805 // extended enough. 1806 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0)); 1807 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 1808 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 1809 } 1810 } 1811 1812 // fold (sext_inreg (extload x)) -> (sextload x) 1813 if (N0.getOpcode() == ISD::EXTLOAD && 1814 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1815 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1816 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1817 N0.getOperand(1), N0.getOperand(2), 1818 EVT); 1819 CombineTo(N, ExtLoad); 1820 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1821 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1822 } 1823 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 1824 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() && 1825 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1826 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1827 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1828 N0.getOperand(1), N0.getOperand(2), 1829 EVT); 1830 CombineTo(N, ExtLoad); 1831 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1832 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1833 } 1834 return SDOperand(); 1835} 1836 1837SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 1838 SDOperand N0 = N->getOperand(0); 1839 MVT::ValueType VT = N->getValueType(0); 1840 1841 // noop truncate 1842 if (N0.getValueType() == N->getValueType(0)) 1843 return N0; 1844 // fold (truncate c1) -> c1 1845 if (isa<ConstantSDNode>(N0)) 1846 return DAG.getNode(ISD::TRUNCATE, VT, N0); 1847 // fold (truncate (truncate x)) -> (truncate x) 1848 if (N0.getOpcode() == ISD::TRUNCATE) 1849 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1850 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 1851 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 1852 N0.getOpcode() == ISD::ANY_EXTEND) { 1853 if (N0.getValueType() < VT) 1854 // if the source is smaller than the dest, we still need an extend 1855 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1856 else if (N0.getValueType() > VT) 1857 // if the source is larger than the dest, than we just need the truncate 1858 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1859 else 1860 // if the source and dest are the same type, we can drop both the extend 1861 // and the truncate 1862 return N0.getOperand(0); 1863 } 1864 // fold (truncate (load x)) -> (smaller load x) 1865 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1866 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 1867 "Cannot truncate to larger type!"); 1868 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1869 // For big endian targets, we need to add an offset to the pointer to load 1870 // the correct bytes. For little endian systems, we merely need to read 1871 // fewer bytes from the same pointer. 1872 uint64_t PtrOff = 1873 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 1874 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 1875 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 1876 DAG.getConstant(PtrOff, PtrType)); 1877 AddToWorkList(NewPtr.Val); 1878 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 1879 AddToWorkList(N); 1880 CombineTo(N0.Val, Load, Load.getValue(1)); 1881 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1882 } 1883 return SDOperand(); 1884} 1885 1886SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 1887 SDOperand N0 = N->getOperand(0); 1888 MVT::ValueType VT = N->getValueType(0); 1889 1890 // If the input is a constant, let getNode() fold it. 1891 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 1892 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 1893 if (Res.Val != N) return Res; 1894 } 1895 1896 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 1897 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 1898 1899 // fold (conv (load x)) -> (load (conv*)x) 1900 // FIXME: These xforms need to know that the resultant load doesn't need a 1901 // higher alignment than the original! 1902 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1903 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1), 1904 N0.getOperand(2)); 1905 AddToWorkList(N); 1906 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 1907 Load.getValue(1)); 1908 return Load; 1909 } 1910 1911 return SDOperand(); 1912} 1913 1914SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) { 1915 SDOperand N0 = N->getOperand(0); 1916 MVT::ValueType VT = N->getValueType(0); 1917 1918 // If the input is a VBUILD_VECTOR with all constant elements, fold this now. 1919 // First check to see if this is all constant. 1920 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() && 1921 VT == MVT::Vector) { 1922 bool isSimple = true; 1923 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i) 1924 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 1925 N0.getOperand(i).getOpcode() != ISD::Constant && 1926 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 1927 isSimple = false; 1928 break; 1929 } 1930 1931 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT(); 1932 if (isSimple && !MVT::isVector(DestEltVT)) { 1933 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT); 1934 } 1935 } 1936 1937 return SDOperand(); 1938} 1939 1940/// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector 1941/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 1942/// destination element value type. 1943SDOperand DAGCombiner:: 1944ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 1945 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 1946 1947 // If this is already the right type, we're done. 1948 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 1949 1950 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 1951 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 1952 1953 // If this is a conversion of N elements of one type to N elements of another 1954 // type, convert each element. This handles FP<->INT cases. 1955 if (SrcBitSize == DstBitSize) { 1956 std::vector<SDOperand> Ops; 1957 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 1958 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 1959 AddToWorkList(Ops.back().Val); 1960 } 1961 Ops.push_back(*(BV->op_end()-2)); // Add num elements. 1962 Ops.push_back(DAG.getValueType(DstEltVT)); 1963 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 1964 } 1965 1966 // Otherwise, we're growing or shrinking the elements. To avoid having to 1967 // handle annoying details of growing/shrinking FP values, we convert them to 1968 // int first. 1969 if (MVT::isFloatingPoint(SrcEltVT)) { 1970 // Convert the input float vector to a int vector where the elements are the 1971 // same sizes. 1972 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 1973 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 1974 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val; 1975 SrcEltVT = IntVT; 1976 } 1977 1978 // Now we know the input is an integer vector. If the output is a FP type, 1979 // convert to integer first, then to FP of the right size. 1980 if (MVT::isFloatingPoint(DstEltVT)) { 1981 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 1982 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 1983 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val; 1984 1985 // Next, convert to FP elements of the same size. 1986 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT); 1987 } 1988 1989 // Okay, we know the src/dst types are both integers of differing types. 1990 // Handling growing first. 1991 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 1992 if (SrcBitSize < DstBitSize) { 1993 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 1994 1995 std::vector<SDOperand> Ops; 1996 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; 1997 i += NumInputsPerOutput) { 1998 bool isLE = TLI.isLittleEndian(); 1999 uint64_t NewBits = 0; 2000 bool EltIsUndef = true; 2001 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 2002 // Shift the previously computed bits over. 2003 NewBits <<= SrcBitSize; 2004 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 2005 if (Op.getOpcode() == ISD::UNDEF) continue; 2006 EltIsUndef = false; 2007 2008 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 2009 } 2010 2011 if (EltIsUndef) 2012 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2013 else 2014 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 2015 } 2016 2017 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2018 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2019 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 2020 } 2021 2022 // Finally, this must be the case where we are shrinking elements: each input 2023 // turns into multiple outputs. 2024 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 2025 std::vector<SDOperand> Ops; 2026 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2027 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 2028 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 2029 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2030 continue; 2031 } 2032 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 2033 2034 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 2035 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 2036 OpVal >>= DstBitSize; 2037 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 2038 } 2039 2040 // For big endian targets, swap the order of the pieces of each element. 2041 if (!TLI.isLittleEndian()) 2042 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 2043 } 2044 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2045 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2046 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 2047} 2048 2049 2050 2051SDOperand DAGCombiner::visitFADD(SDNode *N) { 2052 SDOperand N0 = N->getOperand(0); 2053 SDOperand N1 = N->getOperand(1); 2054 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2055 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2056 MVT::ValueType VT = N->getValueType(0); 2057 2058 // fold (fadd c1, c2) -> c1+c2 2059 if (N0CFP && N1CFP) 2060 return DAG.getNode(ISD::FADD, VT, N0, N1); 2061 // canonicalize constant to RHS 2062 if (N0CFP && !N1CFP) 2063 return DAG.getNode(ISD::FADD, VT, N1, N0); 2064 // fold (A + (-B)) -> A-B 2065 if (N1.getOpcode() == ISD::FNEG) 2066 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 2067 // fold ((-A) + B) -> B-A 2068 if (N0.getOpcode() == ISD::FNEG) 2069 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 2070 return SDOperand(); 2071} 2072 2073SDOperand DAGCombiner::visitFSUB(SDNode *N) { 2074 SDOperand N0 = N->getOperand(0); 2075 SDOperand N1 = N->getOperand(1); 2076 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2077 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2078 MVT::ValueType VT = N->getValueType(0); 2079 2080 // fold (fsub c1, c2) -> c1-c2 2081 if (N0CFP && N1CFP) 2082 return DAG.getNode(ISD::FSUB, VT, N0, N1); 2083 // fold (A-(-B)) -> A+B 2084 if (N1.getOpcode() == ISD::FNEG) 2085 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 2086 return SDOperand(); 2087} 2088 2089SDOperand DAGCombiner::visitFMUL(SDNode *N) { 2090 SDOperand N0 = N->getOperand(0); 2091 SDOperand N1 = N->getOperand(1); 2092 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2093 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2094 MVT::ValueType VT = N->getValueType(0); 2095 2096 // fold (fmul c1, c2) -> c1*c2 2097 if (N0CFP && N1CFP) 2098 return DAG.getNode(ISD::FMUL, VT, N0, N1); 2099 // canonicalize constant to RHS 2100 if (N0CFP && !N1CFP) 2101 return DAG.getNode(ISD::FMUL, VT, N1, N0); 2102 // fold (fmul X, 2.0) -> (fadd X, X) 2103 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 2104 return DAG.getNode(ISD::FADD, VT, N0, N0); 2105 return SDOperand(); 2106} 2107 2108SDOperand DAGCombiner::visitFDIV(SDNode *N) { 2109 SDOperand N0 = N->getOperand(0); 2110 SDOperand N1 = N->getOperand(1); 2111 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2112 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2113 MVT::ValueType VT = N->getValueType(0); 2114 2115 // fold (fdiv c1, c2) -> c1/c2 2116 if (N0CFP && N1CFP) 2117 return DAG.getNode(ISD::FDIV, VT, N0, N1); 2118 return SDOperand(); 2119} 2120 2121SDOperand DAGCombiner::visitFREM(SDNode *N) { 2122 SDOperand N0 = N->getOperand(0); 2123 SDOperand N1 = N->getOperand(1); 2124 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2125 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2126 MVT::ValueType VT = N->getValueType(0); 2127 2128 // fold (frem c1, c2) -> fmod(c1,c2) 2129 if (N0CFP && N1CFP) 2130 return DAG.getNode(ISD::FREM, VT, N0, N1); 2131 return SDOperand(); 2132} 2133 2134SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 2135 SDOperand N0 = N->getOperand(0); 2136 SDOperand N1 = N->getOperand(1); 2137 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2138 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2139 MVT::ValueType VT = N->getValueType(0); 2140 2141 if (N0CFP && N1CFP) // Constant fold 2142 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 2143 2144 if (N1CFP) { 2145 // copysign(x, c1) -> fabs(x) iff ispos(c1) 2146 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 2147 union { 2148 double d; 2149 int64_t i; 2150 } u; 2151 u.d = N1CFP->getValue(); 2152 if (u.i >= 0) 2153 return DAG.getNode(ISD::FABS, VT, N0); 2154 else 2155 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 2156 } 2157 2158 // copysign(fabs(x), y) -> copysign(x, y) 2159 // copysign(fneg(x), y) -> copysign(x, y) 2160 // copysign(copysign(x,z), y) -> copysign(x, y) 2161 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 2162 N0.getOpcode() == ISD::FCOPYSIGN) 2163 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 2164 2165 // copysign(x, abs(y)) -> abs(x) 2166 if (N1.getOpcode() == ISD::FABS) 2167 return DAG.getNode(ISD::FABS, VT, N0); 2168 2169 // copysign(x, copysign(y,z)) -> copysign(x, z) 2170 if (N1.getOpcode() == ISD::FCOPYSIGN) 2171 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 2172 2173 // copysign(x, fp_extend(y)) -> copysign(x, y) 2174 // copysign(x, fp_round(y)) -> copysign(x, y) 2175 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 2176 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 2177 2178 return SDOperand(); 2179} 2180 2181 2182 2183SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 2184 SDOperand N0 = N->getOperand(0); 2185 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2186 MVT::ValueType VT = N->getValueType(0); 2187 2188 // fold (sint_to_fp c1) -> c1fp 2189 if (N0C) 2190 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 2191 return SDOperand(); 2192} 2193 2194SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 2195 SDOperand N0 = N->getOperand(0); 2196 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2197 MVT::ValueType VT = N->getValueType(0); 2198 2199 // fold (uint_to_fp c1) -> c1fp 2200 if (N0C) 2201 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 2202 return SDOperand(); 2203} 2204 2205SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 2206 SDOperand N0 = N->getOperand(0); 2207 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2208 MVT::ValueType VT = N->getValueType(0); 2209 2210 // fold (fp_to_sint c1fp) -> c1 2211 if (N0CFP) 2212 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 2213 return SDOperand(); 2214} 2215 2216SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 2217 SDOperand N0 = N->getOperand(0); 2218 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2219 MVT::ValueType VT = N->getValueType(0); 2220 2221 // fold (fp_to_uint c1fp) -> c1 2222 if (N0CFP) 2223 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 2224 return SDOperand(); 2225} 2226 2227SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 2228 SDOperand N0 = N->getOperand(0); 2229 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2230 MVT::ValueType VT = N->getValueType(0); 2231 2232 // fold (fp_round c1fp) -> c1fp 2233 if (N0CFP) 2234 return DAG.getNode(ISD::FP_ROUND, VT, N0); 2235 2236 // fold (fp_round (fp_extend x)) -> x 2237 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 2238 return N0.getOperand(0); 2239 2240 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 2241 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 2242 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 2243 AddToWorkList(Tmp.Val); 2244 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 2245 } 2246 2247 return SDOperand(); 2248} 2249 2250SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 2251 SDOperand N0 = N->getOperand(0); 2252 MVT::ValueType VT = N->getValueType(0); 2253 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2254 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2255 2256 // fold (fp_round_inreg c1fp) -> c1fp 2257 if (N0CFP) { 2258 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 2259 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 2260 } 2261 return SDOperand(); 2262} 2263 2264SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 2265 SDOperand N0 = N->getOperand(0); 2266 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2267 MVT::ValueType VT = N->getValueType(0); 2268 2269 // fold (fp_extend c1fp) -> c1fp 2270 if (N0CFP) 2271 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 2272 2273 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 2274 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 2275 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) { 2276 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0), 2277 N0.getOperand(1), N0.getOperand(2), 2278 N0.getValueType()); 2279 CombineTo(N, ExtLoad); 2280 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 2281 ExtLoad.getValue(1)); 2282 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2283 } 2284 2285 2286 return SDOperand(); 2287} 2288 2289SDOperand DAGCombiner::visitFNEG(SDNode *N) { 2290 SDOperand N0 = N->getOperand(0); 2291 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2292 MVT::ValueType VT = N->getValueType(0); 2293 2294 // fold (fneg c1) -> -c1 2295 if (N0CFP) 2296 return DAG.getNode(ISD::FNEG, VT, N0); 2297 // fold (fneg (sub x, y)) -> (sub y, x) 2298 if (N0.getOpcode() == ISD::SUB) 2299 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0)); 2300 // fold (fneg (fneg x)) -> x 2301 if (N0.getOpcode() == ISD::FNEG) 2302 return N0.getOperand(0); 2303 return SDOperand(); 2304} 2305 2306SDOperand DAGCombiner::visitFABS(SDNode *N) { 2307 SDOperand N0 = N->getOperand(0); 2308 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2309 MVT::ValueType VT = N->getValueType(0); 2310 2311 // fold (fabs c1) -> fabs(c1) 2312 if (N0CFP) 2313 return DAG.getNode(ISD::FABS, VT, N0); 2314 // fold (fabs (fabs x)) -> (fabs x) 2315 if (N0.getOpcode() == ISD::FABS) 2316 return N->getOperand(0); 2317 // fold (fabs (fneg x)) -> (fabs x) 2318 // fold (fabs (fcopysign x, y)) -> (fabs x) 2319 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 2320 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 2321 2322 return SDOperand(); 2323} 2324 2325SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 2326 SDOperand Chain = N->getOperand(0); 2327 SDOperand N1 = N->getOperand(1); 2328 SDOperand N2 = N->getOperand(2); 2329 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2330 2331 // never taken branch, fold to chain 2332 if (N1C && N1C->isNullValue()) 2333 return Chain; 2334 // unconditional branch 2335 if (N1C && N1C->getValue() == 1) 2336 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2337 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 2338 // on the target. 2339 if (N1.getOpcode() == ISD::SETCC && 2340 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 2341 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 2342 N1.getOperand(0), N1.getOperand(1), N2); 2343 } 2344 return SDOperand(); 2345} 2346 2347// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 2348// 2349SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 2350 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 2351 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 2352 2353 // Use SimplifySetCC to simplify SETCC's. 2354 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 2355 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 2356 2357 // fold br_cc true, dest -> br dest (unconditional branch) 2358 if (SCCC && SCCC->getValue()) 2359 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 2360 N->getOperand(4)); 2361 // fold br_cc false, dest -> unconditional fall through 2362 if (SCCC && SCCC->isNullValue()) 2363 return N->getOperand(0); 2364 // fold to a simpler setcc 2365 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 2366 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 2367 Simp.getOperand(2), Simp.getOperand(0), 2368 Simp.getOperand(1), N->getOperand(4)); 2369 return SDOperand(); 2370} 2371 2372SDOperand DAGCombiner::visitLOAD(SDNode *N) { 2373 SDOperand Chain = N->getOperand(0); 2374 SDOperand Ptr = N->getOperand(1); 2375 SDOperand SrcValue = N->getOperand(2); 2376 2377 // If there are no uses of the loaded value, change uses of the chain value 2378 // into uses of the chain input (i.e. delete the dead load). 2379 if (N->hasNUsesOfValue(0, 0)) 2380 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 2381 2382 // If this load is directly stored, replace the load value with the stored 2383 // value. 2384 // TODO: Handle store large -> read small portion. 2385 // TODO: Handle TRUNCSTORE/EXTLOAD 2386 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2387 Chain.getOperand(1).getValueType() == N->getValueType(0)) 2388 return CombineTo(N, Chain.getOperand(1), Chain); 2389 2390 return SDOperand(); 2391} 2392 2393/// visitXEXTLOAD - Handle EXTLOAD/ZEXTLOAD/SEXTLOAD. 2394SDOperand DAGCombiner::visitXEXTLOAD(SDNode *N) { 2395 SDOperand Chain = N->getOperand(0); 2396 SDOperand Ptr = N->getOperand(1); 2397 SDOperand SrcValue = N->getOperand(2); 2398 SDOperand EVT = N->getOperand(3); 2399 2400 // If there are no uses of the loaded value, change uses of the chain value 2401 // into uses of the chain input (i.e. delete the dead load). 2402 if (N->hasNUsesOfValue(0, 0)) 2403 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 2404 2405 return SDOperand(); 2406} 2407 2408SDOperand DAGCombiner::visitSTORE(SDNode *N) { 2409 SDOperand Chain = N->getOperand(0); 2410 SDOperand Value = N->getOperand(1); 2411 SDOperand Ptr = N->getOperand(2); 2412 SDOperand SrcValue = N->getOperand(3); 2413 2414 // If this is a store that kills a previous store, remove the previous store. 2415 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2416 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ && 2417 // Make sure that these stores are the same value type: 2418 // FIXME: we really care that the second store is >= size of the first. 2419 Value.getValueType() == Chain.getOperand(1).getValueType()) { 2420 // Create a new store of Value that replaces both stores. 2421 SDNode *PrevStore = Chain.Val; 2422 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 2423 return Chain; 2424 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 2425 PrevStore->getOperand(0), Value, Ptr, 2426 SrcValue); 2427 CombineTo(N, NewStore); // Nuke this store. 2428 CombineTo(PrevStore, NewStore); // Nuke the previous store. 2429 return SDOperand(N, 0); 2430 } 2431 2432 // If this is a store of a bit convert, store the input value. 2433 // FIXME: This needs to know that the resultant store does not need a 2434 // higher alignment than the original. 2435 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) 2436 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0), 2437 Ptr, SrcValue); 2438 2439 return SDOperand(); 2440} 2441 2442SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 2443 SDOperand InVec = N->getOperand(0); 2444 SDOperand InVal = N->getOperand(1); 2445 SDOperand EltNo = N->getOperand(2); 2446 2447 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 2448 // vector with the inserted element. 2449 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 2450 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 2451 std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 2452 if (Elt < Ops.size()) 2453 Ops[Elt] = InVal; 2454 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), Ops); 2455 } 2456 2457 return SDOperand(); 2458} 2459 2460SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) { 2461 SDOperand InVec = N->getOperand(0); 2462 SDOperand InVal = N->getOperand(1); 2463 SDOperand EltNo = N->getOperand(2); 2464 SDOperand NumElts = N->getOperand(3); 2465 SDOperand EltType = N->getOperand(4); 2466 2467 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new 2468 // vector with the inserted element. 2469 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 2470 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 2471 std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 2472 if (Elt < Ops.size()-2) 2473 Ops[Elt] = InVal; 2474 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), Ops); 2475 } 2476 2477 return SDOperand(); 2478} 2479 2480SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) { 2481 unsigned NumInScalars = N->getNumOperands()-2; 2482 SDOperand NumElts = N->getOperand(NumInScalars); 2483 SDOperand EltType = N->getOperand(NumInScalars+1); 2484 2485 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT 2486 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most 2487 // two distinct vectors, turn this into a shuffle node. 2488 SDOperand VecIn1, VecIn2; 2489 for (unsigned i = 0; i != NumInScalars; ++i) { 2490 // Ignore undef inputs. 2491 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 2492 2493 // If this input is something other than a VEXTRACT_VECTOR_ELT with a 2494 // constant index, bail out. 2495 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT || 2496 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 2497 VecIn1 = VecIn2 = SDOperand(0, 0); 2498 break; 2499 } 2500 2501 // If the input vector type disagrees with the result of the vbuild_vector, 2502 // we can't make a shuffle. 2503 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 2504 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts || 2505 *(ExtractedFromVec.Val->op_end()-1) != EltType) { 2506 VecIn1 = VecIn2 = SDOperand(0, 0); 2507 break; 2508 } 2509 2510 // Otherwise, remember this. We allow up to two distinct input vectors. 2511 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 2512 continue; 2513 2514 if (VecIn1.Val == 0) { 2515 VecIn1 = ExtractedFromVec; 2516 } else if (VecIn2.Val == 0) { 2517 VecIn2 = ExtractedFromVec; 2518 } else { 2519 // Too many inputs. 2520 VecIn1 = VecIn2 = SDOperand(0, 0); 2521 break; 2522 } 2523 } 2524 2525 // If everything is good, we can make a shuffle operation. 2526 if (VecIn1.Val) { 2527 std::vector<SDOperand> BuildVecIndices; 2528 for (unsigned i = 0; i != NumInScalars; ++i) { 2529 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 2530 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 2531 continue; 2532 } 2533 2534 SDOperand Extract = N->getOperand(i); 2535 2536 // If extracting from the first vector, just use the index directly. 2537 if (Extract.getOperand(0) == VecIn1) { 2538 BuildVecIndices.push_back(Extract.getOperand(1)); 2539 continue; 2540 } 2541 2542 // Otherwise, use InIdx + VecSize 2543 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 2544 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32)); 2545 } 2546 2547 // Add count and size info. 2548 BuildVecIndices.push_back(NumElts); 2549 BuildVecIndices.push_back(DAG.getValueType(MVT::i32)); 2550 2551 // Return the new VVECTOR_SHUFFLE node. 2552 std::vector<SDOperand> Ops; 2553 Ops.push_back(VecIn1); 2554 if (VecIn2.Val) { 2555 Ops.push_back(VecIn2); 2556 } else { 2557 // Use an undef vbuild_vector as input for the second operand. 2558 std::vector<SDOperand> UnOps(NumInScalars, 2559 DAG.getNode(ISD::UNDEF, 2560 cast<VTSDNode>(EltType)->getVT())); 2561 UnOps.push_back(NumElts); 2562 UnOps.push_back(EltType); 2563 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, UnOps)); 2564 AddToWorkList(Ops.back().Val); 2565 } 2566 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, BuildVecIndices)); 2567 Ops.push_back(NumElts); 2568 Ops.push_back(EltType); 2569 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops); 2570 } 2571 2572 return SDOperand(); 2573} 2574 2575SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 2576 SDOperand ShufMask = N->getOperand(2); 2577 unsigned NumElts = ShufMask.getNumOperands(); 2578 2579 // If the shuffle mask is an identity operation on the LHS, return the LHS. 2580 bool isIdentity = true; 2581 for (unsigned i = 0; i != NumElts; ++i) { 2582 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2583 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 2584 isIdentity = false; 2585 break; 2586 } 2587 } 2588 if (isIdentity) return N->getOperand(0); 2589 2590 // If the shuffle mask is an identity operation on the RHS, return the RHS. 2591 isIdentity = true; 2592 for (unsigned i = 0; i != NumElts; ++i) { 2593 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2594 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 2595 isIdentity = false; 2596 break; 2597 } 2598 } 2599 if (isIdentity) return N->getOperand(1); 2600 2601 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 2602 // needed at all. 2603 bool isUnary = true; 2604 int VecNum = -1; 2605 for (unsigned i = 0; i != NumElts; ++i) 2606 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 2607 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 2608 int V = (Idx < NumElts) ? 0 : 1; 2609 if (VecNum == -1) 2610 VecNum = V; 2611 else if (VecNum != V) { 2612 isUnary = false; 2613 break; 2614 } 2615 } 2616 2617 SDOperand N0 = N->getOperand(0); 2618 SDOperand N1 = N->getOperand(1); 2619 // Normalize unary shuffle so the RHS is undef. 2620 if (isUnary && VecNum == 1) 2621 std::swap(N0, N1); 2622 2623 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 2624 // into an undef. 2625 if (isUnary || N0 == N1) { 2626 if (N0.getOpcode() == ISD::UNDEF) 2627 return DAG.getNode(ISD::UNDEF, N->getValueType(0)); 2628 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 2629 // first operand. 2630 std::vector<SDOperand> MappedOps; 2631 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) { 2632 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 2633 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 2634 MappedOps.push_back(ShufMask.getOperand(i)); 2635 } else { 2636 unsigned NewIdx = 2637 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 2638 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 2639 } 2640 } 2641 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 2642 MappedOps); 2643 AddToWorkList(ShufMask.Val); 2644 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 2645 N0, 2646 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 2647 ShufMask); 2648 } 2649 2650 return SDOperand(); 2651} 2652 2653SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) { 2654 SDOperand ShufMask = N->getOperand(2); 2655 unsigned NumElts = ShufMask.getNumOperands()-2; 2656 2657 // If the shuffle mask is an identity operation on the LHS, return the LHS. 2658 bool isIdentity = true; 2659 for (unsigned i = 0; i != NumElts; ++i) { 2660 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2661 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 2662 isIdentity = false; 2663 break; 2664 } 2665 } 2666 if (isIdentity) return N->getOperand(0); 2667 2668 // If the shuffle mask is an identity operation on the RHS, return the RHS. 2669 isIdentity = true; 2670 for (unsigned i = 0; i != NumElts; ++i) { 2671 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2672 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 2673 isIdentity = false; 2674 break; 2675 } 2676 } 2677 if (isIdentity) return N->getOperand(1); 2678 2679 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 2680 // needed at all. 2681 bool isUnary = true; 2682 int VecNum = -1; 2683 for (unsigned i = 0; i != NumElts; ++i) 2684 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 2685 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 2686 int V = (Idx < NumElts) ? 0 : 1; 2687 if (VecNum == -1) 2688 VecNum = V; 2689 else if (VecNum != V) { 2690 isUnary = false; 2691 break; 2692 } 2693 } 2694 2695 SDOperand N0 = N->getOperand(0); 2696 SDOperand N1 = N->getOperand(1); 2697 // Normalize unary shuffle so the RHS is undef. 2698 if (isUnary && VecNum == 1) 2699 std::swap(N0, N1); 2700 2701 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 2702 // into an undef. 2703 if (isUnary || N0 == N1) { 2704 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 2705 // first operand. 2706 std::vector<SDOperand> MappedOps; 2707 for (unsigned i = 0; i != NumElts; ++i) { 2708 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 2709 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 2710 MappedOps.push_back(ShufMask.getOperand(i)); 2711 } else { 2712 unsigned NewIdx = 2713 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 2714 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 2715 } 2716 } 2717 // Add the type/#elts values. 2718 MappedOps.push_back(ShufMask.getOperand(NumElts)); 2719 MappedOps.push_back(ShufMask.getOperand(NumElts+1)); 2720 2721 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(), 2722 MappedOps); 2723 AddToWorkList(ShufMask.Val); 2724 2725 // Build the undef vector. 2726 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType()); 2727 for (unsigned i = 0; i != NumElts; ++i) 2728 MappedOps[i] = UDVal; 2729 MappedOps[NumElts ] = *(N0.Val->op_end()-2); 2730 MappedOps[NumElts+1] = *(N0.Val->op_end()-1); 2731 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, MappedOps); 2732 2733 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 2734 N0, UDVal, ShufMask, 2735 MappedOps[NumElts], MappedOps[NumElts+1]); 2736 } 2737 2738 return SDOperand(); 2739} 2740 2741/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 2742/// a VAND to a vector_shuffle with the destination vector and a zero vector. 2743/// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 2744/// vector_shuffle V, Zero, <0, 4, 2, 4> 2745SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 2746 SDOperand LHS = N->getOperand(0); 2747 SDOperand RHS = N->getOperand(1); 2748 if (N->getOpcode() == ISD::VAND) { 2749 SDOperand DstVecSize = *(LHS.Val->op_end()-2); 2750 SDOperand DstVecEVT = *(LHS.Val->op_end()-1); 2751 if (RHS.getOpcode() == ISD::VBIT_CONVERT) 2752 RHS = RHS.getOperand(0); 2753 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) { 2754 std::vector<SDOperand> IdxOps; 2755 unsigned NumOps = RHS.getNumOperands(); 2756 unsigned NumElts = NumOps-2; 2757 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT(); 2758 for (unsigned i = 0; i != NumElts; ++i) { 2759 SDOperand Elt = RHS.getOperand(i); 2760 if (!isa<ConstantSDNode>(Elt)) 2761 return SDOperand(); 2762 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 2763 IdxOps.push_back(DAG.getConstant(i, EVT)); 2764 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 2765 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 2766 else 2767 return SDOperand(); 2768 } 2769 2770 // Let's see if the target supports this vector_shuffle. 2771 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 2772 return SDOperand(); 2773 2774 // Return the new VVECTOR_SHUFFLE node. 2775 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32); 2776 SDOperand EVTNode = DAG.getValueType(EVT); 2777 std::vector<SDOperand> Ops; 2778 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode, EVTNode); 2779 Ops.push_back(LHS); 2780 AddToWorkList(LHS.Val); 2781 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 2782 ZeroOps.push_back(NumEltsNode); 2783 ZeroOps.push_back(EVTNode); 2784 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, ZeroOps)); 2785 IdxOps.push_back(NumEltsNode); 2786 IdxOps.push_back(EVTNode); 2787 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, IdxOps)); 2788 Ops.push_back(NumEltsNode); 2789 Ops.push_back(EVTNode); 2790 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops); 2791 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) { 2792 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 2793 DstVecSize, DstVecEVT); 2794 } 2795 return Result; 2796 } 2797 } 2798 return SDOperand(); 2799} 2800 2801/// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates 2802/// the scalar operation of the vop if it is operating on an integer vector 2803/// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD). 2804SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp, 2805 ISD::NodeType FPOp) { 2806 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT(); 2807 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp; 2808 SDOperand LHS = N->getOperand(0); 2809 SDOperand RHS = N->getOperand(1); 2810 SDOperand Shuffle = XformToShuffleWithZero(N); 2811 if (Shuffle.Val) return Shuffle; 2812 2813 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold 2814 // this operation. 2815 if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 2816 RHS.getOpcode() == ISD::VBUILD_VECTOR) { 2817 std::vector<SDOperand> Ops; 2818 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) { 2819 SDOperand LHSOp = LHS.getOperand(i); 2820 SDOperand RHSOp = RHS.getOperand(i); 2821 // If these two elements can't be folded, bail out. 2822 if ((LHSOp.getOpcode() != ISD::UNDEF && 2823 LHSOp.getOpcode() != ISD::Constant && 2824 LHSOp.getOpcode() != ISD::ConstantFP) || 2825 (RHSOp.getOpcode() != ISD::UNDEF && 2826 RHSOp.getOpcode() != ISD::Constant && 2827 RHSOp.getOpcode() != ISD::ConstantFP)) 2828 break; 2829 // Can't fold divide by zero. 2830 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) { 2831 if ((RHSOp.getOpcode() == ISD::Constant && 2832 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 2833 (RHSOp.getOpcode() == ISD::ConstantFP && 2834 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue())) 2835 break; 2836 } 2837 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp)); 2838 AddToWorkList(Ops.back().Val); 2839 assert((Ops.back().getOpcode() == ISD::UNDEF || 2840 Ops.back().getOpcode() == ISD::Constant || 2841 Ops.back().getOpcode() == ISD::ConstantFP) && 2842 "Scalar binop didn't fold!"); 2843 } 2844 2845 if (Ops.size() == LHS.getNumOperands()-2) { 2846 Ops.push_back(*(LHS.Val->op_end()-2)); 2847 Ops.push_back(*(LHS.Val->op_end()-1)); 2848 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 2849 } 2850 } 2851 2852 return SDOperand(); 2853} 2854 2855SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 2856 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 2857 2858 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 2859 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 2860 // If we got a simplified select_cc node back from SimplifySelectCC, then 2861 // break it down into a new SETCC node, and a new SELECT node, and then return 2862 // the SELECT node, since we were called with a SELECT node. 2863 if (SCC.Val) { 2864 // Check to see if we got a select_cc back (to turn into setcc/select). 2865 // Otherwise, just return whatever node we got back, like fabs. 2866 if (SCC.getOpcode() == ISD::SELECT_CC) { 2867 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 2868 SCC.getOperand(0), SCC.getOperand(1), 2869 SCC.getOperand(4)); 2870 AddToWorkList(SETCC.Val); 2871 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 2872 SCC.getOperand(3), SETCC); 2873 } 2874 return SCC; 2875 } 2876 return SDOperand(); 2877} 2878 2879/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 2880/// are the two values being selected between, see if we can simplify the 2881/// select. Callers of this should assume that TheSelect is deleted if this 2882/// returns true. As such, they should return the appropriate thing (e.g. the 2883/// node) back to the top-level of the DAG combiner loop to avoid it being 2884/// looked at. 2885/// 2886bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 2887 SDOperand RHS) { 2888 2889 // If this is a select from two identical things, try to pull the operation 2890 // through the select. 2891 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 2892#if 0 2893 std::cerr << "SELECT: ["; LHS.Val->dump(); 2894 std::cerr << "] ["; RHS.Val->dump(); 2895 std::cerr << "]\n"; 2896#endif 2897 2898 // If this is a load and the token chain is identical, replace the select 2899 // of two loads with a load through a select of the address to load from. 2900 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 2901 // constants have been dropped into the constant pool. 2902 if ((LHS.getOpcode() == ISD::LOAD || 2903 LHS.getOpcode() == ISD::EXTLOAD || 2904 LHS.getOpcode() == ISD::ZEXTLOAD || 2905 LHS.getOpcode() == ISD::SEXTLOAD) && 2906 // Token chains must be identical. 2907 LHS.getOperand(0) == RHS.getOperand(0) && 2908 // If this is an EXTLOAD, the VT's must match. 2909 (LHS.getOpcode() == ISD::LOAD || 2910 LHS.getOperand(3) == RHS.getOperand(3))) { 2911 // FIXME: this conflates two src values, discarding one. This is not 2912 // the right thing to do, but nothing uses srcvalues now. When they do, 2913 // turn SrcValue into a list of locations. 2914 SDOperand Addr; 2915 if (TheSelect->getOpcode() == ISD::SELECT) 2916 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(), 2917 TheSelect->getOperand(0), LHS.getOperand(1), 2918 RHS.getOperand(1)); 2919 else 2920 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(), 2921 TheSelect->getOperand(0), 2922 TheSelect->getOperand(1), 2923 LHS.getOperand(1), RHS.getOperand(1), 2924 TheSelect->getOperand(4)); 2925 2926 SDOperand Load; 2927 if (LHS.getOpcode() == ISD::LOAD) 2928 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0), 2929 Addr, LHS.getOperand(2)); 2930 else 2931 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0), 2932 LHS.getOperand(0), Addr, LHS.getOperand(2), 2933 cast<VTSDNode>(LHS.getOperand(3))->getVT()); 2934 // Users of the select now use the result of the load. 2935 CombineTo(TheSelect, Load); 2936 2937 // Users of the old loads now use the new load's chain. We know the 2938 // old-load value is dead now. 2939 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 2940 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 2941 return true; 2942 } 2943 } 2944 2945 return false; 2946} 2947 2948SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 2949 SDOperand N2, SDOperand N3, 2950 ISD::CondCode CC) { 2951 2952 MVT::ValueType VT = N2.getValueType(); 2953 //ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 2954 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 2955 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 2956 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 2957 2958 // Determine if the condition we're dealing with is constant 2959 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2960 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 2961 2962 // fold select_cc true, x, y -> x 2963 if (SCCC && SCCC->getValue()) 2964 return N2; 2965 // fold select_cc false, x, y -> y 2966 if (SCCC && SCCC->getValue() == 0) 2967 return N3; 2968 2969 // Check to see if we can simplify the select into an fabs node 2970 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 2971 // Allow either -0.0 or 0.0 2972 if (CFP->getValue() == 0.0) { 2973 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 2974 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 2975 N0 == N2 && N3.getOpcode() == ISD::FNEG && 2976 N2 == N3.getOperand(0)) 2977 return DAG.getNode(ISD::FABS, VT, N0); 2978 2979 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 2980 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 2981 N0 == N3 && N2.getOpcode() == ISD::FNEG && 2982 N2.getOperand(0) == N3) 2983 return DAG.getNode(ISD::FABS, VT, N3); 2984 } 2985 } 2986 2987 // Check to see if we can perform the "gzip trick", transforming 2988 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 2989 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 2990 MVT::isInteger(N0.getValueType()) && 2991 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 2992 MVT::ValueType XType = N0.getValueType(); 2993 MVT::ValueType AType = N2.getValueType(); 2994 if (XType >= AType) { 2995 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 2996 // single-bit constant. 2997 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 2998 unsigned ShCtV = Log2_64(N2C->getValue()); 2999 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 3000 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 3001 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 3002 AddToWorkList(Shift.Val); 3003 if (XType > AType) { 3004 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 3005 AddToWorkList(Shift.Val); 3006 } 3007 return DAG.getNode(ISD::AND, AType, Shift, N2); 3008 } 3009 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 3010 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3011 TLI.getShiftAmountTy())); 3012 AddToWorkList(Shift.Val); 3013 if (XType > AType) { 3014 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 3015 AddToWorkList(Shift.Val); 3016 } 3017 return DAG.getNode(ISD::AND, AType, Shift, N2); 3018 } 3019 } 3020 3021 // fold select C, 16, 0 -> shl C, 4 3022 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 3023 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 3024 // Get a SetCC of the condition 3025 // FIXME: Should probably make sure that setcc is legal if we ever have a 3026 // target where it isn't. 3027 SDOperand Temp, SCC; 3028 // cast from setcc result type to select result type 3029 if (AfterLegalize) { 3030 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 3031 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 3032 } else { 3033 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 3034 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 3035 } 3036 AddToWorkList(SCC.Val); 3037 AddToWorkList(Temp.Val); 3038 // shl setcc result by log2 n2c 3039 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 3040 DAG.getConstant(Log2_64(N2C->getValue()), 3041 TLI.getShiftAmountTy())); 3042 } 3043 3044 // Check to see if this is the equivalent of setcc 3045 // FIXME: Turn all of these into setcc if setcc if setcc is legal 3046 // otherwise, go ahead with the folds. 3047 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 3048 MVT::ValueType XType = N0.getValueType(); 3049 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 3050 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 3051 if (Res.getValueType() != VT) 3052 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 3053 return Res; 3054 } 3055 3056 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 3057 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 3058 TLI.isOperationLegal(ISD::CTLZ, XType)) { 3059 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 3060 return DAG.getNode(ISD::SRL, XType, Ctlz, 3061 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 3062 TLI.getShiftAmountTy())); 3063 } 3064 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 3065 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 3066 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 3067 N0); 3068 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 3069 DAG.getConstant(~0ULL, XType)); 3070 return DAG.getNode(ISD::SRL, XType, 3071 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 3072 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3073 TLI.getShiftAmountTy())); 3074 } 3075 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 3076 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 3077 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 3078 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3079 TLI.getShiftAmountTy())); 3080 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 3081 } 3082 } 3083 3084 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 3085 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 3086 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 3087 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 3088 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 3089 MVT::ValueType XType = N0.getValueType(); 3090 if (SubC->isNullValue() && MVT::isInteger(XType)) { 3091 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 3092 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3093 TLI.getShiftAmountTy())); 3094 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 3095 AddToWorkList(Shift.Val); 3096 AddToWorkList(Add.Val); 3097 return DAG.getNode(ISD::XOR, XType, Add, Shift); 3098 } 3099 } 3100 } 3101 3102 return SDOperand(); 3103} 3104 3105SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 3106 SDOperand N1, ISD::CondCode Cond, 3107 bool foldBooleans) { 3108 // These setcc operations always fold. 3109 switch (Cond) { 3110 default: break; 3111 case ISD::SETFALSE: 3112 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 3113 case ISD::SETTRUE: 3114 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 3115 } 3116 3117 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 3118 uint64_t C1 = N1C->getValue(); 3119 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 3120 uint64_t C0 = N0C->getValue(); 3121 3122 // Sign extend the operands if required 3123 if (ISD::isSignedIntSetCC(Cond)) { 3124 C0 = N0C->getSignExtended(); 3125 C1 = N1C->getSignExtended(); 3126 } 3127 3128 switch (Cond) { 3129 default: assert(0 && "Unknown integer setcc!"); 3130 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 3131 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 3132 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 3133 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 3134 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 3135 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 3136 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 3137 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 3138 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 3139 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 3140 } 3141 } else { 3142 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 3143 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 3144 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 3145 3146 // If the comparison constant has bits in the upper part, the 3147 // zero-extended value could never match. 3148 if (C1 & (~0ULL << InSize)) { 3149 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 3150 switch (Cond) { 3151 case ISD::SETUGT: 3152 case ISD::SETUGE: 3153 case ISD::SETEQ: return DAG.getConstant(0, VT); 3154 case ISD::SETULT: 3155 case ISD::SETULE: 3156 case ISD::SETNE: return DAG.getConstant(1, VT); 3157 case ISD::SETGT: 3158 case ISD::SETGE: 3159 // True if the sign bit of C1 is set. 3160 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 3161 case ISD::SETLT: 3162 case ISD::SETLE: 3163 // True if the sign bit of C1 isn't set. 3164 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 3165 default: 3166 break; 3167 } 3168 } 3169 3170 // Otherwise, we can perform the comparison with the low bits. 3171 switch (Cond) { 3172 case ISD::SETEQ: 3173 case ISD::SETNE: 3174 case ISD::SETUGT: 3175 case ISD::SETUGE: 3176 case ISD::SETULT: 3177 case ISD::SETULE: 3178 return DAG.getSetCC(VT, N0.getOperand(0), 3179 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 3180 Cond); 3181 default: 3182 break; // todo, be more careful with signed comparisons 3183 } 3184 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3185 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 3186 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 3187 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 3188 MVT::ValueType ExtDstTy = N0.getValueType(); 3189 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 3190 3191 // If the extended part has any inconsistent bits, it cannot ever 3192 // compare equal. In other words, they have to be all ones or all 3193 // zeros. 3194 uint64_t ExtBits = 3195 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 3196 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 3197 return DAG.getConstant(Cond == ISD::SETNE, VT); 3198 3199 SDOperand ZextOp; 3200 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 3201 if (Op0Ty == ExtSrcTy) { 3202 ZextOp = N0.getOperand(0); 3203 } else { 3204 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 3205 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 3206 DAG.getConstant(Imm, Op0Ty)); 3207 } 3208 AddToWorkList(ZextOp.Val); 3209 // Otherwise, make this a use of a zext. 3210 return DAG.getSetCC(VT, ZextOp, 3211 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 3212 ExtDstTy), 3213 Cond); 3214 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && 3215 (Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3216 (N0.getOpcode() == ISD::XOR || 3217 (N0.getOpcode() == ISD::AND && 3218 N0.getOperand(0).getOpcode() == ISD::XOR && 3219 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 3220 isa<ConstantSDNode>(N0.getOperand(1)) && 3221 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { 3222 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can 3223 // only do this if the top bits are known zero. 3224 if (TLI.MaskedValueIsZero(N1, 3225 MVT::getIntVTBitMask(N0.getValueType())-1)) { 3226 // Okay, get the un-inverted input value. 3227 SDOperand Val; 3228 if (N0.getOpcode() == ISD::XOR) 3229 Val = N0.getOperand(0); 3230 else { 3231 assert(N0.getOpcode() == ISD::AND && 3232 N0.getOperand(0).getOpcode() == ISD::XOR); 3233 // ((X^1)&1)^1 -> X & 1 3234 Val = DAG.getNode(ISD::AND, N0.getValueType(), 3235 N0.getOperand(0).getOperand(0), N0.getOperand(1)); 3236 } 3237 return DAG.getSetCC(VT, Val, N1, 3238 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 3239 } 3240 } 3241 3242 uint64_t MinVal, MaxVal; 3243 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 3244 if (ISD::isSignedIntSetCC(Cond)) { 3245 MinVal = 1ULL << (OperandBitSize-1); 3246 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 3247 MaxVal = ~0ULL >> (65-OperandBitSize); 3248 else 3249 MaxVal = 0; 3250 } else { 3251 MinVal = 0; 3252 MaxVal = ~0ULL >> (64-OperandBitSize); 3253 } 3254 3255 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 3256 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 3257 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 3258 --C1; // X >= C0 --> X > (C0-1) 3259 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 3260 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 3261 } 3262 3263 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 3264 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 3265 ++C1; // X <= C0 --> X < (C0+1) 3266 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 3267 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 3268 } 3269 3270 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 3271 return DAG.getConstant(0, VT); // X < MIN --> false 3272 3273 // Canonicalize setgt X, Min --> setne X, Min 3274 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 3275 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 3276 // Canonicalize setlt X, Max --> setne X, Max 3277 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 3278 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 3279 3280 // If we have setult X, 1, turn it into seteq X, 0 3281 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 3282 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 3283 ISD::SETEQ); 3284 // If we have setugt X, Max-1, turn it into seteq X, Max 3285 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 3286 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 3287 ISD::SETEQ); 3288 3289 // If we have "setcc X, C0", check to see if we can shrink the immediate 3290 // by changing cc. 3291 3292 // SETUGT X, SINTMAX -> SETLT X, 0 3293 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 3294 C1 == (~0ULL >> (65-OperandBitSize))) 3295 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 3296 ISD::SETLT); 3297 3298 // FIXME: Implement the rest of these. 3299 3300 // Fold bit comparisons when we can. 3301 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3302 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 3303 if (ConstantSDNode *AndRHS = 3304 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3305 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 3306 // Perform the xform if the AND RHS is a single bit. 3307 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 3308 return DAG.getNode(ISD::SRL, VT, N0, 3309 DAG.getConstant(Log2_64(AndRHS->getValue()), 3310 TLI.getShiftAmountTy())); 3311 } 3312 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 3313 // (X & 8) == 8 --> (X & 8) >> 3 3314 // Perform the xform if C1 is a single bit. 3315 if ((C1 & (C1-1)) == 0) { 3316 return DAG.getNode(ISD::SRL, VT, N0, 3317 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 3318 } 3319 } 3320 } 3321 } 3322 } else if (isa<ConstantSDNode>(N0.Val)) { 3323 // Ensure that the constant occurs on the RHS. 3324 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 3325 } 3326 3327 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 3328 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 3329 double C0 = N0C->getValue(), C1 = N1C->getValue(); 3330 3331 switch (Cond) { 3332 default: break; // FIXME: Implement the rest of these! 3333 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 3334 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 3335 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 3336 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 3337 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 3338 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 3339 } 3340 } else { 3341 // Ensure that the constant occurs on the RHS. 3342 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 3343 } 3344 3345 if (N0 == N1) { 3346 // We can always fold X == Y for integer setcc's. 3347 if (MVT::isInteger(N0.getValueType())) 3348 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 3349 unsigned UOF = ISD::getUnorderedFlavor(Cond); 3350 if (UOF == 2) // FP operators that are undefined on NaNs. 3351 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 3352 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 3353 return DAG.getConstant(UOF, VT); 3354 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 3355 // if it is not already. 3356 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 3357 if (NewCond != Cond) 3358 return DAG.getSetCC(VT, N0, N1, NewCond); 3359 } 3360 3361 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3362 MVT::isInteger(N0.getValueType())) { 3363 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 3364 N0.getOpcode() == ISD::XOR) { 3365 // Simplify (X+Y) == (X+Z) --> Y == Z 3366 if (N0.getOpcode() == N1.getOpcode()) { 3367 if (N0.getOperand(0) == N1.getOperand(0)) 3368 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 3369 if (N0.getOperand(1) == N1.getOperand(1)) 3370 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 3371 if (isCommutativeBinOp(N0.getOpcode())) { 3372 // If X op Y == Y op X, try other combinations. 3373 if (N0.getOperand(0) == N1.getOperand(1)) 3374 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 3375 if (N0.getOperand(1) == N1.getOperand(0)) 3376 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 3377 } 3378 } 3379 3380 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 3381 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3382 // Turn (X+C1) == C2 --> X == C2-C1 3383 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 3384 return DAG.getSetCC(VT, N0.getOperand(0), 3385 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 3386 N0.getValueType()), Cond); 3387 } 3388 3389 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 3390 if (N0.getOpcode() == ISD::XOR) 3391 // If we know that all of the inverted bits are zero, don't bother 3392 // performing the inversion. 3393 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) 3394 return DAG.getSetCC(VT, N0.getOperand(0), 3395 DAG.getConstant(LHSR->getValue()^RHSC->getValue(), 3396 N0.getValueType()), Cond); 3397 } 3398 3399 // Turn (C1-X) == C2 --> X == C1-C2 3400 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 3401 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 3402 return DAG.getSetCC(VT, N0.getOperand(1), 3403 DAG.getConstant(SUBC->getValue()-RHSC->getValue(), 3404 N0.getValueType()), Cond); 3405 } 3406 } 3407 } 3408 3409 // Simplify (X+Z) == X --> Z == 0 3410 if (N0.getOperand(0) == N1) 3411 return DAG.getSetCC(VT, N0.getOperand(1), 3412 DAG.getConstant(0, N0.getValueType()), Cond); 3413 if (N0.getOperand(1) == N1) { 3414 if (isCommutativeBinOp(N0.getOpcode())) 3415 return DAG.getSetCC(VT, N0.getOperand(0), 3416 DAG.getConstant(0, N0.getValueType()), Cond); 3417 else { 3418 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 3419 // (Z-X) == X --> Z == X<<1 3420 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 3421 N1, 3422 DAG.getConstant(1,TLI.getShiftAmountTy())); 3423 AddToWorkList(SH.Val); 3424 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 3425 } 3426 } 3427 } 3428 3429 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 3430 N1.getOpcode() == ISD::XOR) { 3431 // Simplify X == (X+Z) --> Z == 0 3432 if (N1.getOperand(0) == N0) { 3433 return DAG.getSetCC(VT, N1.getOperand(1), 3434 DAG.getConstant(0, N1.getValueType()), Cond); 3435 } else if (N1.getOperand(1) == N0) { 3436 if (isCommutativeBinOp(N1.getOpcode())) { 3437 return DAG.getSetCC(VT, N1.getOperand(0), 3438 DAG.getConstant(0, N1.getValueType()), Cond); 3439 } else { 3440 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 3441 // X == (Z-X) --> X<<1 == Z 3442 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 3443 DAG.getConstant(1,TLI.getShiftAmountTy())); 3444 AddToWorkList(SH.Val); 3445 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 3446 } 3447 } 3448 } 3449 } 3450 3451 // Fold away ALL boolean setcc's. 3452 SDOperand Temp; 3453 if (N0.getValueType() == MVT::i1 && foldBooleans) { 3454 switch (Cond) { 3455 default: assert(0 && "Unknown integer setcc!"); 3456 case ISD::SETEQ: // X == Y -> (X^Y)^1 3457 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 3458 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 3459 AddToWorkList(Temp.Val); 3460 break; 3461 case ISD::SETNE: // X != Y --> (X^Y) 3462 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 3463 break; 3464 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 3465 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 3466 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 3467 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 3468 AddToWorkList(Temp.Val); 3469 break; 3470 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 3471 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 3472 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 3473 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 3474 AddToWorkList(Temp.Val); 3475 break; 3476 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 3477 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 3478 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 3479 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 3480 AddToWorkList(Temp.Val); 3481 break; 3482 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 3483 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 3484 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 3485 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 3486 break; 3487 } 3488 if (VT != MVT::i1) { 3489 AddToWorkList(N0.Val); 3490 // FIXME: If running after legalize, we probably can't do this. 3491 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 3492 } 3493 return N0; 3494 } 3495 3496 // Could not fold it. 3497 return SDOperand(); 3498} 3499 3500/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3501/// return a DAG expression to select that will generate the same value by 3502/// multiplying by a magic number. See: 3503/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3504SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 3505 std::vector<SDNode*> Built; 3506 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 3507 3508 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 3509 ii != ee; ++ii) 3510 AddToWorkList(*ii); 3511 return S; 3512} 3513 3514/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3515/// return a DAG expression to select that will generate the same value by 3516/// multiplying by a magic number. See: 3517/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3518SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 3519 std::vector<SDNode*> Built; 3520 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 3521 3522 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 3523 ii != ee; ++ii) 3524 AddToWorkList(*ii); 3525 return S; 3526} 3527 3528// SelectionDAG::Combine - This is the entry point for the file. 3529// 3530void SelectionDAG::Combine(bool RunningAfterLegalize) { 3531 /// run - This is the main entry point to this class. 3532 /// 3533 DAGCombiner(*this).Run(RunningAfterLegalize); 3534} 3535