DAGCombiner.cpp revision f79e60649a5edea03bdccf8521d77c15cbb33af4
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32using namespace llvm; 33 34STATISTIC(NodesCombined , "Number of dag nodes combined"); 35STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 36STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 37 38namespace { 39#ifndef NDEBUG 40 static cl::opt<bool> 41 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 42 cl::desc("Pop up a window to show dags before the first " 43 "dag combine pass")); 44 static cl::opt<bool> 45 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 46 cl::desc("Pop up a window to show dags before the second " 47 "dag combine pass")); 48#else 49 static const bool ViewDAGCombine1 = false; 50 static const bool ViewDAGCombine2 = false; 51#endif 52 53 static cl::opt<bool> 54 CombinerAA("combiner-alias-analysis", cl::Hidden, 55 cl::desc("Turn on alias analysis during testing")); 56 57 static cl::opt<bool> 58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 59 cl::desc("Include global information in alias analysis")); 60 61//------------------------------ DAGCombiner ---------------------------------// 62 63 class VISIBILITY_HIDDEN DAGCombiner { 64 SelectionDAG &DAG; 65 TargetLowering &TLI; 66 bool AfterLegalize; 67 68 // Worklist of all of the nodes that need to be simplified. 69 std::vector<SDNode*> WorkList; 70 71 // AA - Used for DAG load/store alias analysis. 72 AliasAnalysis &AA; 73 74 /// AddUsersToWorkList - When an instruction is simplified, add all users of 75 /// the instruction to the work lists because they might get more simplified 76 /// now. 77 /// 78 void AddUsersToWorkList(SDNode *N) { 79 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 80 UI != UE; ++UI) 81 AddToWorkList(*UI); 82 } 83 84 /// visit - call the node-specific routine that knows how to fold each 85 /// particular type of node. 86 SDOperand visit(SDNode *N); 87 88 public: 89 /// AddToWorkList - Add to the work list making sure it's instance is at the 90 /// the back (next to be processed.) 91 void AddToWorkList(SDNode *N) { 92 removeFromWorkList(N); 93 WorkList.push_back(N); 94 } 95 96 /// removeFromWorkList - remove all instances of N from the worklist. 97 /// 98 void removeFromWorkList(SDNode *N) { 99 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 100 WorkList.end()); 101 } 102 103 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 104 bool AddTo = true); 105 106 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 107 return CombineTo(N, &Res, 1, AddTo); 108 } 109 110 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 111 bool AddTo = true) { 112 SDOperand To[] = { Res0, Res1 }; 113 return CombineTo(N, To, 2, AddTo); 114 } 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDOperand Op) { 122 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 123 return SimplifyDemandedBits(Op, Demanded); 124 } 125 126 bool SimplifyDemandedBits(SDOperand Op, const APInt &Demanded); 127 128 bool CombineToPreIndexedLoadStore(SDNode *N); 129 bool CombineToPostIndexedLoadStore(SDNode *N); 130 131 132 /// combine - call the node-specific routine that knows how to fold each 133 /// particular type of node. If that doesn't do anything, try the 134 /// target-specific DAG combines. 135 SDOperand combine(SDNode *N); 136 137 // Visitation implementation - Implement dag node combining for different 138 // node types. The semantics are as follows: 139 // Return Value: 140 // SDOperand.Val == 0 - No change was made 141 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 142 // otherwise - N should be replaced by the returned Operand. 143 // 144 SDOperand visitTokenFactor(SDNode *N); 145 SDOperand visitMERGE_VALUES(SDNode *N); 146 SDOperand visitADD(SDNode *N); 147 SDOperand visitSUB(SDNode *N); 148 SDOperand visitADDC(SDNode *N); 149 SDOperand visitADDE(SDNode *N); 150 SDOperand visitMUL(SDNode *N); 151 SDOperand visitSDIV(SDNode *N); 152 SDOperand visitUDIV(SDNode *N); 153 SDOperand visitSREM(SDNode *N); 154 SDOperand visitUREM(SDNode *N); 155 SDOperand visitMULHU(SDNode *N); 156 SDOperand visitMULHS(SDNode *N); 157 SDOperand visitSMUL_LOHI(SDNode *N); 158 SDOperand visitUMUL_LOHI(SDNode *N); 159 SDOperand visitSDIVREM(SDNode *N); 160 SDOperand visitUDIVREM(SDNode *N); 161 SDOperand visitAND(SDNode *N); 162 SDOperand visitOR(SDNode *N); 163 SDOperand visitXOR(SDNode *N); 164 SDOperand SimplifyVBinOp(SDNode *N); 165 SDOperand visitSHL(SDNode *N); 166 SDOperand visitSRA(SDNode *N); 167 SDOperand visitSRL(SDNode *N); 168 SDOperand visitCTLZ(SDNode *N); 169 SDOperand visitCTTZ(SDNode *N); 170 SDOperand visitCTPOP(SDNode *N); 171 SDOperand visitSELECT(SDNode *N); 172 SDOperand visitSELECT_CC(SDNode *N); 173 SDOperand visitSETCC(SDNode *N); 174 SDOperand visitSIGN_EXTEND(SDNode *N); 175 SDOperand visitZERO_EXTEND(SDNode *N); 176 SDOperand visitANY_EXTEND(SDNode *N); 177 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 178 SDOperand visitTRUNCATE(SDNode *N); 179 SDOperand visitBIT_CONVERT(SDNode *N); 180 SDOperand visitFADD(SDNode *N); 181 SDOperand visitFSUB(SDNode *N); 182 SDOperand visitFMUL(SDNode *N); 183 SDOperand visitFDIV(SDNode *N); 184 SDOperand visitFREM(SDNode *N); 185 SDOperand visitFCOPYSIGN(SDNode *N); 186 SDOperand visitSINT_TO_FP(SDNode *N); 187 SDOperand visitUINT_TO_FP(SDNode *N); 188 SDOperand visitFP_TO_SINT(SDNode *N); 189 SDOperand visitFP_TO_UINT(SDNode *N); 190 SDOperand visitFP_ROUND(SDNode *N); 191 SDOperand visitFP_ROUND_INREG(SDNode *N); 192 SDOperand visitFP_EXTEND(SDNode *N); 193 SDOperand visitFNEG(SDNode *N); 194 SDOperand visitFABS(SDNode *N); 195 SDOperand visitBRCOND(SDNode *N); 196 SDOperand visitBR_CC(SDNode *N); 197 SDOperand visitLOAD(SDNode *N); 198 SDOperand visitSTORE(SDNode *N); 199 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 200 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N); 201 SDOperand visitBUILD_VECTOR(SDNode *N); 202 SDOperand visitCONCAT_VECTORS(SDNode *N); 203 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 204 205 SDOperand XformToShuffleWithZero(SDNode *N); 206 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 207 208 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt); 209 210 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 211 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 212 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 213 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 214 SDOperand N3, ISD::CondCode CC, 215 bool NotExtCompare = false); 216 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 217 ISD::CondCode Cond, bool foldBooleans = true); 218 SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 219 unsigned HiOp); 220 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); 221 SDOperand BuildSDIV(SDNode *N); 222 SDOperand BuildUDIV(SDNode *N); 223 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 224 SDOperand ReduceLoadWidth(SDNode *N); 225 226 SDOperand GetDemandedBits(SDOperand V, const APInt &Mask); 227 228 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 229 /// looking for aliasing nodes and adding them to the Aliases vector. 230 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 231 SmallVector<SDOperand, 8> &Aliases); 232 233 /// isAlias - Return true if there is any possibility that the two addresses 234 /// overlap. 235 bool isAlias(SDOperand Ptr1, int64_t Size1, 236 const Value *SrcValue1, int SrcValueOffset1, 237 SDOperand Ptr2, int64_t Size2, 238 const Value *SrcValue2, int SrcValueOffset2); 239 240 /// FindAliasInfo - Extracts the relevant alias information from the memory 241 /// node. Returns true if the operand was a load. 242 bool FindAliasInfo(SDNode *N, 243 SDOperand &Ptr, int64_t &Size, 244 const Value *&SrcValue, int &SrcValueOffset); 245 246 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 247 /// looking for a better chain (aliasing node.) 248 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 249 250public: 251 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 252 : DAG(D), 253 TLI(D.getTargetLoweringInfo()), 254 AfterLegalize(false), 255 AA(A) {} 256 257 /// Run - runs the dag combiner on all nodes in the work list 258 void Run(bool RunningAfterLegalize); 259 }; 260} 261 262 263namespace { 264/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 265/// nodes from the worklist. 266class VISIBILITY_HIDDEN WorkListRemover : 267 public SelectionDAG::DAGUpdateListener { 268 DAGCombiner &DC; 269public: 270 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 271 272 virtual void NodeDeleted(SDNode *N) { 273 DC.removeFromWorkList(N); 274 } 275 276 virtual void NodeUpdated(SDNode *N) { 277 // Ignore updates. 278 } 279}; 280} 281 282//===----------------------------------------------------------------------===// 283// TargetLowering::DAGCombinerInfo implementation 284//===----------------------------------------------------------------------===// 285 286void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 287 ((DAGCombiner*)DC)->AddToWorkList(N); 288} 289 290SDOperand TargetLowering::DAGCombinerInfo:: 291CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 292 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 293} 294 295SDOperand TargetLowering::DAGCombinerInfo:: 296CombineTo(SDNode *N, SDOperand Res) { 297 return ((DAGCombiner*)DC)->CombineTo(N, Res); 298} 299 300 301SDOperand TargetLowering::DAGCombinerInfo:: 302CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 303 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 304} 305 306 307//===----------------------------------------------------------------------===// 308// Helper Functions 309//===----------------------------------------------------------------------===// 310 311/// isNegatibleForFree - Return 1 if we can compute the negated form of the 312/// specified expression for the same cost as the expression itself, or 2 if we 313/// can compute the negated form more cheaply than the expression itself. 314static char isNegatibleForFree(SDOperand Op, bool AfterLegalize, 315 unsigned Depth = 0) { 316 // No compile time optimizations on this type. 317 if (Op.getValueType() == MVT::ppcf128) 318 return 0; 319 320 // fneg is removable even if it has multiple uses. 321 if (Op.getOpcode() == ISD::FNEG) return 2; 322 323 // Don't allow anything with multiple uses. 324 if (!Op.hasOneUse()) return 0; 325 326 // Don't recurse exponentially. 327 if (Depth > 6) return 0; 328 329 switch (Op.getOpcode()) { 330 default: return false; 331 case ISD::ConstantFP: 332 // Don't invert constant FP values after legalize. The negated constant 333 // isn't necessarily legal. 334 return AfterLegalize ? 0 : 1; 335 case ISD::FADD: 336 // FIXME: determine better conditions for this xform. 337 if (!UnsafeFPMath) return 0; 338 339 // -(A+B) -> -A - B 340 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 341 return V; 342 // -(A+B) -> -B - A 343 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 344 case ISD::FSUB: 345 // We can't turn -(A-B) into B-A when we honor signed zeros. 346 if (!UnsafeFPMath) return 0; 347 348 // -(A-B) -> B-A 349 return 1; 350 351 case ISD::FMUL: 352 case ISD::FDIV: 353 if (HonorSignDependentRoundingFPMath()) return 0; 354 355 // -(X*Y) -> (-X * Y) or (X*-Y) 356 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 357 return V; 358 359 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 360 361 case ISD::FP_EXTEND: 362 case ISD::FP_ROUND: 363 case ISD::FSIN: 364 return isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1); 365 } 366} 367 368/// GetNegatedExpression - If isNegatibleForFree returns true, this function 369/// returns the newly negated expression. 370static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 371 bool AfterLegalize, unsigned Depth = 0) { 372 // fneg is removable even if it has multiple uses. 373 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 374 375 // Don't allow anything with multiple uses. 376 assert(Op.hasOneUse() && "Unknown reuse!"); 377 378 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 379 switch (Op.getOpcode()) { 380 default: assert(0 && "Unknown code"); 381 case ISD::ConstantFP: { 382 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 383 V.changeSign(); 384 return DAG.getConstantFP(V, Op.getValueType()); 385 } 386 case ISD::FADD: 387 // FIXME: determine better conditions for this xform. 388 assert(UnsafeFPMath); 389 390 // -(A+B) -> -A - B 391 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 392 return DAG.getNode(ISD::FSUB, Op.getValueType(), 393 GetNegatedExpression(Op.getOperand(0), DAG, 394 AfterLegalize, Depth+1), 395 Op.getOperand(1)); 396 // -(A+B) -> -B - A 397 return DAG.getNode(ISD::FSUB, Op.getValueType(), 398 GetNegatedExpression(Op.getOperand(1), DAG, 399 AfterLegalize, Depth+1), 400 Op.getOperand(0)); 401 case ISD::FSUB: 402 // We can't turn -(A-B) into B-A when we honor signed zeros. 403 assert(UnsafeFPMath); 404 405 // -(0-B) -> B 406 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 407 if (N0CFP->getValueAPF().isZero()) 408 return Op.getOperand(1); 409 410 // -(A-B) -> B-A 411 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 412 Op.getOperand(0)); 413 414 case ISD::FMUL: 415 case ISD::FDIV: 416 assert(!HonorSignDependentRoundingFPMath()); 417 418 // -(X*Y) -> -X * Y 419 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 420 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 421 GetNegatedExpression(Op.getOperand(0), DAG, 422 AfterLegalize, Depth+1), 423 Op.getOperand(1)); 424 425 // -(X*Y) -> X * -Y 426 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 427 Op.getOperand(0), 428 GetNegatedExpression(Op.getOperand(1), DAG, 429 AfterLegalize, Depth+1)); 430 431 case ISD::FP_EXTEND: 432 case ISD::FSIN: 433 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 434 GetNegatedExpression(Op.getOperand(0), DAG, 435 AfterLegalize, Depth+1)); 436 case ISD::FP_ROUND: 437 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 438 GetNegatedExpression(Op.getOperand(0), DAG, 439 AfterLegalize, Depth+1), 440 Op.getOperand(1)); 441 } 442} 443 444 445// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 446// that selects between the values 1 and 0, making it equivalent to a setcc. 447// Also, set the incoming LHS, RHS, and CC references to the appropriate 448// nodes based on the type of node we are checking. This simplifies life a 449// bit for the callers. 450static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 451 SDOperand &CC) { 452 if (N.getOpcode() == ISD::SETCC) { 453 LHS = N.getOperand(0); 454 RHS = N.getOperand(1); 455 CC = N.getOperand(2); 456 return true; 457 } 458 if (N.getOpcode() == ISD::SELECT_CC && 459 N.getOperand(2).getOpcode() == ISD::Constant && 460 N.getOperand(3).getOpcode() == ISD::Constant && 461 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 462 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 463 LHS = N.getOperand(0); 464 RHS = N.getOperand(1); 465 CC = N.getOperand(4); 466 return true; 467 } 468 return false; 469} 470 471// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 472// one use. If this is true, it allows the users to invert the operation for 473// free when it is profitable to do so. 474static bool isOneUseSetCC(SDOperand N) { 475 SDOperand N0, N1, N2; 476 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 477 return true; 478 return false; 479} 480 481SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 482 MVT::ValueType VT = N0.getValueType(); 483 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 484 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 485 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 486 if (isa<ConstantSDNode>(N1)) { 487 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 488 AddToWorkList(OpNode.Val); 489 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 490 } else if (N0.hasOneUse()) { 491 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 492 AddToWorkList(OpNode.Val); 493 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 494 } 495 } 496 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 497 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 498 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 499 if (isa<ConstantSDNode>(N0)) { 500 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 501 AddToWorkList(OpNode.Val); 502 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 503 } else if (N1.hasOneUse()) { 504 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 505 AddToWorkList(OpNode.Val); 506 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 507 } 508 } 509 return SDOperand(); 510} 511 512SDOperand DAGCombiner::CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 513 bool AddTo) { 514 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 515 ++NodesCombined; 516 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 517 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 518 DOUT << " and " << NumTo-1 << " other values\n"; 519 WorkListRemover DeadNodes(*this); 520 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 521 522 if (AddTo) { 523 // Push the new nodes and any users onto the worklist 524 for (unsigned i = 0, e = NumTo; i != e; ++i) { 525 AddToWorkList(To[i].Val); 526 AddUsersToWorkList(To[i].Val); 527 } 528 } 529 530 // Nodes can be reintroduced into the worklist. Make sure we do not 531 // process a node that has been replaced. 532 removeFromWorkList(N); 533 534 // Finally, since the node is now dead, remove it from the graph. 535 DAG.DeleteNode(N); 536 return SDOperand(N, 0); 537} 538 539/// SimplifyDemandedBits - Check the specified integer node value to see if 540/// it can be simplified or if things it uses can be simplified by bit 541/// propagation. If so, return true. 542bool DAGCombiner::SimplifyDemandedBits(SDOperand Op, const APInt &Demanded) { 543 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize); 544 APInt KnownZero, KnownOne; 545 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 546 return false; 547 548 // Revisit the node. 549 AddToWorkList(Op.Val); 550 551 // Replace the old value with the new one. 552 ++NodesCombined; 553 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 554 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 555 DOUT << '\n'; 556 557 // Replace all uses. If any nodes become isomorphic to other nodes and 558 // are deleted, make sure to remove them from our worklist. 559 WorkListRemover DeadNodes(*this); 560 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 561 562 // Push the new node and any (possibly new) users onto the worklist. 563 AddToWorkList(TLO.New.Val); 564 AddUsersToWorkList(TLO.New.Val); 565 566 // Finally, if the node is now dead, remove it from the graph. The node 567 // may not be dead if the replacement process recursively simplified to 568 // something else needing this node. 569 if (TLO.Old.Val->use_empty()) { 570 removeFromWorkList(TLO.Old.Val); 571 572 // If the operands of this node are only used by the node, they will now 573 // be dead. Make sure to visit them first to delete dead nodes early. 574 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 575 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 576 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 577 578 DAG.DeleteNode(TLO.Old.Val); 579 } 580 return true; 581} 582 583//===----------------------------------------------------------------------===// 584// Main DAG Combiner implementation 585//===----------------------------------------------------------------------===// 586 587void DAGCombiner::Run(bool RunningAfterLegalize) { 588 // set the instance variable, so that the various visit routines may use it. 589 AfterLegalize = RunningAfterLegalize; 590 591 // Add all the dag nodes to the worklist. 592 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 593 E = DAG.allnodes_end(); I != E; ++I) 594 WorkList.push_back(I); 595 596 // Create a dummy node (which is not added to allnodes), that adds a reference 597 // to the root node, preventing it from being deleted, and tracking any 598 // changes of the root. 599 HandleSDNode Dummy(DAG.getRoot()); 600 601 // The root of the dag may dangle to deleted nodes until the dag combiner is 602 // done. Set it to null to avoid confusion. 603 DAG.setRoot(SDOperand()); 604 605 // while the worklist isn't empty, inspect the node on the end of it and 606 // try and combine it. 607 while (!WorkList.empty()) { 608 SDNode *N = WorkList.back(); 609 WorkList.pop_back(); 610 611 // If N has no uses, it is dead. Make sure to revisit all N's operands once 612 // N is deleted from the DAG, since they too may now be dead or may have a 613 // reduced number of uses, allowing other xforms. 614 if (N->use_empty() && N != &Dummy) { 615 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 616 AddToWorkList(N->getOperand(i).Val); 617 618 DAG.DeleteNode(N); 619 continue; 620 } 621 622 SDOperand RV = combine(N); 623 624 if (RV.Val == 0) 625 continue; 626 627 ++NodesCombined; 628 629 // If we get back the same node we passed in, rather than a new node or 630 // zero, we know that the node must have defined multiple values and 631 // CombineTo was used. Since CombineTo takes care of the worklist 632 // mechanics for us, we have no work to do in this case. 633 if (RV.Val == N) 634 continue; 635 636 assert(N->getOpcode() != ISD::DELETED_NODE && 637 RV.Val->getOpcode() != ISD::DELETED_NODE && 638 "Node was deleted but visit returned new node!"); 639 640 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 641 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 642 DOUT << '\n'; 643 WorkListRemover DeadNodes(*this); 644 if (N->getNumValues() == RV.Val->getNumValues()) 645 DAG.ReplaceAllUsesWith(N, RV.Val, &DeadNodes); 646 else { 647 assert(N->getValueType(0) == RV.getValueType() && 648 N->getNumValues() == 1 && "Type mismatch"); 649 SDOperand OpV = RV; 650 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 651 } 652 653 // Push the new node and any users onto the worklist 654 AddToWorkList(RV.Val); 655 AddUsersToWorkList(RV.Val); 656 657 // Add any uses of the old node to the worklist in case this node is the 658 // last one that uses them. They may become dead after this node is 659 // deleted. 660 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 661 AddToWorkList(N->getOperand(i).Val); 662 663 // Nodes can be reintroduced into the worklist. Make sure we do not 664 // process a node that has been replaced. 665 removeFromWorkList(N); 666 667 // Finally, since the node is now dead, remove it from the graph. 668 DAG.DeleteNode(N); 669 } 670 671 // If the root changed (e.g. it was a dead load, update the root). 672 DAG.setRoot(Dummy.getValue()); 673} 674 675SDOperand DAGCombiner::visit(SDNode *N) { 676 switch(N->getOpcode()) { 677 default: break; 678 case ISD::TokenFactor: return visitTokenFactor(N); 679 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 680 case ISD::ADD: return visitADD(N); 681 case ISD::SUB: return visitSUB(N); 682 case ISD::ADDC: return visitADDC(N); 683 case ISD::ADDE: return visitADDE(N); 684 case ISD::MUL: return visitMUL(N); 685 case ISD::SDIV: return visitSDIV(N); 686 case ISD::UDIV: return visitUDIV(N); 687 case ISD::SREM: return visitSREM(N); 688 case ISD::UREM: return visitUREM(N); 689 case ISD::MULHU: return visitMULHU(N); 690 case ISD::MULHS: return visitMULHS(N); 691 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 692 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 693 case ISD::SDIVREM: return visitSDIVREM(N); 694 case ISD::UDIVREM: return visitUDIVREM(N); 695 case ISD::AND: return visitAND(N); 696 case ISD::OR: return visitOR(N); 697 case ISD::XOR: return visitXOR(N); 698 case ISD::SHL: return visitSHL(N); 699 case ISD::SRA: return visitSRA(N); 700 case ISD::SRL: return visitSRL(N); 701 case ISD::CTLZ: return visitCTLZ(N); 702 case ISD::CTTZ: return visitCTTZ(N); 703 case ISD::CTPOP: return visitCTPOP(N); 704 case ISD::SELECT: return visitSELECT(N); 705 case ISD::SELECT_CC: return visitSELECT_CC(N); 706 case ISD::SETCC: return visitSETCC(N); 707 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 708 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 709 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 710 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 711 case ISD::TRUNCATE: return visitTRUNCATE(N); 712 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 713 case ISD::FADD: return visitFADD(N); 714 case ISD::FSUB: return visitFSUB(N); 715 case ISD::FMUL: return visitFMUL(N); 716 case ISD::FDIV: return visitFDIV(N); 717 case ISD::FREM: return visitFREM(N); 718 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 719 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 720 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 721 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 722 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 723 case ISD::FP_ROUND: return visitFP_ROUND(N); 724 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 725 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 726 case ISD::FNEG: return visitFNEG(N); 727 case ISD::FABS: return visitFABS(N); 728 case ISD::BRCOND: return visitBRCOND(N); 729 case ISD::BR_CC: return visitBR_CC(N); 730 case ISD::LOAD: return visitLOAD(N); 731 case ISD::STORE: return visitSTORE(N); 732 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 733 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 734 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 735 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 736 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 737 } 738 return SDOperand(); 739} 740 741SDOperand DAGCombiner::combine(SDNode *N) { 742 743 SDOperand RV = visit(N); 744 745 // If nothing happened, try a target-specific DAG combine. 746 if (RV.Val == 0) { 747 assert(N->getOpcode() != ISD::DELETED_NODE && 748 "Node was deleted but visit returned NULL!"); 749 750 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 751 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 752 753 // Expose the DAG combiner to the target combiner impls. 754 TargetLowering::DAGCombinerInfo 755 DagCombineInfo(DAG, !AfterLegalize, false, this); 756 757 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 758 } 759 } 760 761 return RV; 762} 763 764/// getInputChainForNode - Given a node, return its input chain if it has one, 765/// otherwise return a null sd operand. 766static SDOperand getInputChainForNode(SDNode *N) { 767 if (unsigned NumOps = N->getNumOperands()) { 768 if (N->getOperand(0).getValueType() == MVT::Other) 769 return N->getOperand(0); 770 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 771 return N->getOperand(NumOps-1); 772 for (unsigned i = 1; i < NumOps-1; ++i) 773 if (N->getOperand(i).getValueType() == MVT::Other) 774 return N->getOperand(i); 775 } 776 return SDOperand(0, 0); 777} 778 779SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 780 // If N has two operands, where one has an input chain equal to the other, 781 // the 'other' chain is redundant. 782 if (N->getNumOperands() == 2) { 783 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 784 return N->getOperand(0); 785 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 786 return N->getOperand(1); 787 } 788 789 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 790 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 791 SmallPtrSet<SDNode*, 16> SeenOps; 792 bool Changed = false; // If we should replace this token factor. 793 794 // Start out with this token factor. 795 TFs.push_back(N); 796 797 // Iterate through token factors. The TFs grows when new token factors are 798 // encountered. 799 for (unsigned i = 0; i < TFs.size(); ++i) { 800 SDNode *TF = TFs[i]; 801 802 // Check each of the operands. 803 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 804 SDOperand Op = TF->getOperand(i); 805 806 switch (Op.getOpcode()) { 807 case ISD::EntryToken: 808 // Entry tokens don't need to be added to the list. They are 809 // rededundant. 810 Changed = true; 811 break; 812 813 case ISD::TokenFactor: 814 if ((CombinerAA || Op.hasOneUse()) && 815 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 816 // Queue up for processing. 817 TFs.push_back(Op.Val); 818 // Clean up in case the token factor is removed. 819 AddToWorkList(Op.Val); 820 Changed = true; 821 break; 822 } 823 // Fall thru 824 825 default: 826 // Only add if it isn't already in the list. 827 if (SeenOps.insert(Op.Val)) 828 Ops.push_back(Op); 829 else 830 Changed = true; 831 break; 832 } 833 } 834 } 835 836 SDOperand Result; 837 838 // If we've change things around then replace token factor. 839 if (Changed) { 840 if (Ops.empty()) { 841 // The entry token is the only possible outcome. 842 Result = DAG.getEntryNode(); 843 } else { 844 // New and improved token factor. 845 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 846 } 847 848 // Don't add users to work list. 849 return CombineTo(N, Result, false); 850 } 851 852 return Result; 853} 854 855/// MERGE_VALUES can always be eliminated. 856SDOperand DAGCombiner::visitMERGE_VALUES(SDNode *N) { 857 WorkListRemover DeadNodes(*this); 858 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 859 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, i), N->getOperand(i), 860 &DeadNodes); 861 removeFromWorkList(N); 862 DAG.DeleteNode(N); 863 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 864} 865 866 867static 868SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 869 MVT::ValueType VT = N0.getValueType(); 870 SDOperand N00 = N0.getOperand(0); 871 SDOperand N01 = N0.getOperand(1); 872 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 873 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 874 isa<ConstantSDNode>(N00.getOperand(1))) { 875 N0 = DAG.getNode(ISD::ADD, VT, 876 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 877 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 878 return DAG.getNode(ISD::ADD, VT, N0, N1); 879 } 880 return SDOperand(); 881} 882 883static 884SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 885 SelectionDAG &DAG) { 886 MVT::ValueType VT = N->getValueType(0); 887 unsigned Opc = N->getOpcode(); 888 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 889 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 890 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 891 ISD::CondCode CC = ISD::SETCC_INVALID; 892 if (isSlctCC) 893 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 894 else { 895 SDOperand CCOp = Slct.getOperand(0); 896 if (CCOp.getOpcode() == ISD::SETCC) 897 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 898 } 899 900 bool DoXform = false; 901 bool InvCC = false; 902 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 903 "Bad input!"); 904 if (LHS.getOpcode() == ISD::Constant && 905 cast<ConstantSDNode>(LHS)->isNullValue()) 906 DoXform = true; 907 else if (CC != ISD::SETCC_INVALID && 908 RHS.getOpcode() == ISD::Constant && 909 cast<ConstantSDNode>(RHS)->isNullValue()) { 910 std::swap(LHS, RHS); 911 SDOperand Op0 = Slct.getOperand(0); 912 bool isInt = MVT::isInteger(isSlctCC ? Op0.getValueType() 913 : Op0.getOperand(0).getValueType()); 914 CC = ISD::getSetCCInverse(CC, isInt); 915 DoXform = true; 916 InvCC = true; 917 } 918 919 if (DoXform) { 920 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 921 if (isSlctCC) 922 return DAG.getSelectCC(OtherOp, Result, 923 Slct.getOperand(0), Slct.getOperand(1), CC); 924 SDOperand CCOp = Slct.getOperand(0); 925 if (InvCC) 926 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 927 CCOp.getOperand(1), CC); 928 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 929 } 930 return SDOperand(); 931} 932 933SDOperand DAGCombiner::visitADD(SDNode *N) { 934 SDOperand N0 = N->getOperand(0); 935 SDOperand N1 = N->getOperand(1); 936 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 937 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 938 MVT::ValueType VT = N0.getValueType(); 939 940 // fold vector ops 941 if (MVT::isVector(VT)) { 942 SDOperand FoldedVOp = SimplifyVBinOp(N); 943 if (FoldedVOp.Val) return FoldedVOp; 944 } 945 946 // fold (add x, undef) -> undef 947 if (N0.getOpcode() == ISD::UNDEF) 948 return N0; 949 if (N1.getOpcode() == ISD::UNDEF) 950 return N1; 951 // fold (add c1, c2) -> c1+c2 952 if (N0C && N1C) 953 return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT); 954 // canonicalize constant to RHS 955 if (N0C && !N1C) 956 return DAG.getNode(ISD::ADD, VT, N1, N0); 957 // fold (add x, 0) -> x 958 if (N1C && N1C->isNullValue()) 959 return N0; 960 // fold ((c1-A)+c2) -> (c1+c2)-A 961 if (N1C && N0.getOpcode() == ISD::SUB) 962 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 963 return DAG.getNode(ISD::SUB, VT, 964 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 965 N0.getOperand(1)); 966 // reassociate add 967 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 968 if (RADD.Val != 0) 969 return RADD; 970 // fold ((0-A) + B) -> B-A 971 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 972 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 973 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 974 // fold (A + (0-B)) -> A-B 975 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 976 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 977 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 978 // fold (A+(B-A)) -> B 979 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 980 return N1.getOperand(0); 981 982 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 983 return SDOperand(N, 0); 984 985 // fold (a+b) -> (a|b) iff a and b share no bits. 986 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 987 APInt LHSZero, LHSOne; 988 APInt RHSZero, RHSOne; 989 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); 990 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 991 if (LHSZero.getBoolValue()) { 992 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 993 994 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 995 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 996 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 997 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 998 return DAG.getNode(ISD::OR, VT, N0, N1); 999 } 1000 } 1001 1002 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1003 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 1004 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 1005 if (Result.Val) return Result; 1006 } 1007 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 1008 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 1009 if (Result.Val) return Result; 1010 } 1011 1012 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1013 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 1014 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 1015 if (Result.Val) return Result; 1016 } 1017 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1018 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1019 if (Result.Val) return Result; 1020 } 1021 1022 return SDOperand(); 1023} 1024 1025SDOperand DAGCombiner::visitADDC(SDNode *N) { 1026 SDOperand N0 = N->getOperand(0); 1027 SDOperand N1 = N->getOperand(1); 1028 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1029 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1030 MVT::ValueType VT = N0.getValueType(); 1031 1032 // If the flag result is dead, turn this into an ADD. 1033 if (N->hasNUsesOfValue(0, 1)) 1034 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1035 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1036 1037 // canonicalize constant to RHS. 1038 if (N0C && !N1C) { 1039 SDOperand Ops[] = { N1, N0 }; 1040 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1041 } 1042 1043 // fold (addc x, 0) -> x + no carry out 1044 if (N1C && N1C->isNullValue()) 1045 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1046 1047 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1048 APInt LHSZero, LHSOne; 1049 APInt RHSZero, RHSOne; 1050 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); 1051 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1052 if (LHSZero.getBoolValue()) { 1053 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1054 1055 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1056 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1057 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1058 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1059 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1060 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1061 } 1062 1063 return SDOperand(); 1064} 1065 1066SDOperand DAGCombiner::visitADDE(SDNode *N) { 1067 SDOperand N0 = N->getOperand(0); 1068 SDOperand N1 = N->getOperand(1); 1069 SDOperand CarryIn = N->getOperand(2); 1070 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1071 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1072 //MVT::ValueType VT = N0.getValueType(); 1073 1074 // canonicalize constant to RHS 1075 if (N0C && !N1C) { 1076 SDOperand Ops[] = { N1, N0, CarryIn }; 1077 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 1078 } 1079 1080 // fold (adde x, y, false) -> (addc x, y) 1081 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 1082 SDOperand Ops[] = { N1, N0 }; 1083 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1084 } 1085 1086 return SDOperand(); 1087} 1088 1089 1090 1091SDOperand DAGCombiner::visitSUB(SDNode *N) { 1092 SDOperand N0 = N->getOperand(0); 1093 SDOperand N1 = N->getOperand(1); 1094 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1095 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1096 MVT::ValueType VT = N0.getValueType(); 1097 1098 // fold vector ops 1099 if (MVT::isVector(VT)) { 1100 SDOperand FoldedVOp = SimplifyVBinOp(N); 1101 if (FoldedVOp.Val) return FoldedVOp; 1102 } 1103 1104 // fold (sub x, x) -> 0 1105 if (N0 == N1) 1106 if (ISD::isBuildVectorAllZeros(N0.Val)) 1107 // Zero vectors might be normalized to a particular vector type to ensure 1108 // they are CSE'd. Return it as it is. 1109 return N0; 1110 return DAG.getConstant(0, N->getValueType(0)); 1111 // fold (sub c1, c2) -> c1-c2 1112 if (N0C && N1C) 1113 return DAG.getNode(ISD::SUB, VT, N0, N1); 1114 // fold (sub x, c) -> (add x, -c) 1115 if (N1C) 1116 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 1117 // fold (A+B)-A -> B 1118 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1119 return N0.getOperand(1); 1120 // fold (A+B)-B -> A 1121 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1122 return N0.getOperand(0); 1123 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1124 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1125 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1126 if (Result.Val) return Result; 1127 } 1128 // If either operand of a sub is undef, the result is undef 1129 if (N0.getOpcode() == ISD::UNDEF) 1130 return N0; 1131 if (N1.getOpcode() == ISD::UNDEF) 1132 return N1; 1133 1134 return SDOperand(); 1135} 1136 1137SDOperand DAGCombiner::visitMUL(SDNode *N) { 1138 SDOperand N0 = N->getOperand(0); 1139 SDOperand N1 = N->getOperand(1); 1140 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1141 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1142 MVT::ValueType VT = N0.getValueType(); 1143 1144 // fold vector ops 1145 if (MVT::isVector(VT)) { 1146 SDOperand FoldedVOp = SimplifyVBinOp(N); 1147 if (FoldedVOp.Val) return FoldedVOp; 1148 } 1149 1150 // fold (mul x, undef) -> 0 1151 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1152 return DAG.getConstant(0, VT); 1153 // fold (mul c1, c2) -> c1*c2 1154 if (N0C && N1C) 1155 return DAG.getNode(ISD::MUL, VT, N0, N1); 1156 // canonicalize constant to RHS 1157 if (N0C && !N1C) 1158 return DAG.getNode(ISD::MUL, VT, N1, N0); 1159 // fold (mul x, 0) -> 0 1160 if (N1C && N1C->isNullValue()) 1161 return N1; 1162 // fold (mul x, -1) -> 0-x 1163 if (N1C && N1C->isAllOnesValue()) 1164 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1165 // fold (mul x, (1 << c)) -> x << c 1166 if (N1C && isPowerOf2_64(N1C->getValue())) 1167 return DAG.getNode(ISD::SHL, VT, N0, 1168 DAG.getConstant(Log2_64(N1C->getValue()), 1169 TLI.getShiftAmountTy())); 1170 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1171 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1172 // FIXME: If the input is something that is easily negated (e.g. a 1173 // single-use add), we should put the negate there. 1174 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1175 DAG.getNode(ISD::SHL, VT, N0, 1176 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1177 TLI.getShiftAmountTy()))); 1178 } 1179 1180 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1181 if (N1C && N0.getOpcode() == ISD::SHL && 1182 isa<ConstantSDNode>(N0.getOperand(1))) { 1183 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1184 AddToWorkList(C3.Val); 1185 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1186 } 1187 1188 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1189 // use. 1190 { 1191 SDOperand Sh(0,0), Y(0,0); 1192 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1193 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1194 N0.Val->hasOneUse()) { 1195 Sh = N0; Y = N1; 1196 } else if (N1.getOpcode() == ISD::SHL && 1197 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1198 Sh = N1; Y = N0; 1199 } 1200 if (Sh.Val) { 1201 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1202 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1203 } 1204 } 1205 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1206 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1207 isa<ConstantSDNode>(N0.getOperand(1))) { 1208 return DAG.getNode(ISD::ADD, VT, 1209 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1210 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1211 } 1212 1213 // reassociate mul 1214 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1215 if (RMUL.Val != 0) 1216 return RMUL; 1217 1218 return SDOperand(); 1219} 1220 1221SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1222 SDOperand N0 = N->getOperand(0); 1223 SDOperand N1 = N->getOperand(1); 1224 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1225 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1226 MVT::ValueType VT = N->getValueType(0); 1227 1228 // fold vector ops 1229 if (MVT::isVector(VT)) { 1230 SDOperand FoldedVOp = SimplifyVBinOp(N); 1231 if (FoldedVOp.Val) return FoldedVOp; 1232 } 1233 1234 // fold (sdiv c1, c2) -> c1/c2 1235 if (N0C && N1C && !N1C->isNullValue()) 1236 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1237 // fold (sdiv X, 1) -> X 1238 if (N1C && N1C->getSignExtended() == 1LL) 1239 return N0; 1240 // fold (sdiv X, -1) -> 0-X 1241 if (N1C && N1C->isAllOnesValue()) 1242 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1243 // If we know the sign bits of both operands are zero, strength reduce to a 1244 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1245 if (!MVT::isVector(VT)) { 1246 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1247 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1248 } 1249 // fold (sdiv X, pow2) -> simple ops after legalize 1250 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 1251 (isPowerOf2_64(N1C->getSignExtended()) || 1252 isPowerOf2_64(-N1C->getSignExtended()))) { 1253 // If dividing by powers of two is cheap, then don't perform the following 1254 // fold. 1255 if (TLI.isPow2DivCheap()) 1256 return SDOperand(); 1257 int64_t pow2 = N1C->getSignExtended(); 1258 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1259 unsigned lg2 = Log2_64(abs2); 1260 // Splat the sign bit into the register 1261 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1262 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1263 TLI.getShiftAmountTy())); 1264 AddToWorkList(SGN.Val); 1265 // Add (N0 < 0) ? abs2 - 1 : 0; 1266 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1267 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1268 TLI.getShiftAmountTy())); 1269 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1270 AddToWorkList(SRL.Val); 1271 AddToWorkList(ADD.Val); // Divide by pow2 1272 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1273 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1274 // If we're dividing by a positive value, we're done. Otherwise, we must 1275 // negate the result. 1276 if (pow2 > 0) 1277 return SRA; 1278 AddToWorkList(SRA.Val); 1279 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1280 } 1281 // if integer divide is expensive and we satisfy the requirements, emit an 1282 // alternate sequence. 1283 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1284 !TLI.isIntDivCheap()) { 1285 SDOperand Op = BuildSDIV(N); 1286 if (Op.Val) return Op; 1287 } 1288 1289 // undef / X -> 0 1290 if (N0.getOpcode() == ISD::UNDEF) 1291 return DAG.getConstant(0, VT); 1292 // X / undef -> undef 1293 if (N1.getOpcode() == ISD::UNDEF) 1294 return N1; 1295 1296 return SDOperand(); 1297} 1298 1299SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1300 SDOperand N0 = N->getOperand(0); 1301 SDOperand N1 = N->getOperand(1); 1302 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1303 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1304 MVT::ValueType VT = N->getValueType(0); 1305 1306 // fold vector ops 1307 if (MVT::isVector(VT)) { 1308 SDOperand FoldedVOp = SimplifyVBinOp(N); 1309 if (FoldedVOp.Val) return FoldedVOp; 1310 } 1311 1312 // fold (udiv c1, c2) -> c1/c2 1313 if (N0C && N1C && !N1C->isNullValue()) 1314 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1315 // fold (udiv x, (1 << c)) -> x >>u c 1316 if (N1C && isPowerOf2_64(N1C->getValue())) 1317 return DAG.getNode(ISD::SRL, VT, N0, 1318 DAG.getConstant(Log2_64(N1C->getValue()), 1319 TLI.getShiftAmountTy())); 1320 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1321 if (N1.getOpcode() == ISD::SHL) { 1322 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1323 if (isPowerOf2_64(SHC->getValue())) { 1324 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1325 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1326 DAG.getConstant(Log2_64(SHC->getValue()), 1327 ADDVT)); 1328 AddToWorkList(Add.Val); 1329 return DAG.getNode(ISD::SRL, VT, N0, Add); 1330 } 1331 } 1332 } 1333 // fold (udiv x, c) -> alternate 1334 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1335 SDOperand Op = BuildUDIV(N); 1336 if (Op.Val) return Op; 1337 } 1338 1339 // undef / X -> 0 1340 if (N0.getOpcode() == ISD::UNDEF) 1341 return DAG.getConstant(0, VT); 1342 // X / undef -> undef 1343 if (N1.getOpcode() == ISD::UNDEF) 1344 return N1; 1345 1346 return SDOperand(); 1347} 1348 1349SDOperand DAGCombiner::visitSREM(SDNode *N) { 1350 SDOperand N0 = N->getOperand(0); 1351 SDOperand N1 = N->getOperand(1); 1352 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1353 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1354 MVT::ValueType VT = N->getValueType(0); 1355 1356 // fold (srem c1, c2) -> c1%c2 1357 if (N0C && N1C && !N1C->isNullValue()) 1358 return DAG.getNode(ISD::SREM, VT, N0, N1); 1359 // If we know the sign bits of both operands are zero, strength reduce to a 1360 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1361 if (!MVT::isVector(VT)) { 1362 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1363 return DAG.getNode(ISD::UREM, VT, N0, N1); 1364 } 1365 1366 // If X/C can be simplified by the division-by-constant logic, lower 1367 // X%C to the equivalent of X-X/C*C. 1368 if (N1C && !N1C->isNullValue()) { 1369 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1370 AddToWorkList(Div.Val); 1371 SDOperand OptimizedDiv = combine(Div.Val); 1372 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1373 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1374 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1375 AddToWorkList(Mul.Val); 1376 return Sub; 1377 } 1378 } 1379 1380 // undef % X -> 0 1381 if (N0.getOpcode() == ISD::UNDEF) 1382 return DAG.getConstant(0, VT); 1383 // X % undef -> undef 1384 if (N1.getOpcode() == ISD::UNDEF) 1385 return N1; 1386 1387 return SDOperand(); 1388} 1389 1390SDOperand DAGCombiner::visitUREM(SDNode *N) { 1391 SDOperand N0 = N->getOperand(0); 1392 SDOperand N1 = N->getOperand(1); 1393 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1394 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1395 MVT::ValueType VT = N->getValueType(0); 1396 1397 // fold (urem c1, c2) -> c1%c2 1398 if (N0C && N1C && !N1C->isNullValue()) 1399 return DAG.getNode(ISD::UREM, VT, N0, N1); 1400 // fold (urem x, pow2) -> (and x, pow2-1) 1401 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1402 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1403 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1404 if (N1.getOpcode() == ISD::SHL) { 1405 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1406 if (isPowerOf2_64(SHC->getValue())) { 1407 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1408 AddToWorkList(Add.Val); 1409 return DAG.getNode(ISD::AND, VT, N0, Add); 1410 } 1411 } 1412 } 1413 1414 // If X/C can be simplified by the division-by-constant logic, lower 1415 // X%C to the equivalent of X-X/C*C. 1416 if (N1C && !N1C->isNullValue()) { 1417 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1418 SDOperand OptimizedDiv = combine(Div.Val); 1419 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1420 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1421 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1422 AddToWorkList(Mul.Val); 1423 return Sub; 1424 } 1425 } 1426 1427 // undef % X -> 0 1428 if (N0.getOpcode() == ISD::UNDEF) 1429 return DAG.getConstant(0, VT); 1430 // X % undef -> undef 1431 if (N1.getOpcode() == ISD::UNDEF) 1432 return N1; 1433 1434 return SDOperand(); 1435} 1436 1437SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1438 SDOperand N0 = N->getOperand(0); 1439 SDOperand N1 = N->getOperand(1); 1440 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1441 MVT::ValueType VT = N->getValueType(0); 1442 1443 // fold (mulhs x, 0) -> 0 1444 if (N1C && N1C->isNullValue()) 1445 return N1; 1446 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1447 if (N1C && N1C->getValue() == 1) 1448 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1449 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1450 TLI.getShiftAmountTy())); 1451 // fold (mulhs x, undef) -> 0 1452 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1453 return DAG.getConstant(0, VT); 1454 1455 return SDOperand(); 1456} 1457 1458SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1459 SDOperand N0 = N->getOperand(0); 1460 SDOperand N1 = N->getOperand(1); 1461 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1462 MVT::ValueType VT = N->getValueType(0); 1463 1464 // fold (mulhu x, 0) -> 0 1465 if (N1C && N1C->isNullValue()) 1466 return N1; 1467 // fold (mulhu x, 1) -> 0 1468 if (N1C && N1C->getValue() == 1) 1469 return DAG.getConstant(0, N0.getValueType()); 1470 // fold (mulhu x, undef) -> 0 1471 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1472 return DAG.getConstant(0, VT); 1473 1474 return SDOperand(); 1475} 1476 1477/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1478/// compute two values. LoOp and HiOp give the opcodes for the two computations 1479/// that are being performed. Return true if a simplification was made. 1480/// 1481SDOperand DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1482 unsigned HiOp) { 1483 // If the high half is not needed, just compute the low half. 1484 bool HiExists = N->hasAnyUseOfValue(1); 1485 if (!HiExists && 1486 (!AfterLegalize || 1487 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1488 SDOperand Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1489 N->getNumOperands()); 1490 return CombineTo(N, Res, Res); 1491 } 1492 1493 // If the low half is not needed, just compute the high half. 1494 bool LoExists = N->hasAnyUseOfValue(0); 1495 if (!LoExists && 1496 (!AfterLegalize || 1497 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1498 SDOperand Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1499 N->getNumOperands()); 1500 return CombineTo(N, Res, Res); 1501 } 1502 1503 // If both halves are used, return as it is. 1504 if (LoExists && HiExists) 1505 return SDOperand(); 1506 1507 // If the two computed results can be simplified separately, separate them. 1508 if (LoExists) { 1509 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0), 1510 N->op_begin(), N->getNumOperands()); 1511 AddToWorkList(Lo.Val); 1512 SDOperand LoOpt = combine(Lo.Val); 1513 if (LoOpt.Val && LoOpt.Val != Lo.Val && 1514 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())) 1515 return CombineTo(N, LoOpt, LoOpt); 1516 } 1517 1518 if (HiExists) { 1519 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1), 1520 N->op_begin(), N->getNumOperands()); 1521 AddToWorkList(Hi.Val); 1522 SDOperand HiOpt = combine(Hi.Val); 1523 if (HiOpt.Val && HiOpt != Hi && 1524 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) 1525 return CombineTo(N, HiOpt, HiOpt); 1526 } 1527 return SDOperand(); 1528} 1529 1530SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1531 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1532 if (Res.Val) return Res; 1533 1534 return SDOperand(); 1535} 1536 1537SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1538 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1539 if (Res.Val) return Res; 1540 1541 return SDOperand(); 1542} 1543 1544SDOperand DAGCombiner::visitSDIVREM(SDNode *N) { 1545 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1546 if (Res.Val) return Res; 1547 1548 return SDOperand(); 1549} 1550 1551SDOperand DAGCombiner::visitUDIVREM(SDNode *N) { 1552 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1553 if (Res.Val) return Res; 1554 1555 return SDOperand(); 1556} 1557 1558/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1559/// two operands of the same opcode, try to simplify it. 1560SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1561 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1562 MVT::ValueType VT = N0.getValueType(); 1563 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1564 1565 // For each of OP in AND/OR/XOR: 1566 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1567 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1568 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1569 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1570 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1571 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1572 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1573 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1574 N0.getOperand(0).getValueType(), 1575 N0.getOperand(0), N1.getOperand(0)); 1576 AddToWorkList(ORNode.Val); 1577 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1578 } 1579 1580 // For each of OP in SHL/SRL/SRA/AND... 1581 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1582 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1583 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1584 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1585 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1586 N0.getOperand(1) == N1.getOperand(1)) { 1587 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1588 N0.getOperand(0).getValueType(), 1589 N0.getOperand(0), N1.getOperand(0)); 1590 AddToWorkList(ORNode.Val); 1591 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1592 } 1593 1594 return SDOperand(); 1595} 1596 1597SDOperand DAGCombiner::visitAND(SDNode *N) { 1598 SDOperand N0 = N->getOperand(0); 1599 SDOperand N1 = N->getOperand(1); 1600 SDOperand LL, LR, RL, RR, CC0, CC1; 1601 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1602 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1603 MVT::ValueType VT = N1.getValueType(); 1604 unsigned BitWidth = MVT::getSizeInBits(VT); 1605 1606 // fold vector ops 1607 if (MVT::isVector(VT)) { 1608 SDOperand FoldedVOp = SimplifyVBinOp(N); 1609 if (FoldedVOp.Val) return FoldedVOp; 1610 } 1611 1612 // fold (and x, undef) -> 0 1613 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1614 return DAG.getConstant(0, VT); 1615 // fold (and c1, c2) -> c1&c2 1616 if (N0C && N1C) 1617 return DAG.getNode(ISD::AND, VT, N0, N1); 1618 // canonicalize constant to RHS 1619 if (N0C && !N1C) 1620 return DAG.getNode(ISD::AND, VT, N1, N0); 1621 // fold (and x, -1) -> x 1622 if (N1C && N1C->isAllOnesValue()) 1623 return N0; 1624 // if (and x, c) is known to be zero, return 0 1625 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), 1626 APInt::getAllOnesValue(BitWidth))) 1627 return DAG.getConstant(0, VT); 1628 // reassociate and 1629 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1630 if (RAND.Val != 0) 1631 return RAND; 1632 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1633 if (N1C && N0.getOpcode() == ISD::OR) 1634 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1635 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1636 return N1; 1637 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1638 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1639 SDOperand N0Op0 = N0.getOperand(0); 1640 APInt Mask = ~N1C->getAPIntValue(); 1641 Mask.trunc(N0Op0.getValueSizeInBits()); 1642 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1643 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1644 N0Op0); 1645 1646 // Replace uses of the AND with uses of the Zero extend node. 1647 CombineTo(N, Zext); 1648 1649 // We actually want to replace all uses of the any_extend with the 1650 // zero_extend, to avoid duplicating things. This will later cause this 1651 // AND to be folded. 1652 CombineTo(N0.Val, Zext); 1653 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1654 } 1655 } 1656 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1657 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1658 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1659 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1660 1661 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1662 MVT::isInteger(LL.getValueType())) { 1663 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1664 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1665 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1666 AddToWorkList(ORNode.Val); 1667 return DAG.getSetCC(VT, ORNode, LR, Op1); 1668 } 1669 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1670 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1671 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1672 AddToWorkList(ANDNode.Val); 1673 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1674 } 1675 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1676 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1677 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1678 AddToWorkList(ORNode.Val); 1679 return DAG.getSetCC(VT, ORNode, LR, Op1); 1680 } 1681 } 1682 // canonicalize equivalent to ll == rl 1683 if (LL == RR && LR == RL) { 1684 Op1 = ISD::getSetCCSwappedOperands(Op1); 1685 std::swap(RL, RR); 1686 } 1687 if (LL == RL && LR == RR) { 1688 bool isInteger = MVT::isInteger(LL.getValueType()); 1689 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1690 if (Result != ISD::SETCC_INVALID) 1691 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1692 } 1693 } 1694 1695 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1696 if (N0.getOpcode() == N1.getOpcode()) { 1697 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1698 if (Tmp.Val) return Tmp; 1699 } 1700 1701 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1702 // fold (and (sra)) -> (and (srl)) when possible. 1703 if (!MVT::isVector(VT) && 1704 SimplifyDemandedBits(SDOperand(N, 0))) 1705 return SDOperand(N, 0); 1706 // fold (zext_inreg (extload x)) -> (zextload x) 1707 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1708 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1709 MVT::ValueType EVT = LN0->getMemoryVT(); 1710 // If we zero all the possible extended bits, then we can turn this into 1711 // a zextload if we are running before legalize or the operation is legal. 1712 unsigned BitWidth = N1.getValueSizeInBits(); 1713 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1714 BitWidth - MVT::getSizeInBits(EVT))) && 1715 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1716 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1717 LN0->getBasePtr(), LN0->getSrcValue(), 1718 LN0->getSrcValueOffset(), EVT, 1719 LN0->isVolatile(), 1720 LN0->getAlignment()); 1721 AddToWorkList(N); 1722 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1723 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1724 } 1725 } 1726 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1727 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1728 N0.hasOneUse()) { 1729 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1730 MVT::ValueType EVT = LN0->getMemoryVT(); 1731 // If we zero all the possible extended bits, then we can turn this into 1732 // a zextload if we are running before legalize or the operation is legal. 1733 unsigned BitWidth = N1.getValueSizeInBits(); 1734 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1735 BitWidth - MVT::getSizeInBits(EVT))) && 1736 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1737 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1738 LN0->getBasePtr(), LN0->getSrcValue(), 1739 LN0->getSrcValueOffset(), EVT, 1740 LN0->isVolatile(), 1741 LN0->getAlignment()); 1742 AddToWorkList(N); 1743 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1744 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1745 } 1746 } 1747 1748 // fold (and (load x), 255) -> (zextload x, i8) 1749 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1750 if (N1C && N0.getOpcode() == ISD::LOAD) { 1751 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1752 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1753 LN0->isUnindexed() && N0.hasOneUse()) { 1754 MVT::ValueType EVT, LoadedVT; 1755 if (N1C->getValue() == 255) 1756 EVT = MVT::i8; 1757 else if (N1C->getValue() == 65535) 1758 EVT = MVT::i16; 1759 else if (N1C->getValue() == ~0U) 1760 EVT = MVT::i32; 1761 else 1762 EVT = MVT::Other; 1763 1764 LoadedVT = LN0->getMemoryVT(); 1765 if (EVT != MVT::Other && LoadedVT > EVT && 1766 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1767 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1768 // For big endian targets, we need to add an offset to the pointer to 1769 // load the correct bytes. For little endian systems, we merely need to 1770 // read fewer bytes from the same pointer. 1771 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8; 1772 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8; 1773 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1774 unsigned Alignment = LN0->getAlignment(); 1775 SDOperand NewPtr = LN0->getBasePtr(); 1776 if (TLI.isBigEndian()) { 1777 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1778 DAG.getConstant(PtrOff, PtrType)); 1779 Alignment = MinAlign(Alignment, PtrOff); 1780 } 1781 AddToWorkList(NewPtr.Val); 1782 SDOperand Load = 1783 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1784 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1785 LN0->isVolatile(), Alignment); 1786 AddToWorkList(N); 1787 CombineTo(N0.Val, Load, Load.getValue(1)); 1788 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1789 } 1790 } 1791 } 1792 1793 return SDOperand(); 1794} 1795 1796SDOperand DAGCombiner::visitOR(SDNode *N) { 1797 SDOperand N0 = N->getOperand(0); 1798 SDOperand N1 = N->getOperand(1); 1799 SDOperand LL, LR, RL, RR, CC0, CC1; 1800 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1801 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1802 MVT::ValueType VT = N1.getValueType(); 1803 1804 // fold vector ops 1805 if (MVT::isVector(VT)) { 1806 SDOperand FoldedVOp = SimplifyVBinOp(N); 1807 if (FoldedVOp.Val) return FoldedVOp; 1808 } 1809 1810 // fold (or x, undef) -> -1 1811 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1812 return DAG.getConstant(~0ULL, VT); 1813 // fold (or c1, c2) -> c1|c2 1814 if (N0C && N1C) 1815 return DAG.getNode(ISD::OR, VT, N0, N1); 1816 // canonicalize constant to RHS 1817 if (N0C && !N1C) 1818 return DAG.getNode(ISD::OR, VT, N1, N0); 1819 // fold (or x, 0) -> x 1820 if (N1C && N1C->isNullValue()) 1821 return N0; 1822 // fold (or x, -1) -> -1 1823 if (N1C && N1C->isAllOnesValue()) 1824 return N1; 1825 // fold (or x, c) -> c iff (x & ~c) == 0 1826 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1827 return N1; 1828 // reassociate or 1829 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1830 if (ROR.Val != 0) 1831 return ROR; 1832 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1833 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1834 isa<ConstantSDNode>(N0.getOperand(1))) { 1835 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1836 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1837 N1), 1838 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1839 } 1840 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1841 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1842 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1843 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1844 1845 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1846 MVT::isInteger(LL.getValueType())) { 1847 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1848 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1849 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1850 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1851 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1852 AddToWorkList(ORNode.Val); 1853 return DAG.getSetCC(VT, ORNode, LR, Op1); 1854 } 1855 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1856 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1857 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1858 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1859 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1860 AddToWorkList(ANDNode.Val); 1861 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1862 } 1863 } 1864 // canonicalize equivalent to ll == rl 1865 if (LL == RR && LR == RL) { 1866 Op1 = ISD::getSetCCSwappedOperands(Op1); 1867 std::swap(RL, RR); 1868 } 1869 if (LL == RL && LR == RR) { 1870 bool isInteger = MVT::isInteger(LL.getValueType()); 1871 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1872 if (Result != ISD::SETCC_INVALID) 1873 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1874 } 1875 } 1876 1877 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1878 if (N0.getOpcode() == N1.getOpcode()) { 1879 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1880 if (Tmp.Val) return Tmp; 1881 } 1882 1883 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1884 if (N0.getOpcode() == ISD::AND && 1885 N1.getOpcode() == ISD::AND && 1886 N0.getOperand(1).getOpcode() == ISD::Constant && 1887 N1.getOperand(1).getOpcode() == ISD::Constant && 1888 // Don't increase # computations. 1889 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1890 // We can only do this xform if we know that bits from X that are set in C2 1891 // but not in C1 are already zero. Likewise for Y. 1892 const APInt &LHSMask = 1893 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1894 const APInt &RHSMask = 1895 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 1896 1897 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1898 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1899 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1900 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1901 } 1902 } 1903 1904 1905 // See if this is some rotate idiom. 1906 if (SDNode *Rot = MatchRotate(N0, N1)) 1907 return SDOperand(Rot, 0); 1908 1909 return SDOperand(); 1910} 1911 1912 1913/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1914static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1915 if (Op.getOpcode() == ISD::AND) { 1916 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1917 Mask = Op.getOperand(1); 1918 Op = Op.getOperand(0); 1919 } else { 1920 return false; 1921 } 1922 } 1923 1924 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1925 Shift = Op; 1926 return true; 1927 } 1928 return false; 1929} 1930 1931 1932// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1933// idioms for rotate, and if the target supports rotation instructions, generate 1934// a rot[lr]. 1935SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1936 // Must be a legal type. Expanded an promoted things won't work with rotates. 1937 MVT::ValueType VT = LHS.getValueType(); 1938 if (!TLI.isTypeLegal(VT)) return 0; 1939 1940 // The target must have at least one rotate flavor. 1941 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1942 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1943 if (!HasROTL && !HasROTR) return 0; 1944 1945 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1946 SDOperand LHSShift; // The shift. 1947 SDOperand LHSMask; // AND value if any. 1948 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1949 return 0; // Not part of a rotate. 1950 1951 SDOperand RHSShift; // The shift. 1952 SDOperand RHSMask; // AND value if any. 1953 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1954 return 0; // Not part of a rotate. 1955 1956 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1957 return 0; // Not shifting the same value. 1958 1959 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1960 return 0; // Shifts must disagree. 1961 1962 // Canonicalize shl to left side in a shl/srl pair. 1963 if (RHSShift.getOpcode() == ISD::SHL) { 1964 std::swap(LHS, RHS); 1965 std::swap(LHSShift, RHSShift); 1966 std::swap(LHSMask , RHSMask ); 1967 } 1968 1969 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1970 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1971 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1972 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1973 1974 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1975 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1976 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1977 RHSShiftAmt.getOpcode() == ISD::Constant) { 1978 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1979 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1980 if ((LShVal + RShVal) != OpSizeInBits) 1981 return 0; 1982 1983 SDOperand Rot; 1984 if (HasROTL) 1985 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1986 else 1987 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1988 1989 // If there is an AND of either shifted operand, apply it to the result. 1990 if (LHSMask.Val || RHSMask.Val) { 1991 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 1992 1993 if (LHSMask.Val) { 1994 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 1995 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 1996 } 1997 if (RHSMask.Val) { 1998 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 1999 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2000 } 2001 2002 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 2003 } 2004 2005 return Rot.Val; 2006 } 2007 2008 // If there is a mask here, and we have a variable shift, we can't be sure 2009 // that we're masking out the right stuff. 2010 if (LHSMask.Val || RHSMask.Val) 2011 return 0; 2012 2013 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2014 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2015 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2016 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2017 if (ConstantSDNode *SUBC = 2018 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2019 if (SUBC->getValue() == OpSizeInBits) { 2020 if (HasROTL) 2021 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2022 else 2023 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2024 } 2025 } 2026 } 2027 2028 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2029 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2030 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2031 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2032 if (ConstantSDNode *SUBC = 2033 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2034 if (SUBC->getValue() == OpSizeInBits) { 2035 if (HasROTL) 2036 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2037 else 2038 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2039 } 2040 } 2041 } 2042 2043 // Look for sign/zext/any-extended cases: 2044 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2045 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2046 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 2047 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2048 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2049 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 2050 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 2051 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 2052 if (RExtOp0.getOpcode() == ISD::SUB && 2053 RExtOp0.getOperand(1) == LExtOp0) { 2054 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2055 // (rotr x, y) 2056 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2057 // (rotl x, (sub 32, y)) 2058 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2059 if (SUBC->getValue() == OpSizeInBits) { 2060 if (HasROTL) 2061 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2062 else 2063 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2064 } 2065 } 2066 } else if (LExtOp0.getOpcode() == ISD::SUB && 2067 RExtOp0 == LExtOp0.getOperand(1)) { 2068 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2069 // (rotl x, y) 2070 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2071 // (rotr x, (sub 32, y)) 2072 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2073 if (SUBC->getValue() == OpSizeInBits) { 2074 if (HasROTL) 2075 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 2076 else 2077 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2078 } 2079 } 2080 } 2081 } 2082 2083 return 0; 2084} 2085 2086 2087SDOperand DAGCombiner::visitXOR(SDNode *N) { 2088 SDOperand N0 = N->getOperand(0); 2089 SDOperand N1 = N->getOperand(1); 2090 SDOperand LHS, RHS, CC; 2091 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2092 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2093 MVT::ValueType VT = N0.getValueType(); 2094 2095 // fold vector ops 2096 if (MVT::isVector(VT)) { 2097 SDOperand FoldedVOp = SimplifyVBinOp(N); 2098 if (FoldedVOp.Val) return FoldedVOp; 2099 } 2100 2101 // fold (xor x, undef) -> undef 2102 if (N0.getOpcode() == ISD::UNDEF) 2103 return N0; 2104 if (N1.getOpcode() == ISD::UNDEF) 2105 return N1; 2106 // fold (xor c1, c2) -> c1^c2 2107 if (N0C && N1C) 2108 return DAG.getNode(ISD::XOR, VT, N0, N1); 2109 // canonicalize constant to RHS 2110 if (N0C && !N1C) 2111 return DAG.getNode(ISD::XOR, VT, N1, N0); 2112 // fold (xor x, 0) -> x 2113 if (N1C && N1C->isNullValue()) 2114 return N0; 2115 // reassociate xor 2116 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 2117 if (RXOR.Val != 0) 2118 return RXOR; 2119 // fold !(x cc y) -> (x !cc y) 2120 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2121 bool isInt = MVT::isInteger(LHS.getValueType()); 2122 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2123 isInt); 2124 if (N0.getOpcode() == ISD::SETCC) 2125 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2126 if (N0.getOpcode() == ISD::SELECT_CC) 2127 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2128 assert(0 && "Unhandled SetCC Equivalent!"); 2129 abort(); 2130 } 2131 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2132 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2133 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2134 SDOperand V = N0.getOperand(0); 2135 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2136 DAG.getConstant(1, V.getValueType())); 2137 AddToWorkList(V.Val); 2138 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2139 } 2140 2141 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2142 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 2143 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2144 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2145 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2146 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2147 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2148 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2149 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2150 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2151 } 2152 } 2153 // fold !(x or y) -> (!x and !y) iff x or y are constants 2154 if (N1C && N1C->isAllOnesValue() && 2155 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2156 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2157 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2158 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2159 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2160 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2161 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2162 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2163 } 2164 } 2165 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2166 if (N1C && N0.getOpcode() == ISD::XOR) { 2167 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2168 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2169 if (N00C) 2170 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2171 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 2172 if (N01C) 2173 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2174 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 2175 } 2176 // fold (xor x, x) -> 0 2177 if (N0 == N1) { 2178 if (!MVT::isVector(VT)) { 2179 return DAG.getConstant(0, VT); 2180 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2181 // Produce a vector of zeros. 2182 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); 2183 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 2184 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2185 } 2186 } 2187 2188 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2189 if (N0.getOpcode() == N1.getOpcode()) { 2190 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2191 if (Tmp.Val) return Tmp; 2192 } 2193 2194 // Simplify the expression using non-local knowledge. 2195 if (!MVT::isVector(VT) && 2196 SimplifyDemandedBits(SDOperand(N, 0))) 2197 return SDOperand(N, 0); 2198 2199 return SDOperand(); 2200} 2201 2202/// visitShiftByConstant - Handle transforms common to the three shifts, when 2203/// the shift amount is a constant. 2204SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2205 SDNode *LHS = N->getOperand(0).Val; 2206 if (!LHS->hasOneUse()) return SDOperand(); 2207 2208 // We want to pull some binops through shifts, so that we have (and (shift)) 2209 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2210 // thing happens with address calculations, so it's important to canonicalize 2211 // it. 2212 bool HighBitSet = false; // Can we transform this if the high bit is set? 2213 2214 switch (LHS->getOpcode()) { 2215 default: return SDOperand(); 2216 case ISD::OR: 2217 case ISD::XOR: 2218 HighBitSet = false; // We can only transform sra if the high bit is clear. 2219 break; 2220 case ISD::AND: 2221 HighBitSet = true; // We can only transform sra if the high bit is set. 2222 break; 2223 case ISD::ADD: 2224 if (N->getOpcode() != ISD::SHL) 2225 return SDOperand(); // only shl(add) not sr[al](add). 2226 HighBitSet = false; // We can only transform sra if the high bit is clear. 2227 break; 2228 } 2229 2230 // We require the RHS of the binop to be a constant as well. 2231 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2232 if (!BinOpCst) return SDOperand(); 2233 2234 2235 // FIXME: disable this for unless the input to the binop is a shift by a 2236 // constant. If it is not a shift, it pessimizes some common cases like: 2237 // 2238 //void foo(int *X, int i) { X[i & 1235] = 1; } 2239 //int bar(int *X, int i) { return X[i & 255]; } 2240 SDNode *BinOpLHSVal = LHS->getOperand(0).Val; 2241 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2242 BinOpLHSVal->getOpcode() != ISD::SRA && 2243 BinOpLHSVal->getOpcode() != ISD::SRL) || 2244 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2245 return SDOperand(); 2246 2247 MVT::ValueType VT = N->getValueType(0); 2248 2249 // If this is a signed shift right, and the high bit is modified 2250 // by the logical operation, do not perform the transformation. 2251 // The highBitSet boolean indicates the value of the high bit of 2252 // the constant which would cause it to be modified for this 2253 // operation. 2254 if (N->getOpcode() == ISD::SRA) { 2255 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2256 if (BinOpRHSSignSet != HighBitSet) 2257 return SDOperand(); 2258 } 2259 2260 // Fold the constants, shifting the binop RHS by the shift amount. 2261 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2262 LHS->getOperand(1), N->getOperand(1)); 2263 2264 // Create the new shift. 2265 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2266 N->getOperand(1)); 2267 2268 // Create the new binop. 2269 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2270} 2271 2272 2273SDOperand DAGCombiner::visitSHL(SDNode *N) { 2274 SDOperand N0 = N->getOperand(0); 2275 SDOperand N1 = N->getOperand(1); 2276 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2277 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2278 MVT::ValueType VT = N0.getValueType(); 2279 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2280 2281 // fold (shl c1, c2) -> c1<<c2 2282 if (N0C && N1C) 2283 return DAG.getNode(ISD::SHL, VT, N0, N1); 2284 // fold (shl 0, x) -> 0 2285 if (N0C && N0C->isNullValue()) 2286 return N0; 2287 // fold (shl x, c >= size(x)) -> undef 2288 if (N1C && N1C->getValue() >= OpSizeInBits) 2289 return DAG.getNode(ISD::UNDEF, VT); 2290 // fold (shl x, 0) -> x 2291 if (N1C && N1C->isNullValue()) 2292 return N0; 2293 // if (shl x, c) is known to be zero, return 0 2294 if (DAG.MaskedValueIsZero(SDOperand(N, 0), 2295 APInt::getAllOnesValue(MVT::getSizeInBits(VT)))) 2296 return DAG.getConstant(0, VT); 2297 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2298 return SDOperand(N, 0); 2299 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2300 if (N1C && N0.getOpcode() == ISD::SHL && 2301 N0.getOperand(1).getOpcode() == ISD::Constant) { 2302 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2303 uint64_t c2 = N1C->getValue(); 2304 if (c1 + c2 > OpSizeInBits) 2305 return DAG.getConstant(0, VT); 2306 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2307 DAG.getConstant(c1 + c2, N1.getValueType())); 2308 } 2309 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2310 // (srl (and x, -1 << c1), c1-c2) 2311 if (N1C && N0.getOpcode() == ISD::SRL && 2312 N0.getOperand(1).getOpcode() == ISD::Constant) { 2313 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2314 uint64_t c2 = N1C->getValue(); 2315 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2316 DAG.getConstant(~0ULL << c1, VT)); 2317 if (c2 > c1) 2318 return DAG.getNode(ISD::SHL, VT, Mask, 2319 DAG.getConstant(c2-c1, N1.getValueType())); 2320 else 2321 return DAG.getNode(ISD::SRL, VT, Mask, 2322 DAG.getConstant(c1-c2, N1.getValueType())); 2323 } 2324 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2325 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2326 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2327 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2328 2329 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2330} 2331 2332SDOperand DAGCombiner::visitSRA(SDNode *N) { 2333 SDOperand N0 = N->getOperand(0); 2334 SDOperand N1 = N->getOperand(1); 2335 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2336 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2337 MVT::ValueType VT = N0.getValueType(); 2338 2339 // fold (sra c1, c2) -> c1>>c2 2340 if (N0C && N1C) 2341 return DAG.getNode(ISD::SRA, VT, N0, N1); 2342 // fold (sra 0, x) -> 0 2343 if (N0C && N0C->isNullValue()) 2344 return N0; 2345 // fold (sra -1, x) -> -1 2346 if (N0C && N0C->isAllOnesValue()) 2347 return N0; 2348 // fold (sra x, c >= size(x)) -> undef 2349 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 2350 return DAG.getNode(ISD::UNDEF, VT); 2351 // fold (sra x, 0) -> x 2352 if (N1C && N1C->isNullValue()) 2353 return N0; 2354 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2355 // sext_inreg. 2356 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2357 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 2358 MVT::ValueType EVT; 2359 switch (LowBits) { 2360 default: EVT = MVT::Other; break; 2361 case 1: EVT = MVT::i1; break; 2362 case 8: EVT = MVT::i8; break; 2363 case 16: EVT = MVT::i16; break; 2364 case 32: EVT = MVT::i32; break; 2365 } 2366 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 2367 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2368 DAG.getValueType(EVT)); 2369 } 2370 2371 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2372 if (N1C && N0.getOpcode() == ISD::SRA) { 2373 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2374 unsigned Sum = N1C->getValue() + C1->getValue(); 2375 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 2376 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2377 DAG.getConstant(Sum, N1C->getValueType(0))); 2378 } 2379 } 2380 2381 // Simplify, based on bits shifted out of the LHS. 2382 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2383 return SDOperand(N, 0); 2384 2385 2386 // If the sign bit is known to be zero, switch this to a SRL. 2387 if (DAG.SignBitIsZero(N0)) 2388 return DAG.getNode(ISD::SRL, VT, N0, N1); 2389 2390 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2391} 2392 2393SDOperand DAGCombiner::visitSRL(SDNode *N) { 2394 SDOperand N0 = N->getOperand(0); 2395 SDOperand N1 = N->getOperand(1); 2396 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2397 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2398 MVT::ValueType VT = N0.getValueType(); 2399 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2400 2401 // fold (srl c1, c2) -> c1 >>u c2 2402 if (N0C && N1C) 2403 return DAG.getNode(ISD::SRL, VT, N0, N1); 2404 // fold (srl 0, x) -> 0 2405 if (N0C && N0C->isNullValue()) 2406 return N0; 2407 // fold (srl x, c >= size(x)) -> undef 2408 if (N1C && N1C->getValue() >= OpSizeInBits) 2409 return DAG.getNode(ISD::UNDEF, VT); 2410 // fold (srl x, 0) -> x 2411 if (N1C && N1C->isNullValue()) 2412 return N0; 2413 // if (srl x, c) is known to be zero, return 0 2414 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), 2415 APInt::getAllOnesValue(OpSizeInBits))) 2416 return DAG.getConstant(0, VT); 2417 2418 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2419 if (N1C && N0.getOpcode() == ISD::SRL && 2420 N0.getOperand(1).getOpcode() == ISD::Constant) { 2421 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2422 uint64_t c2 = N1C->getValue(); 2423 if (c1 + c2 > OpSizeInBits) 2424 return DAG.getConstant(0, VT); 2425 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2426 DAG.getConstant(c1 + c2, N1.getValueType())); 2427 } 2428 2429 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2430 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2431 // Shifting in all undef bits? 2432 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 2433 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 2434 return DAG.getNode(ISD::UNDEF, VT); 2435 2436 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2437 AddToWorkList(SmallShift.Val); 2438 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2439 } 2440 2441 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2442 // bit, which is unmodified by sra. 2443 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 2444 if (N0.getOpcode() == ISD::SRA) 2445 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2446 } 2447 2448 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2449 if (N1C && N0.getOpcode() == ISD::CTLZ && 2450 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 2451 APInt KnownZero, KnownOne; 2452 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); 2453 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2454 2455 // If any of the input bits are KnownOne, then the input couldn't be all 2456 // zeros, thus the result of the srl will always be zero. 2457 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2458 2459 // If all of the bits input the to ctlz node are known to be zero, then 2460 // the result of the ctlz is "32" and the result of the shift is one. 2461 APInt UnknownBits = ~KnownZero & Mask; 2462 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2463 2464 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2465 if ((UnknownBits & (UnknownBits-1)) == 0) { 2466 // Okay, we know that only that the single bit specified by UnknownBits 2467 // could be set on input to the CTLZ node. If this bit is set, the SRL 2468 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2469 // to an SRL,XOR pair, which is likely to simplify more. 2470 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2471 SDOperand Op = N0.getOperand(0); 2472 if (ShAmt) { 2473 Op = DAG.getNode(ISD::SRL, VT, Op, 2474 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2475 AddToWorkList(Op.Val); 2476 } 2477 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2478 } 2479 } 2480 2481 // fold operands of srl based on knowledge that the low bits are not 2482 // demanded. 2483 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2484 return SDOperand(N, 0); 2485 2486 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2487} 2488 2489SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2490 SDOperand N0 = N->getOperand(0); 2491 MVT::ValueType VT = N->getValueType(0); 2492 2493 // fold (ctlz c1) -> c2 2494 if (isa<ConstantSDNode>(N0)) 2495 return DAG.getNode(ISD::CTLZ, VT, N0); 2496 return SDOperand(); 2497} 2498 2499SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2500 SDOperand N0 = N->getOperand(0); 2501 MVT::ValueType VT = N->getValueType(0); 2502 2503 // fold (cttz c1) -> c2 2504 if (isa<ConstantSDNode>(N0)) 2505 return DAG.getNode(ISD::CTTZ, VT, N0); 2506 return SDOperand(); 2507} 2508 2509SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2510 SDOperand N0 = N->getOperand(0); 2511 MVT::ValueType VT = N->getValueType(0); 2512 2513 // fold (ctpop c1) -> c2 2514 if (isa<ConstantSDNode>(N0)) 2515 return DAG.getNode(ISD::CTPOP, VT, N0); 2516 return SDOperand(); 2517} 2518 2519SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2520 SDOperand N0 = N->getOperand(0); 2521 SDOperand N1 = N->getOperand(1); 2522 SDOperand N2 = N->getOperand(2); 2523 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2524 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2525 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2526 MVT::ValueType VT = N->getValueType(0); 2527 MVT::ValueType VT0 = N0.getValueType(); 2528 2529 // fold select C, X, X -> X 2530 if (N1 == N2) 2531 return N1; 2532 // fold select true, X, Y -> X 2533 if (N0C && !N0C->isNullValue()) 2534 return N1; 2535 // fold select false, X, Y -> Y 2536 if (N0C && N0C->isNullValue()) 2537 return N2; 2538 // fold select C, 1, X -> C | X 2539 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 2540 return DAG.getNode(ISD::OR, VT, N0, N2); 2541 // fold select C, 0, 1 -> ~C 2542 if (MVT::isInteger(VT) && MVT::isInteger(VT0) && 2543 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) { 2544 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2545 if (VT == VT0) 2546 return XORNode; 2547 AddToWorkList(XORNode.Val); 2548 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0)) 2549 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2550 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2551 } 2552 // fold select C, 0, X -> ~C & X 2553 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2554 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2555 AddToWorkList(XORNode.Val); 2556 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2557 } 2558 // fold select C, X, 1 -> ~C | X 2559 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getValue() == 1) { 2560 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2561 AddToWorkList(XORNode.Val); 2562 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2563 } 2564 // fold select C, X, 0 -> C & X 2565 // FIXME: this should check for C type == X type, not i1? 2566 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2567 return DAG.getNode(ISD::AND, VT, N0, N1); 2568 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2569 if (MVT::i1 == VT && N0 == N1) 2570 return DAG.getNode(ISD::OR, VT, N0, N2); 2571 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2572 if (MVT::i1 == VT && N0 == N2) 2573 return DAG.getNode(ISD::AND, VT, N0, N1); 2574 2575 // If we can fold this based on the true/false value, do so. 2576 if (SimplifySelectOps(N, N1, N2)) 2577 return SDOperand(N, 0); // Don't revisit N. 2578 2579 // fold selects based on a setcc into other things, such as min/max/abs 2580 if (N0.getOpcode() == ISD::SETCC) { 2581 // FIXME: 2582 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2583 // having to say they don't support SELECT_CC on every type the DAG knows 2584 // about, since there is no way to mark an opcode illegal at all value types 2585 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2586 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2587 N1, N2, N0.getOperand(2)); 2588 else 2589 return SimplifySelect(N0, N1, N2); 2590 } 2591 return SDOperand(); 2592} 2593 2594SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2595 SDOperand N0 = N->getOperand(0); 2596 SDOperand N1 = N->getOperand(1); 2597 SDOperand N2 = N->getOperand(2); 2598 SDOperand N3 = N->getOperand(3); 2599 SDOperand N4 = N->getOperand(4); 2600 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2601 2602 // fold select_cc lhs, rhs, x, x, cc -> x 2603 if (N2 == N3) 2604 return N2; 2605 2606 // Determine if the condition we're dealing with is constant 2607 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2608 if (SCC.Val) AddToWorkList(SCC.Val); 2609 2610 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2611 if (SCCC->getValue()) 2612 return N2; // cond always true -> true val 2613 else 2614 return N3; // cond always false -> false val 2615 } 2616 2617 // Fold to a simpler select_cc 2618 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2619 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2620 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2621 SCC.getOperand(2)); 2622 2623 // If we can fold this based on the true/false value, do so. 2624 if (SimplifySelectOps(N, N2, N3)) 2625 return SDOperand(N, 0); // Don't revisit N. 2626 2627 // fold select_cc into other things, such as min/max/abs 2628 return SimplifySelectCC(N0, N1, N2, N3, CC); 2629} 2630 2631SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2632 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2633 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2634} 2635 2636// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2637// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2638// transformation. Returns true if extension are possible and the above 2639// mentioned transformation is profitable. 2640static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0, 2641 unsigned ExtOpc, 2642 SmallVector<SDNode*, 4> &ExtendNodes, 2643 TargetLowering &TLI) { 2644 bool HasCopyToRegUses = false; 2645 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2646 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end(); 2647 UI != UE; ++UI) { 2648 SDNode *User = *UI; 2649 if (User == N) 2650 continue; 2651 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2652 if (User->getOpcode() == ISD::SETCC) { 2653 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2654 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2655 // Sign bits will be lost after a zext. 2656 return false; 2657 bool Add = false; 2658 for (unsigned i = 0; i != 2; ++i) { 2659 SDOperand UseOp = User->getOperand(i); 2660 if (UseOp == N0) 2661 continue; 2662 if (!isa<ConstantSDNode>(UseOp)) 2663 return false; 2664 Add = true; 2665 } 2666 if (Add) 2667 ExtendNodes.push_back(User); 2668 } else { 2669 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2670 SDOperand UseOp = User->getOperand(i); 2671 if (UseOp == N0) { 2672 // If truncate from extended type to original load type is free 2673 // on this target, then it's ok to extend a CopyToReg. 2674 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2675 HasCopyToRegUses = true; 2676 else 2677 return false; 2678 } 2679 } 2680 } 2681 } 2682 2683 if (HasCopyToRegUses) { 2684 bool BothLiveOut = false; 2685 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2686 UI != UE; ++UI) { 2687 SDNode *User = *UI; 2688 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2689 SDOperand UseOp = User->getOperand(i); 2690 if (UseOp.Val == N && UseOp.ResNo == 0) { 2691 BothLiveOut = true; 2692 break; 2693 } 2694 } 2695 } 2696 if (BothLiveOut) 2697 // Both unextended and extended values are live out. There had better be 2698 // good a reason for the transformation. 2699 return ExtendNodes.size(); 2700 } 2701 return true; 2702} 2703 2704SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2705 SDOperand N0 = N->getOperand(0); 2706 MVT::ValueType VT = N->getValueType(0); 2707 2708 // fold (sext c1) -> c1 2709 if (isa<ConstantSDNode>(N0)) 2710 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2711 2712 // fold (sext (sext x)) -> (sext x) 2713 // fold (sext (aext x)) -> (sext x) 2714 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2715 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2716 2717 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2718 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2719 if (N0.getOpcode() == ISD::TRUNCATE) { 2720 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2721 if (NarrowLoad.Val) { 2722 if (NarrowLoad.Val != N0.Val) 2723 CombineTo(N0.Val, NarrowLoad); 2724 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2725 } 2726 } 2727 2728 // See if the value being truncated is already sign extended. If so, just 2729 // eliminate the trunc/sext pair. 2730 if (N0.getOpcode() == ISD::TRUNCATE) { 2731 SDOperand Op = N0.getOperand(0); 2732 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2733 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2734 unsigned DestBits = MVT::getSizeInBits(VT); 2735 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2736 2737 if (OpBits == DestBits) { 2738 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2739 // bits, it is already ready. 2740 if (NumSignBits > DestBits-MidBits) 2741 return Op; 2742 } else if (OpBits < DestBits) { 2743 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2744 // bits, just sext from i32. 2745 if (NumSignBits > OpBits-MidBits) 2746 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2747 } else { 2748 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2749 // bits, just truncate to i32. 2750 if (NumSignBits > OpBits-MidBits) 2751 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2752 } 2753 2754 // fold (sext (truncate x)) -> (sextinreg x). 2755 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2756 N0.getValueType())) { 2757 if (Op.getValueType() < VT) 2758 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2759 else if (Op.getValueType() > VT) 2760 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2761 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2762 DAG.getValueType(N0.getValueType())); 2763 } 2764 } 2765 2766 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2767 if (ISD::isNON_EXTLoad(N0.Val) && 2768 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2769 bool DoXform = true; 2770 SmallVector<SDNode*, 4> SetCCs; 2771 if (!N0.hasOneUse()) 2772 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2773 if (DoXform) { 2774 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2775 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2776 LN0->getBasePtr(), LN0->getSrcValue(), 2777 LN0->getSrcValueOffset(), 2778 N0.getValueType(), 2779 LN0->isVolatile(), 2780 LN0->getAlignment()); 2781 CombineTo(N, ExtLoad); 2782 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2783 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2784 // Extend SetCC uses if necessary. 2785 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2786 SDNode *SetCC = SetCCs[i]; 2787 SmallVector<SDOperand, 4> Ops; 2788 for (unsigned j = 0; j != 2; ++j) { 2789 SDOperand SOp = SetCC->getOperand(j); 2790 if (SOp == Trunc) 2791 Ops.push_back(ExtLoad); 2792 else 2793 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2794 } 2795 Ops.push_back(SetCC->getOperand(2)); 2796 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2797 &Ops[0], Ops.size())); 2798 } 2799 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2800 } 2801 } 2802 2803 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2804 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2805 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2806 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2807 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2808 MVT::ValueType EVT = LN0->getMemoryVT(); 2809 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2810 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2811 LN0->getBasePtr(), LN0->getSrcValue(), 2812 LN0->getSrcValueOffset(), EVT, 2813 LN0->isVolatile(), 2814 LN0->getAlignment()); 2815 CombineTo(N, ExtLoad); 2816 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2817 ExtLoad.getValue(1)); 2818 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2819 } 2820 } 2821 2822 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2823 if (N0.getOpcode() == ISD::SETCC) { 2824 SDOperand SCC = 2825 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2826 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2827 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2828 if (SCC.Val) return SCC; 2829 } 2830 2831 return SDOperand(); 2832} 2833 2834SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2835 SDOperand N0 = N->getOperand(0); 2836 MVT::ValueType VT = N->getValueType(0); 2837 2838 // fold (zext c1) -> c1 2839 if (isa<ConstantSDNode>(N0)) 2840 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2841 // fold (zext (zext x)) -> (zext x) 2842 // fold (zext (aext x)) -> (zext x) 2843 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2844 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2845 2846 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2847 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2848 if (N0.getOpcode() == ISD::TRUNCATE) { 2849 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2850 if (NarrowLoad.Val) { 2851 if (NarrowLoad.Val != N0.Val) 2852 CombineTo(N0.Val, NarrowLoad); 2853 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2854 } 2855 } 2856 2857 // fold (zext (truncate x)) -> (and x, mask) 2858 if (N0.getOpcode() == ISD::TRUNCATE && 2859 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2860 SDOperand Op = N0.getOperand(0); 2861 if (Op.getValueType() < VT) { 2862 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2863 } else if (Op.getValueType() > VT) { 2864 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2865 } 2866 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2867 } 2868 2869 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2870 if (N0.getOpcode() == ISD::AND && 2871 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2872 N0.getOperand(1).getOpcode() == ISD::Constant) { 2873 SDOperand X = N0.getOperand(0).getOperand(0); 2874 if (X.getValueType() < VT) { 2875 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2876 } else if (X.getValueType() > VT) { 2877 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2878 } 2879 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2880 Mask.zext(MVT::getSizeInBits(VT)); 2881 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2882 } 2883 2884 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2885 if (ISD::isNON_EXTLoad(N0.Val) && 2886 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2887 bool DoXform = true; 2888 SmallVector<SDNode*, 4> SetCCs; 2889 if (!N0.hasOneUse()) 2890 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 2891 if (DoXform) { 2892 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2893 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2894 LN0->getBasePtr(), LN0->getSrcValue(), 2895 LN0->getSrcValueOffset(), 2896 N0.getValueType(), 2897 LN0->isVolatile(), 2898 LN0->getAlignment()); 2899 CombineTo(N, ExtLoad); 2900 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2901 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2902 // Extend SetCC uses if necessary. 2903 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2904 SDNode *SetCC = SetCCs[i]; 2905 SmallVector<SDOperand, 4> Ops; 2906 for (unsigned j = 0; j != 2; ++j) { 2907 SDOperand SOp = SetCC->getOperand(j); 2908 if (SOp == Trunc) 2909 Ops.push_back(ExtLoad); 2910 else 2911 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 2912 } 2913 Ops.push_back(SetCC->getOperand(2)); 2914 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2915 &Ops[0], Ops.size())); 2916 } 2917 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2918 } 2919 } 2920 2921 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2922 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2923 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2924 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2925 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2926 MVT::ValueType EVT = LN0->getMemoryVT(); 2927 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2928 LN0->getBasePtr(), LN0->getSrcValue(), 2929 LN0->getSrcValueOffset(), EVT, 2930 LN0->isVolatile(), 2931 LN0->getAlignment()); 2932 CombineTo(N, ExtLoad); 2933 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2934 ExtLoad.getValue(1)); 2935 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2936 } 2937 2938 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2939 if (N0.getOpcode() == ISD::SETCC) { 2940 SDOperand SCC = 2941 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2942 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2943 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2944 if (SCC.Val) return SCC; 2945 } 2946 2947 return SDOperand(); 2948} 2949 2950SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2951 SDOperand N0 = N->getOperand(0); 2952 MVT::ValueType VT = N->getValueType(0); 2953 2954 // fold (aext c1) -> c1 2955 if (isa<ConstantSDNode>(N0)) 2956 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2957 // fold (aext (aext x)) -> (aext x) 2958 // fold (aext (zext x)) -> (zext x) 2959 // fold (aext (sext x)) -> (sext x) 2960 if (N0.getOpcode() == ISD::ANY_EXTEND || 2961 N0.getOpcode() == ISD::ZERO_EXTEND || 2962 N0.getOpcode() == ISD::SIGN_EXTEND) 2963 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2964 2965 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2966 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 2967 if (N0.getOpcode() == ISD::TRUNCATE) { 2968 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2969 if (NarrowLoad.Val) { 2970 if (NarrowLoad.Val != N0.Val) 2971 CombineTo(N0.Val, NarrowLoad); 2972 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 2973 } 2974 } 2975 2976 // fold (aext (truncate x)) 2977 if (N0.getOpcode() == ISD::TRUNCATE) { 2978 SDOperand TruncOp = N0.getOperand(0); 2979 if (TruncOp.getValueType() == VT) 2980 return TruncOp; // x iff x size == zext size. 2981 if (TruncOp.getValueType() > VT) 2982 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2983 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2984 } 2985 2986 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2987 if (N0.getOpcode() == ISD::AND && 2988 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2989 N0.getOperand(1).getOpcode() == ISD::Constant) { 2990 SDOperand X = N0.getOperand(0).getOperand(0); 2991 if (X.getValueType() < VT) { 2992 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2993 } else if (X.getValueType() > VT) { 2994 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2995 } 2996 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2997 Mask.zext(MVT::getSizeInBits(VT)); 2998 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2999 } 3000 3001 // fold (aext (load x)) -> (aext (truncate (extload x))) 3002 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3003 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3004 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3005 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3006 LN0->getBasePtr(), LN0->getSrcValue(), 3007 LN0->getSrcValueOffset(), 3008 N0.getValueType(), 3009 LN0->isVolatile(), 3010 LN0->getAlignment()); 3011 CombineTo(N, ExtLoad); 3012 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3013 ExtLoad.getValue(1)); 3014 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3015 } 3016 3017 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3018 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3019 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3020 if (N0.getOpcode() == ISD::LOAD && 3021 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3022 N0.hasOneUse()) { 3023 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3024 MVT::ValueType EVT = LN0->getMemoryVT(); 3025 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3026 LN0->getChain(), LN0->getBasePtr(), 3027 LN0->getSrcValue(), 3028 LN0->getSrcValueOffset(), EVT, 3029 LN0->isVolatile(), 3030 LN0->getAlignment()); 3031 CombineTo(N, ExtLoad); 3032 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3033 ExtLoad.getValue(1)); 3034 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3035 } 3036 3037 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3038 if (N0.getOpcode() == ISD::SETCC) { 3039 SDOperand SCC = 3040 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3041 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3042 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3043 if (SCC.Val) 3044 return SCC; 3045 } 3046 3047 return SDOperand(); 3048} 3049 3050/// GetDemandedBits - See if the specified operand can be simplified with the 3051/// knowledge that only the bits specified by Mask are used. If so, return the 3052/// simpler operand, otherwise return a null SDOperand. 3053SDOperand DAGCombiner::GetDemandedBits(SDOperand V, const APInt &Mask) { 3054 switch (V.getOpcode()) { 3055 default: break; 3056 case ISD::OR: 3057 case ISD::XOR: 3058 // If the LHS or RHS don't contribute bits to the or, drop them. 3059 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3060 return V.getOperand(1); 3061 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3062 return V.getOperand(0); 3063 break; 3064 case ISD::SRL: 3065 // Only look at single-use SRLs. 3066 if (!V.Val->hasOneUse()) 3067 break; 3068 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3069 // See if we can recursively simplify the LHS. 3070 unsigned Amt = RHSC->getValue(); 3071 APInt NewMask = Mask << Amt; 3072 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3073 if (SimplifyLHS.Val) { 3074 return DAG.getNode(ISD::SRL, V.getValueType(), 3075 SimplifyLHS, V.getOperand(1)); 3076 } 3077 } 3078 } 3079 return SDOperand(); 3080} 3081 3082/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3083/// bits and then truncated to a narrower type and where N is a multiple 3084/// of number of bits of the narrower type, transform it to a narrower load 3085/// from address + N / num of bits of new type. If the result is to be 3086/// extended, also fold the extension to form a extending load. 3087SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 3088 unsigned Opc = N->getOpcode(); 3089 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3090 SDOperand N0 = N->getOperand(0); 3091 MVT::ValueType VT = N->getValueType(0); 3092 MVT::ValueType EVT = N->getValueType(0); 3093 3094 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3095 // extended to VT. 3096 if (Opc == ISD::SIGN_EXTEND_INREG) { 3097 ExtType = ISD::SEXTLOAD; 3098 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3099 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 3100 return SDOperand(); 3101 } 3102 3103 unsigned EVTBits = MVT::getSizeInBits(EVT); 3104 unsigned ShAmt = 0; 3105 bool CombineSRL = false; 3106 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3107 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3108 ShAmt = N01->getValue(); 3109 // Is the shift amount a multiple of size of VT? 3110 if ((ShAmt & (EVTBits-1)) == 0) { 3111 N0 = N0.getOperand(0); 3112 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 3113 return SDOperand(); 3114 CombineSRL = true; 3115 } 3116 } 3117 } 3118 3119 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3120 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 3121 // zero extended form: by shrinking the load, we lose track of the fact 3122 // that it is already zero extended. 3123 // FIXME: This should be reevaluated. 3124 VT != MVT::i1) { 3125 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 3126 "Cannot truncate to larger type!"); 3127 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3128 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 3129 // For big endian targets, we need to adjust the offset to the pointer to 3130 // load the correct bytes. 3131 if (TLI.isBigEndian()) { 3132 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType()); 3133 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT); 3134 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3135 } 3136 uint64_t PtrOff = ShAmt / 8; 3137 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3138 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3139 DAG.getConstant(PtrOff, PtrType)); 3140 AddToWorkList(NewPtr.Val); 3141 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 3142 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3143 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3144 LN0->isVolatile(), NewAlign) 3145 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3146 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 3147 LN0->isVolatile(), NewAlign); 3148 AddToWorkList(N); 3149 if (CombineSRL) { 3150 WorkListRemover DeadNodes(*this); 3151 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3152 &DeadNodes); 3153 CombineTo(N->getOperand(0).Val, Load); 3154 } else 3155 CombineTo(N0.Val, Load, Load.getValue(1)); 3156 if (ShAmt) { 3157 if (Opc == ISD::SIGN_EXTEND_INREG) 3158 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3159 else 3160 return DAG.getNode(Opc, VT, Load); 3161 } 3162 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3163 } 3164 3165 return SDOperand(); 3166} 3167 3168 3169SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3170 SDOperand N0 = N->getOperand(0); 3171 SDOperand N1 = N->getOperand(1); 3172 MVT::ValueType VT = N->getValueType(0); 3173 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 3174 unsigned VTBits = MVT::getSizeInBits(VT); 3175 unsigned EVTBits = MVT::getSizeInBits(EVT); 3176 3177 // fold (sext_in_reg c1) -> c1 3178 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3179 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3180 3181 // If the input is already sign extended, just drop the extension. 3182 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 3183 return N0; 3184 3185 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3186 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3187 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 3188 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3189 } 3190 3191 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3192 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3193 return DAG.getZeroExtendInReg(N0, EVT); 3194 3195 // fold operands of sext_in_reg based on knowledge that the top bits are not 3196 // demanded. 3197 if (SimplifyDemandedBits(SDOperand(N, 0))) 3198 return SDOperand(N, 0); 3199 3200 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3201 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3202 SDOperand NarrowLoad = ReduceLoadWidth(N); 3203 if (NarrowLoad.Val) 3204 return NarrowLoad; 3205 3206 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3207 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3208 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3209 if (N0.getOpcode() == ISD::SRL) { 3210 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3211 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 3212 // We can turn this into an SRA iff the input to the SRL is already sign 3213 // extended enough. 3214 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3215 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 3216 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3217 } 3218 } 3219 3220 // fold (sext_inreg (extload x)) -> (sextload x) 3221 if (ISD::isEXTLoad(N0.Val) && 3222 ISD::isUNINDEXEDLoad(N0.Val) && 3223 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3224 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3225 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3226 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3227 LN0->getBasePtr(), LN0->getSrcValue(), 3228 LN0->getSrcValueOffset(), EVT, 3229 LN0->isVolatile(), 3230 LN0->getAlignment()); 3231 CombineTo(N, ExtLoad); 3232 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3233 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3234 } 3235 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3236 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3237 N0.hasOneUse() && 3238 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3239 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3240 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3241 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3242 LN0->getBasePtr(), LN0->getSrcValue(), 3243 LN0->getSrcValueOffset(), EVT, 3244 LN0->isVolatile(), 3245 LN0->getAlignment()); 3246 CombineTo(N, ExtLoad); 3247 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3248 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3249 } 3250 return SDOperand(); 3251} 3252 3253SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 3254 SDOperand N0 = N->getOperand(0); 3255 MVT::ValueType VT = N->getValueType(0); 3256 3257 // noop truncate 3258 if (N0.getValueType() == N->getValueType(0)) 3259 return N0; 3260 // fold (truncate c1) -> c1 3261 if (isa<ConstantSDNode>(N0)) 3262 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3263 // fold (truncate (truncate x)) -> (truncate x) 3264 if (N0.getOpcode() == ISD::TRUNCATE) 3265 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3266 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3267 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3268 N0.getOpcode() == ISD::ANY_EXTEND) { 3269 if (N0.getOperand(0).getValueType() < VT) 3270 // if the source is smaller than the dest, we still need an extend 3271 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3272 else if (N0.getOperand(0).getValueType() > VT) 3273 // if the source is larger than the dest, than we just need the truncate 3274 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3275 else 3276 // if the source and dest are the same type, we can drop both the extend 3277 // and the truncate 3278 return N0.getOperand(0); 3279 } 3280 3281 // See if we can simplify the input to this truncate through knowledge that 3282 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3283 // -> trunc y 3284 SDOperand Shorter = 3285 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3286 MVT::getSizeInBits(VT))); 3287 if (Shorter.Val) 3288 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3289 3290 // fold (truncate (load x)) -> (smaller load x) 3291 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3292 return ReduceLoadWidth(N); 3293} 3294 3295SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3296 SDOperand N0 = N->getOperand(0); 3297 MVT::ValueType VT = N->getValueType(0); 3298 3299 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3300 // Only do this before legalize, since afterward the target may be depending 3301 // on the bitconvert. 3302 // First check to see if this is all constant. 3303 if (!AfterLegalize && 3304 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 3305 MVT::isVector(VT)) { 3306 bool isSimple = true; 3307 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3308 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3309 N0.getOperand(i).getOpcode() != ISD::Constant && 3310 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3311 isSimple = false; 3312 break; 3313 } 3314 3315 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); 3316 assert(!MVT::isVector(DestEltVT) && 3317 "Element type of vector ValueType must not be vector!"); 3318 if (isSimple) { 3319 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 3320 } 3321 } 3322 3323 // If the input is a constant, let getNode() fold it. 3324 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3325 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3326 if (Res.Val != N) return Res; 3327 } 3328 3329 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3330 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3331 3332 // fold (conv (load x)) -> (load (conv*)x) 3333 // If the resultant load doesn't need a higher alignment than the original! 3334 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() && 3335 TLI.isOperationLegal(ISD::LOAD, VT)) { 3336 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3337 unsigned Align = TLI.getTargetMachine().getTargetData()-> 3338 getABITypeAlignment(MVT::getTypeForValueType(VT)); 3339 unsigned OrigAlign = LN0->getAlignment(); 3340 if (Align <= OrigAlign) { 3341 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3342 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3343 LN0->isVolatile(), Align); 3344 AddToWorkList(N); 3345 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3346 Load.getValue(1)); 3347 return Load; 3348 } 3349 } 3350 3351 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3352 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3353 // This often reduces constant pool loads. 3354 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3355 N0.Val->hasOneUse() && MVT::isInteger(VT) && !MVT::isVector(VT)) { 3356 SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3357 AddToWorkList(NewConv.Val); 3358 3359 APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT)); 3360 if (N0.getOpcode() == ISD::FNEG) 3361 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3362 assert(N0.getOpcode() == ISD::FABS); 3363 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3364 } 3365 3366 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3367 // Note that we don't handle copysign(x,cst) because this can always be folded 3368 // to an fneg or fabs. 3369 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() && 3370 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3371 MVT::isInteger(VT) && !MVT::isVector(VT)) { 3372 unsigned OrigXWidth = MVT::getSizeInBits(N0.getOperand(1).getValueType()); 3373 SDOperand X = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(OrigXWidth), 3374 N0.getOperand(1)); 3375 AddToWorkList(X.Val); 3376 3377 // If X has a different width than the result/lhs, sext it or truncate it. 3378 unsigned VTWidth = MVT::getSizeInBits(VT); 3379 if (OrigXWidth < VTWidth) { 3380 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3381 AddToWorkList(X.Val); 3382 } else if (OrigXWidth > VTWidth) { 3383 // To get the sign bit in the right place, we have to shift it right 3384 // before truncating. 3385 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3386 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3387 AddToWorkList(X.Val); 3388 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3389 AddToWorkList(X.Val); 3390 } 3391 3392 APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT)); 3393 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3394 AddToWorkList(X.Val); 3395 3396 SDOperand Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3397 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3398 AddToWorkList(Cst.Val); 3399 3400 return DAG.getNode(ISD::OR, VT, X, Cst); 3401 } 3402 3403 return SDOperand(); 3404} 3405 3406/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3407/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3408/// destination element value type. 3409SDOperand DAGCombiner:: 3410ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 3411 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 3412 3413 // If this is already the right type, we're done. 3414 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 3415 3416 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 3417 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 3418 3419 // If this is a conversion of N elements of one type to N elements of another 3420 // type, convert each element. This handles FP<->INT cases. 3421 if (SrcBitSize == DstBitSize) { 3422 SmallVector<SDOperand, 8> Ops; 3423 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3424 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3425 AddToWorkList(Ops.back().Val); 3426 } 3427 MVT::ValueType VT = 3428 MVT::getVectorType(DstEltVT, 3429 MVT::getVectorNumElements(BV->getValueType(0))); 3430 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3431 } 3432 3433 // Otherwise, we're growing or shrinking the elements. To avoid having to 3434 // handle annoying details of growing/shrinking FP values, we convert them to 3435 // int first. 3436 if (MVT::isFloatingPoint(SrcEltVT)) { 3437 // Convert the input float vector to a int vector where the elements are the 3438 // same sizes. 3439 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3440 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3441 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 3442 SrcEltVT = IntVT; 3443 } 3444 3445 // Now we know the input is an integer vector. If the output is a FP type, 3446 // convert to integer first, then to FP of the right size. 3447 if (MVT::isFloatingPoint(DstEltVT)) { 3448 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3449 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3450 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 3451 3452 // Next, convert to FP elements of the same size. 3453 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3454 } 3455 3456 // Okay, we know the src/dst types are both integers of differing types. 3457 // Handling growing first. 3458 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 3459 if (SrcBitSize < DstBitSize) { 3460 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3461 3462 SmallVector<SDOperand, 8> Ops; 3463 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3464 i += NumInputsPerOutput) { 3465 bool isLE = TLI.isLittleEndian(); 3466 APInt NewBits = APInt(DstBitSize, 0); 3467 bool EltIsUndef = true; 3468 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3469 // Shift the previously computed bits over. 3470 NewBits <<= SrcBitSize; 3471 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3472 if (Op.getOpcode() == ISD::UNDEF) continue; 3473 EltIsUndef = false; 3474 3475 NewBits |= 3476 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3477 } 3478 3479 if (EltIsUndef) 3480 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3481 else 3482 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3483 } 3484 3485 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); 3486 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3487 } 3488 3489 // Finally, this must be the case where we are shrinking elements: each input 3490 // turns into multiple outputs. 3491 bool isS2V = ISD::isScalarToVector(BV); 3492 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3493 MVT::ValueType VT = MVT::getVectorType(DstEltVT, 3494 NumOutputsPerInput * BV->getNumOperands()); 3495 SmallVector<SDOperand, 8> Ops; 3496 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3497 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3498 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3499 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3500 continue; 3501 } 3502 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3503 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3504 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3505 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3506 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3507 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3508 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3509 OpVal = OpVal.lshr(DstBitSize); 3510 } 3511 3512 // For big endian targets, swap the order of the pieces of each element. 3513 if (TLI.isBigEndian()) 3514 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3515 } 3516 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3517} 3518 3519 3520 3521SDOperand DAGCombiner::visitFADD(SDNode *N) { 3522 SDOperand N0 = N->getOperand(0); 3523 SDOperand N1 = N->getOperand(1); 3524 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3525 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3526 MVT::ValueType VT = N->getValueType(0); 3527 3528 // fold vector ops 3529 if (MVT::isVector(VT)) { 3530 SDOperand FoldedVOp = SimplifyVBinOp(N); 3531 if (FoldedVOp.Val) return FoldedVOp; 3532 } 3533 3534 // fold (fadd c1, c2) -> c1+c2 3535 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3536 return DAG.getNode(ISD::FADD, VT, N0, N1); 3537 // canonicalize constant to RHS 3538 if (N0CFP && !N1CFP) 3539 return DAG.getNode(ISD::FADD, VT, N1, N0); 3540 // fold (A + (-B)) -> A-B 3541 if (isNegatibleForFree(N1, AfterLegalize) == 2) 3542 return DAG.getNode(ISD::FSUB, VT, N0, 3543 GetNegatedExpression(N1, DAG, AfterLegalize)); 3544 // fold ((-A) + B) -> B-A 3545 if (isNegatibleForFree(N0, AfterLegalize) == 2) 3546 return DAG.getNode(ISD::FSUB, VT, N1, 3547 GetNegatedExpression(N0, DAG, AfterLegalize)); 3548 3549 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3550 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3551 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3552 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3553 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3554 3555 return SDOperand(); 3556} 3557 3558SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3559 SDOperand N0 = N->getOperand(0); 3560 SDOperand N1 = N->getOperand(1); 3561 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3562 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3563 MVT::ValueType VT = N->getValueType(0); 3564 3565 // fold vector ops 3566 if (MVT::isVector(VT)) { 3567 SDOperand FoldedVOp = SimplifyVBinOp(N); 3568 if (FoldedVOp.Val) return FoldedVOp; 3569 } 3570 3571 // fold (fsub c1, c2) -> c1-c2 3572 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3573 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3574 // fold (0-B) -> -B 3575 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3576 if (isNegatibleForFree(N1, AfterLegalize)) 3577 return GetNegatedExpression(N1, DAG, AfterLegalize); 3578 return DAG.getNode(ISD::FNEG, VT, N1); 3579 } 3580 // fold (A-(-B)) -> A+B 3581 if (isNegatibleForFree(N1, AfterLegalize)) 3582 return DAG.getNode(ISD::FADD, VT, N0, 3583 GetNegatedExpression(N1, DAG, AfterLegalize)); 3584 3585 return SDOperand(); 3586} 3587 3588SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3589 SDOperand N0 = N->getOperand(0); 3590 SDOperand N1 = N->getOperand(1); 3591 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3592 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3593 MVT::ValueType VT = N->getValueType(0); 3594 3595 // fold vector ops 3596 if (MVT::isVector(VT)) { 3597 SDOperand FoldedVOp = SimplifyVBinOp(N); 3598 if (FoldedVOp.Val) return FoldedVOp; 3599 } 3600 3601 // fold (fmul c1, c2) -> c1*c2 3602 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3603 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3604 // canonicalize constant to RHS 3605 if (N0CFP && !N1CFP) 3606 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3607 // fold (fmul X, 2.0) -> (fadd X, X) 3608 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3609 return DAG.getNode(ISD::FADD, VT, N0, N0); 3610 // fold (fmul X, -1.0) -> (fneg X) 3611 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3612 return DAG.getNode(ISD::FNEG, VT, N0); 3613 3614 // -X * -Y -> X*Y 3615 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3616 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3617 // Both can be negated for free, check to see if at least one is cheaper 3618 // negated. 3619 if (LHSNeg == 2 || RHSNeg == 2) 3620 return DAG.getNode(ISD::FMUL, VT, 3621 GetNegatedExpression(N0, DAG, AfterLegalize), 3622 GetNegatedExpression(N1, DAG, AfterLegalize)); 3623 } 3624 } 3625 3626 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3627 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3628 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3629 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3630 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3631 3632 return SDOperand(); 3633} 3634 3635SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3636 SDOperand N0 = N->getOperand(0); 3637 SDOperand N1 = N->getOperand(1); 3638 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3639 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3640 MVT::ValueType VT = N->getValueType(0); 3641 3642 // fold vector ops 3643 if (MVT::isVector(VT)) { 3644 SDOperand FoldedVOp = SimplifyVBinOp(N); 3645 if (FoldedVOp.Val) return FoldedVOp; 3646 } 3647 3648 // fold (fdiv c1, c2) -> c1/c2 3649 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3650 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3651 3652 3653 // -X / -Y -> X*Y 3654 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3655 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3656 // Both can be negated for free, check to see if at least one is cheaper 3657 // negated. 3658 if (LHSNeg == 2 || RHSNeg == 2) 3659 return DAG.getNode(ISD::FDIV, VT, 3660 GetNegatedExpression(N0, DAG, AfterLegalize), 3661 GetNegatedExpression(N1, DAG, AfterLegalize)); 3662 } 3663 } 3664 3665 return SDOperand(); 3666} 3667 3668SDOperand DAGCombiner::visitFREM(SDNode *N) { 3669 SDOperand N0 = N->getOperand(0); 3670 SDOperand N1 = N->getOperand(1); 3671 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3672 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3673 MVT::ValueType VT = N->getValueType(0); 3674 3675 // fold (frem c1, c2) -> fmod(c1,c2) 3676 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3677 return DAG.getNode(ISD::FREM, VT, N0, N1); 3678 3679 return SDOperand(); 3680} 3681 3682SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3683 SDOperand N0 = N->getOperand(0); 3684 SDOperand N1 = N->getOperand(1); 3685 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3686 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3687 MVT::ValueType VT = N->getValueType(0); 3688 3689 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3690 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3691 3692 if (N1CFP) { 3693 const APFloat& V = N1CFP->getValueAPF(); 3694 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3695 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3696 if (!V.isNegative()) 3697 return DAG.getNode(ISD::FABS, VT, N0); 3698 else 3699 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3700 } 3701 3702 // copysign(fabs(x), y) -> copysign(x, y) 3703 // copysign(fneg(x), y) -> copysign(x, y) 3704 // copysign(copysign(x,z), y) -> copysign(x, y) 3705 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3706 N0.getOpcode() == ISD::FCOPYSIGN) 3707 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3708 3709 // copysign(x, abs(y)) -> abs(x) 3710 if (N1.getOpcode() == ISD::FABS) 3711 return DAG.getNode(ISD::FABS, VT, N0); 3712 3713 // copysign(x, copysign(y,z)) -> copysign(x, z) 3714 if (N1.getOpcode() == ISD::FCOPYSIGN) 3715 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3716 3717 // copysign(x, fp_extend(y)) -> copysign(x, y) 3718 // copysign(x, fp_round(y)) -> copysign(x, y) 3719 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3720 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3721 3722 return SDOperand(); 3723} 3724 3725 3726 3727SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3728 SDOperand N0 = N->getOperand(0); 3729 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3730 MVT::ValueType VT = N->getValueType(0); 3731 3732 // fold (sint_to_fp c1) -> c1fp 3733 if (N0C && N0.getValueType() != MVT::ppcf128) 3734 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3735 return SDOperand(); 3736} 3737 3738SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3739 SDOperand N0 = N->getOperand(0); 3740 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3741 MVT::ValueType VT = N->getValueType(0); 3742 3743 // fold (uint_to_fp c1) -> c1fp 3744 if (N0C && N0.getValueType() != MVT::ppcf128) 3745 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3746 return SDOperand(); 3747} 3748 3749SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3750 SDOperand N0 = N->getOperand(0); 3751 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3752 MVT::ValueType VT = N->getValueType(0); 3753 3754 // fold (fp_to_sint c1fp) -> c1 3755 if (N0CFP) 3756 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3757 return SDOperand(); 3758} 3759 3760SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3761 SDOperand N0 = N->getOperand(0); 3762 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3763 MVT::ValueType VT = N->getValueType(0); 3764 3765 // fold (fp_to_uint c1fp) -> c1 3766 if (N0CFP && VT != MVT::ppcf128) 3767 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3768 return SDOperand(); 3769} 3770 3771SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3772 SDOperand N0 = N->getOperand(0); 3773 SDOperand N1 = N->getOperand(1); 3774 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3775 MVT::ValueType VT = N->getValueType(0); 3776 3777 // fold (fp_round c1fp) -> c1fp 3778 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3779 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 3780 3781 // fold (fp_round (fp_extend x)) -> x 3782 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3783 return N0.getOperand(0); 3784 3785 // fold (fp_round (fp_round x)) -> (fp_round x) 3786 if (N0.getOpcode() == ISD::FP_ROUND) { 3787 // This is a value preserving truncation if both round's are. 3788 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 3789 N0.Val->getConstantOperandVal(1) == 1; 3790 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 3791 DAG.getIntPtrConstant(IsTrunc)); 3792 } 3793 3794 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3795 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3796 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 3797 AddToWorkList(Tmp.Val); 3798 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3799 } 3800 3801 return SDOperand(); 3802} 3803 3804SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3805 SDOperand N0 = N->getOperand(0); 3806 MVT::ValueType VT = N->getValueType(0); 3807 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3808 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3809 3810 // fold (fp_round_inreg c1fp) -> c1fp 3811 if (N0CFP) { 3812 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3813 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3814 } 3815 return SDOperand(); 3816} 3817 3818SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3819 SDOperand N0 = N->getOperand(0); 3820 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3821 MVT::ValueType VT = N->getValueType(0); 3822 3823 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 3824 if (N->hasOneUse() && (*N->use_begin())->getOpcode() == ISD::FP_ROUND) 3825 return SDOperand(); 3826 3827 // fold (fp_extend c1fp) -> c1fp 3828 if (N0CFP && VT != MVT::ppcf128) 3829 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3830 3831 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 3832 // value of X. 3833 if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){ 3834 SDOperand In = N0.getOperand(0); 3835 if (In.getValueType() == VT) return In; 3836 if (VT < In.getValueType()) 3837 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 3838 return DAG.getNode(ISD::FP_EXTEND, VT, In); 3839 } 3840 3841 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 3842 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3843 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3844 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3845 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3846 LN0->getBasePtr(), LN0->getSrcValue(), 3847 LN0->getSrcValueOffset(), 3848 N0.getValueType(), 3849 LN0->isVolatile(), 3850 LN0->getAlignment()); 3851 CombineTo(N, ExtLoad); 3852 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad, 3853 DAG.getIntPtrConstant(1)), 3854 ExtLoad.getValue(1)); 3855 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3856 } 3857 3858 3859 return SDOperand(); 3860} 3861 3862SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3863 SDOperand N0 = N->getOperand(0); 3864 3865 if (isNegatibleForFree(N0, AfterLegalize)) 3866 return GetNegatedExpression(N0, DAG, AfterLegalize); 3867 3868 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 3869 // constant pool values. 3870 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 3871 MVT::isInteger(N0.getOperand(0).getValueType()) && 3872 !MVT::isVector(N0.getOperand(0).getValueType())) { 3873 SDOperand Int = N0.getOperand(0); 3874 MVT::ValueType IntVT = Int.getValueType(); 3875 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { 3876 Int = DAG.getNode(ISD::XOR, IntVT, Int, 3877 DAG.getConstant(MVT::getIntVTSignBit(IntVT), IntVT)); 3878 AddToWorkList(Int.Val); 3879 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 3880 } 3881 } 3882 3883 return SDOperand(); 3884} 3885 3886SDOperand DAGCombiner::visitFABS(SDNode *N) { 3887 SDOperand N0 = N->getOperand(0); 3888 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3889 MVT::ValueType VT = N->getValueType(0); 3890 3891 // fold (fabs c1) -> fabs(c1) 3892 if (N0CFP && VT != MVT::ppcf128) 3893 return DAG.getNode(ISD::FABS, VT, N0); 3894 // fold (fabs (fabs x)) -> (fabs x) 3895 if (N0.getOpcode() == ISD::FABS) 3896 return N->getOperand(0); 3897 // fold (fabs (fneg x)) -> (fabs x) 3898 // fold (fabs (fcopysign x, y)) -> (fabs x) 3899 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3900 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3901 3902 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 3903 // constant pool values. 3904 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 3905 MVT::isInteger(N0.getOperand(0).getValueType()) && 3906 !MVT::isVector(N0.getOperand(0).getValueType())) { 3907 SDOperand Int = N0.getOperand(0); 3908 MVT::ValueType IntVT = Int.getValueType(); 3909 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { 3910 Int = DAG.getNode(ISD::AND, IntVT, Int, 3911 DAG.getConstant(~MVT::getIntVTSignBit(IntVT), IntVT)); 3912 AddToWorkList(Int.Val); 3913 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 3914 } 3915 } 3916 3917 return SDOperand(); 3918} 3919 3920SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3921 SDOperand Chain = N->getOperand(0); 3922 SDOperand N1 = N->getOperand(1); 3923 SDOperand N2 = N->getOperand(2); 3924 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3925 3926 // never taken branch, fold to chain 3927 if (N1C && N1C->isNullValue()) 3928 return Chain; 3929 // unconditional branch 3930 if (N1C && N1C->getValue() == 1) 3931 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3932 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3933 // on the target. 3934 if (N1.getOpcode() == ISD::SETCC && 3935 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3936 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3937 N1.getOperand(0), N1.getOperand(1), N2); 3938 } 3939 return SDOperand(); 3940} 3941 3942// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3943// 3944SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3945 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3946 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3947 3948 // Use SimplifySetCC to simplify SETCC's. 3949 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3950 if (Simp.Val) AddToWorkList(Simp.Val); 3951 3952 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3953 3954 // fold br_cc true, dest -> br dest (unconditional branch) 3955 if (SCCC && SCCC->getValue()) 3956 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3957 N->getOperand(4)); 3958 // fold br_cc false, dest -> unconditional fall through 3959 if (SCCC && SCCC->isNullValue()) 3960 return N->getOperand(0); 3961 3962 // fold to a simpler setcc 3963 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 3964 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 3965 Simp.getOperand(2), Simp.getOperand(0), 3966 Simp.getOperand(1), N->getOperand(4)); 3967 return SDOperand(); 3968} 3969 3970 3971/// CombineToPreIndexedLoadStore - Try turning a load / store and a 3972/// pre-indexed load / store when the base pointer is a add or subtract 3973/// and it has other uses besides the load / store. After the 3974/// transformation, the new indexed load / store has effectively folded 3975/// the add / subtract in and all of its other uses are redirected to the 3976/// new load / store. 3977bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 3978 if (!AfterLegalize) 3979 return false; 3980 3981 bool isLoad = true; 3982 SDOperand Ptr; 3983 MVT::ValueType VT; 3984 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3985 if (LD->isIndexed()) 3986 return false; 3987 VT = LD->getMemoryVT(); 3988 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 3989 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 3990 return false; 3991 Ptr = LD->getBasePtr(); 3992 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3993 if (ST->isIndexed()) 3994 return false; 3995 VT = ST->getMemoryVT(); 3996 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 3997 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 3998 return false; 3999 Ptr = ST->getBasePtr(); 4000 isLoad = false; 4001 } else 4002 return false; 4003 4004 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4005 // out. There is no reason to make this a preinc/predec. 4006 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4007 Ptr.Val->hasOneUse()) 4008 return false; 4009 4010 // Ask the target to do addressing mode selection. 4011 SDOperand BasePtr; 4012 SDOperand Offset; 4013 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4014 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4015 return false; 4016 // Don't create a indexed load / store with zero offset. 4017 if (isa<ConstantSDNode>(Offset) && 4018 cast<ConstantSDNode>(Offset)->getValue() == 0) 4019 return false; 4020 4021 // Try turning it into a pre-indexed load / store except when: 4022 // 1) The new base ptr is a frame index. 4023 // 2) If N is a store and the new base ptr is either the same as or is a 4024 // predecessor of the value being stored. 4025 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4026 // that would create a cycle. 4027 // 4) All uses are load / store ops that use it as old base ptr. 4028 4029 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4030 // (plus the implicit offset) to a register to preinc anyway. 4031 if (isa<FrameIndexSDNode>(BasePtr)) 4032 return false; 4033 4034 // Check #2. 4035 if (!isLoad) { 4036 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 4037 if (Val == BasePtr || BasePtr.Val->isPredecessorOf(Val.Val)) 4038 return false; 4039 } 4040 4041 // Now check for #3 and #4. 4042 bool RealUse = false; 4043 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4044 E = Ptr.Val->use_end(); I != E; ++I) { 4045 SDNode *Use = *I; 4046 if (Use == N) 4047 continue; 4048 if (Use->isPredecessorOf(N)) 4049 return false; 4050 4051 if (!((Use->getOpcode() == ISD::LOAD && 4052 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4053 (Use->getOpcode() == ISD::STORE && 4054 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4055 RealUse = true; 4056 } 4057 if (!RealUse) 4058 return false; 4059 4060 SDOperand Result; 4061 if (isLoad) 4062 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 4063 else 4064 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4065 ++PreIndexedNodes; 4066 ++NodesCombined; 4067 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4068 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4069 DOUT << '\n'; 4070 WorkListRemover DeadNodes(*this); 4071 if (isLoad) { 4072 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4073 &DeadNodes); 4074 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4075 &DeadNodes); 4076 } else { 4077 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4078 &DeadNodes); 4079 } 4080 4081 // Finally, since the node is now dead, remove it from the graph. 4082 DAG.DeleteNode(N); 4083 4084 // Replace the uses of Ptr with uses of the updated base value. 4085 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4086 &DeadNodes); 4087 removeFromWorkList(Ptr.Val); 4088 DAG.DeleteNode(Ptr.Val); 4089 4090 return true; 4091} 4092 4093/// CombineToPostIndexedLoadStore - Try combine a load / store with a 4094/// add / sub of the base pointer node into a post-indexed load / store. 4095/// The transformation folded the add / subtract into the new indexed 4096/// load / store effectively and all of its uses are redirected to the 4097/// new load / store. 4098bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4099 if (!AfterLegalize) 4100 return false; 4101 4102 bool isLoad = true; 4103 SDOperand Ptr; 4104 MVT::ValueType VT; 4105 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4106 if (LD->isIndexed()) 4107 return false; 4108 VT = LD->getMemoryVT(); 4109 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4110 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4111 return false; 4112 Ptr = LD->getBasePtr(); 4113 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4114 if (ST->isIndexed()) 4115 return false; 4116 VT = ST->getMemoryVT(); 4117 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4118 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4119 return false; 4120 Ptr = ST->getBasePtr(); 4121 isLoad = false; 4122 } else 4123 return false; 4124 4125 if (Ptr.Val->hasOneUse()) 4126 return false; 4127 4128 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4129 E = Ptr.Val->use_end(); I != E; ++I) { 4130 SDNode *Op = *I; 4131 if (Op == N || 4132 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4133 continue; 4134 4135 SDOperand BasePtr; 4136 SDOperand Offset; 4137 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4138 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4139 if (Ptr == Offset) 4140 std::swap(BasePtr, Offset); 4141 if (Ptr != BasePtr) 4142 continue; 4143 // Don't create a indexed load / store with zero offset. 4144 if (isa<ConstantSDNode>(Offset) && 4145 cast<ConstantSDNode>(Offset)->getValue() == 0) 4146 continue; 4147 4148 // Try turning it into a post-indexed load / store except when 4149 // 1) All uses are load / store ops that use it as base ptr. 4150 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4151 // nor a successor of N. Otherwise, if Op is folded that would 4152 // create a cycle. 4153 4154 // Check for #1. 4155 bool TryNext = false; 4156 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 4157 EE = BasePtr.Val->use_end(); II != EE; ++II) { 4158 SDNode *Use = *II; 4159 if (Use == Ptr.Val) 4160 continue; 4161 4162 // If all the uses are load / store addresses, then don't do the 4163 // transformation. 4164 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4165 bool RealUse = false; 4166 for (SDNode::use_iterator III = Use->use_begin(), 4167 EEE = Use->use_end(); III != EEE; ++III) { 4168 SDNode *UseUse = *III; 4169 if (!((UseUse->getOpcode() == ISD::LOAD && 4170 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 4171 (UseUse->getOpcode() == ISD::STORE && 4172 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))) 4173 RealUse = true; 4174 } 4175 4176 if (!RealUse) { 4177 TryNext = true; 4178 break; 4179 } 4180 } 4181 } 4182 if (TryNext) 4183 continue; 4184 4185 // Check for #2 4186 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4187 SDOperand Result = isLoad 4188 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 4189 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4190 ++PostIndexedNodes; 4191 ++NodesCombined; 4192 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4193 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4194 DOUT << '\n'; 4195 WorkListRemover DeadNodes(*this); 4196 if (isLoad) { 4197 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4198 &DeadNodes); 4199 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4200 &DeadNodes); 4201 } else { 4202 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4203 &DeadNodes); 4204 } 4205 4206 // Finally, since the node is now dead, remove it from the graph. 4207 DAG.DeleteNode(N); 4208 4209 // Replace the uses of Use with uses of the updated base value. 4210 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 4211 Result.getValue(isLoad ? 1 : 0), 4212 &DeadNodes); 4213 removeFromWorkList(Op); 4214 DAG.DeleteNode(Op); 4215 return true; 4216 } 4217 } 4218 } 4219 return false; 4220} 4221 4222/// InferAlignment - If we can infer some alignment information from this 4223/// pointer, return it. 4224static unsigned InferAlignment(SDOperand Ptr, SelectionDAG &DAG) { 4225 // If this is a direct reference to a stack slot, use information about the 4226 // stack slot's alignment. 4227 int FrameIdx = 1 << 31; 4228 int64_t FrameOffset = 0; 4229 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4230 FrameIdx = FI->getIndex(); 4231 } else if (Ptr.getOpcode() == ISD::ADD && 4232 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4233 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4234 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4235 FrameOffset = Ptr.getConstantOperandVal(1); 4236 } 4237 4238 if (FrameIdx != (1 << 31)) { 4239 // FIXME: Handle FI+CST. 4240 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4241 if (MFI.isFixedObjectIndex(FrameIdx)) { 4242 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx); 4243 4244 // The alignment of the frame index can be determined from its offset from 4245 // the incoming frame position. If the frame object is at offset 32 and 4246 // the stack is guaranteed to be 16-byte aligned, then we know that the 4247 // object is 16-byte aligned. 4248 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4249 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4250 4251 // Finally, the frame object itself may have a known alignment. Factor 4252 // the alignment + offset into a new alignment. For example, if we know 4253 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4254 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4255 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4256 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4257 FrameOffset); 4258 return std::max(Align, FIInfoAlign); 4259 } 4260 } 4261 4262 return 0; 4263} 4264 4265SDOperand DAGCombiner::visitLOAD(SDNode *N) { 4266 LoadSDNode *LD = cast<LoadSDNode>(N); 4267 SDOperand Chain = LD->getChain(); 4268 SDOperand Ptr = LD->getBasePtr(); 4269 4270 // Try to infer better alignment information than the load already has. 4271 if (LD->isUnindexed()) { 4272 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4273 if (Align > LD->getAlignment()) 4274 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4275 Chain, Ptr, LD->getSrcValue(), 4276 LD->getSrcValueOffset(), LD->getMemoryVT(), 4277 LD->isVolatile(), Align); 4278 } 4279 } 4280 4281 4282 // If load is not volatile and there are no uses of the loaded value (and 4283 // the updated indexed value in case of indexed loads), change uses of the 4284 // chain value into uses of the chain input (i.e. delete the dead load). 4285 if (!LD->isVolatile()) { 4286 if (N->getValueType(1) == MVT::Other) { 4287 // Unindexed loads. 4288 if (N->hasNUsesOfValue(0, 0)) { 4289 // It's not safe to use the two value CombineTo variant here. e.g. 4290 // v1, chain2 = load chain1, loc 4291 // v2, chain3 = load chain2, loc 4292 // v3 = add v2, c 4293 // Now we replace use of chain2 with chain1. This makes the second load 4294 // isomorphic to the one we are deleting, and thus makes this load live. 4295 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4296 DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG)); 4297 DOUT << "\n"; 4298 WorkListRemover DeadNodes(*this); 4299 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Chain, &DeadNodes); 4300 if (N->use_empty()) { 4301 removeFromWorkList(N); 4302 DAG.DeleteNode(N); 4303 } 4304 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4305 } 4306 } else { 4307 // Indexed loads. 4308 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4309 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4310 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4311 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4312 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG)); 4313 DOUT << " and 2 other values\n"; 4314 WorkListRemover DeadNodes(*this); 4315 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &DeadNodes); 4316 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), 4317 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4318 &DeadNodes); 4319 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 2), Chain, &DeadNodes); 4320 removeFromWorkList(N); 4321 DAG.DeleteNode(N); 4322 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4323 } 4324 } 4325 } 4326 4327 // If this load is directly stored, replace the load value with the stored 4328 // value. 4329 // TODO: Handle store large -> read small portion. 4330 // TODO: Handle TRUNCSTORE/LOADEXT 4331 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4332 if (ISD::isNON_TRUNCStore(Chain.Val)) { 4333 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4334 if (PrevST->getBasePtr() == Ptr && 4335 PrevST->getValue().getValueType() == N->getValueType(0)) 4336 return CombineTo(N, Chain.getOperand(1), Chain); 4337 } 4338 } 4339 4340 if (CombinerAA) { 4341 // Walk up chain skipping non-aliasing memory nodes. 4342 SDOperand BetterChain = FindBetterChain(N, Chain); 4343 4344 // If there is a better chain. 4345 if (Chain != BetterChain) { 4346 SDOperand ReplLoad; 4347 4348 // Replace the chain to void dependency. 4349 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4350 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4351 LD->getSrcValue(), LD->getSrcValueOffset(), 4352 LD->isVolatile(), LD->getAlignment()); 4353 } else { 4354 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4355 LD->getValueType(0), 4356 BetterChain, Ptr, LD->getSrcValue(), 4357 LD->getSrcValueOffset(), 4358 LD->getMemoryVT(), 4359 LD->isVolatile(), 4360 LD->getAlignment()); 4361 } 4362 4363 // Create token factor to keep old chain connected. 4364 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4365 Chain, ReplLoad.getValue(1)); 4366 4367 // Replace uses with load result and token factor. Don't add users 4368 // to work list. 4369 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4370 } 4371 } 4372 4373 // Try transforming N to an indexed load. 4374 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4375 return SDOperand(N, 0); 4376 4377 return SDOperand(); 4378} 4379 4380 4381SDOperand DAGCombiner::visitSTORE(SDNode *N) { 4382 StoreSDNode *ST = cast<StoreSDNode>(N); 4383 SDOperand Chain = ST->getChain(); 4384 SDOperand Value = ST->getValue(); 4385 SDOperand Ptr = ST->getBasePtr(); 4386 4387 // Try to infer better alignment information than the store already has. 4388 if (ST->isUnindexed()) { 4389 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4390 if (Align > ST->getAlignment()) 4391 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4392 ST->getSrcValueOffset(), ST->getMemoryVT(), 4393 ST->isVolatile(), Align); 4394 } 4395 } 4396 4397 // If this is a store of a bit convert, store the input value if the 4398 // resultant store does not need a higher alignment than the original. 4399 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4400 ST->isUnindexed()) { 4401 unsigned Align = ST->getAlignment(); 4402 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 4403 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 4404 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 4405 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 4406 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4407 ST->getSrcValueOffset(), ST->isVolatile(), Align); 4408 } 4409 4410 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4411 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4412 if (Value.getOpcode() != ISD::TargetConstantFP) { 4413 SDOperand Tmp; 4414 switch (CFP->getValueType(0)) { 4415 default: assert(0 && "Unknown FP type"); 4416 case MVT::f80: // We don't do this for these yet. 4417 case MVT::f128: 4418 case MVT::ppcf128: 4419 break; 4420 case MVT::f32: 4421 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 4422 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4423 convertToAPInt().getZExtValue(), MVT::i32); 4424 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4425 ST->getSrcValueOffset(), ST->isVolatile(), 4426 ST->getAlignment()); 4427 } 4428 break; 4429 case MVT::f64: 4430 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 4431 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 4432 getZExtValue(), MVT::i64); 4433 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4434 ST->getSrcValueOffset(), ST->isVolatile(), 4435 ST->getAlignment()); 4436 } else if (TLI.isTypeLegal(MVT::i32)) { 4437 // Many FP stores are not made apparent until after legalize, e.g. for 4438 // argument passing. Since this is so common, custom legalize the 4439 // 64-bit integer store into two 32-bit stores. 4440 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 4441 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4442 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 4443 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4444 4445 int SVOffset = ST->getSrcValueOffset(); 4446 unsigned Alignment = ST->getAlignment(); 4447 bool isVolatile = ST->isVolatile(); 4448 4449 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4450 ST->getSrcValueOffset(), 4451 isVolatile, ST->getAlignment()); 4452 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4453 DAG.getConstant(4, Ptr.getValueType())); 4454 SVOffset += 4; 4455 Alignment = MinAlign(Alignment, 4U); 4456 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4457 SVOffset, isVolatile, Alignment); 4458 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4459 } 4460 break; 4461 } 4462 } 4463 } 4464 4465 if (CombinerAA) { 4466 // Walk up chain skipping non-aliasing memory nodes. 4467 SDOperand BetterChain = FindBetterChain(N, Chain); 4468 4469 // If there is a better chain. 4470 if (Chain != BetterChain) { 4471 // Replace the chain to avoid dependency. 4472 SDOperand ReplStore; 4473 if (ST->isTruncatingStore()) { 4474 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4475 ST->getSrcValue(),ST->getSrcValueOffset(), 4476 ST->getMemoryVT(), 4477 ST->isVolatile(), ST->getAlignment()); 4478 } else { 4479 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4480 ST->getSrcValue(), ST->getSrcValueOffset(), 4481 ST->isVolatile(), ST->getAlignment()); 4482 } 4483 4484 // Create token to keep both nodes around. 4485 SDOperand Token = 4486 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4487 4488 // Don't add users to work list. 4489 return CombineTo(N, Token, false); 4490 } 4491 } 4492 4493 // Try transforming N to an indexed store. 4494 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4495 return SDOperand(N, 0); 4496 4497 // FIXME: is there such a thing as a truncating indexed store? 4498 if (ST->isTruncatingStore() && ST->isUnindexed() && 4499 MVT::isInteger(Value.getValueType())) { 4500 // See if we can simplify the input to this truncstore with knowledge that 4501 // only the low bits are being used. For example: 4502 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4503 SDOperand Shorter = 4504 GetDemandedBits(Value, 4505 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4506 MVT::getSizeInBits(ST->getMemoryVT()))); 4507 AddToWorkList(Value.Val); 4508 if (Shorter.Val) 4509 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4510 ST->getSrcValueOffset(), ST->getMemoryVT(), 4511 ST->isVolatile(), ST->getAlignment()); 4512 4513 // Otherwise, see if we can simplify the operation with 4514 // SimplifyDemandedBits, which only works if the value has a single use. 4515 if (SimplifyDemandedBits(Value, 4516 APInt::getLowBitsSet( 4517 Value.getValueSizeInBits(), 4518 MVT::getSizeInBits(ST->getMemoryVT())))) 4519 return SDOperand(N, 0); 4520 } 4521 4522 // If this is a load followed by a store to the same location, then the store 4523 // is dead/noop. 4524 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4525 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4526 ST->isUnindexed() && !ST->isVolatile() && 4527 // There can't be any side effects between the load and store, such as 4528 // a call or store. 4529 Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) { 4530 // The store is dead, remove it. 4531 return Chain; 4532 } 4533 } 4534 4535 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4536 // truncating store. We can do this even if this is already a truncstore. 4537 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4538 && TLI.isTypeLegal(Value.getOperand(0).getValueType()) && 4539 Value.Val->hasOneUse() && ST->isUnindexed() && 4540 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4541 ST->getMemoryVT())) { 4542 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4543 ST->getSrcValueOffset(), ST->getMemoryVT(), 4544 ST->isVolatile(), ST->getAlignment()); 4545 } 4546 4547 return SDOperand(); 4548} 4549 4550SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4551 SDOperand InVec = N->getOperand(0); 4552 SDOperand InVal = N->getOperand(1); 4553 SDOperand EltNo = N->getOperand(2); 4554 4555 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4556 // vector with the inserted element. 4557 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4558 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4559 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 4560 if (Elt < Ops.size()) 4561 Ops[Elt] = InVal; 4562 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4563 &Ops[0], Ops.size()); 4564 } 4565 4566 return SDOperand(); 4567} 4568 4569SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4570 SDOperand InVec = N->getOperand(0); 4571 SDOperand EltNo = N->getOperand(1); 4572 4573 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 4574 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr) 4575 if (isa<ConstantSDNode>(EltNo)) { 4576 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4577 bool NewLoad = false; 4578 if (Elt == 0) { 4579 MVT::ValueType VT = InVec.getValueType(); 4580 MVT::ValueType EVT = MVT::getVectorElementType(VT); 4581 MVT::ValueType LVT = EVT; 4582 unsigned NumElts = MVT::getVectorNumElements(VT); 4583 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4584 MVT::ValueType BCVT = InVec.getOperand(0).getValueType(); 4585 if (!MVT::isVector(BCVT) || 4586 NumElts != MVT::getVectorNumElements(BCVT)) 4587 return SDOperand(); 4588 InVec = InVec.getOperand(0); 4589 EVT = MVT::getVectorElementType(BCVT); 4590 NewLoad = true; 4591 } 4592 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4593 InVec.getOperand(0).getValueType() == EVT && 4594 ISD::isNormalLoad(InVec.getOperand(0).Val) && 4595 InVec.getOperand(0).hasOneUse()) { 4596 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4597 unsigned Align = LN0->getAlignment(); 4598 if (NewLoad) { 4599 // Check the resultant load doesn't need a higher alignment than the 4600 // original load. 4601 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 4602 getABITypeAlignment(MVT::getTypeForValueType(LVT)); 4603 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align) 4604 return SDOperand(); 4605 Align = NewAlign; 4606 } 4607 4608 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(), 4609 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4610 LN0->isVolatile(), Align); 4611 } 4612 } 4613 } 4614 return SDOperand(); 4615} 4616 4617 4618SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4619 unsigned NumInScalars = N->getNumOperands(); 4620 MVT::ValueType VT = N->getValueType(0); 4621 unsigned NumElts = MVT::getVectorNumElements(VT); 4622 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4623 4624 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4625 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4626 // at most two distinct vectors, turn this into a shuffle node. 4627 SDOperand VecIn1, VecIn2; 4628 for (unsigned i = 0; i != NumInScalars; ++i) { 4629 // Ignore undef inputs. 4630 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4631 4632 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4633 // constant index, bail out. 4634 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4635 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4636 VecIn1 = VecIn2 = SDOperand(0, 0); 4637 break; 4638 } 4639 4640 // If the input vector type disagrees with the result of the build_vector, 4641 // we can't make a shuffle. 4642 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 4643 if (ExtractedFromVec.getValueType() != VT) { 4644 VecIn1 = VecIn2 = SDOperand(0, 0); 4645 break; 4646 } 4647 4648 // Otherwise, remember this. We allow up to two distinct input vectors. 4649 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4650 continue; 4651 4652 if (VecIn1.Val == 0) { 4653 VecIn1 = ExtractedFromVec; 4654 } else if (VecIn2.Val == 0) { 4655 VecIn2 = ExtractedFromVec; 4656 } else { 4657 // Too many inputs. 4658 VecIn1 = VecIn2 = SDOperand(0, 0); 4659 break; 4660 } 4661 } 4662 4663 // If everything is good, we can make a shuffle operation. 4664 if (VecIn1.Val) { 4665 SmallVector<SDOperand, 8> BuildVecIndices; 4666 for (unsigned i = 0; i != NumInScalars; ++i) { 4667 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4668 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4669 continue; 4670 } 4671 4672 SDOperand Extract = N->getOperand(i); 4673 4674 // If extracting from the first vector, just use the index directly. 4675 if (Extract.getOperand(0) == VecIn1) { 4676 BuildVecIndices.push_back(Extract.getOperand(1)); 4677 continue; 4678 } 4679 4680 // Otherwise, use InIdx + VecSize 4681 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 4682 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 4683 } 4684 4685 // Add count and size info. 4686 MVT::ValueType BuildVecVT = MVT::getVectorType(TLI.getPointerTy(), NumElts); 4687 4688 // Return the new VECTOR_SHUFFLE node. 4689 SDOperand Ops[5]; 4690 Ops[0] = VecIn1; 4691 if (VecIn2.Val) { 4692 Ops[1] = VecIn2; 4693 } else { 4694 // Use an undef build_vector as input for the second operand. 4695 std::vector<SDOperand> UnOps(NumInScalars, 4696 DAG.getNode(ISD::UNDEF, 4697 EltType)); 4698 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4699 &UnOps[0], UnOps.size()); 4700 AddToWorkList(Ops[1].Val); 4701 } 4702 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4703 &BuildVecIndices[0], BuildVecIndices.size()); 4704 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4705 } 4706 4707 return SDOperand(); 4708} 4709 4710SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4711 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4712 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4713 // inputs come from at most two distinct vectors, turn this into a shuffle 4714 // node. 4715 4716 // If we only have one input vector, we don't need to do any concatenation. 4717 if (N->getNumOperands() == 1) { 4718 return N->getOperand(0); 4719 } 4720 4721 return SDOperand(); 4722} 4723 4724SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4725 SDOperand ShufMask = N->getOperand(2); 4726 unsigned NumElts = ShufMask.getNumOperands(); 4727 4728 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4729 bool isIdentity = true; 4730 for (unsigned i = 0; i != NumElts; ++i) { 4731 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4732 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4733 isIdentity = false; 4734 break; 4735 } 4736 } 4737 if (isIdentity) return N->getOperand(0); 4738 4739 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4740 isIdentity = true; 4741 for (unsigned i = 0; i != NumElts; ++i) { 4742 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4743 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4744 isIdentity = false; 4745 break; 4746 } 4747 } 4748 if (isIdentity) return N->getOperand(1); 4749 4750 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4751 // needed at all. 4752 bool isUnary = true; 4753 bool isSplat = true; 4754 int VecNum = -1; 4755 unsigned BaseIdx = 0; 4756 for (unsigned i = 0; i != NumElts; ++i) 4757 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4758 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4759 int V = (Idx < NumElts) ? 0 : 1; 4760 if (VecNum == -1) { 4761 VecNum = V; 4762 BaseIdx = Idx; 4763 } else { 4764 if (BaseIdx != Idx) 4765 isSplat = false; 4766 if (VecNum != V) { 4767 isUnary = false; 4768 break; 4769 } 4770 } 4771 } 4772 4773 SDOperand N0 = N->getOperand(0); 4774 SDOperand N1 = N->getOperand(1); 4775 // Normalize unary shuffle so the RHS is undef. 4776 if (isUnary && VecNum == 1) 4777 std::swap(N0, N1); 4778 4779 // If it is a splat, check if the argument vector is a build_vector with 4780 // all scalar elements the same. 4781 if (isSplat) { 4782 SDNode *V = N0.Val; 4783 4784 // If this is a bit convert that changes the element type of the vector but 4785 // not the number of vector elements, look through it. Be careful not to 4786 // look though conversions that change things like v4f32 to v2f64. 4787 if (V->getOpcode() == ISD::BIT_CONVERT) { 4788 SDOperand ConvInput = V->getOperand(0); 4789 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) 4790 V = ConvInput.Val; 4791 } 4792 4793 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4794 unsigned NumElems = V->getNumOperands(); 4795 if (NumElems > BaseIdx) { 4796 SDOperand Base; 4797 bool AllSame = true; 4798 for (unsigned i = 0; i != NumElems; ++i) { 4799 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4800 Base = V->getOperand(i); 4801 break; 4802 } 4803 } 4804 // Splat of <u, u, u, u>, return <u, u, u, u> 4805 if (!Base.Val) 4806 return N0; 4807 for (unsigned i = 0; i != NumElems; ++i) { 4808 if (V->getOperand(i) != Base) { 4809 AllSame = false; 4810 break; 4811 } 4812 } 4813 // Splat of <x, x, x, x>, return <x, x, x, x> 4814 if (AllSame) 4815 return N0; 4816 } 4817 } 4818 } 4819 4820 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4821 // into an undef. 4822 if (isUnary || N0 == N1) { 4823 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4824 // first operand. 4825 SmallVector<SDOperand, 8> MappedOps; 4826 for (unsigned i = 0; i != NumElts; ++i) { 4827 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4828 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4829 MappedOps.push_back(ShufMask.getOperand(i)); 4830 } else { 4831 unsigned NewIdx = 4832 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4833 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4834 } 4835 } 4836 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 4837 &MappedOps[0], MappedOps.size()); 4838 AddToWorkList(ShufMask.Val); 4839 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 4840 N0, 4841 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 4842 ShufMask); 4843 } 4844 4845 return SDOperand(); 4846} 4847 4848/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4849/// an AND to a vector_shuffle with the destination vector and a zero vector. 4850/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4851/// vector_shuffle V, Zero, <0, 4, 2, 4> 4852SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4853 SDOperand LHS = N->getOperand(0); 4854 SDOperand RHS = N->getOperand(1); 4855 if (N->getOpcode() == ISD::AND) { 4856 if (RHS.getOpcode() == ISD::BIT_CONVERT) 4857 RHS = RHS.getOperand(0); 4858 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 4859 std::vector<SDOperand> IdxOps; 4860 unsigned NumOps = RHS.getNumOperands(); 4861 unsigned NumElts = NumOps; 4862 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); 4863 for (unsigned i = 0; i != NumElts; ++i) { 4864 SDOperand Elt = RHS.getOperand(i); 4865 if (!isa<ConstantSDNode>(Elt)) 4866 return SDOperand(); 4867 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 4868 IdxOps.push_back(DAG.getConstant(i, EVT)); 4869 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 4870 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 4871 else 4872 return SDOperand(); 4873 } 4874 4875 // Let's see if the target supports this vector_shuffle. 4876 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 4877 return SDOperand(); 4878 4879 // Return the new VECTOR_SHUFFLE node. 4880 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); 4881 std::vector<SDOperand> Ops; 4882 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 4883 Ops.push_back(LHS); 4884 AddToWorkList(LHS.Val); 4885 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 4886 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4887 &ZeroOps[0], ZeroOps.size())); 4888 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4889 &IdxOps[0], IdxOps.size())); 4890 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 4891 &Ops[0], Ops.size()); 4892 if (VT != LHS.getValueType()) { 4893 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result); 4894 } 4895 return Result; 4896 } 4897 } 4898 return SDOperand(); 4899} 4900 4901/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 4902SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 4903 // After legalize, the target may be depending on adds and other 4904 // binary ops to provide legal ways to construct constants or other 4905 // things. Simplifying them may result in a loss of legality. 4906 if (AfterLegalize) return SDOperand(); 4907 4908 MVT::ValueType VT = N->getValueType(0); 4909 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); 4910 4911 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4912 SDOperand LHS = N->getOperand(0); 4913 SDOperand RHS = N->getOperand(1); 4914 SDOperand Shuffle = XformToShuffleWithZero(N); 4915 if (Shuffle.Val) return Shuffle; 4916 4917 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 4918 // this operation. 4919 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 4920 RHS.getOpcode() == ISD::BUILD_VECTOR) { 4921 SmallVector<SDOperand, 8> Ops; 4922 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 4923 SDOperand LHSOp = LHS.getOperand(i); 4924 SDOperand RHSOp = RHS.getOperand(i); 4925 // If these two elements can't be folded, bail out. 4926 if ((LHSOp.getOpcode() != ISD::UNDEF && 4927 LHSOp.getOpcode() != ISD::Constant && 4928 LHSOp.getOpcode() != ISD::ConstantFP) || 4929 (RHSOp.getOpcode() != ISD::UNDEF && 4930 RHSOp.getOpcode() != ISD::Constant && 4931 RHSOp.getOpcode() != ISD::ConstantFP)) 4932 break; 4933 // Can't fold divide by zero. 4934 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 4935 N->getOpcode() == ISD::FDIV) { 4936 if ((RHSOp.getOpcode() == ISD::Constant && 4937 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 4938 (RHSOp.getOpcode() == ISD::ConstantFP && 4939 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 4940 break; 4941 } 4942 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 4943 AddToWorkList(Ops.back().Val); 4944 assert((Ops.back().getOpcode() == ISD::UNDEF || 4945 Ops.back().getOpcode() == ISD::Constant || 4946 Ops.back().getOpcode() == ISD::ConstantFP) && 4947 "Scalar binop didn't fold!"); 4948 } 4949 4950 if (Ops.size() == LHS.getNumOperands()) { 4951 MVT::ValueType VT = LHS.getValueType(); 4952 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 4953 } 4954 } 4955 4956 return SDOperand(); 4957} 4958 4959SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 4960 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 4961 4962 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 4963 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4964 // If we got a simplified select_cc node back from SimplifySelectCC, then 4965 // break it down into a new SETCC node, and a new SELECT node, and then return 4966 // the SELECT node, since we were called with a SELECT node. 4967 if (SCC.Val) { 4968 // Check to see if we got a select_cc back (to turn into setcc/select). 4969 // Otherwise, just return whatever node we got back, like fabs. 4970 if (SCC.getOpcode() == ISD::SELECT_CC) { 4971 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 4972 SCC.getOperand(0), SCC.getOperand(1), 4973 SCC.getOperand(4)); 4974 AddToWorkList(SETCC.Val); 4975 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 4976 SCC.getOperand(3), SETCC); 4977 } 4978 return SCC; 4979 } 4980 return SDOperand(); 4981} 4982 4983/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 4984/// are the two values being selected between, see if we can simplify the 4985/// select. Callers of this should assume that TheSelect is deleted if this 4986/// returns true. As such, they should return the appropriate thing (e.g. the 4987/// node) back to the top-level of the DAG combiner loop to avoid it being 4988/// looked at. 4989/// 4990bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 4991 SDOperand RHS) { 4992 4993 // If this is a select from two identical things, try to pull the operation 4994 // through the select. 4995 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 4996 // If this is a load and the token chain is identical, replace the select 4997 // of two loads with a load through a select of the address to load from. 4998 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 4999 // constants have been dropped into the constant pool. 5000 if (LHS.getOpcode() == ISD::LOAD && 5001 // Token chains must be identical. 5002 LHS.getOperand(0) == RHS.getOperand(0)) { 5003 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5004 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5005 5006 // If this is an EXTLOAD, the VT's must match. 5007 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5008 // FIXME: this conflates two src values, discarding one. This is not 5009 // the right thing to do, but nothing uses srcvalues now. When they do, 5010 // turn SrcValue into a list of locations. 5011 SDOperand Addr; 5012 if (TheSelect->getOpcode() == ISD::SELECT) { 5013 // Check that the condition doesn't reach either load. If so, folding 5014 // this will induce a cycle into the DAG. 5015 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5016 !RLD->isPredecessorOf(TheSelect->getOperand(0).Val)) { 5017 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5018 TheSelect->getOperand(0), LLD->getBasePtr(), 5019 RLD->getBasePtr()); 5020 } 5021 } else { 5022 // Check that the condition doesn't reach either load. If so, folding 5023 // this will induce a cycle into the DAG. 5024 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5025 !RLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5026 !LLD->isPredecessorOf(TheSelect->getOperand(1).Val) && 5027 !RLD->isPredecessorOf(TheSelect->getOperand(1).Val)) { 5028 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5029 TheSelect->getOperand(0), 5030 TheSelect->getOperand(1), 5031 LLD->getBasePtr(), RLD->getBasePtr(), 5032 TheSelect->getOperand(4)); 5033 } 5034 } 5035 5036 if (Addr.Val) { 5037 SDOperand Load; 5038 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5039 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5040 Addr,LLD->getSrcValue(), 5041 LLD->getSrcValueOffset(), 5042 LLD->isVolatile(), 5043 LLD->getAlignment()); 5044 else { 5045 Load = DAG.getExtLoad(LLD->getExtensionType(), 5046 TheSelect->getValueType(0), 5047 LLD->getChain(), Addr, LLD->getSrcValue(), 5048 LLD->getSrcValueOffset(), 5049 LLD->getMemoryVT(), 5050 LLD->isVolatile(), 5051 LLD->getAlignment()); 5052 } 5053 // Users of the select now use the result of the load. 5054 CombineTo(TheSelect, Load); 5055 5056 // Users of the old loads now use the new load's chain. We know the 5057 // old-load value is dead now. 5058 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 5059 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 5060 return true; 5061 } 5062 } 5063 } 5064 } 5065 5066 return false; 5067} 5068 5069SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 5070 SDOperand N2, SDOperand N3, 5071 ISD::CondCode CC, bool NotExtCompare) { 5072 5073 MVT::ValueType VT = N2.getValueType(); 5074 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 5075 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 5076 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 5077 5078 // Determine if the condition we're dealing with is constant 5079 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 5080 if (SCC.Val) AddToWorkList(SCC.Val); 5081 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 5082 5083 // fold select_cc true, x, y -> x 5084 if (SCCC && SCCC->getValue()) 5085 return N2; 5086 // fold select_cc false, x, y -> y 5087 if (SCCC && SCCC->getValue() == 0) 5088 return N3; 5089 5090 // Check to see if we can simplify the select into an fabs node 5091 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5092 // Allow either -0.0 or 0.0 5093 if (CFP->getValueAPF().isZero()) { 5094 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5095 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5096 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5097 N2 == N3.getOperand(0)) 5098 return DAG.getNode(ISD::FABS, VT, N0); 5099 5100 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5101 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5102 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5103 N2.getOperand(0) == N3) 5104 return DAG.getNode(ISD::FABS, VT, N3); 5105 } 5106 } 5107 5108 // Check to see if we can perform the "gzip trick", transforming 5109 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5110 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5111 MVT::isInteger(N0.getValueType()) && 5112 MVT::isInteger(N2.getValueType()) && 5113 (N1C->isNullValue() || // (a < 0) ? b : 0 5114 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5115 MVT::ValueType XType = N0.getValueType(); 5116 MVT::ValueType AType = N2.getValueType(); 5117 if (XType >= AType) { 5118 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5119 // single-bit constant. 5120 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 5121 unsigned ShCtV = Log2_64(N2C->getValue()); 5122 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 5123 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5124 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5125 AddToWorkList(Shift.Val); 5126 if (XType > AType) { 5127 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5128 AddToWorkList(Shift.Val); 5129 } 5130 return DAG.getNode(ISD::AND, AType, Shift, N2); 5131 } 5132 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5133 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5134 TLI.getShiftAmountTy())); 5135 AddToWorkList(Shift.Val); 5136 if (XType > AType) { 5137 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5138 AddToWorkList(Shift.Val); 5139 } 5140 return DAG.getNode(ISD::AND, AType, Shift, N2); 5141 } 5142 } 5143 5144 // fold select C, 16, 0 -> shl C, 4 5145 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 5146 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 5147 5148 // If the caller doesn't want us to simplify this into a zext of a compare, 5149 // don't do it. 5150 if (NotExtCompare && N2C->getValue() == 1) 5151 return SDOperand(); 5152 5153 // Get a SetCC of the condition 5154 // FIXME: Should probably make sure that setcc is legal if we ever have a 5155 // target where it isn't. 5156 SDOperand Temp, SCC; 5157 // cast from setcc result type to select result type 5158 if (AfterLegalize) { 5159 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 5160 if (N2.getValueType() < SCC.getValueType()) 5161 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5162 else 5163 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5164 } else { 5165 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5166 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5167 } 5168 AddToWorkList(SCC.Val); 5169 AddToWorkList(Temp.Val); 5170 5171 if (N2C->getValue() == 1) 5172 return Temp; 5173 // shl setcc result by log2 n2c 5174 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5175 DAG.getConstant(Log2_64(N2C->getValue()), 5176 TLI.getShiftAmountTy())); 5177 } 5178 5179 // Check to see if this is the equivalent of setcc 5180 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5181 // otherwise, go ahead with the folds. 5182 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 5183 MVT::ValueType XType = N0.getValueType(); 5184 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 5185 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 5186 if (Res.getValueType() != VT) 5187 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5188 return Res; 5189 } 5190 5191 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5192 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5193 TLI.isOperationLegal(ISD::CTLZ, XType)) { 5194 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5195 return DAG.getNode(ISD::SRL, XType, Ctlz, 5196 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 5197 TLI.getShiftAmountTy())); 5198 } 5199 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5200 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5201 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5202 N0); 5203 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5204 DAG.getConstant(~0ULL, XType)); 5205 return DAG.getNode(ISD::SRL, XType, 5206 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5207 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5208 TLI.getShiftAmountTy())); 5209 } 5210 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5211 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5212 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 5213 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5214 TLI.getShiftAmountTy())); 5215 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5216 } 5217 } 5218 5219 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5220 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5221 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5222 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5223 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 5224 MVT::ValueType XType = N0.getValueType(); 5225 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5226 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5227 TLI.getShiftAmountTy())); 5228 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5229 AddToWorkList(Shift.Val); 5230 AddToWorkList(Add.Val); 5231 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5232 } 5233 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5234 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5235 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5236 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5237 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5238 MVT::ValueType XType = N0.getValueType(); 5239 if (SubC->isNullValue() && MVT::isInteger(XType)) { 5240 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5241 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5242 TLI.getShiftAmountTy())); 5243 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5244 AddToWorkList(Shift.Val); 5245 AddToWorkList(Add.Val); 5246 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5247 } 5248 } 5249 } 5250 5251 return SDOperand(); 5252} 5253 5254/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5255SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 5256 SDOperand N1, ISD::CondCode Cond, 5257 bool foldBooleans) { 5258 TargetLowering::DAGCombinerInfo 5259 DagCombineInfo(DAG, !AfterLegalize, false, this); 5260 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5261} 5262 5263/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5264/// return a DAG expression to select that will generate the same value by 5265/// multiplying by a magic number. See: 5266/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5267SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 5268 std::vector<SDNode*> Built; 5269 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 5270 5271 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5272 ii != ee; ++ii) 5273 AddToWorkList(*ii); 5274 return S; 5275} 5276 5277/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5278/// return a DAG expression to select that will generate the same value by 5279/// multiplying by a magic number. See: 5280/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5281SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 5282 std::vector<SDNode*> Built; 5283 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 5284 5285 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5286 ii != ee; ++ii) 5287 AddToWorkList(*ii); 5288 return S; 5289} 5290 5291/// FindBaseOffset - Return true if base is known not to alias with anything 5292/// but itself. Provides base object and offset as results. 5293static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 5294 // Assume it is a primitive operation. 5295 Base = Ptr; Offset = 0; 5296 5297 // If it's an adding a simple constant then integrate the offset. 5298 if (Base.getOpcode() == ISD::ADD) { 5299 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5300 Base = Base.getOperand(0); 5301 Offset += C->getValue(); 5302 } 5303 } 5304 5305 // If it's any of the following then it can't alias with anything but itself. 5306 return isa<FrameIndexSDNode>(Base) || 5307 isa<ConstantPoolSDNode>(Base) || 5308 isa<GlobalAddressSDNode>(Base); 5309} 5310 5311/// isAlias - Return true if there is any possibility that the two addresses 5312/// overlap. 5313bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 5314 const Value *SrcValue1, int SrcValueOffset1, 5315 SDOperand Ptr2, int64_t Size2, 5316 const Value *SrcValue2, int SrcValueOffset2) 5317{ 5318 // If they are the same then they must be aliases. 5319 if (Ptr1 == Ptr2) return true; 5320 5321 // Gather base node and offset information. 5322 SDOperand Base1, Base2; 5323 int64_t Offset1, Offset2; 5324 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5325 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5326 5327 // If they have a same base address then... 5328 if (Base1 == Base2) { 5329 // Check to see if the addresses overlap. 5330 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5331 } 5332 5333 // If we know both bases then they can't alias. 5334 if (KnownBase1 && KnownBase2) return false; 5335 5336 if (CombinerGlobalAA) { 5337 // Use alias analysis information. 5338 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5339 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5340 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5341 AliasAnalysis::AliasResult AAResult = 5342 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5343 if (AAResult == AliasAnalysis::NoAlias) 5344 return false; 5345 } 5346 5347 // Otherwise we have to assume they alias. 5348 return true; 5349} 5350 5351/// FindAliasInfo - Extracts the relevant alias information from the memory 5352/// node. Returns true if the operand was a load. 5353bool DAGCombiner::FindAliasInfo(SDNode *N, 5354 SDOperand &Ptr, int64_t &Size, 5355 const Value *&SrcValue, int &SrcValueOffset) { 5356 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5357 Ptr = LD->getBasePtr(); 5358 Size = MVT::getSizeInBits(LD->getMemoryVT()) >> 3; 5359 SrcValue = LD->getSrcValue(); 5360 SrcValueOffset = LD->getSrcValueOffset(); 5361 return true; 5362 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5363 Ptr = ST->getBasePtr(); 5364 Size = MVT::getSizeInBits(ST->getMemoryVT()) >> 3; 5365 SrcValue = ST->getSrcValue(); 5366 SrcValueOffset = ST->getSrcValueOffset(); 5367 } else { 5368 assert(0 && "FindAliasInfo expected a memory operand"); 5369 } 5370 5371 return false; 5372} 5373 5374/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5375/// looking for aliasing nodes and adding them to the Aliases vector. 5376void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 5377 SmallVector<SDOperand, 8> &Aliases) { 5378 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 5379 std::set<SDNode *> Visited; // Visited node set. 5380 5381 // Get alias information for node. 5382 SDOperand Ptr; 5383 int64_t Size; 5384 const Value *SrcValue; 5385 int SrcValueOffset; 5386 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5387 5388 // Starting off. 5389 Chains.push_back(OriginalChain); 5390 5391 // Look at each chain and determine if it is an alias. If so, add it to the 5392 // aliases list. If not, then continue up the chain looking for the next 5393 // candidate. 5394 while (!Chains.empty()) { 5395 SDOperand Chain = Chains.back(); 5396 Chains.pop_back(); 5397 5398 // Don't bother if we've been before. 5399 if (Visited.find(Chain.Val) != Visited.end()) continue; 5400 Visited.insert(Chain.Val); 5401 5402 switch (Chain.getOpcode()) { 5403 case ISD::EntryToken: 5404 // Entry token is ideal chain operand, but handled in FindBetterChain. 5405 break; 5406 5407 case ISD::LOAD: 5408 case ISD::STORE: { 5409 // Get alias information for Chain. 5410 SDOperand OpPtr; 5411 int64_t OpSize; 5412 const Value *OpSrcValue; 5413 int OpSrcValueOffset; 5414 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 5415 OpSrcValue, OpSrcValueOffset); 5416 5417 // If chain is alias then stop here. 5418 if (!(IsLoad && IsOpLoad) && 5419 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5420 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5421 Aliases.push_back(Chain); 5422 } else { 5423 // Look further up the chain. 5424 Chains.push_back(Chain.getOperand(0)); 5425 // Clean up old chain. 5426 AddToWorkList(Chain.Val); 5427 } 5428 break; 5429 } 5430 5431 case ISD::TokenFactor: 5432 // We have to check each of the operands of the token factor, so we queue 5433 // then up. Adding the operands to the queue (stack) in reverse order 5434 // maintains the original order and increases the likelihood that getNode 5435 // will find a matching token factor (CSE.) 5436 for (unsigned n = Chain.getNumOperands(); n;) 5437 Chains.push_back(Chain.getOperand(--n)); 5438 // Eliminate the token factor if we can. 5439 AddToWorkList(Chain.Val); 5440 break; 5441 5442 default: 5443 // For all other instructions we will just have to take what we can get. 5444 Aliases.push_back(Chain); 5445 break; 5446 } 5447 } 5448} 5449 5450/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5451/// for a better chain (aliasing node.) 5452SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 5453 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 5454 5455 // Accumulate all the aliases to this node. 5456 GatherAllAliases(N, OldChain, Aliases); 5457 5458 if (Aliases.size() == 0) { 5459 // If no operands then chain to entry token. 5460 return DAG.getEntryNode(); 5461 } else if (Aliases.size() == 1) { 5462 // If a single operand then chain to it. We don't need to revisit it. 5463 return Aliases[0]; 5464 } 5465 5466 // Construct a custom tailored token factor. 5467 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5468 &Aliases[0], Aliases.size()); 5469 5470 // Make sure the old chain gets cleaned up. 5471 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 5472 5473 return NewChain; 5474} 5475 5476// SelectionDAG::Combine - This is the entry point for the file. 5477// 5478void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 5479 if (!RunningAfterLegalize && ViewDAGCombine1) 5480 viewGraph(); 5481 if (RunningAfterLegalize && ViewDAGCombine2) 5482 viewGraph(); 5483 /// run - This is the main entry point to this class. 5484 /// 5485 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 5486} 5487