TargetLowering.cpp revision a6bc5a4d2138ea3cba90f5a794dd525228ec2c73
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/Target/TargetMachine.h" 16#include "llvm/Target/MRegisterInfo.h" 17#include "llvm/CodeGen/SelectionDAG.h" 18#include "llvm/ADT/StringExtras.h" 19#include "llvm/Support/MathExtras.h" 20using namespace llvm; 21 22TargetLowering::TargetLowering(TargetMachine &tm) 23 : TM(tm), TD(TM.getTargetData()) { 24 assert(ISD::BUILTIN_OP_END <= 128 && 25 "Fixed size array in TargetLowering is not large enough!"); 26 // All operations default to being supported. 27 memset(OpActions, 0, sizeof(OpActions)); 28 29 IsLittleEndian = TD.isLittleEndian(); 30 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType()); 31 ShiftAmtHandling = Undefined; 32 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 33 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 34 allowUnalignedMemoryAccesses = false; 35 UseUnderscoreSetJmpLongJmp = false; 36 IntDivIsCheap = false; 37 Pow2DivIsCheap = false; 38 StackPointerRegisterToSaveRestore = 0; 39 SchedPreferenceInfo = SchedulingForLatency; 40} 41 42TargetLowering::~TargetLowering() {} 43 44/// setValueTypeAction - Set the action for a particular value type. This 45/// assumes an action has not already been set for this value type. 46static void SetValueTypeAction(MVT::ValueType VT, 47 TargetLowering::LegalizeAction Action, 48 TargetLowering &TLI, 49 MVT::ValueType *TransformToType, 50 TargetLowering::ValueTypeActionImpl &ValueTypeActions) { 51 ValueTypeActions.setTypeAction(VT, Action); 52 if (Action == TargetLowering::Promote) { 53 MVT::ValueType PromoteTo; 54 if (VT == MVT::f32) 55 PromoteTo = MVT::f64; 56 else { 57 unsigned LargerReg = VT+1; 58 while (!TLI.isTypeLegal((MVT::ValueType)LargerReg)) { 59 ++LargerReg; 60 assert(MVT::isInteger((MVT::ValueType)LargerReg) && 61 "Nothing to promote to??"); 62 } 63 PromoteTo = (MVT::ValueType)LargerReg; 64 } 65 66 assert(MVT::isInteger(VT) == MVT::isInteger(PromoteTo) && 67 MVT::isFloatingPoint(VT) == MVT::isFloatingPoint(PromoteTo) && 68 "Can only promote from int->int or fp->fp!"); 69 assert(VT < PromoteTo && "Must promote to a larger type!"); 70 TransformToType[VT] = PromoteTo; 71 } else if (Action == TargetLowering::Expand) { 72 assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 && 73 "Cannot expand this type: target must support SOME integer reg!"); 74 // Expand to the next smaller integer type! 75 TransformToType[VT] = (MVT::ValueType)(VT-1); 76 } 77} 78 79 80/// computeRegisterProperties - Once all of the register classes are added, 81/// this allows us to compute derived properties we expose. 82void TargetLowering::computeRegisterProperties() { 83 assert(MVT::LAST_VALUETYPE <= 32 && 84 "Too many value types for ValueTypeActions to hold!"); 85 86 // Everything defaults to one. 87 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) 88 NumElementsForVT[i] = 1; 89 90 // Find the largest integer register class. 91 unsigned LargestIntReg = MVT::i128; 92 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 93 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 94 95 // Every integer value type larger than this largest register takes twice as 96 // many registers to represent as the previous ValueType. 97 unsigned ExpandedReg = LargestIntReg; ++LargestIntReg; 98 for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg) 99 NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1]; 100 101 // Inspect all of the ValueType's possible, deciding how to process them. 102 for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg) 103 // If we are expanding this type, expand it! 104 if (getNumElements((MVT::ValueType)IntReg) != 1) 105 SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType, 106 ValueTypeActions); 107 else if (!isTypeLegal((MVT::ValueType)IntReg)) 108 // Otherwise, if we don't have native support, we must promote to a 109 // larger type. 110 SetValueTypeAction((MVT::ValueType)IntReg, Promote, *this, 111 TransformToType, ValueTypeActions); 112 else 113 TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg; 114 115 // If the target does not have native support for F32, promote it to F64. 116 if (!isTypeLegal(MVT::f32)) 117 SetValueTypeAction(MVT::f32, Promote, *this, 118 TransformToType, ValueTypeActions); 119 else 120 TransformToType[MVT::f32] = MVT::f32; 121 122 // Set MVT::Vector to always be Expanded 123 SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType, 124 ValueTypeActions); 125 126 assert(isTypeLegal(MVT::f64) && "Target does not support FP?"); 127 TransformToType[MVT::f64] = MVT::f64; 128} 129 130const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 131 return NULL; 132} 133 134//===----------------------------------------------------------------------===// 135// Optimization Methods 136//===----------------------------------------------------------------------===// 137 138/// ShrinkDemandedConstant - Check to see if the specified operand of the 139/// specified instruction is a constant integer. If so, check to see if there 140/// are any bits set in the constant that are not demanded. If so, shrink the 141/// constant and return true. 142bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op, 143 uint64_t Demanded) { 144 // FIXME: ISD::SELECT, ISD::SELECT_CC 145 switch(Op.getOpcode()) { 146 default: break; 147 case ISD::AND: 148 case ISD::OR: 149 case ISD::XOR: 150 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 151 if ((~Demanded & C->getValue()) != 0) { 152 MVT::ValueType VT = Op.getValueType(); 153 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 154 DAG.getConstant(Demanded & C->getValue(), 155 VT)); 156 return CombineTo(Op, New); 157 } 158 break; 159 } 160 return false; 161} 162 163/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 164/// DemandedMask bits of the result of Op are ever used downstream. If we can 165/// use this information to simplify Op, create a new simplified DAG node and 166/// return true, returning the original and new nodes in Old and New. Otherwise, 167/// analyze the expression and return a mask of KnownOne and KnownZero bits for 168/// the expression (used to simplify the caller). The KnownZero/One bits may 169/// only be accurate for those bits in the DemandedMask. 170bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 171 uint64_t &KnownZero, 172 uint64_t &KnownOne, 173 TargetLoweringOpt &TLO, 174 unsigned Depth) const { 175 KnownZero = KnownOne = 0; // Don't know anything. 176 // Other users may use these bits. 177 if (!Op.Val->hasOneUse()) { 178 if (Depth != 0) { 179 // If not at the root, Just compute the KnownZero/KnownOne bits to 180 // simplify things downstream. 181 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 182 return false; 183 } 184 // If this is the root being simplified, allow it to have multiple uses, 185 // just set the DemandedMask to all bits. 186 DemandedMask = MVT::getIntVTBitMask(Op.getValueType()); 187 } else if (DemandedMask == 0) { 188 // Not demanding any bits from Op. 189 if (Op.getOpcode() != ISD::UNDEF) 190 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 191 return false; 192 } else if (Depth == 6) { // Limit search depth. 193 return false; 194 } 195 196 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 197 switch (Op.getOpcode()) { 198 case ISD::Constant: 199 // We know all of the bits for a constant! 200 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask; 201 KnownZero = ~KnownOne & DemandedMask; 202 return false; // Don't fall through, will infinitely loop. 203 case ISD::AND: 204 // If the RHS is a constant, check to see if the LHS would be zero without 205 // using the bits from the RHS. Below, we use knowledge about the RHS to 206 // simplify the LHS, here we're using information from the LHS to simplify 207 // the RHS. 208 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 209 uint64_t LHSZero, LHSOne; 210 ComputeMaskedBits(Op.getOperand(0), DemandedMask, 211 LHSZero, LHSOne, Depth+1); 212 // If the LHS already has zeros where RHSC does, this and is dead. 213 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask)) 214 return TLO.CombineTo(Op, Op.getOperand(0)); 215 // If any of the set bits in the RHS are known zero on the LHS, shrink 216 // the constant. 217 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask)) 218 return true; 219 } 220 221 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 222 KnownOne, TLO, Depth+1)) 223 return true; 224 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 225 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero, 226 KnownZero2, KnownOne2, TLO, Depth+1)) 227 return true; 228 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 229 230 // If all of the demanded bits are known one on one side, return the other. 231 // These bits cannot contribute to the result of the 'and'. 232 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2)) 233 return TLO.CombineTo(Op, Op.getOperand(0)); 234 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero)) 235 return TLO.CombineTo(Op, Op.getOperand(1)); 236 // If all of the demanded bits in the inputs are known zeros, return zero. 237 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask) 238 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 239 // If the RHS is a constant, see if we can simplify it. 240 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2)) 241 return true; 242 243 // Output known-1 bits are only known if set in both the LHS & RHS. 244 KnownOne &= KnownOne2; 245 // Output known-0 are known to be clear if zero in either the LHS | RHS. 246 KnownZero |= KnownZero2; 247 break; 248 case ISD::OR: 249 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 250 KnownOne, TLO, Depth+1)) 251 return true; 252 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 253 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne, 254 KnownZero2, KnownOne2, TLO, Depth+1)) 255 return true; 256 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 257 258 // If all of the demanded bits are known zero on one side, return the other. 259 // These bits cannot contribute to the result of the 'or'. 260 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2)) 261 return TLO.CombineTo(Op, Op.getOperand(0)); 262 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne)) 263 return TLO.CombineTo(Op, Op.getOperand(1)); 264 // If all of the potentially set bits on one side are known to be set on 265 // the other side, just use the 'other' side. 266 if ((DemandedMask & (~KnownZero) & KnownOne2) == 267 (DemandedMask & (~KnownZero))) 268 return TLO.CombineTo(Op, Op.getOperand(0)); 269 if ((DemandedMask & (~KnownZero2) & KnownOne) == 270 (DemandedMask & (~KnownZero2))) 271 return TLO.CombineTo(Op, Op.getOperand(1)); 272 // If the RHS is a constant, see if we can simplify it. 273 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 274 return true; 275 276 // Output known-0 bits are only known if clear in both the LHS & RHS. 277 KnownZero &= KnownZero2; 278 // Output known-1 are known to be set if set in either the LHS | RHS. 279 KnownOne |= KnownOne2; 280 break; 281 case ISD::XOR: 282 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 283 KnownOne, TLO, Depth+1)) 284 return true; 285 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 286 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2, 287 KnownOne2, TLO, Depth+1)) 288 return true; 289 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 290 291 // If all of the demanded bits are known zero on one side, return the other. 292 // These bits cannot contribute to the result of the 'xor'. 293 if ((DemandedMask & KnownZero) == DemandedMask) 294 return TLO.CombineTo(Op, Op.getOperand(0)); 295 if ((DemandedMask & KnownZero2) == DemandedMask) 296 return TLO.CombineTo(Op, Op.getOperand(1)); 297 298 // Output known-0 bits are known if clear or set in both the LHS & RHS. 299 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 300 // Output known-1 are known to be set if set in only one of the LHS, RHS. 301 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 302 303 // If all of the unknown bits are known to be zero on one side or the other 304 // (but not both) turn this into an *inclusive* or. 305 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 306 if (uint64_t UnknownBits = DemandedMask & ~(KnownZeroOut|KnownOneOut)) 307 if ((UnknownBits & (KnownZero|KnownZero2)) == UnknownBits) 308 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 309 Op.getOperand(0), 310 Op.getOperand(1))); 311 // If all of the demanded bits on one side are known, and all of the set 312 // bits on that side are also known to be set on the other side, turn this 313 // into an AND, as we know the bits will be cleared. 314 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 315 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known 316 if ((KnownOne & KnownOne2) == KnownOne) { 317 MVT::ValueType VT = Op.getValueType(); 318 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT); 319 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 320 ANDC)); 321 } 322 } 323 324 // If the RHS is a constant, see if we can simplify it. 325 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1. 326 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 327 return true; 328 329 KnownZero = KnownZeroOut; 330 KnownOne = KnownOneOut; 331 break; 332 case ISD::SETCC: 333 // If we know the result of a setcc has the top bits zero, use this info. 334 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) 335 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 336 break; 337 case ISD::SELECT: 338 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero, 339 KnownOne, TLO, Depth+1)) 340 return true; 341 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2, 342 KnownOne2, TLO, Depth+1)) 343 return true; 344 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 345 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 346 347 // If the operands are constants, see if we can simplify them. 348 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 349 return true; 350 351 // Only known if known in both the LHS and RHS. 352 KnownOne &= KnownOne2; 353 KnownZero &= KnownZero2; 354 break; 355 case ISD::SELECT_CC: 356 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero, 357 KnownOne, TLO, Depth+1)) 358 return true; 359 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2, 360 KnownOne2, TLO, Depth+1)) 361 return true; 362 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 363 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 364 365 // If the operands are constants, see if we can simplify them. 366 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 367 return true; 368 369 // Only known if known in both the LHS and RHS. 370 KnownOne &= KnownOne2; 371 KnownZero &= KnownZero2; 372 break; 373 case ISD::SHL: 374 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 375 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> SA->getValue(), 376 KnownZero, KnownOne, TLO, Depth+1)) 377 return true; 378 KnownZero <<= SA->getValue(); 379 KnownOne <<= SA->getValue(); 380 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. 381 } 382 break; 383 case ISD::SRL: 384 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 385 MVT::ValueType VT = Op.getValueType(); 386 unsigned ShAmt = SA->getValue(); 387 388 // Compute the new bits that are at the top now. 389 uint64_t HighBits = (1ULL << ShAmt)-1; 390 HighBits <<= MVT::getSizeInBits(VT) - ShAmt; 391 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 392 393 if (SimplifyDemandedBits(Op.getOperand(0), 394 (DemandedMask << ShAmt) & TypeMask, 395 KnownZero, KnownOne, TLO, Depth+1)) 396 return true; 397 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 398 KnownZero &= TypeMask; 399 KnownOne &= TypeMask; 400 KnownZero >>= ShAmt; 401 KnownOne >>= ShAmt; 402 KnownZero |= HighBits; // high bits known zero. 403 } 404 break; 405 case ISD::SRA: 406 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 407 MVT::ValueType VT = Op.getValueType(); 408 unsigned ShAmt = SA->getValue(); 409 410 // Compute the new bits that are at the top now. 411 uint64_t HighBits = (1ULL << ShAmt)-1; 412 HighBits <<= MVT::getSizeInBits(VT) - ShAmt; 413 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 414 415 if (SimplifyDemandedBits(Op.getOperand(0), 416 (DemandedMask << ShAmt) & TypeMask, 417 KnownZero, KnownOne, TLO, Depth+1)) 418 return true; 419 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 420 KnownZero &= TypeMask; 421 KnownOne &= TypeMask; 422 KnownZero >>= SA->getValue(); 423 KnownOne >>= SA->getValue(); 424 425 // Handle the sign bits. 426 uint64_t SignBit = MVT::getIntVTSignBit(VT); 427 SignBit >>= SA->getValue(); // Adjust to where it is now in the mask. 428 429 // If the input sign bit is known to be zero, or if none of the top bits 430 // are demanded, turn this into an unsigned shift right. 431 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) { 432 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 433 Op.getOperand(1))); 434 } else if (KnownOne & SignBit) { // New bits are known one. 435 KnownOne |= HighBits; 436 } 437 } 438 break; 439 case ISD::SIGN_EXTEND_INREG: { 440 MVT::ValueType VT = Op.getValueType(); 441 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 442 443 // Sign extension. Compute the demanded bits in the result that are not 444 // present in the input. 445 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask; 446 447 // If none of the extended bits are demanded, eliminate the sextinreg. 448 if (NewBits == 0) 449 return TLO.CombineTo(Op, Op.getOperand(0)); 450 451 uint64_t InSignBit = MVT::getIntVTSignBit(EVT); 452 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT); 453 454 // Since the sign extended bits are demanded, we know that the sign 455 // bit is demanded. 456 InputDemandedBits |= InSignBit; 457 458 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 459 KnownZero, KnownOne, TLO, Depth+1)) 460 return true; 461 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 462 463 // If the sign bit of the input is known set or clear, then we know the 464 // top bits of the result. 465 466 // If the input sign bit is known zero, convert this into a zero extension. 467 if (KnownZero & InSignBit) 468 return TLO.CombineTo(Op, 469 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); 470 471 if (KnownOne & InSignBit) { // Input sign bit known set 472 KnownOne |= NewBits; 473 KnownZero &= ~NewBits; 474 } else { // Input sign bit unknown 475 KnownZero &= ~NewBits; 476 KnownOne &= ~NewBits; 477 } 478 break; 479 } 480 case ISD::CTTZ: 481 case ISD::CTLZ: 482 case ISD::CTPOP: { 483 MVT::ValueType VT = Op.getValueType(); 484 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1; 485 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT); 486 KnownOne = 0; 487 break; 488 } 489 case ISD::ZEXTLOAD: { 490 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT(); 491 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask; 492 break; 493 } 494 case ISD::ZERO_EXTEND: { 495 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 496 497 // If none of the top bits are demanded, convert this into an any_extend. 498 uint64_t NewBits = (~InMask) & DemandedMask; 499 if (NewBits == 0) 500 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, 501 Op.getValueType(), 502 Op.getOperand(0))); 503 504 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 505 KnownZero, KnownOne, TLO, Depth+1)) 506 return true; 507 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 508 KnownZero |= NewBits; 509 break; 510 } 511 case ISD::SIGN_EXTEND: { 512 MVT::ValueType InVT = Op.getOperand(0).getValueType(); 513 uint64_t InMask = MVT::getIntVTBitMask(InVT); 514 uint64_t InSignBit = MVT::getIntVTSignBit(InVT); 515 uint64_t NewBits = (~InMask) & DemandedMask; 516 517 // If none of the top bits are demanded, convert this into an any_extend. 518 if (NewBits == 0) 519 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), 520 Op.getOperand(0))); 521 522 // Since some of the sign extended bits are demanded, we know that the sign 523 // bit is demanded. 524 uint64_t InDemandedBits = DemandedMask & InMask; 525 InDemandedBits |= InSignBit; 526 527 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 528 KnownOne, TLO, Depth+1)) 529 return true; 530 531 // If the sign bit is known zero, convert this to a zero extend. 532 if (KnownZero & InSignBit) 533 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, 534 Op.getValueType(), 535 Op.getOperand(0))); 536 537 // If the sign bit is known one, the top bits match. 538 if (KnownOne & InSignBit) { 539 KnownOne |= NewBits; 540 KnownZero &= ~NewBits; 541 } else { // Otherwise, top bits aren't known. 542 KnownOne &= ~NewBits; 543 KnownZero &= ~NewBits; 544 } 545 break; 546 } 547 case ISD::ANY_EXTEND: { 548 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 549 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 550 KnownZero, KnownOne, TLO, Depth+1)) 551 return true; 552 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 553 break; 554 } 555 case ISD::AssertZext: { 556 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 557 uint64_t InMask = MVT::getIntVTBitMask(VT); 558 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 559 KnownZero, KnownOne, TLO, Depth+1)) 560 return true; 561 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 562 KnownZero |= ~InMask & DemandedMask; 563 break; 564 } 565 case ISD::ADD: 566 if (ConstantSDNode *AA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 567 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero, 568 KnownOne, TLO, Depth+1)) 569 return true; 570 // Compute the KnownOne/KnownZero masks for the constant, so we can set 571 // KnownZero appropriately if we're adding a constant that has all low 572 // bits cleared. 573 ComputeMaskedBits(Op.getOperand(1), 574 MVT::getIntVTBitMask(Op.getValueType()), 575 KnownZero2, KnownOne2, Depth+1); 576 577 uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero), 578 CountTrailingZeros_64(~KnownZero2)); 579 KnownZero = (1ULL << KnownZeroOut) - 1; 580 KnownOne = 0; 581 582 SDOperand SH = Op.getOperand(0); 583 // fold (add (shl x, c1), (shl c2, c1)) -> (shl (add x, c2), c1) 584 if (KnownZero && SH.getOpcode() == ISD::SHL && SH.Val->hasOneUse() && 585 Op.Val->hasOneUse()) { 586 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(SH.getOperand(1))) { 587 MVT::ValueType VT = Op.getValueType(); 588 unsigned ShiftAmt = SA->getValue(); 589 uint64_t AddAmt = AA->getValue(); 590 uint64_t AddShr = AddAmt >> ShiftAmt; 591 if (AddAmt == (AddShr << ShiftAmt)) { 592 SDOperand ADD = TLO.DAG.getNode(ISD::ADD, VT, SH.getOperand(0), 593 TLO.DAG.getConstant(AddShr, VT)); 594 SDOperand SHL = TLO.DAG.getNode(ISD::SHL, VT, ADD,SH.getOperand(1)); 595 return TLO.CombineTo(Op, SHL); 596 } 597 } 598 } 599 } 600 break; 601 case ISD::SUB: 602 // Just use ComputeMaskedBits to compute output bits, there are no 603 // simplifications that can be done here, and sub always demands all input 604 // bits. 605 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 606 break; 607 } 608 609 // If we know the value of all of the demanded bits, return this as a 610 // constant. 611 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) 612 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 613 614 return false; 615} 616 617/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 618/// this predicate to simplify operations downstream. Mask is known to be zero 619/// for bits that V cannot have. 620bool TargetLowering::MaskedValueIsZero(SDOperand Op, uint64_t Mask, 621 unsigned Depth) const { 622 uint64_t KnownZero, KnownOne; 623 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 624 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 625 return (KnownZero & Mask) == Mask; 626} 627 628/// ComputeMaskedBits - Determine which of the bits specified in Mask are 629/// known to be either zero or one and return them in the KnownZero/KnownOne 630/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 631/// processing. 632void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask, 633 uint64_t &KnownZero, uint64_t &KnownOne, 634 unsigned Depth) const { 635 KnownZero = KnownOne = 0; // Don't know anything. 636 if (Depth == 6 || Mask == 0) 637 return; // Limit search depth. 638 639 uint64_t KnownZero2, KnownOne2; 640 641 switch (Op.getOpcode()) { 642 case ISD::Constant: 643 // We know all of the bits for a constant! 644 KnownOne = cast<ConstantSDNode>(Op)->getValue() & Mask; 645 KnownZero = ~KnownOne & Mask; 646 return; 647 case ISD::AND: 648 // If either the LHS or the RHS are Zero, the result is zero. 649 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 650 Mask &= ~KnownZero; 651 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 652 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 653 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 654 655 // Output known-1 bits are only known if set in both the LHS & RHS. 656 KnownOne &= KnownOne2; 657 // Output known-0 are known to be clear if zero in either the LHS | RHS. 658 KnownZero |= KnownZero2; 659 return; 660 case ISD::OR: 661 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 662 Mask &= ~KnownOne; 663 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 664 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 665 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 666 667 // Output known-0 bits are only known if clear in both the LHS & RHS. 668 KnownZero &= KnownZero2; 669 // Output known-1 are known to be set if set in either the LHS | RHS. 670 KnownOne |= KnownOne2; 671 return; 672 case ISD::XOR: { 673 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 674 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 675 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 676 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 677 678 // Output known-0 bits are known if clear or set in both the LHS & RHS. 679 uint64_t KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 680 // Output known-1 are known to be set if set in only one of the LHS, RHS. 681 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 682 KnownZero = KnownZeroOut; 683 return; 684 } 685 case ISD::SELECT: 686 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 687 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 688 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 689 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 690 691 // Only known if known in both the LHS and RHS. 692 KnownOne &= KnownOne2; 693 KnownZero &= KnownZero2; 694 return; 695 case ISD::SELECT_CC: 696 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 697 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 698 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 699 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 700 701 // Only known if known in both the LHS and RHS. 702 KnownOne &= KnownOne2; 703 KnownZero &= KnownZero2; 704 return; 705 case ISD::SETCC: 706 // If we know the result of a setcc has the top bits zero, use this info. 707 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) 708 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 709 return; 710 case ISD::SHL: 711 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 712 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 713 Mask >>= SA->getValue(); 714 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 715 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 716 KnownZero <<= SA->getValue(); 717 KnownOne <<= SA->getValue(); 718 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. 719 } 720 return; 721 case ISD::SRL: 722 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 723 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 724 uint64_t HighBits = (1ULL << SA->getValue())-1; 725 HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue(); 726 Mask <<= SA->getValue(); 727 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 728 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 729 KnownZero >>= SA->getValue(); 730 KnownOne >>= SA->getValue(); 731 KnownZero |= HighBits; // high bits known zero. 732 } 733 return; 734 case ISD::SRA: 735 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 736 uint64_t HighBits = (1ULL << SA->getValue())-1; 737 HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue(); 738 Mask <<= SA->getValue(); 739 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 740 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 741 KnownZero >>= SA->getValue(); 742 KnownOne >>= SA->getValue(); 743 744 // Handle the sign bits. 745 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(Op.getValueType())-1); 746 SignBit >>= SA->getValue(); // Adjust to where it is now in the mask. 747 748 if (KnownZero & SignBit) { // New bits are known zero. 749 KnownZero |= HighBits; 750 } else if (KnownOne & SignBit) { // New bits are known one. 751 KnownOne |= HighBits; 752 } 753 } 754 return; 755 case ISD::SIGN_EXTEND_INREG: { 756 MVT::ValueType VT = Op.getValueType(); 757 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 758 759 // Sign extension. Compute the demanded bits in the result that are not 760 // present in the input. 761 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & Mask; 762 763 uint64_t InSignBit = MVT::getIntVTSignBit(EVT); 764 int64_t InputDemandedBits = Mask & MVT::getIntVTBitMask(EVT); 765 766 // If the sign extended bits are demanded, we know that the sign 767 // bit is demanded. 768 if (NewBits) 769 InputDemandedBits |= InSignBit; 770 771 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 772 KnownZero, KnownOne, Depth+1); 773 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 774 775 // If the sign bit of the input is known set or clear, then we know the 776 // top bits of the result. 777 if (KnownZero & InSignBit) { // Input sign bit known clear 778 KnownZero |= NewBits; 779 KnownOne &= ~NewBits; 780 } else if (KnownOne & InSignBit) { // Input sign bit known set 781 KnownOne |= NewBits; 782 KnownZero &= ~NewBits; 783 } else { // Input sign bit unknown 784 KnownZero &= ~NewBits; 785 KnownOne &= ~NewBits; 786 } 787 return; 788 } 789 case ISD::CTTZ: 790 case ISD::CTLZ: 791 case ISD::CTPOP: { 792 MVT::ValueType VT = Op.getValueType(); 793 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1; 794 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT); 795 KnownOne = 0; 796 return; 797 } 798 case ISD::ZEXTLOAD: { 799 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT(); 800 KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask; 801 return; 802 } 803 case ISD::ZERO_EXTEND: { 804 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 805 uint64_t NewBits = (~InMask) & Mask; 806 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 807 KnownOne, Depth+1); 808 KnownZero |= NewBits & Mask; 809 KnownOne &= ~NewBits; 810 return; 811 } 812 case ISD::SIGN_EXTEND: { 813 MVT::ValueType InVT = Op.getOperand(0).getValueType(); 814 unsigned InBits = MVT::getSizeInBits(InVT); 815 uint64_t InMask = MVT::getIntVTBitMask(InVT); 816 uint64_t InSignBit = 1ULL << (InBits-1); 817 uint64_t NewBits = (~InMask) & Mask; 818 uint64_t InDemandedBits = Mask & InMask; 819 820 // If any of the sign extended bits are demanded, we know that the sign 821 // bit is demanded. 822 if (NewBits & Mask) 823 InDemandedBits |= InSignBit; 824 825 ComputeMaskedBits(Op.getOperand(0), InDemandedBits, KnownZero, 826 KnownOne, Depth+1); 827 // If the sign bit is known zero or one, the top bits match. 828 if (KnownZero & InSignBit) { 829 KnownZero |= NewBits; 830 KnownOne &= ~NewBits; 831 } else if (KnownOne & InSignBit) { 832 KnownOne |= NewBits; 833 KnownZero &= ~NewBits; 834 } else { // Otherwise, top bits aren't known. 835 KnownOne &= ~NewBits; 836 KnownZero &= ~NewBits; 837 } 838 return; 839 } 840 case ISD::ANY_EXTEND: { 841 MVT::ValueType VT = Op.getOperand(0).getValueType(); 842 ComputeMaskedBits(Op.getOperand(0), Mask & MVT::getIntVTBitMask(VT), 843 KnownZero, KnownOne, Depth+1); 844 return; 845 } 846 case ISD::AssertZext: { 847 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 848 uint64_t InMask = MVT::getIntVTBitMask(VT); 849 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 850 KnownOne, Depth+1); 851 KnownZero |= (~InMask) & Mask; 852 return; 853 } 854 case ISD::ADD: { 855 // If either the LHS or the RHS are Zero, the result is zero. 856 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 857 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 858 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 859 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 860 861 // Output known-0 bits are known if clear or set in both the low clear bits 862 // common to both LHS & RHS; 863 uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero), 864 CountTrailingZeros_64(~KnownZero2)); 865 866 KnownZero = (1ULL << KnownZeroOut) - 1; 867 KnownOne = 0; 868 return; 869 } 870 case ISD::SUB: { 871 ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 872 if (!CLHS) return; 873 874 // We know that the top bits of C-X are clear if X contains less bits 875 // than C (i.e. no wrap-around can happen). For example, 20-X is 876 // positive if we can prove that X is >= 0 and < 16. 877 MVT::ValueType VT = CLHS->getValueType(0); 878 if ((CLHS->getValue() & MVT::getIntVTSignBit(VT)) == 0) { // sign bit clear 879 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1); 880 uint64_t MaskV = (1ULL << (63-NLZ))-1; // NLZ can't be 64 with no sign bit 881 MaskV = ~MaskV & MVT::getIntVTBitMask(VT); 882 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero, KnownOne, Depth+1); 883 884 // If all of the MaskV bits are known to be zero, then we know the output 885 // top bits are zero, because we now know that the output is from [0-C]. 886 if ((KnownZero & MaskV) == MaskV) { 887 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue()); 888 KnownZero = ~((1ULL << (64-NLZ2))-1) & Mask; // Top bits known zero. 889 KnownOne = 0; // No one bits known. 890 } else { 891 KnownOne = KnownOne = 0; // Otherwise, nothing known. 892 } 893 } 894 return; 895 } 896 default: 897 // Allow the target to implement this method for its nodes. 898 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) 899 computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne); 900 return; 901 } 902} 903 904/// computeMaskedBitsForTargetNode - Determine which of the bits specified 905/// in Mask are known to be either zero or one and return them in the 906/// KnownZero/KnownOne bitsets. 907void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 908 uint64_t Mask, 909 uint64_t &KnownZero, 910 uint64_t &KnownOne, 911 unsigned Depth) const { 912 assert(Op.getOpcode() >= ISD::BUILTIN_OP_END && 913 "Should use MaskedValueIsZero if you don't know whether Op" 914 " is a target node!"); 915 KnownZero = 0; 916 KnownOne = 0; 917} 918 919//===----------------------------------------------------------------------===// 920// Inline Assembler Implementation Methods 921//===----------------------------------------------------------------------===// 922 923TargetLowering::ConstraintType 924TargetLowering::getConstraintType(char ConstraintLetter) const { 925 // FIXME: lots more standard ones to handle. 926 switch (ConstraintLetter) { 927 default: return C_Unknown; 928 case 'r': return C_RegisterClass; 929 case 'm': // memory 930 case 'o': // offsetable 931 case 'V': // not offsetable 932 return C_Memory; 933 case 'i': // Simple Integer or Relocatable Constant 934 case 'n': // Simple Integer 935 case 's': // Relocatable Constant 936 case 'I': // Target registers. 937 case 'J': 938 case 'K': 939 case 'L': 940 case 'M': 941 case 'N': 942 case 'O': 943 case 'P': 944 return C_Other; 945 } 946} 947 948bool TargetLowering::isOperandValidForConstraint(SDOperand Op, 949 char ConstraintLetter) { 950 switch (ConstraintLetter) { 951 default: return false; 952 case 'i': // Simple Integer or Relocatable Constant 953 case 'n': // Simple Integer 954 case 's': // Relocatable Constant 955 return true; // FIXME: not right. 956 } 957} 958 959 960std::vector<unsigned> TargetLowering:: 961getRegClassForInlineAsmConstraint(const std::string &Constraint, 962 MVT::ValueType VT) const { 963 return std::vector<unsigned>(); 964} 965 966 967std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 968getRegForInlineAsmConstraint(const std::string &Constraint, 969 MVT::ValueType VT) const { 970 if (Constraint[0] != '{') 971 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 972 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 973 974 // Remove the braces from around the name. 975 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 976 977 // Figure out which register class contains this reg. 978 const MRegisterInfo *RI = TM.getRegisterInfo(); 979 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 980 E = RI->regclass_end(); RCI != E; ++RCI) { 981 const TargetRegisterClass *RC = *RCI; 982 983 // If none of the the value types for this register class are valid, we 984 // can't use it. For example, 64-bit reg classes on 32-bit targets. 985 bool isLegal = false; 986 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 987 I != E; ++I) { 988 if (isTypeLegal(*I)) { 989 isLegal = true; 990 break; 991 } 992 } 993 994 if (!isLegal) continue; 995 996 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 997 I != E; ++I) { 998 if (StringsEqualNoCase(RegName, RI->get(*I).Name)) 999 return std::make_pair(*I, RC); 1000 } 1001 } 1002 1003 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1004} 1005