TargetLowering.cpp revision b514ac9e3cddb3663c74afcf7bfa359a867e2780
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetAsmInfo.h" 15#include "llvm/Target/TargetLowering.h" 16#include "llvm/Target/TargetSubtarget.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetRegisterInfo.h" 20#include "llvm/GlobalVariable.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24#include "llvm/ADT/StringExtras.h" 25#include "llvm/ADT/STLExtras.h" 26#include "llvm/Support/MathExtras.h" 27using namespace llvm; 28 29/// InitLibcallNames - Set default libcall names. 30/// 31static void InitLibcallNames(const char **Names) { 32 Names[RTLIB::SHL_I32] = "__ashlsi3"; 33 Names[RTLIB::SHL_I64] = "__ashldi3"; 34 Names[RTLIB::SHL_I128] = "__ashlti3"; 35 Names[RTLIB::SRL_I32] = "__lshrsi3"; 36 Names[RTLIB::SRL_I64] = "__lshrdi3"; 37 Names[RTLIB::SRL_I128] = "__lshrti3"; 38 Names[RTLIB::SRA_I32] = "__ashrsi3"; 39 Names[RTLIB::SRA_I64] = "__ashrdi3"; 40 Names[RTLIB::SRA_I128] = "__ashrti3"; 41 Names[RTLIB::MUL_I32] = "__mulsi3"; 42 Names[RTLIB::MUL_I64] = "__muldi3"; 43 Names[RTLIB::MUL_I128] = "__multi3"; 44 Names[RTLIB::SDIV_I32] = "__divsi3"; 45 Names[RTLIB::SDIV_I64] = "__divdi3"; 46 Names[RTLIB::SDIV_I128] = "__divti3"; 47 Names[RTLIB::UDIV_I32] = "__udivsi3"; 48 Names[RTLIB::UDIV_I64] = "__udivdi3"; 49 Names[RTLIB::UDIV_I128] = "__udivti3"; 50 Names[RTLIB::SREM_I32] = "__modsi3"; 51 Names[RTLIB::SREM_I64] = "__moddi3"; 52 Names[RTLIB::SREM_I128] = "__modti3"; 53 Names[RTLIB::UREM_I32] = "__umodsi3"; 54 Names[RTLIB::UREM_I64] = "__umoddi3"; 55 Names[RTLIB::UREM_I128] = "__umodti3"; 56 Names[RTLIB::NEG_I32] = "__negsi2"; 57 Names[RTLIB::NEG_I64] = "__negdi2"; 58 Names[RTLIB::ADD_F32] = "__addsf3"; 59 Names[RTLIB::ADD_F64] = "__adddf3"; 60 Names[RTLIB::ADD_F80] = "__addxf3"; 61 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 62 Names[RTLIB::SUB_F32] = "__subsf3"; 63 Names[RTLIB::SUB_F64] = "__subdf3"; 64 Names[RTLIB::SUB_F80] = "__subxf3"; 65 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 66 Names[RTLIB::MUL_F32] = "__mulsf3"; 67 Names[RTLIB::MUL_F64] = "__muldf3"; 68 Names[RTLIB::MUL_F80] = "__mulxf3"; 69 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 70 Names[RTLIB::DIV_F32] = "__divsf3"; 71 Names[RTLIB::DIV_F64] = "__divdf3"; 72 Names[RTLIB::DIV_F80] = "__divxf3"; 73 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 74 Names[RTLIB::REM_F32] = "fmodf"; 75 Names[RTLIB::REM_F64] = "fmod"; 76 Names[RTLIB::REM_F80] = "fmodl"; 77 Names[RTLIB::REM_PPCF128] = "fmodl"; 78 Names[RTLIB::POWI_F32] = "__powisf2"; 79 Names[RTLIB::POWI_F64] = "__powidf2"; 80 Names[RTLIB::POWI_F80] = "__powixf2"; 81 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 82 Names[RTLIB::SQRT_F32] = "sqrtf"; 83 Names[RTLIB::SQRT_F64] = "sqrt"; 84 Names[RTLIB::SQRT_F80] = "sqrtl"; 85 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 86 Names[RTLIB::LOG_F32] = "logf"; 87 Names[RTLIB::LOG_F64] = "log"; 88 Names[RTLIB::LOG_F80] = "logl"; 89 Names[RTLIB::LOG_PPCF128] = "logl"; 90 Names[RTLIB::LOG2_F32] = "log2f"; 91 Names[RTLIB::LOG2_F64] = "log2"; 92 Names[RTLIB::LOG2_F80] = "log2l"; 93 Names[RTLIB::LOG2_PPCF128] = "log2l"; 94 Names[RTLIB::LOG10_F32] = "log10f"; 95 Names[RTLIB::LOG10_F64] = "log10"; 96 Names[RTLIB::LOG10_F80] = "log10l"; 97 Names[RTLIB::LOG10_PPCF128] = "log10l"; 98 Names[RTLIB::EXP_F32] = "expf"; 99 Names[RTLIB::EXP_F64] = "exp"; 100 Names[RTLIB::EXP_F80] = "expl"; 101 Names[RTLIB::EXP_PPCF128] = "expl"; 102 Names[RTLIB::EXP2_F32] = "exp2f"; 103 Names[RTLIB::EXP2_F64] = "exp2"; 104 Names[RTLIB::EXP2_F80] = "exp2l"; 105 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 106 Names[RTLIB::SIN_F32] = "sinf"; 107 Names[RTLIB::SIN_F64] = "sin"; 108 Names[RTLIB::SIN_F80] = "sinl"; 109 Names[RTLIB::SIN_PPCF128] = "sinl"; 110 Names[RTLIB::COS_F32] = "cosf"; 111 Names[RTLIB::COS_F64] = "cos"; 112 Names[RTLIB::COS_F80] = "cosl"; 113 Names[RTLIB::COS_PPCF128] = "cosl"; 114 Names[RTLIB::POW_F32] = "powf"; 115 Names[RTLIB::POW_F64] = "pow"; 116 Names[RTLIB::POW_F80] = "powl"; 117 Names[RTLIB::POW_PPCF128] = "powl"; 118 Names[RTLIB::CEIL_F32] = "ceilf"; 119 Names[RTLIB::CEIL_F64] = "ceil"; 120 Names[RTLIB::CEIL_F80] = "ceill"; 121 Names[RTLIB::CEIL_PPCF128] = "ceill"; 122 Names[RTLIB::TRUNC_F32] = "truncf"; 123 Names[RTLIB::TRUNC_F64] = "trunc"; 124 Names[RTLIB::TRUNC_F80] = "truncl"; 125 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 126 Names[RTLIB::RINT_F32] = "rintf"; 127 Names[RTLIB::RINT_F64] = "rint"; 128 Names[RTLIB::RINT_F80] = "rintl"; 129 Names[RTLIB::RINT_PPCF128] = "rintl"; 130 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 131 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 132 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 133 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 134 Names[RTLIB::FLOOR_F32] = "floorf"; 135 Names[RTLIB::FLOOR_F64] = "floor"; 136 Names[RTLIB::FLOOR_F80] = "floorl"; 137 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 138 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 139 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 140 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 141 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 142 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 143 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 144 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 145 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 146 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 147 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 148 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 149 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 150 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 151 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 152 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 153 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 154 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 155 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 156 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 157 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 158 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 159 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 160 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 161 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 162 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 163 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 164 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 165 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 166 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 167 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 168 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 169 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 170 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 171 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 172 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 173 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 174 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 175 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 176 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 177 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 178 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 179 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 180 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 181 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 182 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 183 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 184 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 185 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 186 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 187 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 188 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 189 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 190 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 191 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 192 Names[RTLIB::OEQ_F32] = "__eqsf2"; 193 Names[RTLIB::OEQ_F64] = "__eqdf2"; 194 Names[RTLIB::UNE_F32] = "__nesf2"; 195 Names[RTLIB::UNE_F64] = "__nedf2"; 196 Names[RTLIB::OGE_F32] = "__gesf2"; 197 Names[RTLIB::OGE_F64] = "__gedf2"; 198 Names[RTLIB::OLT_F32] = "__ltsf2"; 199 Names[RTLIB::OLT_F64] = "__ltdf2"; 200 Names[RTLIB::OLE_F32] = "__lesf2"; 201 Names[RTLIB::OLE_F64] = "__ledf2"; 202 Names[RTLIB::OGT_F32] = "__gtsf2"; 203 Names[RTLIB::OGT_F64] = "__gtdf2"; 204 Names[RTLIB::UO_F32] = "__unordsf2"; 205 Names[RTLIB::UO_F64] = "__unorddf2"; 206 Names[RTLIB::O_F32] = "__unordsf2"; 207 Names[RTLIB::O_F64] = "__unorddf2"; 208} 209 210/// getFPEXT - Return the FPEXT_*_* value for the given types, or 211/// UNKNOWN_LIBCALL if there is none. 212RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) { 213 if (OpVT == MVT::f32) { 214 if (RetVT == MVT::f64) 215 return FPEXT_F32_F64; 216 } 217 return UNKNOWN_LIBCALL; 218} 219 220/// getFPROUND - Return the FPROUND_*_* value for the given types, or 221/// UNKNOWN_LIBCALL if there is none. 222RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) { 223 if (RetVT == MVT::f32) { 224 if (OpVT == MVT::f64) 225 return FPROUND_F64_F32; 226 if (OpVT == MVT::f80) 227 return FPROUND_F80_F32; 228 if (OpVT == MVT::ppcf128) 229 return FPROUND_PPCF128_F32; 230 } else if (RetVT == MVT::f64) { 231 if (OpVT == MVT::f80) 232 return FPROUND_F80_F64; 233 if (OpVT == MVT::ppcf128) 234 return FPROUND_PPCF128_F64; 235 } 236 return UNKNOWN_LIBCALL; 237} 238 239/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 240/// UNKNOWN_LIBCALL if there is none. 241RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) { 242 if (OpVT == MVT::f32) { 243 if (RetVT == MVT::i32) 244 return FPTOSINT_F32_I32; 245 if (RetVT == MVT::i64) 246 return FPTOSINT_F32_I64; 247 if (RetVT == MVT::i128) 248 return FPTOSINT_F32_I128; 249 } else if (OpVT == MVT::f64) { 250 if (RetVT == MVT::i32) 251 return FPTOSINT_F64_I32; 252 if (RetVT == MVT::i64) 253 return FPTOSINT_F64_I64; 254 if (RetVT == MVT::i128) 255 return FPTOSINT_F64_I128; 256 } else if (OpVT == MVT::f80) { 257 if (RetVT == MVT::i32) 258 return FPTOSINT_F80_I32; 259 if (RetVT == MVT::i64) 260 return FPTOSINT_F80_I64; 261 if (RetVT == MVT::i128) 262 return FPTOSINT_F80_I128; 263 } else if (OpVT == MVT::ppcf128) { 264 if (RetVT == MVT::i32) 265 return FPTOSINT_PPCF128_I32; 266 if (RetVT == MVT::i64) 267 return FPTOSINT_PPCF128_I64; 268 if (RetVT == MVT::i128) 269 return FPTOSINT_PPCF128_I128; 270 } 271 return UNKNOWN_LIBCALL; 272} 273 274/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 275/// UNKNOWN_LIBCALL if there is none. 276RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) { 277 if (OpVT == MVT::f32) { 278 if (RetVT == MVT::i32) 279 return FPTOUINT_F32_I32; 280 if (RetVT == MVT::i64) 281 return FPTOUINT_F32_I64; 282 if (RetVT == MVT::i128) 283 return FPTOUINT_F32_I128; 284 } else if (OpVT == MVT::f64) { 285 if (RetVT == MVT::i32) 286 return FPTOUINT_F64_I32; 287 if (RetVT == MVT::i64) 288 return FPTOUINT_F64_I64; 289 if (RetVT == MVT::i128) 290 return FPTOUINT_F64_I128; 291 } else if (OpVT == MVT::f80) { 292 if (RetVT == MVT::i32) 293 return FPTOUINT_F80_I32; 294 if (RetVT == MVT::i64) 295 return FPTOUINT_F80_I64; 296 if (RetVT == MVT::i128) 297 return FPTOUINT_F80_I128; 298 } else if (OpVT == MVT::ppcf128) { 299 if (RetVT == MVT::i32) 300 return FPTOUINT_PPCF128_I32; 301 if (RetVT == MVT::i64) 302 return FPTOUINT_PPCF128_I64; 303 if (RetVT == MVT::i128) 304 return FPTOUINT_PPCF128_I128; 305 } 306 return UNKNOWN_LIBCALL; 307} 308 309/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 310/// UNKNOWN_LIBCALL if there is none. 311RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) { 312 if (OpVT == MVT::i32) { 313 if (RetVT == MVT::f32) 314 return SINTTOFP_I32_F32; 315 else if (RetVT == MVT::f64) 316 return SINTTOFP_I32_F64; 317 else if (RetVT == MVT::f80) 318 return SINTTOFP_I32_F80; 319 else if (RetVT == MVT::ppcf128) 320 return SINTTOFP_I32_PPCF128; 321 } else if (OpVT == MVT::i64) { 322 if (RetVT == MVT::f32) 323 return SINTTOFP_I64_F32; 324 else if (RetVT == MVT::f64) 325 return SINTTOFP_I64_F64; 326 else if (RetVT == MVT::f80) 327 return SINTTOFP_I64_F80; 328 else if (RetVT == MVT::ppcf128) 329 return SINTTOFP_I64_PPCF128; 330 } else if (OpVT == MVT::i128) { 331 if (RetVT == MVT::f32) 332 return SINTTOFP_I128_F32; 333 else if (RetVT == MVT::f64) 334 return SINTTOFP_I128_F64; 335 else if (RetVT == MVT::f80) 336 return SINTTOFP_I128_F80; 337 else if (RetVT == MVT::ppcf128) 338 return SINTTOFP_I128_PPCF128; 339 } 340 return UNKNOWN_LIBCALL; 341} 342 343/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 344/// UNKNOWN_LIBCALL if there is none. 345RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) { 346 if (OpVT == MVT::i32) { 347 if (RetVT == MVT::f32) 348 return UINTTOFP_I32_F32; 349 else if (RetVT == MVT::f64) 350 return UINTTOFP_I32_F64; 351 else if (RetVT == MVT::f80) 352 return UINTTOFP_I32_F80; 353 else if (RetVT == MVT::ppcf128) 354 return UINTTOFP_I32_PPCF128; 355 } else if (OpVT == MVT::i64) { 356 if (RetVT == MVT::f32) 357 return UINTTOFP_I64_F32; 358 else if (RetVT == MVT::f64) 359 return UINTTOFP_I64_F64; 360 else if (RetVT == MVT::f80) 361 return UINTTOFP_I64_F80; 362 else if (RetVT == MVT::ppcf128) 363 return UINTTOFP_I64_PPCF128; 364 } else if (OpVT == MVT::i128) { 365 if (RetVT == MVT::f32) 366 return UINTTOFP_I128_F32; 367 else if (RetVT == MVT::f64) 368 return UINTTOFP_I128_F64; 369 else if (RetVT == MVT::f80) 370 return UINTTOFP_I128_F80; 371 else if (RetVT == MVT::ppcf128) 372 return UINTTOFP_I128_PPCF128; 373 } 374 return UNKNOWN_LIBCALL; 375} 376 377/// InitCmpLibcallCCs - Set default comparison libcall CC. 378/// 379static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 380 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 381 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 382 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 383 CCs[RTLIB::UNE_F32] = ISD::SETNE; 384 CCs[RTLIB::UNE_F64] = ISD::SETNE; 385 CCs[RTLIB::OGE_F32] = ISD::SETGE; 386 CCs[RTLIB::OGE_F64] = ISD::SETGE; 387 CCs[RTLIB::OLT_F32] = ISD::SETLT; 388 CCs[RTLIB::OLT_F64] = ISD::SETLT; 389 CCs[RTLIB::OLE_F32] = ISD::SETLE; 390 CCs[RTLIB::OLE_F64] = ISD::SETLE; 391 CCs[RTLIB::OGT_F32] = ISD::SETGT; 392 CCs[RTLIB::OGT_F64] = ISD::SETGT; 393 CCs[RTLIB::UO_F32] = ISD::SETNE; 394 CCs[RTLIB::UO_F64] = ISD::SETNE; 395 CCs[RTLIB::O_F32] = ISD::SETEQ; 396 CCs[RTLIB::O_F64] = ISD::SETEQ; 397} 398 399TargetLowering::TargetLowering(TargetMachine &tm) 400 : TM(tm), TD(TM.getTargetData()) { 401 assert(ISD::BUILTIN_OP_END <= OpActionsCapacity && 402 "Fixed size array in TargetLowering is not large enough!"); 403 // All operations default to being supported. 404 memset(OpActions, 0, sizeof(OpActions)); 405 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 406 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 407 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 408 memset(ConvertActions, 0, sizeof(ConvertActions)); 409 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 410 411 // Set default actions for various operations. 412 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 413 // Default all indexed load / store to expand. 414 for (unsigned IM = (unsigned)ISD::PRE_INC; 415 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 416 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 417 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 418 } 419 420 // These operations default to expand. 421 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 422 } 423 424 // Most targets ignore the @llvm.prefetch intrinsic. 425 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 426 427 // ConstantFP nodes default to expand. Targets can either change this to 428 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate 429 // to optimize expansions for certain constants. 430 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 431 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 432 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 433 434 // These library functions default to expand. 435 setOperationAction(ISD::FLOG , MVT::f64, Expand); 436 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 437 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 438 setOperationAction(ISD::FEXP , MVT::f64, Expand); 439 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 440 setOperationAction(ISD::FLOG , MVT::f32, Expand); 441 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 442 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 443 setOperationAction(ISD::FEXP , MVT::f32, Expand); 444 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 445 446 // Default ISD::TRAP to expand (which turns it into abort). 447 setOperationAction(ISD::TRAP, MVT::Other, Expand); 448 449 IsLittleEndian = TD->isLittleEndian(); 450 UsesGlobalOffsetTable = false; 451 ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()); 452 ShiftAmtHandling = Undefined; 453 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 454 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 455 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 456 allowUnalignedMemoryAccesses = false; 457 UseUnderscoreSetJmp = false; 458 UseUnderscoreLongJmp = false; 459 SelectIsExpensive = false; 460 IntDivIsCheap = false; 461 Pow2DivIsCheap = false; 462 StackPointerRegisterToSaveRestore = 0; 463 ExceptionPointerRegister = 0; 464 ExceptionSelectorRegister = 0; 465 SetCCResultContents = UndefinedSetCCResult; 466 SchedPreferenceInfo = SchedulingForLatency; 467 JumpBufSize = 0; 468 JumpBufAlignment = 0; 469 IfCvtBlockSizeLimit = 2; 470 IfCvtDupBlockSizeLimit = 0; 471 PrefLoopAlignment = 0; 472 473 InitLibcallNames(LibcallRoutineNames); 474 InitCmpLibcallCCs(CmpLibcallCCs); 475 476 // Tell Legalize whether the assembler supports DEBUG_LOC. 477 const TargetAsmInfo *TASM = TM.getTargetAsmInfo(); 478 if (!TASM || !TASM->hasDotLocAndDotFile()) 479 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 480} 481 482TargetLowering::~TargetLowering() {} 483 484/// computeRegisterProperties - Once all of the register classes are added, 485/// this allows us to compute derived properties we expose. 486void TargetLowering::computeRegisterProperties() { 487 assert(MVT::LAST_VALUETYPE <= 32 && 488 "Too many value types for ValueTypeActions to hold!"); 489 490 // Everything defaults to needing one register. 491 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 492 NumRegistersForVT[i] = 1; 493 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 494 } 495 // ...except isVoid, which doesn't need any registers. 496 NumRegistersForVT[MVT::isVoid] = 0; 497 498 // Find the largest integer register class. 499 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 500 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 501 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 502 503 // Every integer value type larger than this largest register takes twice as 504 // many registers to represent as the previous ValueType. 505 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 506 MVT EVT = (MVT::SimpleValueType)ExpandedReg; 507 if (!EVT.isInteger()) 508 break; 509 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 510 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 511 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 512 ValueTypeActions.setTypeAction(EVT, Expand); 513 } 514 515 // Inspect all of the ValueType's smaller than the largest integer 516 // register to see which ones need promotion. 517 unsigned LegalIntReg = LargestIntReg; 518 for (unsigned IntReg = LargestIntReg - 1; 519 IntReg >= (unsigned)MVT::i1; --IntReg) { 520 MVT IVT = (MVT::SimpleValueType)IntReg; 521 if (isTypeLegal(IVT)) { 522 LegalIntReg = IntReg; 523 } else { 524 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 525 (MVT::SimpleValueType)LegalIntReg; 526 ValueTypeActions.setTypeAction(IVT, Promote); 527 } 528 } 529 530 // ppcf128 type is really two f64's. 531 if (!isTypeLegal(MVT::ppcf128)) { 532 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 533 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 534 TransformToType[MVT::ppcf128] = MVT::f64; 535 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 536 } 537 538 // Decide how to handle f64. If the target does not have native f64 support, 539 // expand it to i64 and we will be generating soft float library calls. 540 if (!isTypeLegal(MVT::f64)) { 541 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 542 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 543 TransformToType[MVT::f64] = MVT::i64; 544 ValueTypeActions.setTypeAction(MVT::f64, Expand); 545 } 546 547 // Decide how to handle f32. If the target does not have native support for 548 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 549 if (!isTypeLegal(MVT::f32)) { 550 if (isTypeLegal(MVT::f64)) { 551 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 552 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 553 TransformToType[MVT::f32] = MVT::f64; 554 ValueTypeActions.setTypeAction(MVT::f32, Promote); 555 } else { 556 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 557 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 558 TransformToType[MVT::f32] = MVT::i32; 559 ValueTypeActions.setTypeAction(MVT::f32, Expand); 560 } 561 } 562 563 // Loop over all of the vector value types to see which need transformations. 564 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 565 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 566 MVT VT = (MVT::SimpleValueType)i; 567 if (!isTypeLegal(VT)) { 568 MVT IntermediateVT, RegisterVT; 569 unsigned NumIntermediates; 570 NumRegistersForVT[i] = 571 getVectorTypeBreakdown(VT, 572 IntermediateVT, NumIntermediates, 573 RegisterVT); 574 RegisterTypeForVT[i] = RegisterVT; 575 TransformToType[i] = MVT::Other; // this isn't actually used 576 ValueTypeActions.setTypeAction(VT, Promote); 577 } 578 } 579} 580 581const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 582 return NULL; 583} 584 585 586MVT TargetLowering::getSetCCResultType(const SDValue &) const { 587 return getValueType(TD->getIntPtrType()); 588} 589 590 591/// getVectorTypeBreakdown - Vector types are broken down into some number of 592/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 593/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 594/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 595/// 596/// This method returns the number of registers needed, and the VT for each 597/// register. It also returns the VT and quantity of the intermediate values 598/// before they are promoted/expanded. 599/// 600unsigned TargetLowering::getVectorTypeBreakdown(MVT VT, 601 MVT &IntermediateVT, 602 unsigned &NumIntermediates, 603 MVT &RegisterVT) const { 604 // Figure out the right, legal destination reg to copy into. 605 unsigned NumElts = VT.getVectorNumElements(); 606 MVT EltTy = VT.getVectorElementType(); 607 608 unsigned NumVectorRegs = 1; 609 610 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 611 // could break down into LHS/RHS like LegalizeDAG does. 612 if (!isPowerOf2_32(NumElts)) { 613 NumVectorRegs = NumElts; 614 NumElts = 1; 615 } 616 617 // Divide the input until we get to a supported size. This will always 618 // end with a scalar if the target doesn't support vectors. 619 while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 620 NumElts >>= 1; 621 NumVectorRegs <<= 1; 622 } 623 624 NumIntermediates = NumVectorRegs; 625 626 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 627 if (!isTypeLegal(NewVT)) 628 NewVT = EltTy; 629 IntermediateVT = NewVT; 630 631 MVT DestVT = getTypeToTransformTo(NewVT); 632 RegisterVT = DestVT; 633 if (DestVT.bitsLT(NewVT)) { 634 // Value is expanded, e.g. i64 -> i16. 635 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 636 } else { 637 // Otherwise, promotion or legal types use the same number of registers as 638 // the vector decimated to the appropriate level. 639 return NumVectorRegs; 640 } 641 642 return 1; 643} 644 645/// getWidenVectorType: given a vector type, returns the type to widen to 646/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 647/// If there is no vector type that we want to widen to, returns MVT::Other 648/// When and where to widen is target dependent based on the cost of 649/// scalarizing vs using the wider vector type. 650MVT TargetLowering::getWidenVectorType(MVT VT) { 651 assert(VT.isVector()); 652 if (isTypeLegal(VT)) 653 return VT; 654 655 // Default is not to widen until moved to LegalizeTypes 656 return MVT::Other; 657} 658 659/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 660/// function arguments in the caller parameter area. This is the actual 661/// alignment, not its logarithm. 662unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 663 return TD->getCallFrameTypeAlignment(Ty); 664} 665 666SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 667 SelectionDAG &DAG) const { 668 if (usesGlobalOffsetTable()) 669 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); 670 return Table; 671} 672 673bool 674TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 675 // Assume that everything is safe in static mode. 676 if (getTargetMachine().getRelocationModel() == Reloc::Static) 677 return true; 678 679 // In dynamic-no-pic mode, assume that known defined values are safe. 680 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 681 GA && 682 !GA->getGlobal()->isDeclaration() && 683 !GA->getGlobal()->mayBeOverridden()) 684 return true; 685 686 // Otherwise assume nothing is safe. 687 return false; 688} 689 690//===----------------------------------------------------------------------===// 691// Optimization Methods 692//===----------------------------------------------------------------------===// 693 694/// ShrinkDemandedConstant - Check to see if the specified operand of the 695/// specified instruction is a constant integer. If so, check to see if there 696/// are any bits set in the constant that are not demanded. If so, shrink the 697/// constant and return true. 698bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 699 const APInt &Demanded) { 700 // FIXME: ISD::SELECT, ISD::SELECT_CC 701 switch(Op.getOpcode()) { 702 default: break; 703 case ISD::AND: 704 case ISD::OR: 705 case ISD::XOR: 706 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 707 if (C->getAPIntValue().intersects(~Demanded)) { 708 MVT VT = Op.getValueType(); 709 SDValue New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 710 DAG.getConstant(Demanded & 711 C->getAPIntValue(), 712 VT)); 713 return CombineTo(Op, New); 714 } 715 break; 716 } 717 return false; 718} 719 720/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 721/// DemandedMask bits of the result of Op are ever used downstream. If we can 722/// use this information to simplify Op, create a new simplified DAG node and 723/// return true, returning the original and new nodes in Old and New. Otherwise, 724/// analyze the expression and return a mask of KnownOne and KnownZero bits for 725/// the expression (used to simplify the caller). The KnownZero/One bits may 726/// only be accurate for those bits in the DemandedMask. 727bool TargetLowering::SimplifyDemandedBits(SDValue Op, 728 const APInt &DemandedMask, 729 APInt &KnownZero, 730 APInt &KnownOne, 731 TargetLoweringOpt &TLO, 732 unsigned Depth) const { 733 unsigned BitWidth = DemandedMask.getBitWidth(); 734 assert(Op.getValueSizeInBits() == BitWidth && 735 "Mask size mismatches value type size!"); 736 APInt NewMask = DemandedMask; 737 738 // Don't know anything. 739 KnownZero = KnownOne = APInt(BitWidth, 0); 740 741 // Other users may use these bits. 742 if (!Op.getNode()->hasOneUse()) { 743 if (Depth != 0) { 744 // If not at the root, Just compute the KnownZero/KnownOne bits to 745 // simplify things downstream. 746 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 747 return false; 748 } 749 // If this is the root being simplified, allow it to have multiple uses, 750 // just set the NewMask to all bits. 751 NewMask = APInt::getAllOnesValue(BitWidth); 752 } else if (DemandedMask == 0) { 753 // Not demanding any bits from Op. 754 if (Op.getOpcode() != ISD::UNDEF) 755 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 756 return false; 757 } else if (Depth == 6) { // Limit search depth. 758 return false; 759 } 760 761 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 762 switch (Op.getOpcode()) { 763 case ISD::Constant: 764 // We know all of the bits for a constant! 765 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 766 KnownZero = ~KnownOne & NewMask; 767 return false; // Don't fall through, will infinitely loop. 768 case ISD::AND: 769 // If the RHS is a constant, check to see if the LHS would be zero without 770 // using the bits from the RHS. Below, we use knowledge about the RHS to 771 // simplify the LHS, here we're using information from the LHS to simplify 772 // the RHS. 773 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 774 APInt LHSZero, LHSOne; 775 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 776 LHSZero, LHSOne, Depth+1); 777 // If the LHS already has zeros where RHSC does, this and is dead. 778 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 779 return TLO.CombineTo(Op, Op.getOperand(0)); 780 // If any of the set bits in the RHS are known zero on the LHS, shrink 781 // the constant. 782 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 783 return true; 784 } 785 786 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 787 KnownOne, TLO, Depth+1)) 788 return true; 789 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 790 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 791 KnownZero2, KnownOne2, TLO, Depth+1)) 792 return true; 793 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 794 795 // If all of the demanded bits are known one on one side, return the other. 796 // These bits cannot contribute to the result of the 'and'. 797 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 798 return TLO.CombineTo(Op, Op.getOperand(0)); 799 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 800 return TLO.CombineTo(Op, Op.getOperand(1)); 801 // If all of the demanded bits in the inputs are known zeros, return zero. 802 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 803 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 804 // If the RHS is a constant, see if we can simplify it. 805 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 806 return true; 807 808 // Output known-1 bits are only known if set in both the LHS & RHS. 809 KnownOne &= KnownOne2; 810 // Output known-0 are known to be clear if zero in either the LHS | RHS. 811 KnownZero |= KnownZero2; 812 break; 813 case ISD::OR: 814 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 815 KnownOne, TLO, Depth+1)) 816 return true; 817 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 818 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 819 KnownZero2, KnownOne2, TLO, Depth+1)) 820 return true; 821 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 822 823 // If all of the demanded bits are known zero on one side, return the other. 824 // These bits cannot contribute to the result of the 'or'. 825 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 826 return TLO.CombineTo(Op, Op.getOperand(0)); 827 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 828 return TLO.CombineTo(Op, Op.getOperand(1)); 829 // If all of the potentially set bits on one side are known to be set on 830 // the other side, just use the 'other' side. 831 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 832 return TLO.CombineTo(Op, Op.getOperand(0)); 833 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 834 return TLO.CombineTo(Op, Op.getOperand(1)); 835 // If the RHS is a constant, see if we can simplify it. 836 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 837 return true; 838 839 // Output known-0 bits are only known if clear in both the LHS & RHS. 840 KnownZero &= KnownZero2; 841 // Output known-1 are known to be set if set in either the LHS | RHS. 842 KnownOne |= KnownOne2; 843 break; 844 case ISD::XOR: 845 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 846 KnownOne, TLO, Depth+1)) 847 return true; 848 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 849 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 850 KnownOne2, TLO, Depth+1)) 851 return true; 852 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 853 854 // If all of the demanded bits are known zero on one side, return the other. 855 // These bits cannot contribute to the result of the 'xor'. 856 if ((KnownZero & NewMask) == NewMask) 857 return TLO.CombineTo(Op, Op.getOperand(0)); 858 if ((KnownZero2 & NewMask) == NewMask) 859 return TLO.CombineTo(Op, Op.getOperand(1)); 860 861 // If all of the unknown bits are known to be zero on one side or the other 862 // (but not both) turn this into an *inclusive* or. 863 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 864 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 865 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 866 Op.getOperand(0), 867 Op.getOperand(1))); 868 869 // Output known-0 bits are known if clear or set in both the LHS & RHS. 870 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 871 // Output known-1 are known to be set if set in only one of the LHS, RHS. 872 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 873 874 // If all of the demanded bits on one side are known, and all of the set 875 // bits on that side are also known to be set on the other side, turn this 876 // into an AND, as we know the bits will be cleared. 877 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 878 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 879 if ((KnownOne & KnownOne2) == KnownOne) { 880 MVT VT = Op.getValueType(); 881 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 882 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 883 ANDC)); 884 } 885 } 886 887 // If the RHS is a constant, see if we can simplify it. 888 // for XOR, we prefer to force bits to 1 if they will make a -1. 889 // if we can't force bits, try to shrink constant 890 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 891 APInt Expanded = C->getAPIntValue() | (~NewMask); 892 // if we can expand it to have all bits set, do it 893 if (Expanded.isAllOnesValue()) { 894 if (Expanded != C->getAPIntValue()) { 895 MVT VT = Op.getValueType(); 896 SDValue New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 897 TLO.DAG.getConstant(Expanded, VT)); 898 return TLO.CombineTo(Op, New); 899 } 900 // if it already has all the bits set, nothing to change 901 // but don't shrink either! 902 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 903 return true; 904 } 905 } 906 907 KnownZero = KnownZeroOut; 908 KnownOne = KnownOneOut; 909 break; 910 case ISD::SELECT: 911 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 912 KnownOne, TLO, Depth+1)) 913 return true; 914 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 915 KnownOne2, TLO, Depth+1)) 916 return true; 917 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 918 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 919 920 // If the operands are constants, see if we can simplify them. 921 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 922 return true; 923 924 // Only known if known in both the LHS and RHS. 925 KnownOne &= KnownOne2; 926 KnownZero &= KnownZero2; 927 break; 928 case ISD::SELECT_CC: 929 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 930 KnownOne, TLO, Depth+1)) 931 return true; 932 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 933 KnownOne2, TLO, Depth+1)) 934 return true; 935 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 936 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 937 938 // If the operands are constants, see if we can simplify them. 939 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 940 return true; 941 942 // Only known if known in both the LHS and RHS. 943 KnownOne &= KnownOne2; 944 KnownZero &= KnownZero2; 945 break; 946 case ISD::SHL: 947 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 948 unsigned ShAmt = SA->getZExtValue(); 949 SDValue InOp = Op.getOperand(0); 950 951 // If the shift count is an invalid immediate, don't do anything. 952 if (ShAmt >= BitWidth) 953 break; 954 955 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 956 // single shift. We can do this if the bottom bits (which are shifted 957 // out) are never demanded. 958 if (InOp.getOpcode() == ISD::SRL && 959 isa<ConstantSDNode>(InOp.getOperand(1))) { 960 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 961 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 962 unsigned Opc = ISD::SHL; 963 int Diff = ShAmt-C1; 964 if (Diff < 0) { 965 Diff = -Diff; 966 Opc = ISD::SRL; 967 } 968 969 SDValue NewSA = 970 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 971 MVT VT = Op.getValueType(); 972 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 973 InOp.getOperand(0), NewSA)); 974 } 975 } 976 977 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 978 KnownZero, KnownOne, TLO, Depth+1)) 979 return true; 980 KnownZero <<= SA->getZExtValue(); 981 KnownOne <<= SA->getZExtValue(); 982 // low bits known zero. 983 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 984 } 985 break; 986 case ISD::SRL: 987 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 988 MVT VT = Op.getValueType(); 989 unsigned ShAmt = SA->getZExtValue(); 990 unsigned VTSize = VT.getSizeInBits(); 991 SDValue InOp = Op.getOperand(0); 992 993 // If the shift count is an invalid immediate, don't do anything. 994 if (ShAmt >= BitWidth) 995 break; 996 997 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 998 // single shift. We can do this if the top bits (which are shifted out) 999 // are never demanded. 1000 if (InOp.getOpcode() == ISD::SHL && 1001 isa<ConstantSDNode>(InOp.getOperand(1))) { 1002 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1003 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1004 unsigned Opc = ISD::SRL; 1005 int Diff = ShAmt-C1; 1006 if (Diff < 0) { 1007 Diff = -Diff; 1008 Opc = ISD::SHL; 1009 } 1010 1011 SDValue NewSA = 1012 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1013 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 1014 InOp.getOperand(0), NewSA)); 1015 } 1016 } 1017 1018 // Compute the new bits that are at the top now. 1019 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1020 KnownZero, KnownOne, TLO, Depth+1)) 1021 return true; 1022 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1023 KnownZero = KnownZero.lshr(ShAmt); 1024 KnownOne = KnownOne.lshr(ShAmt); 1025 1026 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1027 KnownZero |= HighBits; // High bits known zero. 1028 } 1029 break; 1030 case ISD::SRA: 1031 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1032 MVT VT = Op.getValueType(); 1033 unsigned ShAmt = SA->getZExtValue(); 1034 1035 // If the shift count is an invalid immediate, don't do anything. 1036 if (ShAmt >= BitWidth) 1037 break; 1038 1039 APInt InDemandedMask = (NewMask << ShAmt); 1040 1041 // If any of the demanded bits are produced by the sign extension, we also 1042 // demand the input sign bit. 1043 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1044 if (HighBits.intersects(NewMask)) 1045 InDemandedMask |= APInt::getSignBit(VT.getSizeInBits()); 1046 1047 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1048 KnownZero, KnownOne, TLO, Depth+1)) 1049 return true; 1050 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1051 KnownZero = KnownZero.lshr(ShAmt); 1052 KnownOne = KnownOne.lshr(ShAmt); 1053 1054 // Handle the sign bit, adjusted to where it is now in the mask. 1055 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1056 1057 // If the input sign bit is known to be zero, or if none of the top bits 1058 // are demanded, turn this into an unsigned shift right. 1059 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1060 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 1061 Op.getOperand(1))); 1062 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1063 KnownOne |= HighBits; 1064 } 1065 } 1066 break; 1067 case ISD::SIGN_EXTEND_INREG: { 1068 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1069 1070 // Sign extension. Compute the demanded bits in the result that are not 1071 // present in the input. 1072 APInt NewBits = APInt::getHighBitsSet(BitWidth, 1073 BitWidth - EVT.getSizeInBits()) & 1074 NewMask; 1075 1076 // If none of the extended bits are demanded, eliminate the sextinreg. 1077 if (NewBits == 0) 1078 return TLO.CombineTo(Op, Op.getOperand(0)); 1079 1080 APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits()); 1081 InSignBit.zext(BitWidth); 1082 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, 1083 EVT.getSizeInBits()) & 1084 NewMask; 1085 1086 // Since the sign extended bits are demanded, we know that the sign 1087 // bit is demanded. 1088 InputDemandedBits |= InSignBit; 1089 1090 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1091 KnownZero, KnownOne, TLO, Depth+1)) 1092 return true; 1093 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1094 1095 // If the sign bit of the input is known set or clear, then we know the 1096 // top bits of the result. 1097 1098 // If the input sign bit is known zero, convert this into a zero extension. 1099 if (KnownZero.intersects(InSignBit)) 1100 return TLO.CombineTo(Op, 1101 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); 1102 1103 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1104 KnownOne |= NewBits; 1105 KnownZero &= ~NewBits; 1106 } else { // Input sign bit unknown 1107 KnownZero &= ~NewBits; 1108 KnownOne &= ~NewBits; 1109 } 1110 break; 1111 } 1112 case ISD::ZERO_EXTEND: { 1113 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1114 APInt InMask = NewMask; 1115 InMask.trunc(OperandBitWidth); 1116 1117 // If none of the top bits are demanded, convert this into an any_extend. 1118 APInt NewBits = 1119 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1120 if (!NewBits.intersects(NewMask)) 1121 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, 1122 Op.getValueType(), 1123 Op.getOperand(0))); 1124 1125 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1126 KnownZero, KnownOne, TLO, Depth+1)) 1127 return true; 1128 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1129 KnownZero.zext(BitWidth); 1130 KnownOne.zext(BitWidth); 1131 KnownZero |= NewBits; 1132 break; 1133 } 1134 case ISD::SIGN_EXTEND: { 1135 MVT InVT = Op.getOperand(0).getValueType(); 1136 unsigned InBits = InVT.getSizeInBits(); 1137 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1138 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1139 APInt NewBits = ~InMask & NewMask; 1140 1141 // If none of the top bits are demanded, convert this into an any_extend. 1142 if (NewBits == 0) 1143 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), 1144 Op.getOperand(0))); 1145 1146 // Since some of the sign extended bits are demanded, we know that the sign 1147 // bit is demanded. 1148 APInt InDemandedBits = InMask & NewMask; 1149 InDemandedBits |= InSignBit; 1150 InDemandedBits.trunc(InBits); 1151 1152 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1153 KnownOne, TLO, Depth+1)) 1154 return true; 1155 KnownZero.zext(BitWidth); 1156 KnownOne.zext(BitWidth); 1157 1158 // If the sign bit is known zero, convert this to a zero extend. 1159 if (KnownZero.intersects(InSignBit)) 1160 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, 1161 Op.getValueType(), 1162 Op.getOperand(0))); 1163 1164 // If the sign bit is known one, the top bits match. 1165 if (KnownOne.intersects(InSignBit)) { 1166 KnownOne |= NewBits; 1167 KnownZero &= ~NewBits; 1168 } else { // Otherwise, top bits aren't known. 1169 KnownOne &= ~NewBits; 1170 KnownZero &= ~NewBits; 1171 } 1172 break; 1173 } 1174 case ISD::ANY_EXTEND: { 1175 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1176 APInt InMask = NewMask; 1177 InMask.trunc(OperandBitWidth); 1178 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1179 KnownZero, KnownOne, TLO, Depth+1)) 1180 return true; 1181 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1182 KnownZero.zext(BitWidth); 1183 KnownOne.zext(BitWidth); 1184 break; 1185 } 1186 case ISD::TRUNCATE: { 1187 // Simplify the input, using demanded bit information, and compute the known 1188 // zero/one bits live out. 1189 APInt TruncMask = NewMask; 1190 TruncMask.zext(Op.getOperand(0).getValueSizeInBits()); 1191 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1192 KnownZero, KnownOne, TLO, Depth+1)) 1193 return true; 1194 KnownZero.trunc(BitWidth); 1195 KnownOne.trunc(BitWidth); 1196 1197 // If the input is only used by this truncate, see if we can shrink it based 1198 // on the known demanded bits. 1199 if (Op.getOperand(0).getNode()->hasOneUse()) { 1200 SDValue In = Op.getOperand(0); 1201 unsigned InBitWidth = In.getValueSizeInBits(); 1202 switch (In.getOpcode()) { 1203 default: break; 1204 case ISD::SRL: 1205 // Shrink SRL by a constant if none of the high bits shifted in are 1206 // demanded. 1207 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 1208 APInt HighBits = APInt::getHighBitsSet(InBitWidth, 1209 InBitWidth - BitWidth); 1210 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1211 HighBits.trunc(BitWidth); 1212 1213 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1214 // None of the shifted in bits are needed. Add a truncate of the 1215 // shift input, then shift it. 1216 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, 1217 Op.getValueType(), 1218 In.getOperand(0)); 1219 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(), 1220 NewTrunc, In.getOperand(1))); 1221 } 1222 } 1223 break; 1224 } 1225 } 1226 1227 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1228 break; 1229 } 1230 case ISD::AssertZext: { 1231 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1232 APInt InMask = APInt::getLowBitsSet(BitWidth, 1233 VT.getSizeInBits()); 1234 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 1235 KnownZero, KnownOne, TLO, Depth+1)) 1236 return true; 1237 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1238 KnownZero |= ~InMask & NewMask; 1239 break; 1240 } 1241 case ISD::BIT_CONVERT: 1242#if 0 1243 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1244 // is demanded, turn this into a FGETSIGN. 1245 if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) && 1246 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1247 !MVT::isVector(Op.getOperand(0).getValueType())) { 1248 // Only do this xform if FGETSIGN is valid or if before legalize. 1249 if (!TLO.AfterLegalize || 1250 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1251 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1252 // place. We expect the SHL to be eliminated by other optimizations. 1253 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1254 Op.getOperand(0)); 1255 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1256 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1257 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1258 Sign, ShAmt)); 1259 } 1260 } 1261#endif 1262 break; 1263 default: 1264 // Just use ComputeMaskedBits to compute output bits. 1265 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1266 break; 1267 } 1268 1269 // If we know the value of all of the demanded bits, return this as a 1270 // constant. 1271 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1272 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1273 1274 return false; 1275} 1276 1277/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1278/// in Mask are known to be either zero or one and return them in the 1279/// KnownZero/KnownOne bitsets. 1280void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1281 const APInt &Mask, 1282 APInt &KnownZero, 1283 APInt &KnownOne, 1284 const SelectionDAG &DAG, 1285 unsigned Depth) const { 1286 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1287 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1288 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1289 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1290 "Should use MaskedValueIsZero if you don't know whether Op" 1291 " is a target node!"); 1292 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1293} 1294 1295/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1296/// targets that want to expose additional information about sign bits to the 1297/// DAG Combiner. 1298unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1299 unsigned Depth) const { 1300 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1301 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1302 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1303 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1304 "Should use ComputeNumSignBits if you don't know whether Op" 1305 " is a target node!"); 1306 return 1; 1307} 1308 1309 1310/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1311/// and cc. If it is unable to simplify it, return a null SDValue. 1312SDValue 1313TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 1314 ISD::CondCode Cond, bool foldBooleans, 1315 DAGCombinerInfo &DCI) const { 1316 SelectionDAG &DAG = DCI.DAG; 1317 1318 // These setcc operations always fold. 1319 switch (Cond) { 1320 default: break; 1321 case ISD::SETFALSE: 1322 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1323 case ISD::SETTRUE: 1324 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1325 } 1326 1327 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1328 const APInt &C1 = N1C->getAPIntValue(); 1329 if (isa<ConstantSDNode>(N0.getNode())) { 1330 return DAG.FoldSetCC(VT, N0, N1, Cond); 1331 } else { 1332 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1333 // equality comparison, then we're just comparing whether X itself is 1334 // zero. 1335 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1336 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1337 N0.getOperand(1).getOpcode() == ISD::Constant) { 1338 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1339 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1340 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1341 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1342 // (srl (ctlz x), 5) == 0 -> X != 0 1343 // (srl (ctlz x), 5) != 1 -> X != 0 1344 Cond = ISD::SETNE; 1345 } else { 1346 // (srl (ctlz x), 5) != 0 -> X == 0 1347 // (srl (ctlz x), 5) == 1 -> X == 0 1348 Cond = ISD::SETEQ; 1349 } 1350 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1351 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), 1352 Zero, Cond); 1353 } 1354 } 1355 1356 // If the LHS is '(and load, const)', the RHS is 0, 1357 // the test is for equality or unsigned, and all 1 bits of the const are 1358 // in the same partial word, see if we can shorten the load. 1359 if (DCI.isBeforeLegalize() && 1360 N0.getOpcode() == ISD::AND && C1 == 0 && 1361 isa<LoadSDNode>(N0.getOperand(0)) && 1362 N0.getOperand(0).getNode()->hasOneUse() && 1363 isa<ConstantSDNode>(N0.getOperand(1))) { 1364 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1365 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1366 unsigned bestWidth = 0, bestOffset = 0; 1367 if (!Lod->isVolatile()) { 1368 unsigned origWidth = N0.getValueType().getSizeInBits(); 1369 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1370 uint64_t newMask = (1ULL << width) - 1; 1371 for (unsigned offset=0; offset<origWidth/width; offset++) { 1372 if ((newMask & Mask)==Mask) { 1373 if (!TD->isLittleEndian()) 1374 bestOffset = (origWidth/width - offset - 1) * (width/8); 1375 else 1376 bestOffset = (uint64_t)offset * (width/8); 1377 bestWidth = width; 1378 break; 1379 } 1380 newMask = newMask << width; 1381 } 1382 } 1383 } 1384 if (bestWidth) { 1385 MVT newVT = MVT::getIntegerVT(bestWidth); 1386 if (newVT.isRound()) { 1387 uint64_t bestMask = Mask >> (bestOffset * 8); 1388 MVT PtrType = Lod->getOperand(1).getValueType(); 1389 SDValue Ptr = Lod->getBasePtr(); 1390 if (bestOffset != 0) 1391 Ptr = DAG.getNode(ISD::ADD, PtrType, Lod->getBasePtr(), 1392 DAG.getConstant(bestOffset, PtrType)); 1393 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1394 SDValue NewLoad = DAG.getLoad(newVT, Lod->getChain(), Ptr, 1395 Lod->getSrcValue(), 1396 Lod->getSrcValueOffset() + bestOffset, 1397 false, NewAlign); 1398 return DAG.getSetCC(VT, DAG.getNode(ISD::AND, newVT, NewLoad, 1399 DAG.getConstant(bestMask, newVT)), 1400 DAG.getConstant(0LL, newVT), Cond); 1401 } 1402 } 1403 } 1404 1405 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1406 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1407 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1408 1409 // If the comparison constant has bits in the upper part, the 1410 // zero-extended value could never match. 1411 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1412 C1.getBitWidth() - InSize))) { 1413 switch (Cond) { 1414 case ISD::SETUGT: 1415 case ISD::SETUGE: 1416 case ISD::SETEQ: return DAG.getConstant(0, VT); 1417 case ISD::SETULT: 1418 case ISD::SETULE: 1419 case ISD::SETNE: return DAG.getConstant(1, VT); 1420 case ISD::SETGT: 1421 case ISD::SETGE: 1422 // True if the sign bit of C1 is set. 1423 return DAG.getConstant(C1.isNegative(), VT); 1424 case ISD::SETLT: 1425 case ISD::SETLE: 1426 // True if the sign bit of C1 isn't set. 1427 return DAG.getConstant(C1.isNonNegative(), VT); 1428 default: 1429 break; 1430 } 1431 } 1432 1433 // Otherwise, we can perform the comparison with the low bits. 1434 switch (Cond) { 1435 case ISD::SETEQ: 1436 case ISD::SETNE: 1437 case ISD::SETUGT: 1438 case ISD::SETUGE: 1439 case ISD::SETULT: 1440 case ISD::SETULE: 1441 return DAG.getSetCC(VT, N0.getOperand(0), 1442 DAG.getConstant(APInt(C1).trunc(InSize), 1443 N0.getOperand(0).getValueType()), 1444 Cond); 1445 default: 1446 break; // todo, be more careful with signed comparisons 1447 } 1448 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1449 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1450 MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1451 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1452 MVT ExtDstTy = N0.getValueType(); 1453 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1454 1455 // If the extended part has any inconsistent bits, it cannot ever 1456 // compare equal. In other words, they have to be all ones or all 1457 // zeros. 1458 APInt ExtBits = 1459 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1460 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1461 return DAG.getConstant(Cond == ISD::SETNE, VT); 1462 1463 SDValue ZextOp; 1464 MVT Op0Ty = N0.getOperand(0).getValueType(); 1465 if (Op0Ty == ExtSrcTy) { 1466 ZextOp = N0.getOperand(0); 1467 } else { 1468 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1469 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 1470 DAG.getConstant(Imm, Op0Ty)); 1471 } 1472 if (!DCI.isCalledByLegalizer()) 1473 DCI.AddToWorklist(ZextOp.getNode()); 1474 // Otherwise, make this a use of a zext. 1475 return DAG.getSetCC(VT, ZextOp, 1476 DAG.getConstant(C1 & APInt::getLowBitsSet( 1477 ExtDstTyBits, 1478 ExtSrcTyBits), 1479 ExtDstTy), 1480 Cond); 1481 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1482 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1483 1484 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1485 if (N0.getOpcode() == ISD::SETCC) { 1486 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1); 1487 if (TrueWhenTrue) 1488 return N0; 1489 1490 // Invert the condition. 1491 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1492 CC = ISD::getSetCCInverse(CC, 1493 N0.getOperand(0).getValueType().isInteger()); 1494 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC); 1495 } 1496 1497 if ((N0.getOpcode() == ISD::XOR || 1498 (N0.getOpcode() == ISD::AND && 1499 N0.getOperand(0).getOpcode() == ISD::XOR && 1500 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1501 isa<ConstantSDNode>(N0.getOperand(1)) && 1502 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1503 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1504 // can only do this if the top bits are known zero. 1505 unsigned BitWidth = N0.getValueSizeInBits(); 1506 if (DAG.MaskedValueIsZero(N0, 1507 APInt::getHighBitsSet(BitWidth, 1508 BitWidth-1))) { 1509 // Okay, get the un-inverted input value. 1510 SDValue Val; 1511 if (N0.getOpcode() == ISD::XOR) 1512 Val = N0.getOperand(0); 1513 else { 1514 assert(N0.getOpcode() == ISD::AND && 1515 N0.getOperand(0).getOpcode() == ISD::XOR); 1516 // ((X^1)&1)^1 -> X & 1 1517 Val = DAG.getNode(ISD::AND, N0.getValueType(), 1518 N0.getOperand(0).getOperand(0), 1519 N0.getOperand(1)); 1520 } 1521 return DAG.getSetCC(VT, Val, N1, 1522 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1523 } 1524 } 1525 } 1526 1527 APInt MinVal, MaxVal; 1528 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1529 if (ISD::isSignedIntSetCC(Cond)) { 1530 MinVal = APInt::getSignedMinValue(OperandBitSize); 1531 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1532 } else { 1533 MinVal = APInt::getMinValue(OperandBitSize); 1534 MaxVal = APInt::getMaxValue(OperandBitSize); 1535 } 1536 1537 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1538 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1539 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1540 // X >= C0 --> X > (C0-1) 1541 return DAG.getSetCC(VT, N0, DAG.getConstant(C1-1, N1.getValueType()), 1542 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1543 } 1544 1545 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1546 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1547 // X <= C0 --> X < (C0+1) 1548 return DAG.getSetCC(VT, N0, DAG.getConstant(C1+1, N1.getValueType()), 1549 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1550 } 1551 1552 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1553 return DAG.getConstant(0, VT); // X < MIN --> false 1554 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1555 return DAG.getConstant(1, VT); // X >= MIN --> true 1556 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1557 return DAG.getConstant(0, VT); // X > MAX --> false 1558 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1559 return DAG.getConstant(1, VT); // X <= MAX --> true 1560 1561 // Canonicalize setgt X, Min --> setne X, Min 1562 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1563 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1564 // Canonicalize setlt X, Max --> setne X, Max 1565 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1566 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1567 1568 // If we have setult X, 1, turn it into seteq X, 0 1569 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1570 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 1571 ISD::SETEQ); 1572 // If we have setugt X, Max-1, turn it into seteq X, Max 1573 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1574 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 1575 ISD::SETEQ); 1576 1577 // If we have "setcc X, C0", check to see if we can shrink the immediate 1578 // by changing cc. 1579 1580 // SETUGT X, SINTMAX -> SETLT X, 0 1581 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 1582 C1 == (~0ULL >> (65-OperandBitSize))) 1583 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 1584 ISD::SETLT); 1585 1586 // FIXME: Implement the rest of these. 1587 1588 // Fold bit comparisons when we can. 1589 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1590 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1591 if (ConstantSDNode *AndRHS = 1592 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1593 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1594 // Perform the xform if the AND RHS is a single bit. 1595 if (isPowerOf2_64(AndRHS->getZExtValue())) { 1596 return DAG.getNode(ISD::SRL, VT, N0, 1597 DAG.getConstant(Log2_64(AndRHS->getZExtValue()), 1598 getShiftAmountTy())); 1599 } 1600 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) { 1601 // (X & 8) == 8 --> (X & 8) >> 3 1602 // Perform the xform if C1 is a single bit. 1603 if (C1.isPowerOf2()) { 1604 return DAG.getNode(ISD::SRL, VT, N0, 1605 DAG.getConstant(C1.logBase2(), getShiftAmountTy())); 1606 } 1607 } 1608 } 1609 } 1610 } else if (isa<ConstantSDNode>(N0.getNode())) { 1611 // Ensure that the constant occurs on the RHS. 1612 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1613 } 1614 1615 if (isa<ConstantFPSDNode>(N0.getNode())) { 1616 // Constant fold or commute setcc. 1617 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond); 1618 if (O.getNode()) return O; 1619 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1620 // If the RHS of an FP comparison is a constant, simplify it away in 1621 // some cases. 1622 if (CFP->getValueAPF().isNaN()) { 1623 // If an operand is known to be a nan, we can fold it. 1624 switch (ISD::getUnorderedFlavor(Cond)) { 1625 default: assert(0 && "Unknown flavor!"); 1626 case 0: // Known false. 1627 return DAG.getConstant(0, VT); 1628 case 1: // Known true. 1629 return DAG.getConstant(1, VT); 1630 case 2: // Undefined. 1631 return DAG.getNode(ISD::UNDEF, VT); 1632 } 1633 } 1634 1635 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1636 // constant if knowing that the operand is non-nan is enough. We prefer to 1637 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1638 // materialize 0.0. 1639 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1640 return DAG.getSetCC(VT, N0, N0, Cond); 1641 } 1642 1643 if (N0 == N1) { 1644 // We can always fold X == X for integer setcc's. 1645 if (N0.getValueType().isInteger()) 1646 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1647 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1648 if (UOF == 2) // FP operators that are undefined on NaNs. 1649 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1650 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1651 return DAG.getConstant(UOF, VT); 1652 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1653 // if it is not already. 1654 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1655 if (NewCond != Cond) 1656 return DAG.getSetCC(VT, N0, N1, NewCond); 1657 } 1658 1659 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1660 N0.getValueType().isInteger()) { 1661 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1662 N0.getOpcode() == ISD::XOR) { 1663 // Simplify (X+Y) == (X+Z) --> Y == Z 1664 if (N0.getOpcode() == N1.getOpcode()) { 1665 if (N0.getOperand(0) == N1.getOperand(0)) 1666 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 1667 if (N0.getOperand(1) == N1.getOperand(1)) 1668 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 1669 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1670 // If X op Y == Y op X, try other combinations. 1671 if (N0.getOperand(0) == N1.getOperand(1)) 1672 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 1673 if (N0.getOperand(1) == N1.getOperand(0)) 1674 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 1675 } 1676 } 1677 1678 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1679 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1680 // Turn (X+C1) == C2 --> X == C2-C1 1681 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 1682 return DAG.getSetCC(VT, N0.getOperand(0), 1683 DAG.getConstant(RHSC->getAPIntValue()- 1684 LHSR->getAPIntValue(), 1685 N0.getValueType()), Cond); 1686 } 1687 1688 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1689 if (N0.getOpcode() == ISD::XOR) 1690 // If we know that all of the inverted bits are zero, don't bother 1691 // performing the inversion. 1692 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1693 return 1694 DAG.getSetCC(VT, N0.getOperand(0), 1695 DAG.getConstant(LHSR->getAPIntValue() ^ 1696 RHSC->getAPIntValue(), 1697 N0.getValueType()), 1698 Cond); 1699 } 1700 1701 // Turn (C1-X) == C2 --> X == C1-C2 1702 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1703 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 1704 return 1705 DAG.getSetCC(VT, N0.getOperand(1), 1706 DAG.getConstant(SUBC->getAPIntValue() - 1707 RHSC->getAPIntValue(), 1708 N0.getValueType()), 1709 Cond); 1710 } 1711 } 1712 } 1713 1714 // Simplify (X+Z) == X --> Z == 0 1715 if (N0.getOperand(0) == N1) 1716 return DAG.getSetCC(VT, N0.getOperand(1), 1717 DAG.getConstant(0, N0.getValueType()), Cond); 1718 if (N0.getOperand(1) == N1) { 1719 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1720 return DAG.getSetCC(VT, N0.getOperand(0), 1721 DAG.getConstant(0, N0.getValueType()), Cond); 1722 else if (N0.getNode()->hasOneUse()) { 1723 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1724 // (Z-X) == X --> Z == X<<1 1725 SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), 1726 N1, 1727 DAG.getConstant(1, getShiftAmountTy())); 1728 if (!DCI.isCalledByLegalizer()) 1729 DCI.AddToWorklist(SH.getNode()); 1730 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 1731 } 1732 } 1733 } 1734 1735 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1736 N1.getOpcode() == ISD::XOR) { 1737 // Simplify X == (X+Z) --> Z == 0 1738 if (N1.getOperand(0) == N0) { 1739 return DAG.getSetCC(VT, N1.getOperand(1), 1740 DAG.getConstant(0, N1.getValueType()), Cond); 1741 } else if (N1.getOperand(1) == N0) { 1742 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1743 return DAG.getSetCC(VT, N1.getOperand(0), 1744 DAG.getConstant(0, N1.getValueType()), Cond); 1745 } else if (N1.getNode()->hasOneUse()) { 1746 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1747 // X == (Z-X) --> X<<1 == Z 1748 SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 1749 DAG.getConstant(1, getShiftAmountTy())); 1750 if (!DCI.isCalledByLegalizer()) 1751 DCI.AddToWorklist(SH.getNode()); 1752 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 1753 } 1754 } 1755 } 1756 } 1757 1758 // Fold away ALL boolean setcc's. 1759 SDValue Temp; 1760 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1761 switch (Cond) { 1762 default: assert(0 && "Unknown integer setcc!"); 1763 case ISD::SETEQ: // X == Y -> (X^Y)^1 1764 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1765 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 1766 if (!DCI.isCalledByLegalizer()) 1767 DCI.AddToWorklist(Temp.getNode()); 1768 break; 1769 case ISD::SETNE: // X != Y --> (X^Y) 1770 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1771 break; 1772 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 1773 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 1774 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1775 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 1776 if (!DCI.isCalledByLegalizer()) 1777 DCI.AddToWorklist(Temp.getNode()); 1778 break; 1779 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 1780 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 1781 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1782 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 1783 if (!DCI.isCalledByLegalizer()) 1784 DCI.AddToWorklist(Temp.getNode()); 1785 break; 1786 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 1787 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 1788 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1789 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 1790 if (!DCI.isCalledByLegalizer()) 1791 DCI.AddToWorklist(Temp.getNode()); 1792 break; 1793 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 1794 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 1795 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1796 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 1797 break; 1798 } 1799 if (VT != MVT::i1) { 1800 if (!DCI.isCalledByLegalizer()) 1801 DCI.AddToWorklist(N0.getNode()); 1802 // FIXME: If running after legalize, we probably can't do this. 1803 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1804 } 1805 return N0; 1806 } 1807 1808 // Could not fold it. 1809 return SDValue(); 1810} 1811 1812/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 1813/// node is a GlobalAddress + offset. 1814bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA, 1815 int64_t &Offset) const { 1816 if (isa<GlobalAddressSDNode>(N)) { 1817 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 1818 GA = GASD->getGlobal(); 1819 Offset += GASD->getOffset(); 1820 return true; 1821 } 1822 1823 if (N->getOpcode() == ISD::ADD) { 1824 SDValue N1 = N->getOperand(0); 1825 SDValue N2 = N->getOperand(1); 1826 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 1827 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 1828 if (V) { 1829 Offset += V->getSExtValue(); 1830 return true; 1831 } 1832 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 1833 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 1834 if (V) { 1835 Offset += V->getSExtValue(); 1836 return true; 1837 } 1838 } 1839 } 1840 return false; 1841} 1842 1843 1844/// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is 1845/// loading 'Bytes' bytes from a location that is 'Dist' units away from the 1846/// location that the 'Base' load is loading from. 1847bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base, 1848 unsigned Bytes, int Dist, 1849 const MachineFrameInfo *MFI) const { 1850 if (LD->getOperand(0).getNode() != Base->getOperand(0).getNode()) 1851 return false; 1852 MVT VT = LD->getValueType(0); 1853 if (VT.getSizeInBits() / 8 != Bytes) 1854 return false; 1855 1856 SDValue Loc = LD->getOperand(1); 1857 SDValue BaseLoc = Base->getOperand(1); 1858 if (Loc.getOpcode() == ISD::FrameIndex) { 1859 if (BaseLoc.getOpcode() != ISD::FrameIndex) 1860 return false; 1861 int FI = cast<FrameIndexSDNode>(Loc)->getIndex(); 1862 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex(); 1863 int FS = MFI->getObjectSize(FI); 1864 int BFS = MFI->getObjectSize(BFI); 1865 if (FS != BFS || FS != (int)Bytes) return false; 1866 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes); 1867 } 1868 1869 GlobalValue *GV1 = NULL; 1870 GlobalValue *GV2 = NULL; 1871 int64_t Offset1 = 0; 1872 int64_t Offset2 = 0; 1873 bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1); 1874 bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2); 1875 if (isGA1 && isGA2 && GV1 == GV2) 1876 return Offset1 == (Offset2 + Dist*Bytes); 1877 return false; 1878} 1879 1880 1881SDValue TargetLowering:: 1882PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1883 // Default implementation: no optimization. 1884 return SDValue(); 1885} 1886 1887//===----------------------------------------------------------------------===// 1888// Inline Assembler Implementation Methods 1889//===----------------------------------------------------------------------===// 1890 1891 1892TargetLowering::ConstraintType 1893TargetLowering::getConstraintType(const std::string &Constraint) const { 1894 // FIXME: lots more standard ones to handle. 1895 if (Constraint.size() == 1) { 1896 switch (Constraint[0]) { 1897 default: break; 1898 case 'r': return C_RegisterClass; 1899 case 'm': // memory 1900 case 'o': // offsetable 1901 case 'V': // not offsetable 1902 return C_Memory; 1903 case 'i': // Simple Integer or Relocatable Constant 1904 case 'n': // Simple Integer 1905 case 's': // Relocatable Constant 1906 case 'X': // Allow ANY value. 1907 case 'I': // Target registers. 1908 case 'J': 1909 case 'K': 1910 case 'L': 1911 case 'M': 1912 case 'N': 1913 case 'O': 1914 case 'P': 1915 return C_Other; 1916 } 1917 } 1918 1919 if (Constraint.size() > 1 && Constraint[0] == '{' && 1920 Constraint[Constraint.size()-1] == '}') 1921 return C_Register; 1922 return C_Unknown; 1923} 1924 1925/// LowerXConstraint - try to replace an X constraint, which matches anything, 1926/// with another that has more specific requirements based on the type of the 1927/// corresponding operand. 1928const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{ 1929 if (ConstraintVT.isInteger()) 1930 return "r"; 1931 if (ConstraintVT.isFloatingPoint()) 1932 return "f"; // works for many targets 1933 return 0; 1934} 1935 1936/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1937/// vector. If it is invalid, don't add anything to Ops. 1938void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 1939 char ConstraintLetter, 1940 bool hasMemory, 1941 std::vector<SDValue> &Ops, 1942 SelectionDAG &DAG) const { 1943 switch (ConstraintLetter) { 1944 default: break; 1945 case 'X': // Allows any operand; labels (basic block) use this. 1946 if (Op.getOpcode() == ISD::BasicBlock) { 1947 Ops.push_back(Op); 1948 return; 1949 } 1950 // fall through 1951 case 'i': // Simple Integer or Relocatable Constant 1952 case 'n': // Simple Integer 1953 case 's': { // Relocatable Constant 1954 // These operands are interested in values of the form (GV+C), where C may 1955 // be folded in as an offset of GV, or it may be explicitly added. Also, it 1956 // is possible and fine if either GV or C are missing. 1957 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1958 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 1959 1960 // If we have "(add GV, C)", pull out GV/C 1961 if (Op.getOpcode() == ISD::ADD) { 1962 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1963 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 1964 if (C == 0 || GA == 0) { 1965 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 1966 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 1967 } 1968 if (C == 0 || GA == 0) 1969 C = 0, GA = 0; 1970 } 1971 1972 // If we find a valid operand, map to the TargetXXX version so that the 1973 // value itself doesn't get selected. 1974 if (GA) { // Either &GV or &GV+C 1975 if (ConstraintLetter != 'n') { 1976 int64_t Offs = GA->getOffset(); 1977 if (C) Offs += C->getZExtValue(); 1978 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 1979 Op.getValueType(), Offs)); 1980 return; 1981 } 1982 } 1983 if (C) { // just C, no GV. 1984 // Simple constants are not allowed for 's'. 1985 if (ConstraintLetter != 's') { 1986 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue(), 1987 Op.getValueType())); 1988 return; 1989 } 1990 } 1991 break; 1992 } 1993 } 1994} 1995 1996std::vector<unsigned> TargetLowering:: 1997getRegClassForInlineAsmConstraint(const std::string &Constraint, 1998 MVT VT) const { 1999 return std::vector<unsigned>(); 2000} 2001 2002 2003std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2004getRegForInlineAsmConstraint(const std::string &Constraint, 2005 MVT VT) const { 2006 if (Constraint[0] != '{') 2007 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2008 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2009 2010 // Remove the braces from around the name. 2011 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 2012 2013 // Figure out which register class contains this reg. 2014 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2015 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2016 E = RI->regclass_end(); RCI != E; ++RCI) { 2017 const TargetRegisterClass *RC = *RCI; 2018 2019 // If none of the the value types for this register class are valid, we 2020 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2021 bool isLegal = false; 2022 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2023 I != E; ++I) { 2024 if (isTypeLegal(*I)) { 2025 isLegal = true; 2026 break; 2027 } 2028 } 2029 2030 if (!isLegal) continue; 2031 2032 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2033 I != E; ++I) { 2034 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName)) 2035 return std::make_pair(*I, RC); 2036 } 2037 } 2038 2039 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2040} 2041 2042//===----------------------------------------------------------------------===// 2043// Constraint Selection. 2044 2045/// isMatchingInputConstraint - Return true of this is an input operand that is 2046/// a matching constraint like "4". 2047bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2048 assert(!ConstraintCode.empty() && "No known constraint!"); 2049 return isdigit(ConstraintCode[0]); 2050} 2051 2052/// getMatchedOperand - If this is an input matching constraint, this method 2053/// returns the output operand it matches. 2054unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2055 assert(!ConstraintCode.empty() && "No known constraint!"); 2056 return atoi(ConstraintCode.c_str()); 2057} 2058 2059 2060/// getConstraintGenerality - Return an integer indicating how general CT 2061/// is. 2062static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2063 switch (CT) { 2064 default: assert(0 && "Unknown constraint type!"); 2065 case TargetLowering::C_Other: 2066 case TargetLowering::C_Unknown: 2067 return 0; 2068 case TargetLowering::C_Register: 2069 return 1; 2070 case TargetLowering::C_RegisterClass: 2071 return 2; 2072 case TargetLowering::C_Memory: 2073 return 3; 2074 } 2075} 2076 2077/// ChooseConstraint - If there are multiple different constraints that we 2078/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2079/// This is somewhat tricky: constraints fall into four classes: 2080/// Other -> immediates and magic values 2081/// Register -> one specific register 2082/// RegisterClass -> a group of regs 2083/// Memory -> memory 2084/// Ideally, we would pick the most specific constraint possible: if we have 2085/// something that fits into a register, we would pick it. The problem here 2086/// is that if we have something that could either be in a register or in 2087/// memory that use of the register could cause selection of *other* 2088/// operands to fail: they might only succeed if we pick memory. Because of 2089/// this the heuristic we use is: 2090/// 2091/// 1) If there is an 'other' constraint, and if the operand is valid for 2092/// that constraint, use it. This makes us take advantage of 'i' 2093/// constraints when available. 2094/// 2) Otherwise, pick the most general constraint present. This prefers 2095/// 'm' over 'r', for example. 2096/// 2097static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2098 bool hasMemory, const TargetLowering &TLI, 2099 SDValue Op, SelectionDAG *DAG) { 2100 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2101 unsigned BestIdx = 0; 2102 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2103 int BestGenerality = -1; 2104 2105 // Loop over the options, keeping track of the most general one. 2106 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2107 TargetLowering::ConstraintType CType = 2108 TLI.getConstraintType(OpInfo.Codes[i]); 2109 2110 // If this is an 'other' constraint, see if the operand is valid for it. 2111 // For example, on X86 we might have an 'rI' constraint. If the operand 2112 // is an integer in the range [0..31] we want to use I (saving a load 2113 // of a register), otherwise we must use 'r'. 2114 if (CType == TargetLowering::C_Other && Op.getNode()) { 2115 assert(OpInfo.Codes[i].size() == 1 && 2116 "Unhandled multi-letter 'other' constraint"); 2117 std::vector<SDValue> ResultOps; 2118 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, 2119 ResultOps, *DAG); 2120 if (!ResultOps.empty()) { 2121 BestType = CType; 2122 BestIdx = i; 2123 break; 2124 } 2125 } 2126 2127 // This constraint letter is more general than the previous one, use it. 2128 int Generality = getConstraintGenerality(CType); 2129 if (Generality > BestGenerality) { 2130 BestType = CType; 2131 BestIdx = i; 2132 BestGenerality = Generality; 2133 } 2134 } 2135 2136 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2137 OpInfo.ConstraintType = BestType; 2138} 2139 2140/// ComputeConstraintToUse - Determines the constraint code and constraint 2141/// type to use for the specific AsmOperandInfo, setting 2142/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2143void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2144 SDValue Op, 2145 bool hasMemory, 2146 SelectionDAG *DAG) const { 2147 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2148 2149 // Single-letter constraints ('r') are very common. 2150 if (OpInfo.Codes.size() == 1) { 2151 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2152 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2153 } else { 2154 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); 2155 } 2156 2157 // 'X' matches anything. 2158 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2159 // Labels and constants are handled elsewhere ('X' is the only thing 2160 // that matches labels). 2161 if (isa<BasicBlock>(OpInfo.CallOperandVal) || 2162 isa<ConstantInt>(OpInfo.CallOperandVal)) 2163 return; 2164 2165 // Otherwise, try to resolve it to something we know about by looking at 2166 // the actual operand type. 2167 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2168 OpInfo.ConstraintCode = Repl; 2169 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2170 } 2171 } 2172} 2173 2174//===----------------------------------------------------------------------===// 2175// Loop Strength Reduction hooks 2176//===----------------------------------------------------------------------===// 2177 2178/// isLegalAddressingMode - Return true if the addressing mode represented 2179/// by AM is legal for this target, for a load/store of the specified type. 2180bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2181 const Type *Ty) const { 2182 // The default implementation of this implements a conservative RISCy, r+r and 2183 // r+i addr mode. 2184 2185 // Allows a sign-extended 16-bit immediate field. 2186 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2187 return false; 2188 2189 // No global is ever allowed as a base. 2190 if (AM.BaseGV) 2191 return false; 2192 2193 // Only support r+r, 2194 switch (AM.Scale) { 2195 case 0: // "r+i" or just "i", depending on HasBaseReg. 2196 break; 2197 case 1: 2198 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2199 return false; 2200 // Otherwise we have r+r or r+i. 2201 break; 2202 case 2: 2203 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2204 return false; 2205 // Allow 2*r as r+r. 2206 break; 2207 } 2208 2209 return true; 2210} 2211 2212// Magic for divide replacement 2213 2214struct ms { 2215 int64_t m; // magic number 2216 int64_t s; // shift amount 2217}; 2218 2219struct mu { 2220 uint64_t m; // magic number 2221 int64_t a; // add indicator 2222 int64_t s; // shift amount 2223}; 2224 2225/// magic - calculate the magic numbers required to codegen an integer sdiv as 2226/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 2227/// or -1. 2228static ms magic32(int32_t d) { 2229 int32_t p; 2230 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 2231 const uint32_t two31 = 0x80000000U; 2232 struct ms mag; 2233 2234 ad = abs(d); 2235 t = two31 + ((uint32_t)d >> 31); 2236 anc = t - 1 - t%ad; // absolute value of nc 2237 p = 31; // initialize p 2238 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 2239 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 2240 q2 = two31/ad; // initialize q2 = 2p/abs(d) 2241 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 2242 do { 2243 p = p + 1; 2244 q1 = 2*q1; // update q1 = 2p/abs(nc) 2245 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 2246 if (r1 >= anc) { // must be unsigned comparison 2247 q1 = q1 + 1; 2248 r1 = r1 - anc; 2249 } 2250 q2 = 2*q2; // update q2 = 2p/abs(d) 2251 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 2252 if (r2 >= ad) { // must be unsigned comparison 2253 q2 = q2 + 1; 2254 r2 = r2 - ad; 2255 } 2256 delta = ad - r2; 2257 } while (q1 < delta || (q1 == delta && r1 == 0)); 2258 2259 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 2260 if (d < 0) mag.m = -mag.m; // resulting magic number 2261 mag.s = p - 32; // resulting shift 2262 return mag; 2263} 2264 2265/// magicu - calculate the magic numbers required to codegen an integer udiv as 2266/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 2267static mu magicu32(uint32_t d) { 2268 int32_t p; 2269 uint32_t nc, delta, q1, r1, q2, r2; 2270 struct mu magu; 2271 magu.a = 0; // initialize "add" indicator 2272 nc = - 1 - (-d)%d; 2273 p = 31; // initialize p 2274 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 2275 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 2276 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 2277 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 2278 do { 2279 p = p + 1; 2280 if (r1 >= nc - r1 ) { 2281 q1 = 2*q1 + 1; // update q1 2282 r1 = 2*r1 - nc; // update r1 2283 } 2284 else { 2285 q1 = 2*q1; // update q1 2286 r1 = 2*r1; // update r1 2287 } 2288 if (r2 + 1 >= d - r2) { 2289 if (q2 >= 0x7FFFFFFF) magu.a = 1; 2290 q2 = 2*q2 + 1; // update q2 2291 r2 = 2*r2 + 1 - d; // update r2 2292 } 2293 else { 2294 if (q2 >= 0x80000000) magu.a = 1; 2295 q2 = 2*q2; // update q2 2296 r2 = 2*r2 + 1; // update r2 2297 } 2298 delta = d - 1 - r2; 2299 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 2300 magu.m = q2 + 1; // resulting magic number 2301 magu.s = p - 32; // resulting shift 2302 return magu; 2303} 2304 2305/// magic - calculate the magic numbers required to codegen an integer sdiv as 2306/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 2307/// or -1. 2308static ms magic64(int64_t d) { 2309 int64_t p; 2310 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 2311 const uint64_t two63 = 9223372036854775808ULL; // 2^63 2312 struct ms mag; 2313 2314 ad = d >= 0 ? d : -d; 2315 t = two63 + ((uint64_t)d >> 63); 2316 anc = t - 1 - t%ad; // absolute value of nc 2317 p = 63; // initialize p 2318 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 2319 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 2320 q2 = two63/ad; // initialize q2 = 2p/abs(d) 2321 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 2322 do { 2323 p = p + 1; 2324 q1 = 2*q1; // update q1 = 2p/abs(nc) 2325 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 2326 if (r1 >= anc) { // must be unsigned comparison 2327 q1 = q1 + 1; 2328 r1 = r1 - anc; 2329 } 2330 q2 = 2*q2; // update q2 = 2p/abs(d) 2331 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 2332 if (r2 >= ad) { // must be unsigned comparison 2333 q2 = q2 + 1; 2334 r2 = r2 - ad; 2335 } 2336 delta = ad - r2; 2337 } while (q1 < delta || (q1 == delta && r1 == 0)); 2338 2339 mag.m = q2 + 1; 2340 if (d < 0) mag.m = -mag.m; // resulting magic number 2341 mag.s = p - 64; // resulting shift 2342 return mag; 2343} 2344 2345/// magicu - calculate the magic numbers required to codegen an integer udiv as 2346/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 2347static mu magicu64(uint64_t d) 2348{ 2349 int64_t p; 2350 uint64_t nc, delta, q1, r1, q2, r2; 2351 struct mu magu; 2352 magu.a = 0; // initialize "add" indicator 2353 nc = - 1 - (-d)%d; 2354 p = 63; // initialize p 2355 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 2356 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 2357 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 2358 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 2359 do { 2360 p = p + 1; 2361 if (r1 >= nc - r1 ) { 2362 q1 = 2*q1 + 1; // update q1 2363 r1 = 2*r1 - nc; // update r1 2364 } 2365 else { 2366 q1 = 2*q1; // update q1 2367 r1 = 2*r1; // update r1 2368 } 2369 if (r2 + 1 >= d - r2) { 2370 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 2371 q2 = 2*q2 + 1; // update q2 2372 r2 = 2*r2 + 1 - d; // update r2 2373 } 2374 else { 2375 if (q2 >= 0x8000000000000000ull) magu.a = 1; 2376 q2 = 2*q2; // update q2 2377 r2 = 2*r2 + 1; // update r2 2378 } 2379 delta = d - 1 - r2; 2380 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0))); 2381 magu.m = q2 + 1; // resulting magic number 2382 magu.s = p - 64; // resulting shift 2383 return magu; 2384} 2385 2386/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2387/// return a DAG expression to select that will generate the same value by 2388/// multiplying by a magic number. See: 2389/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2390SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2391 std::vector<SDNode*>* Created) const { 2392 MVT VT = N->getValueType(0); 2393 2394 // Check to see if we can do this. 2395 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2396 return SDValue(); // BuildSDIV only operates on i32 or i64 2397 2398 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSExtValue(); 2399 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 2400 2401 // Multiply the numerator (operand 0) by the magic value 2402 SDValue Q; 2403 if (isOperationLegal(ISD::MULHS, VT)) 2404 Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 2405 DAG.getConstant(magics.m, VT)); 2406 else if (isOperationLegal(ISD::SMUL_LOHI, VT)) 2407 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT), 2408 N->getOperand(0), 2409 DAG.getConstant(magics.m, VT)).getNode(), 1); 2410 else 2411 return SDValue(); // No mulhs or equvialent 2412 // If d > 0 and m < 0, add the numerator 2413 if (d > 0 && magics.m < 0) { 2414 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 2415 if (Created) 2416 Created->push_back(Q.getNode()); 2417 } 2418 // If d < 0 and m > 0, subtract the numerator. 2419 if (d < 0 && magics.m > 0) { 2420 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 2421 if (Created) 2422 Created->push_back(Q.getNode()); 2423 } 2424 // Shift right algebraic if shift value is nonzero 2425 if (magics.s > 0) { 2426 Q = DAG.getNode(ISD::SRA, VT, Q, 2427 DAG.getConstant(magics.s, getShiftAmountTy())); 2428 if (Created) 2429 Created->push_back(Q.getNode()); 2430 } 2431 // Extract the sign bit and add it to the quotient 2432 SDValue T = 2433 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2434 getShiftAmountTy())); 2435 if (Created) 2436 Created->push_back(T.getNode()); 2437 return DAG.getNode(ISD::ADD, VT, Q, T); 2438} 2439 2440/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2441/// return a DAG expression to select that will generate the same value by 2442/// multiplying by a magic number. See: 2443/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2444SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2445 std::vector<SDNode*>* Created) const { 2446 MVT VT = N->getValueType(0); 2447 2448 // Check to see if we can do this. 2449 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2450 return SDValue(); // BuildUDIV only operates on i32 or i64 2451 2452 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 2453 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 2454 2455 // Multiply the numerator (operand 0) by the magic value 2456 SDValue Q; 2457 if (isOperationLegal(ISD::MULHU, VT)) 2458 Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 2459 DAG.getConstant(magics.m, VT)); 2460 else if (isOperationLegal(ISD::UMUL_LOHI, VT)) 2461 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT), 2462 N->getOperand(0), 2463 DAG.getConstant(magics.m, VT)).getNode(), 1); 2464 else 2465 return SDValue(); // No mulhu or equvialent 2466 if (Created) 2467 Created->push_back(Q.getNode()); 2468 2469 if (magics.a == 0) { 2470 return DAG.getNode(ISD::SRL, VT, Q, 2471 DAG.getConstant(magics.s, getShiftAmountTy())); 2472 } else { 2473 SDValue NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 2474 if (Created) 2475 Created->push_back(NPQ.getNode()); 2476 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 2477 DAG.getConstant(1, getShiftAmountTy())); 2478 if (Created) 2479 Created->push_back(NPQ.getNode()); 2480 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 2481 if (Created) 2482 Created->push_back(NPQ.getNode()); 2483 return DAG.getNode(ISD::SRL, VT, NPQ, 2484 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2485 } 2486} 2487