TargetLowering.cpp revision e03262fcfc09356a0e3ec589041bc2e0248944e9
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/MC/MCAsmInfo.h" 16#include "llvm/MC/MCExpr.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetLoweringObjectFile.h" 19#include "llvm/Target/TargetMachine.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/GlobalVariable.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineJumpTableInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/CodeGen/SelectionDAG.h" 27#include "llvm/ADT/STLExtras.h" 28#include "llvm/Support/ErrorHandling.h" 29#include "llvm/Support/MathExtras.h" 30using namespace llvm; 31 32namespace llvm { 33TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 34 bool isLocal = GV->hasLocalLinkage(); 35 bool isDeclaration = GV->isDeclaration(); 36 // FIXME: what should we do for protected and internal visibility? 37 // For variables, is internal different from hidden? 38 bool isHidden = GV->hasHiddenVisibility(); 39 40 if (reloc == Reloc::PIC_) { 41 if (isLocal || isHidden) 42 return TLSModel::LocalDynamic; 43 else 44 return TLSModel::GeneralDynamic; 45 } else { 46 if (!isDeclaration || isHidden) 47 return TLSModel::LocalExec; 48 else 49 return TLSModel::InitialExec; 50 } 51} 52} 53 54/// InitLibcallNames - Set default libcall names. 55/// 56static void InitLibcallNames(const char **Names) { 57 Names[RTLIB::SHL_I16] = "__ashlhi3"; 58 Names[RTLIB::SHL_I32] = "__ashlsi3"; 59 Names[RTLIB::SHL_I64] = "__ashldi3"; 60 Names[RTLIB::SHL_I128] = "__ashlti3"; 61 Names[RTLIB::SRL_I16] = "__lshrhi3"; 62 Names[RTLIB::SRL_I32] = "__lshrsi3"; 63 Names[RTLIB::SRL_I64] = "__lshrdi3"; 64 Names[RTLIB::SRL_I128] = "__lshrti3"; 65 Names[RTLIB::SRA_I16] = "__ashrhi3"; 66 Names[RTLIB::SRA_I32] = "__ashrsi3"; 67 Names[RTLIB::SRA_I64] = "__ashrdi3"; 68 Names[RTLIB::SRA_I128] = "__ashrti3"; 69 Names[RTLIB::MUL_I8] = "__mulqi3"; 70 Names[RTLIB::MUL_I16] = "__mulhi3"; 71 Names[RTLIB::MUL_I32] = "__mulsi3"; 72 Names[RTLIB::MUL_I64] = "__muldi3"; 73 Names[RTLIB::MUL_I128] = "__multi3"; 74 Names[RTLIB::SDIV_I8] = "__divqi3"; 75 Names[RTLIB::SDIV_I16] = "__divhi3"; 76 Names[RTLIB::SDIV_I32] = "__divsi3"; 77 Names[RTLIB::SDIV_I64] = "__divdi3"; 78 Names[RTLIB::SDIV_I128] = "__divti3"; 79 Names[RTLIB::UDIV_I8] = "__udivqi3"; 80 Names[RTLIB::UDIV_I16] = "__udivhi3"; 81 Names[RTLIB::UDIV_I32] = "__udivsi3"; 82 Names[RTLIB::UDIV_I64] = "__udivdi3"; 83 Names[RTLIB::UDIV_I128] = "__udivti3"; 84 Names[RTLIB::SREM_I8] = "__modqi3"; 85 Names[RTLIB::SREM_I16] = "__modhi3"; 86 Names[RTLIB::SREM_I32] = "__modsi3"; 87 Names[RTLIB::SREM_I64] = "__moddi3"; 88 Names[RTLIB::SREM_I128] = "__modti3"; 89 Names[RTLIB::UREM_I8] = "__umodqi3"; 90 Names[RTLIB::UREM_I16] = "__umodhi3"; 91 Names[RTLIB::UREM_I32] = "__umodsi3"; 92 Names[RTLIB::UREM_I64] = "__umoddi3"; 93 Names[RTLIB::UREM_I128] = "__umodti3"; 94 Names[RTLIB::NEG_I32] = "__negsi2"; 95 Names[RTLIB::NEG_I64] = "__negdi2"; 96 Names[RTLIB::ADD_F32] = "__addsf3"; 97 Names[RTLIB::ADD_F64] = "__adddf3"; 98 Names[RTLIB::ADD_F80] = "__addxf3"; 99 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 100 Names[RTLIB::SUB_F32] = "__subsf3"; 101 Names[RTLIB::SUB_F64] = "__subdf3"; 102 Names[RTLIB::SUB_F80] = "__subxf3"; 103 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 104 Names[RTLIB::MUL_F32] = "__mulsf3"; 105 Names[RTLIB::MUL_F64] = "__muldf3"; 106 Names[RTLIB::MUL_F80] = "__mulxf3"; 107 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 108 Names[RTLIB::DIV_F32] = "__divsf3"; 109 Names[RTLIB::DIV_F64] = "__divdf3"; 110 Names[RTLIB::DIV_F80] = "__divxf3"; 111 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 112 Names[RTLIB::REM_F32] = "fmodf"; 113 Names[RTLIB::REM_F64] = "fmod"; 114 Names[RTLIB::REM_F80] = "fmodl"; 115 Names[RTLIB::REM_PPCF128] = "fmodl"; 116 Names[RTLIB::POWI_F32] = "__powisf2"; 117 Names[RTLIB::POWI_F64] = "__powidf2"; 118 Names[RTLIB::POWI_F80] = "__powixf2"; 119 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 120 Names[RTLIB::SQRT_F32] = "sqrtf"; 121 Names[RTLIB::SQRT_F64] = "sqrt"; 122 Names[RTLIB::SQRT_F80] = "sqrtl"; 123 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 124 Names[RTLIB::LOG_F32] = "logf"; 125 Names[RTLIB::LOG_F64] = "log"; 126 Names[RTLIB::LOG_F80] = "logl"; 127 Names[RTLIB::LOG_PPCF128] = "logl"; 128 Names[RTLIB::LOG2_F32] = "log2f"; 129 Names[RTLIB::LOG2_F64] = "log2"; 130 Names[RTLIB::LOG2_F80] = "log2l"; 131 Names[RTLIB::LOG2_PPCF128] = "log2l"; 132 Names[RTLIB::LOG10_F32] = "log10f"; 133 Names[RTLIB::LOG10_F64] = "log10"; 134 Names[RTLIB::LOG10_F80] = "log10l"; 135 Names[RTLIB::LOG10_PPCF128] = "log10l"; 136 Names[RTLIB::EXP_F32] = "expf"; 137 Names[RTLIB::EXP_F64] = "exp"; 138 Names[RTLIB::EXP_F80] = "expl"; 139 Names[RTLIB::EXP_PPCF128] = "expl"; 140 Names[RTLIB::EXP2_F32] = "exp2f"; 141 Names[RTLIB::EXP2_F64] = "exp2"; 142 Names[RTLIB::EXP2_F80] = "exp2l"; 143 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 144 Names[RTLIB::SIN_F32] = "sinf"; 145 Names[RTLIB::SIN_F64] = "sin"; 146 Names[RTLIB::SIN_F80] = "sinl"; 147 Names[RTLIB::SIN_PPCF128] = "sinl"; 148 Names[RTLIB::COS_F32] = "cosf"; 149 Names[RTLIB::COS_F64] = "cos"; 150 Names[RTLIB::COS_F80] = "cosl"; 151 Names[RTLIB::COS_PPCF128] = "cosl"; 152 Names[RTLIB::POW_F32] = "powf"; 153 Names[RTLIB::POW_F64] = "pow"; 154 Names[RTLIB::POW_F80] = "powl"; 155 Names[RTLIB::POW_PPCF128] = "powl"; 156 Names[RTLIB::CEIL_F32] = "ceilf"; 157 Names[RTLIB::CEIL_F64] = "ceil"; 158 Names[RTLIB::CEIL_F80] = "ceill"; 159 Names[RTLIB::CEIL_PPCF128] = "ceill"; 160 Names[RTLIB::TRUNC_F32] = "truncf"; 161 Names[RTLIB::TRUNC_F64] = "trunc"; 162 Names[RTLIB::TRUNC_F80] = "truncl"; 163 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 164 Names[RTLIB::RINT_F32] = "rintf"; 165 Names[RTLIB::RINT_F64] = "rint"; 166 Names[RTLIB::RINT_F80] = "rintl"; 167 Names[RTLIB::RINT_PPCF128] = "rintl"; 168 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 169 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 170 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 171 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 172 Names[RTLIB::FLOOR_F32] = "floorf"; 173 Names[RTLIB::FLOOR_F64] = "floor"; 174 Names[RTLIB::FLOOR_F80] = "floorl"; 175 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 176 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 177 Names[RTLIB::COPYSIGN_F64] = "copysign"; 178 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 179 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 180 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 181 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 182 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 183 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 184 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 185 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 186 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 187 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 188 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 189 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 190 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 191 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 192 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 193 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 194 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 195 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 196 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 197 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 198 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 199 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 200 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 201 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 202 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 203 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 204 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 205 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 206 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 207 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 208 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 209 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 210 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 211 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 212 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 213 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 214 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 215 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 216 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 217 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 218 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 219 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 220 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 221 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 222 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 223 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 224 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 225 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 226 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 227 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 228 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 229 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 230 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 231 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 232 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 233 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 234 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 235 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 236 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 237 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 238 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 239 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 240 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 241 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 242 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 243 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 244 Names[RTLIB::OEQ_F32] = "__eqsf2"; 245 Names[RTLIB::OEQ_F64] = "__eqdf2"; 246 Names[RTLIB::UNE_F32] = "__nesf2"; 247 Names[RTLIB::UNE_F64] = "__nedf2"; 248 Names[RTLIB::OGE_F32] = "__gesf2"; 249 Names[RTLIB::OGE_F64] = "__gedf2"; 250 Names[RTLIB::OLT_F32] = "__ltsf2"; 251 Names[RTLIB::OLT_F64] = "__ltdf2"; 252 Names[RTLIB::OLE_F32] = "__lesf2"; 253 Names[RTLIB::OLE_F64] = "__ledf2"; 254 Names[RTLIB::OGT_F32] = "__gtsf2"; 255 Names[RTLIB::OGT_F64] = "__gtdf2"; 256 Names[RTLIB::UO_F32] = "__unordsf2"; 257 Names[RTLIB::UO_F64] = "__unorddf2"; 258 Names[RTLIB::O_F32] = "__unordsf2"; 259 Names[RTLIB::O_F64] = "__unorddf2"; 260 Names[RTLIB::MEMCPY] = "memcpy"; 261 Names[RTLIB::MEMMOVE] = "memmove"; 262 Names[RTLIB::MEMSET] = "memset"; 263 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 264 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 265 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 268 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 269 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 270 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 271 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 272 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 273 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 274 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 275 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 276 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 277 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 278 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 279 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 280 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 281 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 282 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 283 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 284 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 285 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 286 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4"; 287 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 288 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 289 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 290 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 291 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 292} 293 294/// InitLibcallCallingConvs - Set default libcall CallingConvs. 295/// 296static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 297 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 298 CCs[i] = CallingConv::C; 299 } 300} 301 302/// getFPEXT - Return the FPEXT_*_* value for the given types, or 303/// UNKNOWN_LIBCALL if there is none. 304RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 305 if (OpVT == MVT::f32) { 306 if (RetVT == MVT::f64) 307 return FPEXT_F32_F64; 308 } 309 310 return UNKNOWN_LIBCALL; 311} 312 313/// getFPROUND - Return the FPROUND_*_* value for the given types, or 314/// UNKNOWN_LIBCALL if there is none. 315RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 316 if (RetVT == MVT::f32) { 317 if (OpVT == MVT::f64) 318 return FPROUND_F64_F32; 319 if (OpVT == MVT::f80) 320 return FPROUND_F80_F32; 321 if (OpVT == MVT::ppcf128) 322 return FPROUND_PPCF128_F32; 323 } else if (RetVT == MVT::f64) { 324 if (OpVT == MVT::f80) 325 return FPROUND_F80_F64; 326 if (OpVT == MVT::ppcf128) 327 return FPROUND_PPCF128_F64; 328 } 329 330 return UNKNOWN_LIBCALL; 331} 332 333/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 334/// UNKNOWN_LIBCALL if there is none. 335RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 336 if (OpVT == MVT::f32) { 337 if (RetVT == MVT::i8) 338 return FPTOSINT_F32_I8; 339 if (RetVT == MVT::i16) 340 return FPTOSINT_F32_I16; 341 if (RetVT == MVT::i32) 342 return FPTOSINT_F32_I32; 343 if (RetVT == MVT::i64) 344 return FPTOSINT_F32_I64; 345 if (RetVT == MVT::i128) 346 return FPTOSINT_F32_I128; 347 } else if (OpVT == MVT::f64) { 348 if (RetVT == MVT::i8) 349 return FPTOSINT_F64_I8; 350 if (RetVT == MVT::i16) 351 return FPTOSINT_F64_I16; 352 if (RetVT == MVT::i32) 353 return FPTOSINT_F64_I32; 354 if (RetVT == MVT::i64) 355 return FPTOSINT_F64_I64; 356 if (RetVT == MVT::i128) 357 return FPTOSINT_F64_I128; 358 } else if (OpVT == MVT::f80) { 359 if (RetVT == MVT::i32) 360 return FPTOSINT_F80_I32; 361 if (RetVT == MVT::i64) 362 return FPTOSINT_F80_I64; 363 if (RetVT == MVT::i128) 364 return FPTOSINT_F80_I128; 365 } else if (OpVT == MVT::ppcf128) { 366 if (RetVT == MVT::i32) 367 return FPTOSINT_PPCF128_I32; 368 if (RetVT == MVT::i64) 369 return FPTOSINT_PPCF128_I64; 370 if (RetVT == MVT::i128) 371 return FPTOSINT_PPCF128_I128; 372 } 373 return UNKNOWN_LIBCALL; 374} 375 376/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 377/// UNKNOWN_LIBCALL if there is none. 378RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 379 if (OpVT == MVT::f32) { 380 if (RetVT == MVT::i8) 381 return FPTOUINT_F32_I8; 382 if (RetVT == MVT::i16) 383 return FPTOUINT_F32_I16; 384 if (RetVT == MVT::i32) 385 return FPTOUINT_F32_I32; 386 if (RetVT == MVT::i64) 387 return FPTOUINT_F32_I64; 388 if (RetVT == MVT::i128) 389 return FPTOUINT_F32_I128; 390 } else if (OpVT == MVT::f64) { 391 if (RetVT == MVT::i8) 392 return FPTOUINT_F64_I8; 393 if (RetVT == MVT::i16) 394 return FPTOUINT_F64_I16; 395 if (RetVT == MVT::i32) 396 return FPTOUINT_F64_I32; 397 if (RetVT == MVT::i64) 398 return FPTOUINT_F64_I64; 399 if (RetVT == MVT::i128) 400 return FPTOUINT_F64_I128; 401 } else if (OpVT == MVT::f80) { 402 if (RetVT == MVT::i32) 403 return FPTOUINT_F80_I32; 404 if (RetVT == MVT::i64) 405 return FPTOUINT_F80_I64; 406 if (RetVT == MVT::i128) 407 return FPTOUINT_F80_I128; 408 } else if (OpVT == MVT::ppcf128) { 409 if (RetVT == MVT::i32) 410 return FPTOUINT_PPCF128_I32; 411 if (RetVT == MVT::i64) 412 return FPTOUINT_PPCF128_I64; 413 if (RetVT == MVT::i128) 414 return FPTOUINT_PPCF128_I128; 415 } 416 return UNKNOWN_LIBCALL; 417} 418 419/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 420/// UNKNOWN_LIBCALL if there is none. 421RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 422 if (OpVT == MVT::i32) { 423 if (RetVT == MVT::f32) 424 return SINTTOFP_I32_F32; 425 else if (RetVT == MVT::f64) 426 return SINTTOFP_I32_F64; 427 else if (RetVT == MVT::f80) 428 return SINTTOFP_I32_F80; 429 else if (RetVT == MVT::ppcf128) 430 return SINTTOFP_I32_PPCF128; 431 } else if (OpVT == MVT::i64) { 432 if (RetVT == MVT::f32) 433 return SINTTOFP_I64_F32; 434 else if (RetVT == MVT::f64) 435 return SINTTOFP_I64_F64; 436 else if (RetVT == MVT::f80) 437 return SINTTOFP_I64_F80; 438 else if (RetVT == MVT::ppcf128) 439 return SINTTOFP_I64_PPCF128; 440 } else if (OpVT == MVT::i128) { 441 if (RetVT == MVT::f32) 442 return SINTTOFP_I128_F32; 443 else if (RetVT == MVT::f64) 444 return SINTTOFP_I128_F64; 445 else if (RetVT == MVT::f80) 446 return SINTTOFP_I128_F80; 447 else if (RetVT == MVT::ppcf128) 448 return SINTTOFP_I128_PPCF128; 449 } 450 return UNKNOWN_LIBCALL; 451} 452 453/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 454/// UNKNOWN_LIBCALL if there is none. 455RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 456 if (OpVT == MVT::i32) { 457 if (RetVT == MVT::f32) 458 return UINTTOFP_I32_F32; 459 else if (RetVT == MVT::f64) 460 return UINTTOFP_I32_F64; 461 else if (RetVT == MVT::f80) 462 return UINTTOFP_I32_F80; 463 else if (RetVT == MVT::ppcf128) 464 return UINTTOFP_I32_PPCF128; 465 } else if (OpVT == MVT::i64) { 466 if (RetVT == MVT::f32) 467 return UINTTOFP_I64_F32; 468 else if (RetVT == MVT::f64) 469 return UINTTOFP_I64_F64; 470 else if (RetVT == MVT::f80) 471 return UINTTOFP_I64_F80; 472 else if (RetVT == MVT::ppcf128) 473 return UINTTOFP_I64_PPCF128; 474 } else if (OpVT == MVT::i128) { 475 if (RetVT == MVT::f32) 476 return UINTTOFP_I128_F32; 477 else if (RetVT == MVT::f64) 478 return UINTTOFP_I128_F64; 479 else if (RetVT == MVT::f80) 480 return UINTTOFP_I128_F80; 481 else if (RetVT == MVT::ppcf128) 482 return UINTTOFP_I128_PPCF128; 483 } 484 return UNKNOWN_LIBCALL; 485} 486 487/// InitCmpLibcallCCs - Set default comparison libcall CC. 488/// 489static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 490 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 491 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 492 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 493 CCs[RTLIB::UNE_F32] = ISD::SETNE; 494 CCs[RTLIB::UNE_F64] = ISD::SETNE; 495 CCs[RTLIB::OGE_F32] = ISD::SETGE; 496 CCs[RTLIB::OGE_F64] = ISD::SETGE; 497 CCs[RTLIB::OLT_F32] = ISD::SETLT; 498 CCs[RTLIB::OLT_F64] = ISD::SETLT; 499 CCs[RTLIB::OLE_F32] = ISD::SETLE; 500 CCs[RTLIB::OLE_F64] = ISD::SETLE; 501 CCs[RTLIB::OGT_F32] = ISD::SETGT; 502 CCs[RTLIB::OGT_F64] = ISD::SETGT; 503 CCs[RTLIB::UO_F32] = ISD::SETNE; 504 CCs[RTLIB::UO_F64] = ISD::SETNE; 505 CCs[RTLIB::O_F32] = ISD::SETEQ; 506 CCs[RTLIB::O_F64] = ISD::SETEQ; 507} 508 509/// NOTE: The constructor takes ownership of TLOF. 510TargetLowering::TargetLowering(const TargetMachine &tm, 511 const TargetLoweringObjectFile *tlof) 512 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) { 513 // All operations default to being supported. 514 memset(OpActions, 0, sizeof(OpActions)); 515 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 516 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 517 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 518 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 519 520 // Set default actions for various operations. 521 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 522 // Default all indexed load / store to expand. 523 for (unsigned IM = (unsigned)ISD::PRE_INC; 524 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 525 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 526 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 527 } 528 529 // These operations default to expand. 530 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 531 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 532 } 533 534 // Most targets ignore the @llvm.prefetch intrinsic. 535 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 536 537 // ConstantFP nodes default to expand. Targets can either change this to 538 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 539 // to optimize expansions for certain constants. 540 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 541 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 542 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 543 544 // These library functions default to expand. 545 setOperationAction(ISD::FLOG , MVT::f64, Expand); 546 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 547 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 548 setOperationAction(ISD::FEXP , MVT::f64, Expand); 549 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 550 setOperationAction(ISD::FLOG , MVT::f32, Expand); 551 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 552 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 553 setOperationAction(ISD::FEXP , MVT::f32, Expand); 554 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 555 556 // Default ISD::TRAP to expand (which turns it into abort). 557 setOperationAction(ISD::TRAP, MVT::Other, Expand); 558 559 IsLittleEndian = TD->isLittleEndian(); 560 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 561 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 562 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 563 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 564 benefitFromCodePlacementOpt = false; 565 UseUnderscoreSetJmp = false; 566 UseUnderscoreLongJmp = false; 567 SelectIsExpensive = false; 568 IntDivIsCheap = false; 569 Pow2DivIsCheap = false; 570 StackPointerRegisterToSaveRestore = 0; 571 ExceptionPointerRegister = 0; 572 ExceptionSelectorRegister = 0; 573 BooleanContents = UndefinedBooleanContent; 574 SchedPreferenceInfo = Sched::Latency; 575 JumpBufSize = 0; 576 JumpBufAlignment = 0; 577 IfCvtBlockSizeLimit = 2; 578 IfCvtDupBlockSizeLimit = 0; 579 PrefLoopAlignment = 0; 580 581 InitLibcallNames(LibcallRoutineNames); 582 InitCmpLibcallCCs(CmpLibcallCCs); 583 InitLibcallCallingConvs(LibcallCallingConvs); 584} 585 586TargetLowering::~TargetLowering() { 587 delete &TLOF; 588} 589 590/// canOpTrap - Returns true if the operation can trap for the value type. 591/// VT must be a legal type. 592bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 593 assert(isTypeLegal(VT)); 594 switch (Op) { 595 default: 596 return false; 597 case ISD::FDIV: 598 case ISD::FREM: 599 case ISD::SDIV: 600 case ISD::UDIV: 601 case ISD::SREM: 602 case ISD::UREM: 603 return true; 604 } 605} 606 607 608static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 609 unsigned &NumIntermediates, 610 EVT &RegisterVT, 611 TargetLowering* TLI) { 612 // Figure out the right, legal destination reg to copy into. 613 unsigned NumElts = VT.getVectorNumElements(); 614 MVT EltTy = VT.getVectorElementType(); 615 616 unsigned NumVectorRegs = 1; 617 618 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 619 // could break down into LHS/RHS like LegalizeDAG does. 620 if (!isPowerOf2_32(NumElts)) { 621 NumVectorRegs = NumElts; 622 NumElts = 1; 623 } 624 625 // Divide the input until we get to a supported size. This will always 626 // end with a scalar if the target doesn't support vectors. 627 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 628 NumElts >>= 1; 629 NumVectorRegs <<= 1; 630 } 631 632 NumIntermediates = NumVectorRegs; 633 634 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 635 if (!TLI->isTypeLegal(NewVT)) 636 NewVT = EltTy; 637 IntermediateVT = NewVT; 638 639 EVT DestVT = TLI->getRegisterType(NewVT); 640 RegisterVT = DestVT; 641 if (EVT(DestVT).bitsLT(NewVT)) { 642 // Value is expanded, e.g. i64 -> i16. 643 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 644 } else { 645 // Otherwise, promotion or legal types use the same number of registers as 646 // the vector decimated to the appropriate level. 647 return NumVectorRegs; 648 } 649 650 return 1; 651} 652 653/// computeRegisterProperties - Once all of the register classes are added, 654/// this allows us to compute derived properties we expose. 655void TargetLowering::computeRegisterProperties() { 656 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 657 "Too many value types for ValueTypeActions to hold!"); 658 659 // Everything defaults to needing one register. 660 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 661 NumRegistersForVT[i] = 1; 662 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 663 } 664 // ...except isVoid, which doesn't need any registers. 665 NumRegistersForVT[MVT::isVoid] = 0; 666 667 // Find the largest integer register class. 668 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 669 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 670 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 671 672 // Every integer value type larger than this largest register takes twice as 673 // many registers to represent as the previous ValueType. 674 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 675 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 676 if (!ExpandedVT.isInteger()) 677 break; 678 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 679 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 680 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 681 ValueTypeActions.setTypeAction(ExpandedVT, Expand); 682 } 683 684 // Inspect all of the ValueType's smaller than the largest integer 685 // register to see which ones need promotion. 686 unsigned LegalIntReg = LargestIntReg; 687 for (unsigned IntReg = LargestIntReg - 1; 688 IntReg >= (unsigned)MVT::i1; --IntReg) { 689 EVT IVT = (MVT::SimpleValueType)IntReg; 690 if (isTypeLegal(IVT)) { 691 LegalIntReg = IntReg; 692 } else { 693 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 694 (MVT::SimpleValueType)LegalIntReg; 695 ValueTypeActions.setTypeAction(IVT, Promote); 696 } 697 } 698 699 // ppcf128 type is really two f64's. 700 if (!isTypeLegal(MVT::ppcf128)) { 701 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 702 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 703 TransformToType[MVT::ppcf128] = MVT::f64; 704 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 705 } 706 707 // Decide how to handle f64. If the target does not have native f64 support, 708 // expand it to i64 and we will be generating soft float library calls. 709 if (!isTypeLegal(MVT::f64)) { 710 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 711 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 712 TransformToType[MVT::f64] = MVT::i64; 713 ValueTypeActions.setTypeAction(MVT::f64, Expand); 714 } 715 716 // Decide how to handle f32. If the target does not have native support for 717 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 718 if (!isTypeLegal(MVT::f32)) { 719 if (isTypeLegal(MVT::f64)) { 720 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 721 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 722 TransformToType[MVT::f32] = MVT::f64; 723 ValueTypeActions.setTypeAction(MVT::f32, Promote); 724 } else { 725 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 726 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 727 TransformToType[MVT::f32] = MVT::i32; 728 ValueTypeActions.setTypeAction(MVT::f32, Expand); 729 } 730 } 731 732 // Loop over all of the vector value types to see which need transformations. 733 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 734 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 735 MVT VT = (MVT::SimpleValueType)i; 736 if (!isTypeLegal(VT)) { 737 MVT IntermediateVT; 738 EVT RegisterVT; 739 unsigned NumIntermediates; 740 NumRegistersForVT[i] = 741 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 742 RegisterVT, this); 743 RegisterTypeForVT[i] = RegisterVT; 744 745 // Determine if there is a legal wider type. 746 bool IsLegalWiderType = false; 747 EVT EltVT = VT.getVectorElementType(); 748 unsigned NElts = VT.getVectorNumElements(); 749 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 750 EVT SVT = (MVT::SimpleValueType)nVT; 751 if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT && 752 SVT.getVectorNumElements() > NElts && NElts != 1) { 753 TransformToType[i] = SVT; 754 ValueTypeActions.setTypeAction(VT, Promote); 755 IsLegalWiderType = true; 756 break; 757 } 758 } 759 if (!IsLegalWiderType) { 760 EVT NVT = VT.getPow2VectorType(); 761 if (NVT == VT) { 762 // Type is already a power of 2. The default action is to split. 763 TransformToType[i] = MVT::Other; 764 ValueTypeActions.setTypeAction(VT, Expand); 765 } else { 766 TransformToType[i] = NVT; 767 ValueTypeActions.setTypeAction(VT, Promote); 768 } 769 } 770 } 771 } 772} 773 774const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 775 return NULL; 776} 777 778 779MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const { 780 return PointerTy.SimpleTy; 781} 782 783MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 784 return MVT::i32; // return the default value 785} 786 787/// getVectorTypeBreakdown - Vector types are broken down into some number of 788/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 789/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 790/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 791/// 792/// This method returns the number of registers needed, and the VT for each 793/// register. It also returns the VT and quantity of the intermediate values 794/// before they are promoted/expanded. 795/// 796unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 797 EVT &IntermediateVT, 798 unsigned &NumIntermediates, 799 EVT &RegisterVT) const { 800 // Figure out the right, legal destination reg to copy into. 801 unsigned NumElts = VT.getVectorNumElements(); 802 EVT EltTy = VT.getVectorElementType(); 803 804 unsigned NumVectorRegs = 1; 805 806 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 807 // could break down into LHS/RHS like LegalizeDAG does. 808 if (!isPowerOf2_32(NumElts)) { 809 NumVectorRegs = NumElts; 810 NumElts = 1; 811 } 812 813 // Divide the input until we get to a supported size. This will always 814 // end with a scalar if the target doesn't support vectors. 815 while (NumElts > 1 && !isTypeLegal( 816 EVT::getVectorVT(Context, EltTy, NumElts))) { 817 NumElts >>= 1; 818 NumVectorRegs <<= 1; 819 } 820 821 NumIntermediates = NumVectorRegs; 822 823 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 824 if (!isTypeLegal(NewVT)) 825 NewVT = EltTy; 826 IntermediateVT = NewVT; 827 828 EVT DestVT = getRegisterType(Context, NewVT); 829 RegisterVT = DestVT; 830 if (DestVT.bitsLT(NewVT)) { 831 // Value is expanded, e.g. i64 -> i16. 832 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 833 } else { 834 // Otherwise, promotion or legal types use the same number of registers as 835 // the vector decimated to the appropriate level. 836 return NumVectorRegs; 837 } 838 839 return 1; 840} 841 842/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 843/// function arguments in the caller parameter area. This is the actual 844/// alignment, not its logarithm. 845unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 846 return TD->getCallFrameTypeAlignment(Ty); 847} 848 849/// getJumpTableEncoding - Return the entry encoding for a jump table in the 850/// current function. The returned value is a member of the 851/// MachineJumpTableInfo::JTEntryKind enum. 852unsigned TargetLowering::getJumpTableEncoding() const { 853 // In non-pic modes, just use the address of a block. 854 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 855 return MachineJumpTableInfo::EK_BlockAddress; 856 857 // In PIC mode, if the target supports a GPRel32 directive, use it. 858 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 859 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 860 861 // Otherwise, use a label difference. 862 return MachineJumpTableInfo::EK_LabelDifference32; 863} 864 865SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 866 SelectionDAG &DAG) const { 867 // If our PIC model is GP relative, use the global offset table as the base. 868 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress) 869 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 870 return Table; 871} 872 873/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 874/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 875/// MCExpr. 876const MCExpr * 877TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 878 unsigned JTI,MCContext &Ctx) const{ 879 // The normal PIC reloc base is the label at the start of the jump table. 880 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 881} 882 883bool 884TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 885 // Assume that everything is safe in static mode. 886 if (getTargetMachine().getRelocationModel() == Reloc::Static) 887 return true; 888 889 // In dynamic-no-pic mode, assume that known defined values are safe. 890 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 891 GA && 892 !GA->getGlobal()->isDeclaration() && 893 !GA->getGlobal()->isWeakForLinker()) 894 return true; 895 896 // Otherwise assume nothing is safe. 897 return false; 898} 899 900//===----------------------------------------------------------------------===// 901// Optimization Methods 902//===----------------------------------------------------------------------===// 903 904/// ShrinkDemandedConstant - Check to see if the specified operand of the 905/// specified instruction is a constant integer. If so, check to see if there 906/// are any bits set in the constant that are not demanded. If so, shrink the 907/// constant and return true. 908bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 909 const APInt &Demanded) { 910 DebugLoc dl = Op.getDebugLoc(); 911 912 // FIXME: ISD::SELECT, ISD::SELECT_CC 913 switch (Op.getOpcode()) { 914 default: break; 915 case ISD::XOR: 916 case ISD::AND: 917 case ISD::OR: { 918 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 919 if (!C) return false; 920 921 if (Op.getOpcode() == ISD::XOR && 922 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 923 return false; 924 925 // if we can expand it to have all bits set, do it 926 if (C->getAPIntValue().intersects(~Demanded)) { 927 EVT VT = Op.getValueType(); 928 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 929 DAG.getConstant(Demanded & 930 C->getAPIntValue(), 931 VT)); 932 return CombineTo(Op, New); 933 } 934 935 break; 936 } 937 } 938 939 return false; 940} 941 942/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 943/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 944/// cast, but it could be generalized for targets with other types of 945/// implicit widening casts. 946bool 947TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 948 unsigned BitWidth, 949 const APInt &Demanded, 950 DebugLoc dl) { 951 assert(Op.getNumOperands() == 2 && 952 "ShrinkDemandedOp only supports binary operators!"); 953 assert(Op.getNode()->getNumValues() == 1 && 954 "ShrinkDemandedOp only supports nodes with one result!"); 955 956 // Don't do this if the node has another user, which may require the 957 // full value. 958 if (!Op.getNode()->hasOneUse()) 959 return false; 960 961 // Search for the smallest integer type with free casts to and from 962 // Op's type. For expedience, just check power-of-2 integer types. 963 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 964 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 965 if (!isPowerOf2_32(SmallVTBits)) 966 SmallVTBits = NextPowerOf2(SmallVTBits); 967 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 968 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 969 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 970 TLI.isZExtFree(SmallVT, Op.getValueType())) { 971 // We found a type with free casts. 972 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 973 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 974 Op.getNode()->getOperand(0)), 975 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 976 Op.getNode()->getOperand(1))); 977 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 978 return CombineTo(Op, Z); 979 } 980 } 981 return false; 982} 983 984/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 985/// DemandedMask bits of the result of Op are ever used downstream. If we can 986/// use this information to simplify Op, create a new simplified DAG node and 987/// return true, returning the original and new nodes in Old and New. Otherwise, 988/// analyze the expression and return a mask of KnownOne and KnownZero bits for 989/// the expression (used to simplify the caller). The KnownZero/One bits may 990/// only be accurate for those bits in the DemandedMask. 991bool TargetLowering::SimplifyDemandedBits(SDValue Op, 992 const APInt &DemandedMask, 993 APInt &KnownZero, 994 APInt &KnownOne, 995 TargetLoweringOpt &TLO, 996 unsigned Depth) const { 997 unsigned BitWidth = DemandedMask.getBitWidth(); 998 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 999 "Mask size mismatches value type size!"); 1000 APInt NewMask = DemandedMask; 1001 DebugLoc dl = Op.getDebugLoc(); 1002 1003 // Don't know anything. 1004 KnownZero = KnownOne = APInt(BitWidth, 0); 1005 1006 // Other users may use these bits. 1007 if (!Op.getNode()->hasOneUse()) { 1008 if (Depth != 0) { 1009 // If not at the root, Just compute the KnownZero/KnownOne bits to 1010 // simplify things downstream. 1011 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 1012 return false; 1013 } 1014 // If this is the root being simplified, allow it to have multiple uses, 1015 // just set the NewMask to all bits. 1016 NewMask = APInt::getAllOnesValue(BitWidth); 1017 } else if (DemandedMask == 0) { 1018 // Not demanding any bits from Op. 1019 if (Op.getOpcode() != ISD::UNDEF) 1020 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 1021 return false; 1022 } else if (Depth == 6) { // Limit search depth. 1023 return false; 1024 } 1025 1026 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1027 switch (Op.getOpcode()) { 1028 case ISD::Constant: 1029 // We know all of the bits for a constant! 1030 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 1031 KnownZero = ~KnownOne & NewMask; 1032 return false; // Don't fall through, will infinitely loop. 1033 case ISD::AND: 1034 // If the RHS is a constant, check to see if the LHS would be zero without 1035 // using the bits from the RHS. Below, we use knowledge about the RHS to 1036 // simplify the LHS, here we're using information from the LHS to simplify 1037 // the RHS. 1038 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1039 APInt LHSZero, LHSOne; 1040 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 1041 LHSZero, LHSOne, Depth+1); 1042 // If the LHS already has zeros where RHSC does, this and is dead. 1043 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1044 return TLO.CombineTo(Op, Op.getOperand(0)); 1045 // If any of the set bits in the RHS are known zero on the LHS, shrink 1046 // the constant. 1047 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1048 return true; 1049 } 1050 1051 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1052 KnownOne, TLO, Depth+1)) 1053 return true; 1054 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1055 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1056 KnownZero2, KnownOne2, TLO, Depth+1)) 1057 return true; 1058 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1059 1060 // If all of the demanded bits are known one on one side, return the other. 1061 // These bits cannot contribute to the result of the 'and'. 1062 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1063 return TLO.CombineTo(Op, Op.getOperand(0)); 1064 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1065 return TLO.CombineTo(Op, Op.getOperand(1)); 1066 // If all of the demanded bits in the inputs are known zeros, return zero. 1067 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1068 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1069 // If the RHS is a constant, see if we can simplify it. 1070 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1071 return true; 1072 // If the operation can be done in a smaller type, do so. 1073 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1074 return true; 1075 1076 // Output known-1 bits are only known if set in both the LHS & RHS. 1077 KnownOne &= KnownOne2; 1078 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1079 KnownZero |= KnownZero2; 1080 break; 1081 case ISD::OR: 1082 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1083 KnownOne, TLO, Depth+1)) 1084 return true; 1085 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1086 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1087 KnownZero2, KnownOne2, TLO, Depth+1)) 1088 return true; 1089 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1090 1091 // If all of the demanded bits are known zero on one side, return the other. 1092 // These bits cannot contribute to the result of the 'or'. 1093 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1094 return TLO.CombineTo(Op, Op.getOperand(0)); 1095 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1096 return TLO.CombineTo(Op, Op.getOperand(1)); 1097 // If all of the potentially set bits on one side are known to be set on 1098 // the other side, just use the 'other' side. 1099 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1100 return TLO.CombineTo(Op, Op.getOperand(0)); 1101 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1102 return TLO.CombineTo(Op, Op.getOperand(1)); 1103 // If the RHS is a constant, see if we can simplify it. 1104 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1105 return true; 1106 // If the operation can be done in a smaller type, do so. 1107 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1108 return true; 1109 1110 // Output known-0 bits are only known if clear in both the LHS & RHS. 1111 KnownZero &= KnownZero2; 1112 // Output known-1 are known to be set if set in either the LHS | RHS. 1113 KnownOne |= KnownOne2; 1114 break; 1115 case ISD::XOR: 1116 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1117 KnownOne, TLO, Depth+1)) 1118 return true; 1119 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1120 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1121 KnownOne2, TLO, Depth+1)) 1122 return true; 1123 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1124 1125 // If all of the demanded bits are known zero on one side, return the other. 1126 // These bits cannot contribute to the result of the 'xor'. 1127 if ((KnownZero & NewMask) == NewMask) 1128 return TLO.CombineTo(Op, Op.getOperand(0)); 1129 if ((KnownZero2 & NewMask) == NewMask) 1130 return TLO.CombineTo(Op, Op.getOperand(1)); 1131 // If the operation can be done in a smaller type, do so. 1132 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1133 return true; 1134 1135 // If all of the unknown bits are known to be zero on one side or the other 1136 // (but not both) turn this into an *inclusive* or. 1137 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1138 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1139 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1140 Op.getOperand(0), 1141 Op.getOperand(1))); 1142 1143 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1144 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1145 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1146 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1147 1148 // If all of the demanded bits on one side are known, and all of the set 1149 // bits on that side are also known to be set on the other side, turn this 1150 // into an AND, as we know the bits will be cleared. 1151 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1152 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1153 if ((KnownOne & KnownOne2) == KnownOne) { 1154 EVT VT = Op.getValueType(); 1155 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1156 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1157 Op.getOperand(0), ANDC)); 1158 } 1159 } 1160 1161 // If the RHS is a constant, see if we can simplify it. 1162 // for XOR, we prefer to force bits to 1 if they will make a -1. 1163 // if we can't force bits, try to shrink constant 1164 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1165 APInt Expanded = C->getAPIntValue() | (~NewMask); 1166 // if we can expand it to have all bits set, do it 1167 if (Expanded.isAllOnesValue()) { 1168 if (Expanded != C->getAPIntValue()) { 1169 EVT VT = Op.getValueType(); 1170 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1171 TLO.DAG.getConstant(Expanded, VT)); 1172 return TLO.CombineTo(Op, New); 1173 } 1174 // if it already has all the bits set, nothing to change 1175 // but don't shrink either! 1176 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1177 return true; 1178 } 1179 } 1180 1181 KnownZero = KnownZeroOut; 1182 KnownOne = KnownOneOut; 1183 break; 1184 case ISD::SELECT: 1185 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1186 KnownOne, TLO, Depth+1)) 1187 return true; 1188 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1189 KnownOne2, TLO, Depth+1)) 1190 return true; 1191 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1192 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1193 1194 // If the operands are constants, see if we can simplify them. 1195 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1196 return true; 1197 1198 // Only known if known in both the LHS and RHS. 1199 KnownOne &= KnownOne2; 1200 KnownZero &= KnownZero2; 1201 break; 1202 case ISD::SELECT_CC: 1203 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1204 KnownOne, TLO, Depth+1)) 1205 return true; 1206 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1207 KnownOne2, TLO, Depth+1)) 1208 return true; 1209 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1210 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1211 1212 // If the operands are constants, see if we can simplify them. 1213 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1214 return true; 1215 1216 // Only known if known in both the LHS and RHS. 1217 KnownOne &= KnownOne2; 1218 KnownZero &= KnownZero2; 1219 break; 1220 case ISD::SHL: 1221 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1222 unsigned ShAmt = SA->getZExtValue(); 1223 SDValue InOp = Op.getOperand(0); 1224 1225 // If the shift count is an invalid immediate, don't do anything. 1226 if (ShAmt >= BitWidth) 1227 break; 1228 1229 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1230 // single shift. We can do this if the bottom bits (which are shifted 1231 // out) are never demanded. 1232 if (InOp.getOpcode() == ISD::SRL && 1233 isa<ConstantSDNode>(InOp.getOperand(1))) { 1234 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1235 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1236 unsigned Opc = ISD::SHL; 1237 int Diff = ShAmt-C1; 1238 if (Diff < 0) { 1239 Diff = -Diff; 1240 Opc = ISD::SRL; 1241 } 1242 1243 SDValue NewSA = 1244 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1245 EVT VT = Op.getValueType(); 1246 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1247 InOp.getOperand(0), NewSA)); 1248 } 1249 } 1250 1251 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 1252 KnownZero, KnownOne, TLO, Depth+1)) 1253 return true; 1254 KnownZero <<= SA->getZExtValue(); 1255 KnownOne <<= SA->getZExtValue(); 1256 // low bits known zero. 1257 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1258 } 1259 break; 1260 case ISD::SRL: 1261 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1262 EVT VT = Op.getValueType(); 1263 unsigned ShAmt = SA->getZExtValue(); 1264 unsigned VTSize = VT.getSizeInBits(); 1265 SDValue InOp = Op.getOperand(0); 1266 1267 // If the shift count is an invalid immediate, don't do anything. 1268 if (ShAmt >= BitWidth) 1269 break; 1270 1271 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1272 // single shift. We can do this if the top bits (which are shifted out) 1273 // are never demanded. 1274 if (InOp.getOpcode() == ISD::SHL && 1275 isa<ConstantSDNode>(InOp.getOperand(1))) { 1276 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1277 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1278 unsigned Opc = ISD::SRL; 1279 int Diff = ShAmt-C1; 1280 if (Diff < 0) { 1281 Diff = -Diff; 1282 Opc = ISD::SHL; 1283 } 1284 1285 SDValue NewSA = 1286 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1287 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1288 InOp.getOperand(0), NewSA)); 1289 } 1290 } 1291 1292 // Compute the new bits that are at the top now. 1293 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1294 KnownZero, KnownOne, TLO, Depth+1)) 1295 return true; 1296 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1297 KnownZero = KnownZero.lshr(ShAmt); 1298 KnownOne = KnownOne.lshr(ShAmt); 1299 1300 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1301 KnownZero |= HighBits; // High bits known zero. 1302 } 1303 break; 1304 case ISD::SRA: 1305 // If this is an arithmetic shift right and only the low-bit is set, we can 1306 // always convert this into a logical shr, even if the shift amount is 1307 // variable. The low bit of the shift cannot be an input sign bit unless 1308 // the shift amount is >= the size of the datatype, which is undefined. 1309 if (DemandedMask == 1) 1310 return TLO.CombineTo(Op, 1311 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1312 Op.getOperand(0), Op.getOperand(1))); 1313 1314 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1315 EVT VT = Op.getValueType(); 1316 unsigned ShAmt = SA->getZExtValue(); 1317 1318 // If the shift count is an invalid immediate, don't do anything. 1319 if (ShAmt >= BitWidth) 1320 break; 1321 1322 APInt InDemandedMask = (NewMask << ShAmt); 1323 1324 // If any of the demanded bits are produced by the sign extension, we also 1325 // demand the input sign bit. 1326 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1327 if (HighBits.intersects(NewMask)) 1328 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1329 1330 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1331 KnownZero, KnownOne, TLO, Depth+1)) 1332 return true; 1333 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1334 KnownZero = KnownZero.lshr(ShAmt); 1335 KnownOne = KnownOne.lshr(ShAmt); 1336 1337 // Handle the sign bit, adjusted to where it is now in the mask. 1338 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1339 1340 // If the input sign bit is known to be zero, or if none of the top bits 1341 // are demanded, turn this into an unsigned shift right. 1342 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1343 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1344 Op.getOperand(0), 1345 Op.getOperand(1))); 1346 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1347 KnownOne |= HighBits; 1348 } 1349 } 1350 break; 1351 case ISD::SIGN_EXTEND_INREG: { 1352 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1353 1354 // Sign extension. Compute the demanded bits in the result that are not 1355 // present in the input. 1356 APInt NewBits = 1357 APInt::getHighBitsSet(BitWidth, 1358 BitWidth - EVT.getScalarType().getSizeInBits()) & 1359 NewMask; 1360 1361 // If none of the extended bits are demanded, eliminate the sextinreg. 1362 if (NewBits == 0) 1363 return TLO.CombineTo(Op, Op.getOperand(0)); 1364 1365 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits()); 1366 InSignBit.zext(BitWidth); 1367 APInt InputDemandedBits = 1368 APInt::getLowBitsSet(BitWidth, 1369 EVT.getScalarType().getSizeInBits()) & 1370 NewMask; 1371 1372 // Since the sign extended bits are demanded, we know that the sign 1373 // bit is demanded. 1374 InputDemandedBits |= InSignBit; 1375 1376 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1377 KnownZero, KnownOne, TLO, Depth+1)) 1378 return true; 1379 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1380 1381 // If the sign bit of the input is known set or clear, then we know the 1382 // top bits of the result. 1383 1384 // If the input sign bit is known zero, convert this into a zero extension. 1385 if (KnownZero.intersects(InSignBit)) 1386 return TLO.CombineTo(Op, 1387 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1388 1389 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1390 KnownOne |= NewBits; 1391 KnownZero &= ~NewBits; 1392 } else { // Input sign bit unknown 1393 KnownZero &= ~NewBits; 1394 KnownOne &= ~NewBits; 1395 } 1396 break; 1397 } 1398 case ISD::ZERO_EXTEND: { 1399 unsigned OperandBitWidth = 1400 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1401 APInt InMask = NewMask; 1402 InMask.trunc(OperandBitWidth); 1403 1404 // If none of the top bits are demanded, convert this into an any_extend. 1405 APInt NewBits = 1406 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1407 if (!NewBits.intersects(NewMask)) 1408 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1409 Op.getValueType(), 1410 Op.getOperand(0))); 1411 1412 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1413 KnownZero, KnownOne, TLO, Depth+1)) 1414 return true; 1415 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1416 KnownZero.zext(BitWidth); 1417 KnownOne.zext(BitWidth); 1418 KnownZero |= NewBits; 1419 break; 1420 } 1421 case ISD::SIGN_EXTEND: { 1422 EVT InVT = Op.getOperand(0).getValueType(); 1423 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1424 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1425 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1426 APInt NewBits = ~InMask & NewMask; 1427 1428 // If none of the top bits are demanded, convert this into an any_extend. 1429 if (NewBits == 0) 1430 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1431 Op.getValueType(), 1432 Op.getOperand(0))); 1433 1434 // Since some of the sign extended bits are demanded, we know that the sign 1435 // bit is demanded. 1436 APInt InDemandedBits = InMask & NewMask; 1437 InDemandedBits |= InSignBit; 1438 InDemandedBits.trunc(InBits); 1439 1440 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1441 KnownOne, TLO, Depth+1)) 1442 return true; 1443 KnownZero.zext(BitWidth); 1444 KnownOne.zext(BitWidth); 1445 1446 // If the sign bit is known zero, convert this to a zero extend. 1447 if (KnownZero.intersects(InSignBit)) 1448 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1449 Op.getValueType(), 1450 Op.getOperand(0))); 1451 1452 // If the sign bit is known one, the top bits match. 1453 if (KnownOne.intersects(InSignBit)) { 1454 KnownOne |= NewBits; 1455 KnownZero &= ~NewBits; 1456 } else { // Otherwise, top bits aren't known. 1457 KnownOne &= ~NewBits; 1458 KnownZero &= ~NewBits; 1459 } 1460 break; 1461 } 1462 case ISD::ANY_EXTEND: { 1463 unsigned OperandBitWidth = 1464 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1465 APInt InMask = NewMask; 1466 InMask.trunc(OperandBitWidth); 1467 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1468 KnownZero, KnownOne, TLO, Depth+1)) 1469 return true; 1470 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1471 KnownZero.zext(BitWidth); 1472 KnownOne.zext(BitWidth); 1473 break; 1474 } 1475 case ISD::TRUNCATE: { 1476 // Simplify the input, using demanded bit information, and compute the known 1477 // zero/one bits live out. 1478 unsigned OperandBitWidth = 1479 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1480 APInt TruncMask = NewMask; 1481 TruncMask.zext(OperandBitWidth); 1482 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1483 KnownZero, KnownOne, TLO, Depth+1)) 1484 return true; 1485 KnownZero.trunc(BitWidth); 1486 KnownOne.trunc(BitWidth); 1487 1488 // If the input is only used by this truncate, see if we can shrink it based 1489 // on the known demanded bits. 1490 if (Op.getOperand(0).getNode()->hasOneUse()) { 1491 SDValue In = Op.getOperand(0); 1492 switch (In.getOpcode()) { 1493 default: break; 1494 case ISD::SRL: 1495 // Shrink SRL by a constant if none of the high bits shifted in are 1496 // demanded. 1497 if (TLO.LegalTypes() && 1498 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1499 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1500 // undesirable. 1501 break; 1502 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1503 if (!ShAmt) 1504 break; 1505 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1506 OperandBitWidth - BitWidth); 1507 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1508 HighBits.trunc(BitWidth); 1509 1510 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1511 // None of the shifted in bits are needed. Add a truncate of the 1512 // shift input, then shift it. 1513 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1514 Op.getValueType(), 1515 In.getOperand(0)); 1516 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1517 Op.getValueType(), 1518 NewTrunc, 1519 In.getOperand(1))); 1520 } 1521 break; 1522 } 1523 } 1524 1525 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1526 break; 1527 } 1528 case ISD::AssertZext: { 1529 // Demand all the bits of the input that are demanded in the output. 1530 // The low bits are obvious; the high bits are demanded because we're 1531 // asserting that they're zero here. 1532 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, 1533 KnownZero, KnownOne, TLO, Depth+1)) 1534 return true; 1535 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1536 1537 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1538 APInt InMask = APInt::getLowBitsSet(BitWidth, 1539 VT.getSizeInBits()); 1540 KnownZero |= ~InMask & NewMask; 1541 break; 1542 } 1543 case ISD::BIT_CONVERT: 1544#if 0 1545 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1546 // is demanded, turn this into a FGETSIGN. 1547 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) && 1548 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1549 !MVT::isVector(Op.getOperand(0).getValueType())) { 1550 // Only do this xform if FGETSIGN is valid or if before legalize. 1551 if (!TLO.AfterLegalize || 1552 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1553 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1554 // place. We expect the SHL to be eliminated by other optimizations. 1555 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1556 Op.getOperand(0)); 1557 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1558 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1559 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1560 Sign, ShAmt)); 1561 } 1562 } 1563#endif 1564 break; 1565 case ISD::ADD: 1566 case ISD::MUL: 1567 case ISD::SUB: { 1568 // Add, Sub, and Mul don't demand any bits in positions beyond that 1569 // of the highest bit demanded of them. 1570 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1571 BitWidth - NewMask.countLeadingZeros()); 1572 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1573 KnownOne2, TLO, Depth+1)) 1574 return true; 1575 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1576 KnownOne2, TLO, Depth+1)) 1577 return true; 1578 // See if the operation should be performed at a smaller bit width. 1579 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1580 return true; 1581 } 1582 // FALL THROUGH 1583 default: 1584 // Just use ComputeMaskedBits to compute output bits. 1585 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1586 break; 1587 } 1588 1589 // If we know the value of all of the demanded bits, return this as a 1590 // constant. 1591 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1592 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1593 1594 return false; 1595} 1596 1597/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1598/// in Mask are known to be either zero or one and return them in the 1599/// KnownZero/KnownOne bitsets. 1600void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1601 const APInt &Mask, 1602 APInt &KnownZero, 1603 APInt &KnownOne, 1604 const SelectionDAG &DAG, 1605 unsigned Depth) const { 1606 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1607 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1608 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1609 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1610 "Should use MaskedValueIsZero if you don't know whether Op" 1611 " is a target node!"); 1612 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1613} 1614 1615/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1616/// targets that want to expose additional information about sign bits to the 1617/// DAG Combiner. 1618unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1619 unsigned Depth) const { 1620 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1621 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1622 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1623 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1624 "Should use ComputeNumSignBits if you don't know whether Op" 1625 " is a target node!"); 1626 return 1; 1627} 1628 1629/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1630/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1631/// determine which bit is set. 1632/// 1633static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1634 // A left-shift of a constant one will have exactly one bit set, because 1635 // shifting the bit off the end is undefined. 1636 if (Val.getOpcode() == ISD::SHL) 1637 if (ConstantSDNode *C = 1638 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1639 if (C->getAPIntValue() == 1) 1640 return true; 1641 1642 // Similarly, a right-shift of a constant sign-bit will have exactly 1643 // one bit set. 1644 if (Val.getOpcode() == ISD::SRL) 1645 if (ConstantSDNode *C = 1646 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1647 if (C->getAPIntValue().isSignBit()) 1648 return true; 1649 1650 // More could be done here, though the above checks are enough 1651 // to handle some common cases. 1652 1653 // Fall back to ComputeMaskedBits to catch other known cases. 1654 EVT OpVT = Val.getValueType(); 1655 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1656 APInt Mask = APInt::getAllOnesValue(BitWidth); 1657 APInt KnownZero, KnownOne; 1658 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1659 return (KnownZero.countPopulation() == BitWidth - 1) && 1660 (KnownOne.countPopulation() == 1); 1661} 1662 1663/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1664/// and cc. If it is unable to simplify it, return a null SDValue. 1665SDValue 1666TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1667 ISD::CondCode Cond, bool foldBooleans, 1668 DAGCombinerInfo &DCI, DebugLoc dl) const { 1669 SelectionDAG &DAG = DCI.DAG; 1670 LLVMContext &Context = *DAG.getContext(); 1671 1672 // These setcc operations always fold. 1673 switch (Cond) { 1674 default: break; 1675 case ISD::SETFALSE: 1676 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1677 case ISD::SETTRUE: 1678 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1679 } 1680 1681 if (isa<ConstantSDNode>(N0.getNode())) { 1682 // Ensure that the constant occurs on the RHS, and fold constant 1683 // comparisons. 1684 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1685 } 1686 1687 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1688 const APInt &C1 = N1C->getAPIntValue(); 1689 1690 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1691 // equality comparison, then we're just comparing whether X itself is 1692 // zero. 1693 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1694 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1695 N0.getOperand(1).getOpcode() == ISD::Constant) { 1696 const APInt &ShAmt 1697 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1698 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1699 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1700 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1701 // (srl (ctlz x), 5) == 0 -> X != 0 1702 // (srl (ctlz x), 5) != 1 -> X != 0 1703 Cond = ISD::SETNE; 1704 } else { 1705 // (srl (ctlz x), 5) != 0 -> X == 0 1706 // (srl (ctlz x), 5) == 1 -> X == 0 1707 Cond = ISD::SETEQ; 1708 } 1709 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1710 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1711 Zero, Cond); 1712 } 1713 } 1714 1715 // If the LHS is '(and load, const)', the RHS is 0, 1716 // the test is for equality or unsigned, and all 1 bits of the const are 1717 // in the same partial word, see if we can shorten the load. 1718 if (DCI.isBeforeLegalize() && 1719 N0.getOpcode() == ISD::AND && C1 == 0 && 1720 N0.getNode()->hasOneUse() && 1721 isa<LoadSDNode>(N0.getOperand(0)) && 1722 N0.getOperand(0).getNode()->hasOneUse() && 1723 isa<ConstantSDNode>(N0.getOperand(1))) { 1724 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1725 APInt bestMask; 1726 unsigned bestWidth = 0, bestOffset = 0; 1727 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1728 unsigned origWidth = N0.getValueType().getSizeInBits(); 1729 unsigned maskWidth = origWidth; 1730 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1731 // 8 bits, but have to be careful... 1732 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1733 origWidth = Lod->getMemoryVT().getSizeInBits(); 1734 const APInt &Mask = 1735 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1736 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1737 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 1738 for (unsigned offset=0; offset<origWidth/width; offset++) { 1739 if ((newMask & Mask) == Mask) { 1740 if (!TD->isLittleEndian()) 1741 bestOffset = (origWidth/width - offset - 1) * (width/8); 1742 else 1743 bestOffset = (uint64_t)offset * (width/8); 1744 bestMask = Mask.lshr(offset * (width/8) * 8); 1745 bestWidth = width; 1746 break; 1747 } 1748 newMask = newMask << width; 1749 } 1750 } 1751 } 1752 if (bestWidth) { 1753 EVT newVT = EVT::getIntegerVT(Context, bestWidth); 1754 if (newVT.isRound()) { 1755 EVT PtrType = Lod->getOperand(1).getValueType(); 1756 SDValue Ptr = Lod->getBasePtr(); 1757 if (bestOffset != 0) 1758 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1759 DAG.getConstant(bestOffset, PtrType)); 1760 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1761 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1762 Lod->getSrcValue(), 1763 Lod->getSrcValueOffset() + bestOffset, 1764 false, false, NewAlign); 1765 return DAG.getSetCC(dl, VT, 1766 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1767 DAG.getConstant(bestMask.trunc(bestWidth), 1768 newVT)), 1769 DAG.getConstant(0LL, newVT), Cond); 1770 } 1771 } 1772 } 1773 1774 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1775 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1776 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1777 1778 // If the comparison constant has bits in the upper part, the 1779 // zero-extended value could never match. 1780 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1781 C1.getBitWidth() - InSize))) { 1782 switch (Cond) { 1783 case ISD::SETUGT: 1784 case ISD::SETUGE: 1785 case ISD::SETEQ: return DAG.getConstant(0, VT); 1786 case ISD::SETULT: 1787 case ISD::SETULE: 1788 case ISD::SETNE: return DAG.getConstant(1, VT); 1789 case ISD::SETGT: 1790 case ISD::SETGE: 1791 // True if the sign bit of C1 is set. 1792 return DAG.getConstant(C1.isNegative(), VT); 1793 case ISD::SETLT: 1794 case ISD::SETLE: 1795 // True if the sign bit of C1 isn't set. 1796 return DAG.getConstant(C1.isNonNegative(), VT); 1797 default: 1798 break; 1799 } 1800 } 1801 1802 // Otherwise, we can perform the comparison with the low bits. 1803 switch (Cond) { 1804 case ISD::SETEQ: 1805 case ISD::SETNE: 1806 case ISD::SETUGT: 1807 case ISD::SETUGE: 1808 case ISD::SETULT: 1809 case ISD::SETULE: { 1810 EVT newVT = N0.getOperand(0).getValueType(); 1811 if (DCI.isBeforeLegalizeOps() || 1812 (isOperationLegal(ISD::SETCC, newVT) && 1813 getCondCodeAction(Cond, newVT)==Legal)) 1814 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1815 DAG.getConstant(APInt(C1).trunc(InSize), newVT), 1816 Cond); 1817 break; 1818 } 1819 default: 1820 break; // todo, be more careful with signed comparisons 1821 } 1822 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1823 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1824 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1825 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1826 EVT ExtDstTy = N0.getValueType(); 1827 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1828 1829 // If the extended part has any inconsistent bits, it cannot ever 1830 // compare equal. In other words, they have to be all ones or all 1831 // zeros. 1832 APInt ExtBits = 1833 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1834 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1835 return DAG.getConstant(Cond == ISD::SETNE, VT); 1836 1837 SDValue ZextOp; 1838 EVT Op0Ty = N0.getOperand(0).getValueType(); 1839 if (Op0Ty == ExtSrcTy) { 1840 ZextOp = N0.getOperand(0); 1841 } else { 1842 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1843 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1844 DAG.getConstant(Imm, Op0Ty)); 1845 } 1846 if (!DCI.isCalledByLegalizer()) 1847 DCI.AddToWorklist(ZextOp.getNode()); 1848 // Otherwise, make this a use of a zext. 1849 return DAG.getSetCC(dl, VT, ZextOp, 1850 DAG.getConstant(C1 & APInt::getLowBitsSet( 1851 ExtDstTyBits, 1852 ExtSrcTyBits), 1853 ExtDstTy), 1854 Cond); 1855 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1856 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1857 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1858 if (N0.getOpcode() == ISD::SETCC && 1859 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 1860 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 1861 if (TrueWhenTrue) 1862 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 1863 // Invert the condition. 1864 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1865 CC = ISD::getSetCCInverse(CC, 1866 N0.getOperand(0).getValueType().isInteger()); 1867 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1868 } 1869 1870 if ((N0.getOpcode() == ISD::XOR || 1871 (N0.getOpcode() == ISD::AND && 1872 N0.getOperand(0).getOpcode() == ISD::XOR && 1873 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1874 isa<ConstantSDNode>(N0.getOperand(1)) && 1875 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1876 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1877 // can only do this if the top bits are known zero. 1878 unsigned BitWidth = N0.getValueSizeInBits(); 1879 if (DAG.MaskedValueIsZero(N0, 1880 APInt::getHighBitsSet(BitWidth, 1881 BitWidth-1))) { 1882 // Okay, get the un-inverted input value. 1883 SDValue Val; 1884 if (N0.getOpcode() == ISD::XOR) 1885 Val = N0.getOperand(0); 1886 else { 1887 assert(N0.getOpcode() == ISD::AND && 1888 N0.getOperand(0).getOpcode() == ISD::XOR); 1889 // ((X^1)&1)^1 -> X & 1 1890 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1891 N0.getOperand(0).getOperand(0), 1892 N0.getOperand(1)); 1893 } 1894 1895 return DAG.getSetCC(dl, VT, Val, N1, 1896 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1897 } 1898 } else if (N1C->getAPIntValue() == 1 && 1899 (VT == MVT::i1 || 1900 getBooleanContents() == ZeroOrOneBooleanContent)) { 1901 SDValue Op0 = N0; 1902 if (Op0.getOpcode() == ISD::TRUNCATE) 1903 Op0 = Op0.getOperand(0); 1904 1905 if ((Op0.getOpcode() == ISD::XOR) && 1906 Op0.getOperand(0).getOpcode() == ISD::SETCC && 1907 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 1908 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 1909 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 1910 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 1911 Cond); 1912 } else if (Op0.getOpcode() == ISD::AND && 1913 isa<ConstantSDNode>(Op0.getOperand(1)) && 1914 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 1915 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 1916 if (Op0.getValueType().bitsGT(VT)) 1917 Op0 = DAG.getNode(ISD::AND, dl, VT, 1918 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 1919 DAG.getConstant(1, VT)); 1920 else if (Op0.getValueType().bitsLT(VT)) 1921 Op0 = DAG.getNode(ISD::AND, dl, VT, 1922 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 1923 DAG.getConstant(1, VT)); 1924 1925 return DAG.getSetCC(dl, VT, Op0, 1926 DAG.getConstant(0, Op0.getValueType()), 1927 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1928 } 1929 } 1930 } 1931 1932 APInt MinVal, MaxVal; 1933 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1934 if (ISD::isSignedIntSetCC(Cond)) { 1935 MinVal = APInt::getSignedMinValue(OperandBitSize); 1936 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1937 } else { 1938 MinVal = APInt::getMinValue(OperandBitSize); 1939 MaxVal = APInt::getMaxValue(OperandBitSize); 1940 } 1941 1942 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1943 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1944 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1945 // X >= C0 --> X > (C0-1) 1946 return DAG.getSetCC(dl, VT, N0, 1947 DAG.getConstant(C1-1, N1.getValueType()), 1948 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1949 } 1950 1951 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1952 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1953 // X <= C0 --> X < (C0+1) 1954 return DAG.getSetCC(dl, VT, N0, 1955 DAG.getConstant(C1+1, N1.getValueType()), 1956 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1957 } 1958 1959 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1960 return DAG.getConstant(0, VT); // X < MIN --> false 1961 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1962 return DAG.getConstant(1, VT); // X >= MIN --> true 1963 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1964 return DAG.getConstant(0, VT); // X > MAX --> false 1965 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1966 return DAG.getConstant(1, VT); // X <= MAX --> true 1967 1968 // Canonicalize setgt X, Min --> setne X, Min 1969 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1970 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1971 // Canonicalize setlt X, Max --> setne X, Max 1972 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1973 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1974 1975 // If we have setult X, 1, turn it into seteq X, 0 1976 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1977 return DAG.getSetCC(dl, VT, N0, 1978 DAG.getConstant(MinVal, N0.getValueType()), 1979 ISD::SETEQ); 1980 // If we have setugt X, Max-1, turn it into seteq X, Max 1981 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1982 return DAG.getSetCC(dl, VT, N0, 1983 DAG.getConstant(MaxVal, N0.getValueType()), 1984 ISD::SETEQ); 1985 1986 // If we have "setcc X, C0", check to see if we can shrink the immediate 1987 // by changing cc. 1988 1989 // SETUGT X, SINTMAX -> SETLT X, 0 1990 if (Cond == ISD::SETUGT && 1991 C1 == APInt::getSignedMaxValue(OperandBitSize)) 1992 return DAG.getSetCC(dl, VT, N0, 1993 DAG.getConstant(0, N1.getValueType()), 1994 ISD::SETLT); 1995 1996 // SETULT X, SINTMIN -> SETGT X, -1 1997 if (Cond == ISD::SETULT && 1998 C1 == APInt::getSignedMinValue(OperandBitSize)) { 1999 SDValue ConstMinusOne = 2000 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 2001 N1.getValueType()); 2002 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 2003 } 2004 2005 // Fold bit comparisons when we can. 2006 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2007 (VT == N0.getValueType() || 2008 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 2009 N0.getOpcode() == ISD::AND) 2010 if (ConstantSDNode *AndRHS = 2011 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2012 EVT ShiftTy = DCI.isBeforeLegalize() ? 2013 getPointerTy() : getShiftAmountTy(); 2014 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2015 // Perform the xform if the AND RHS is a single bit. 2016 if (AndRHS->getAPIntValue().isPowerOf2()) { 2017 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2018 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2019 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 2020 } 2021 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 2022 // (X & 8) == 8 --> (X & 8) >> 3 2023 // Perform the xform if C1 is a single bit. 2024 if (C1.isPowerOf2()) { 2025 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2026 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2027 DAG.getConstant(C1.logBase2(), ShiftTy))); 2028 } 2029 } 2030 } 2031 } 2032 2033 if (isa<ConstantFPSDNode>(N0.getNode())) { 2034 // Constant fold or commute setcc. 2035 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2036 if (O.getNode()) return O; 2037 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2038 // If the RHS of an FP comparison is a constant, simplify it away in 2039 // some cases. 2040 if (CFP->getValueAPF().isNaN()) { 2041 // If an operand is known to be a nan, we can fold it. 2042 switch (ISD::getUnorderedFlavor(Cond)) { 2043 default: llvm_unreachable("Unknown flavor!"); 2044 case 0: // Known false. 2045 return DAG.getConstant(0, VT); 2046 case 1: // Known true. 2047 return DAG.getConstant(1, VT); 2048 case 2: // Undefined. 2049 return DAG.getUNDEF(VT); 2050 } 2051 } 2052 2053 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2054 // constant if knowing that the operand is non-nan is enough. We prefer to 2055 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2056 // materialize 0.0. 2057 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2058 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2059 2060 // If the condition is not legal, see if we can find an equivalent one 2061 // which is legal. 2062 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2063 // If the comparison was an awkward floating-point == or != and one of 2064 // the comparison operands is infinity or negative infinity, convert the 2065 // condition to a less-awkward <= or >=. 2066 if (CFP->getValueAPF().isInfinity()) { 2067 if (CFP->getValueAPF().isNegative()) { 2068 if (Cond == ISD::SETOEQ && 2069 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2070 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2071 if (Cond == ISD::SETUEQ && 2072 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2073 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2074 if (Cond == ISD::SETUNE && 2075 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2076 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2077 if (Cond == ISD::SETONE && 2078 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2079 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2080 } else { 2081 if (Cond == ISD::SETOEQ && 2082 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2083 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2084 if (Cond == ISD::SETUEQ && 2085 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2086 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2087 if (Cond == ISD::SETUNE && 2088 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2089 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2090 if (Cond == ISD::SETONE && 2091 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2092 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2093 } 2094 } 2095 } 2096 } 2097 2098 if (N0 == N1) { 2099 // We can always fold X == X for integer setcc's. 2100 if (N0.getValueType().isInteger()) 2101 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2102 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2103 if (UOF == 2) // FP operators that are undefined on NaNs. 2104 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2105 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2106 return DAG.getConstant(UOF, VT); 2107 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2108 // if it is not already. 2109 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2110 if (NewCond != Cond) 2111 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2112 } 2113 2114 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2115 N0.getValueType().isInteger()) { 2116 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2117 N0.getOpcode() == ISD::XOR) { 2118 // Simplify (X+Y) == (X+Z) --> Y == Z 2119 if (N0.getOpcode() == N1.getOpcode()) { 2120 if (N0.getOperand(0) == N1.getOperand(0)) 2121 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2122 if (N0.getOperand(1) == N1.getOperand(1)) 2123 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2124 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2125 // If X op Y == Y op X, try other combinations. 2126 if (N0.getOperand(0) == N1.getOperand(1)) 2127 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2128 Cond); 2129 if (N0.getOperand(1) == N1.getOperand(0)) 2130 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2131 Cond); 2132 } 2133 } 2134 2135 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2136 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2137 // Turn (X+C1) == C2 --> X == C2-C1 2138 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2139 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2140 DAG.getConstant(RHSC->getAPIntValue()- 2141 LHSR->getAPIntValue(), 2142 N0.getValueType()), Cond); 2143 } 2144 2145 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2146 if (N0.getOpcode() == ISD::XOR) 2147 // If we know that all of the inverted bits are zero, don't bother 2148 // performing the inversion. 2149 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2150 return 2151 DAG.getSetCC(dl, VT, N0.getOperand(0), 2152 DAG.getConstant(LHSR->getAPIntValue() ^ 2153 RHSC->getAPIntValue(), 2154 N0.getValueType()), 2155 Cond); 2156 } 2157 2158 // Turn (C1-X) == C2 --> X == C1-C2 2159 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2160 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2161 return 2162 DAG.getSetCC(dl, VT, N0.getOperand(1), 2163 DAG.getConstant(SUBC->getAPIntValue() - 2164 RHSC->getAPIntValue(), 2165 N0.getValueType()), 2166 Cond); 2167 } 2168 } 2169 } 2170 2171 // Simplify (X+Z) == X --> Z == 0 2172 if (N0.getOperand(0) == N1) 2173 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2174 DAG.getConstant(0, N0.getValueType()), Cond); 2175 if (N0.getOperand(1) == N1) { 2176 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2177 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2178 DAG.getConstant(0, N0.getValueType()), Cond); 2179 else if (N0.getNode()->hasOneUse()) { 2180 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2181 // (Z-X) == X --> Z == X<<1 2182 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 2183 N1, 2184 DAG.getConstant(1, getShiftAmountTy())); 2185 if (!DCI.isCalledByLegalizer()) 2186 DCI.AddToWorklist(SH.getNode()); 2187 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2188 } 2189 } 2190 } 2191 2192 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2193 N1.getOpcode() == ISD::XOR) { 2194 // Simplify X == (X+Z) --> Z == 0 2195 if (N1.getOperand(0) == N0) { 2196 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2197 DAG.getConstant(0, N1.getValueType()), Cond); 2198 } else if (N1.getOperand(1) == N0) { 2199 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2200 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2201 DAG.getConstant(0, N1.getValueType()), Cond); 2202 } else if (N1.getNode()->hasOneUse()) { 2203 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2204 // X == (Z-X) --> X<<1 == Z 2205 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2206 DAG.getConstant(1, getShiftAmountTy())); 2207 if (!DCI.isCalledByLegalizer()) 2208 DCI.AddToWorklist(SH.getNode()); 2209 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2210 } 2211 } 2212 } 2213 2214 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2215 // Note that where y is variable and is known to have at most 2216 // one bit set (for example, if it is z&1) we cannot do this; 2217 // the expressions are not equivalent when y==0. 2218 if (N0.getOpcode() == ISD::AND) 2219 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2220 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2221 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2222 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2223 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2224 } 2225 } 2226 if (N1.getOpcode() == ISD::AND) 2227 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2228 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2229 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2230 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2231 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2232 } 2233 } 2234 } 2235 2236 // Fold away ALL boolean setcc's. 2237 SDValue Temp; 2238 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2239 switch (Cond) { 2240 default: llvm_unreachable("Unknown integer setcc!"); 2241 case ISD::SETEQ: // X == Y -> ~(X^Y) 2242 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2243 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2244 if (!DCI.isCalledByLegalizer()) 2245 DCI.AddToWorklist(Temp.getNode()); 2246 break; 2247 case ISD::SETNE: // X != Y --> (X^Y) 2248 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2249 break; 2250 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2251 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2252 Temp = DAG.getNOT(dl, N0, MVT::i1); 2253 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2254 if (!DCI.isCalledByLegalizer()) 2255 DCI.AddToWorklist(Temp.getNode()); 2256 break; 2257 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2258 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2259 Temp = DAG.getNOT(dl, N1, MVT::i1); 2260 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2261 if (!DCI.isCalledByLegalizer()) 2262 DCI.AddToWorklist(Temp.getNode()); 2263 break; 2264 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2265 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2266 Temp = DAG.getNOT(dl, N0, MVT::i1); 2267 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2268 if (!DCI.isCalledByLegalizer()) 2269 DCI.AddToWorklist(Temp.getNode()); 2270 break; 2271 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2272 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2273 Temp = DAG.getNOT(dl, N1, MVT::i1); 2274 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2275 break; 2276 } 2277 if (VT != MVT::i1) { 2278 if (!DCI.isCalledByLegalizer()) 2279 DCI.AddToWorklist(N0.getNode()); 2280 // FIXME: If running after legalize, we probably can't do this. 2281 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2282 } 2283 return N0; 2284 } 2285 2286 // Could not fold it. 2287 return SDValue(); 2288} 2289 2290/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2291/// node is a GlobalAddress + offset. 2292bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA, 2293 int64_t &Offset) const { 2294 if (isa<GlobalAddressSDNode>(N)) { 2295 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2296 GA = GASD->getGlobal(); 2297 Offset += GASD->getOffset(); 2298 return true; 2299 } 2300 2301 if (N->getOpcode() == ISD::ADD) { 2302 SDValue N1 = N->getOperand(0); 2303 SDValue N2 = N->getOperand(1); 2304 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2305 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2306 if (V) { 2307 Offset += V->getSExtValue(); 2308 return true; 2309 } 2310 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2311 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2312 if (V) { 2313 Offset += V->getSExtValue(); 2314 return true; 2315 } 2316 } 2317 } 2318 return false; 2319} 2320 2321 2322SDValue TargetLowering:: 2323PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2324 // Default implementation: no optimization. 2325 return SDValue(); 2326} 2327 2328//===----------------------------------------------------------------------===// 2329// Inline Assembler Implementation Methods 2330//===----------------------------------------------------------------------===// 2331 2332 2333TargetLowering::ConstraintType 2334TargetLowering::getConstraintType(const std::string &Constraint) const { 2335 // FIXME: lots more standard ones to handle. 2336 if (Constraint.size() == 1) { 2337 switch (Constraint[0]) { 2338 default: break; 2339 case 'r': return C_RegisterClass; 2340 case 'm': // memory 2341 case 'o': // offsetable 2342 case 'V': // not offsetable 2343 return C_Memory; 2344 case 'i': // Simple Integer or Relocatable Constant 2345 case 'n': // Simple Integer 2346 case 's': // Relocatable Constant 2347 case 'X': // Allow ANY value. 2348 case 'I': // Target registers. 2349 case 'J': 2350 case 'K': 2351 case 'L': 2352 case 'M': 2353 case 'N': 2354 case 'O': 2355 case 'P': 2356 return C_Other; 2357 } 2358 } 2359 2360 if (Constraint.size() > 1 && Constraint[0] == '{' && 2361 Constraint[Constraint.size()-1] == '}') 2362 return C_Register; 2363 return C_Unknown; 2364} 2365 2366/// LowerXConstraint - try to replace an X constraint, which matches anything, 2367/// with another that has more specific requirements based on the type of the 2368/// corresponding operand. 2369const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2370 if (ConstraintVT.isInteger()) 2371 return "r"; 2372 if (ConstraintVT.isFloatingPoint()) 2373 return "f"; // works for many targets 2374 return 0; 2375} 2376 2377/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2378/// vector. If it is invalid, don't add anything to Ops. 2379void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2380 char ConstraintLetter, 2381 bool hasMemory, 2382 std::vector<SDValue> &Ops, 2383 SelectionDAG &DAG) const { 2384 switch (ConstraintLetter) { 2385 default: break; 2386 case 'X': // Allows any operand; labels (basic block) use this. 2387 if (Op.getOpcode() == ISD::BasicBlock) { 2388 Ops.push_back(Op); 2389 return; 2390 } 2391 // fall through 2392 case 'i': // Simple Integer or Relocatable Constant 2393 case 'n': // Simple Integer 2394 case 's': { // Relocatable Constant 2395 // These operands are interested in values of the form (GV+C), where C may 2396 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2397 // is possible and fine if either GV or C are missing. 2398 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2399 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2400 2401 // If we have "(add GV, C)", pull out GV/C 2402 if (Op.getOpcode() == ISD::ADD) { 2403 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2404 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2405 if (C == 0 || GA == 0) { 2406 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2407 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2408 } 2409 if (C == 0 || GA == 0) 2410 C = 0, GA = 0; 2411 } 2412 2413 // If we find a valid operand, map to the TargetXXX version so that the 2414 // value itself doesn't get selected. 2415 if (GA) { // Either &GV or &GV+C 2416 if (ConstraintLetter != 'n') { 2417 int64_t Offs = GA->getOffset(); 2418 if (C) Offs += C->getZExtValue(); 2419 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2420 Op.getValueType(), Offs)); 2421 return; 2422 } 2423 } 2424 if (C) { // just C, no GV. 2425 // Simple constants are not allowed for 's'. 2426 if (ConstraintLetter != 's') { 2427 // gcc prints these as sign extended. Sign extend value to 64 bits 2428 // now; without this it would get ZExt'd later in 2429 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2430 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2431 MVT::i64)); 2432 return; 2433 } 2434 } 2435 break; 2436 } 2437 } 2438} 2439 2440std::vector<unsigned> TargetLowering:: 2441getRegClassForInlineAsmConstraint(const std::string &Constraint, 2442 EVT VT) const { 2443 return std::vector<unsigned>(); 2444} 2445 2446 2447std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2448getRegForInlineAsmConstraint(const std::string &Constraint, 2449 EVT VT) const { 2450 if (Constraint[0] != '{') 2451 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2452 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2453 2454 // Remove the braces from around the name. 2455 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2456 2457 // Figure out which register class contains this reg. 2458 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2459 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2460 E = RI->regclass_end(); RCI != E; ++RCI) { 2461 const TargetRegisterClass *RC = *RCI; 2462 2463 // If none of the value types for this register class are valid, we 2464 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2465 bool isLegal = false; 2466 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2467 I != E; ++I) { 2468 if (isTypeLegal(*I)) { 2469 isLegal = true; 2470 break; 2471 } 2472 } 2473 2474 if (!isLegal) continue; 2475 2476 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2477 I != E; ++I) { 2478 if (RegName.equals_lower(RI->getName(*I))) 2479 return std::make_pair(*I, RC); 2480 } 2481 } 2482 2483 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2484} 2485 2486//===----------------------------------------------------------------------===// 2487// Constraint Selection. 2488 2489/// isMatchingInputConstraint - Return true of this is an input operand that is 2490/// a matching constraint like "4". 2491bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2492 assert(!ConstraintCode.empty() && "No known constraint!"); 2493 return isdigit(ConstraintCode[0]); 2494} 2495 2496/// getMatchedOperand - If this is an input matching constraint, this method 2497/// returns the output operand it matches. 2498unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2499 assert(!ConstraintCode.empty() && "No known constraint!"); 2500 return atoi(ConstraintCode.c_str()); 2501} 2502 2503 2504/// getConstraintGenerality - Return an integer indicating how general CT 2505/// is. 2506static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2507 switch (CT) { 2508 default: llvm_unreachable("Unknown constraint type!"); 2509 case TargetLowering::C_Other: 2510 case TargetLowering::C_Unknown: 2511 return 0; 2512 case TargetLowering::C_Register: 2513 return 1; 2514 case TargetLowering::C_RegisterClass: 2515 return 2; 2516 case TargetLowering::C_Memory: 2517 return 3; 2518 } 2519} 2520 2521/// ChooseConstraint - If there are multiple different constraints that we 2522/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2523/// This is somewhat tricky: constraints fall into four classes: 2524/// Other -> immediates and magic values 2525/// Register -> one specific register 2526/// RegisterClass -> a group of regs 2527/// Memory -> memory 2528/// Ideally, we would pick the most specific constraint possible: if we have 2529/// something that fits into a register, we would pick it. The problem here 2530/// is that if we have something that could either be in a register or in 2531/// memory that use of the register could cause selection of *other* 2532/// operands to fail: they might only succeed if we pick memory. Because of 2533/// this the heuristic we use is: 2534/// 2535/// 1) If there is an 'other' constraint, and if the operand is valid for 2536/// that constraint, use it. This makes us take advantage of 'i' 2537/// constraints when available. 2538/// 2) Otherwise, pick the most general constraint present. This prefers 2539/// 'm' over 'r', for example. 2540/// 2541static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2542 bool hasMemory, const TargetLowering &TLI, 2543 SDValue Op, SelectionDAG *DAG) { 2544 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2545 unsigned BestIdx = 0; 2546 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2547 int BestGenerality = -1; 2548 2549 // Loop over the options, keeping track of the most general one. 2550 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2551 TargetLowering::ConstraintType CType = 2552 TLI.getConstraintType(OpInfo.Codes[i]); 2553 2554 // If this is an 'other' constraint, see if the operand is valid for it. 2555 // For example, on X86 we might have an 'rI' constraint. If the operand 2556 // is an integer in the range [0..31] we want to use I (saving a load 2557 // of a register), otherwise we must use 'r'. 2558 if (CType == TargetLowering::C_Other && Op.getNode()) { 2559 assert(OpInfo.Codes[i].size() == 1 && 2560 "Unhandled multi-letter 'other' constraint"); 2561 std::vector<SDValue> ResultOps; 2562 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, 2563 ResultOps, *DAG); 2564 if (!ResultOps.empty()) { 2565 BestType = CType; 2566 BestIdx = i; 2567 break; 2568 } 2569 } 2570 2571 // This constraint letter is more general than the previous one, use it. 2572 int Generality = getConstraintGenerality(CType); 2573 if (Generality > BestGenerality) { 2574 BestType = CType; 2575 BestIdx = i; 2576 BestGenerality = Generality; 2577 } 2578 } 2579 2580 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2581 OpInfo.ConstraintType = BestType; 2582} 2583 2584/// ComputeConstraintToUse - Determines the constraint code and constraint 2585/// type to use for the specific AsmOperandInfo, setting 2586/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2587void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2588 SDValue Op, 2589 bool hasMemory, 2590 SelectionDAG *DAG) const { 2591 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2592 2593 // Single-letter constraints ('r') are very common. 2594 if (OpInfo.Codes.size() == 1) { 2595 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2596 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2597 } else { 2598 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); 2599 } 2600 2601 // 'X' matches anything. 2602 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2603 // Labels and constants are handled elsewhere ('X' is the only thing 2604 // that matches labels). For Functions, the type here is the type of 2605 // the result, which is not what we want to look at; leave them alone. 2606 Value *v = OpInfo.CallOperandVal; 2607 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 2608 OpInfo.CallOperandVal = v; 2609 return; 2610 } 2611 2612 // Otherwise, try to resolve it to something we know about by looking at 2613 // the actual operand type. 2614 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2615 OpInfo.ConstraintCode = Repl; 2616 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2617 } 2618 } 2619} 2620 2621//===----------------------------------------------------------------------===// 2622// Loop Strength Reduction hooks 2623//===----------------------------------------------------------------------===// 2624 2625/// isLegalAddressingMode - Return true if the addressing mode represented 2626/// by AM is legal for this target, for a load/store of the specified type. 2627bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2628 const Type *Ty) const { 2629 // The default implementation of this implements a conservative RISCy, r+r and 2630 // r+i addr mode. 2631 2632 // Allows a sign-extended 16-bit immediate field. 2633 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2634 return false; 2635 2636 // No global is ever allowed as a base. 2637 if (AM.BaseGV) 2638 return false; 2639 2640 // Only support r+r, 2641 switch (AM.Scale) { 2642 case 0: // "r+i" or just "i", depending on HasBaseReg. 2643 break; 2644 case 1: 2645 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2646 return false; 2647 // Otherwise we have r+r or r+i. 2648 break; 2649 case 2: 2650 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2651 return false; 2652 // Allow 2*r as r+r. 2653 break; 2654 } 2655 2656 return true; 2657} 2658 2659/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2660/// return a DAG expression to select that will generate the same value by 2661/// multiplying by a magic number. See: 2662/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2663SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2664 std::vector<SDNode*>* Created) const { 2665 EVT VT = N->getValueType(0); 2666 DebugLoc dl= N->getDebugLoc(); 2667 2668 // Check to see if we can do this. 2669 // FIXME: We should be more aggressive here. 2670 if (!isTypeLegal(VT)) 2671 return SDValue(); 2672 2673 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2674 APInt::ms magics = d.magic(); 2675 2676 // Multiply the numerator (operand 0) by the magic value 2677 // FIXME: We should support doing a MUL in a wider type 2678 SDValue Q; 2679 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 2680 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2681 DAG.getConstant(magics.m, VT)); 2682 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2683 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2684 N->getOperand(0), 2685 DAG.getConstant(magics.m, VT)).getNode(), 1); 2686 else 2687 return SDValue(); // No mulhs or equvialent 2688 // If d > 0 and m < 0, add the numerator 2689 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2690 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2691 if (Created) 2692 Created->push_back(Q.getNode()); 2693 } 2694 // If d < 0 and m > 0, subtract the numerator. 2695 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2696 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2697 if (Created) 2698 Created->push_back(Q.getNode()); 2699 } 2700 // Shift right algebraic if shift value is nonzero 2701 if (magics.s > 0) { 2702 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2703 DAG.getConstant(magics.s, getShiftAmountTy())); 2704 if (Created) 2705 Created->push_back(Q.getNode()); 2706 } 2707 // Extract the sign bit and add it to the quotient 2708 SDValue T = 2709 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2710 getShiftAmountTy())); 2711 if (Created) 2712 Created->push_back(T.getNode()); 2713 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2714} 2715 2716/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2717/// return a DAG expression to select that will generate the same value by 2718/// multiplying by a magic number. See: 2719/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2720SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2721 std::vector<SDNode*>* Created) const { 2722 EVT VT = N->getValueType(0); 2723 DebugLoc dl = N->getDebugLoc(); 2724 2725 // Check to see if we can do this. 2726 // FIXME: We should be more aggressive here. 2727 if (!isTypeLegal(VT)) 2728 return SDValue(); 2729 2730 // FIXME: We should use a narrower constant when the upper 2731 // bits are known to be zero. 2732 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 2733 APInt::mu magics = N1C->getAPIntValue().magicu(); 2734 2735 // Multiply the numerator (operand 0) by the magic value 2736 // FIXME: We should support doing a MUL in a wider type 2737 SDValue Q; 2738 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 2739 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 2740 DAG.getConstant(magics.m, VT)); 2741 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2742 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 2743 N->getOperand(0), 2744 DAG.getConstant(magics.m, VT)).getNode(), 1); 2745 else 2746 return SDValue(); // No mulhu or equvialent 2747 if (Created) 2748 Created->push_back(Q.getNode()); 2749 2750 if (magics.a == 0) { 2751 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 2752 "We shouldn't generate an undefined shift!"); 2753 return DAG.getNode(ISD::SRL, dl, VT, Q, 2754 DAG.getConstant(magics.s, getShiftAmountTy())); 2755 } else { 2756 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2757 if (Created) 2758 Created->push_back(NPQ.getNode()); 2759 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2760 DAG.getConstant(1, getShiftAmountTy())); 2761 if (Created) 2762 Created->push_back(NPQ.getNode()); 2763 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2764 if (Created) 2765 Created->push_back(NPQ.getNode()); 2766 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2767 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2768 } 2769} 2770