TargetLowering.cpp revision ff01277841b824128c74cdb66f74d8082d75e3f6
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/ADT/STLExtras.h" 17#include "llvm/CodeGen/Analysis.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineJumpTableInfo.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/DataLayout.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/GlobalVariable.h" 25#include "llvm/MC/MCAsmInfo.h" 26#include "llvm/MC/MCExpr.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/ErrorHandling.h" 29#include "llvm/Support/MathExtras.h" 30#include "llvm/Target/TargetLoweringObjectFile.h" 31#include "llvm/Target/TargetMachine.h" 32#include "llvm/Target/TargetRegisterInfo.h" 33#include <cctype> 34using namespace llvm; 35 36/// InitLibcallNames - Set default libcall names. 37/// 38static void InitLibcallNames(const char **Names) { 39 Names[RTLIB::SHL_I16] = "__ashlhi3"; 40 Names[RTLIB::SHL_I32] = "__ashlsi3"; 41 Names[RTLIB::SHL_I64] = "__ashldi3"; 42 Names[RTLIB::SHL_I128] = "__ashlti3"; 43 Names[RTLIB::SRL_I16] = "__lshrhi3"; 44 Names[RTLIB::SRL_I32] = "__lshrsi3"; 45 Names[RTLIB::SRL_I64] = "__lshrdi3"; 46 Names[RTLIB::SRL_I128] = "__lshrti3"; 47 Names[RTLIB::SRA_I16] = "__ashrhi3"; 48 Names[RTLIB::SRA_I32] = "__ashrsi3"; 49 Names[RTLIB::SRA_I64] = "__ashrdi3"; 50 Names[RTLIB::SRA_I128] = "__ashrti3"; 51 Names[RTLIB::MUL_I8] = "__mulqi3"; 52 Names[RTLIB::MUL_I16] = "__mulhi3"; 53 Names[RTLIB::MUL_I32] = "__mulsi3"; 54 Names[RTLIB::MUL_I64] = "__muldi3"; 55 Names[RTLIB::MUL_I128] = "__multi3"; 56 Names[RTLIB::MULO_I32] = "__mulosi4"; 57 Names[RTLIB::MULO_I64] = "__mulodi4"; 58 Names[RTLIB::MULO_I128] = "__muloti4"; 59 Names[RTLIB::SDIV_I8] = "__divqi3"; 60 Names[RTLIB::SDIV_I16] = "__divhi3"; 61 Names[RTLIB::SDIV_I32] = "__divsi3"; 62 Names[RTLIB::SDIV_I64] = "__divdi3"; 63 Names[RTLIB::SDIV_I128] = "__divti3"; 64 Names[RTLIB::UDIV_I8] = "__udivqi3"; 65 Names[RTLIB::UDIV_I16] = "__udivhi3"; 66 Names[RTLIB::UDIV_I32] = "__udivsi3"; 67 Names[RTLIB::UDIV_I64] = "__udivdi3"; 68 Names[RTLIB::UDIV_I128] = "__udivti3"; 69 Names[RTLIB::SREM_I8] = "__modqi3"; 70 Names[RTLIB::SREM_I16] = "__modhi3"; 71 Names[RTLIB::SREM_I32] = "__modsi3"; 72 Names[RTLIB::SREM_I64] = "__moddi3"; 73 Names[RTLIB::SREM_I128] = "__modti3"; 74 Names[RTLIB::UREM_I8] = "__umodqi3"; 75 Names[RTLIB::UREM_I16] = "__umodhi3"; 76 Names[RTLIB::UREM_I32] = "__umodsi3"; 77 Names[RTLIB::UREM_I64] = "__umoddi3"; 78 Names[RTLIB::UREM_I128] = "__umodti3"; 79 80 // These are generally not available. 81 Names[RTLIB::SDIVREM_I8] = 0; 82 Names[RTLIB::SDIVREM_I16] = 0; 83 Names[RTLIB::SDIVREM_I32] = 0; 84 Names[RTLIB::SDIVREM_I64] = 0; 85 Names[RTLIB::SDIVREM_I128] = 0; 86 Names[RTLIB::UDIVREM_I8] = 0; 87 Names[RTLIB::UDIVREM_I16] = 0; 88 Names[RTLIB::UDIVREM_I32] = 0; 89 Names[RTLIB::UDIVREM_I64] = 0; 90 Names[RTLIB::UDIVREM_I128] = 0; 91 92 Names[RTLIB::NEG_I32] = "__negsi2"; 93 Names[RTLIB::NEG_I64] = "__negdi2"; 94 Names[RTLIB::ADD_F32] = "__addsf3"; 95 Names[RTLIB::ADD_F64] = "__adddf3"; 96 Names[RTLIB::ADD_F80] = "__addxf3"; 97 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 98 Names[RTLIB::SUB_F32] = "__subsf3"; 99 Names[RTLIB::SUB_F64] = "__subdf3"; 100 Names[RTLIB::SUB_F80] = "__subxf3"; 101 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 102 Names[RTLIB::MUL_F32] = "__mulsf3"; 103 Names[RTLIB::MUL_F64] = "__muldf3"; 104 Names[RTLIB::MUL_F80] = "__mulxf3"; 105 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 106 Names[RTLIB::DIV_F32] = "__divsf3"; 107 Names[RTLIB::DIV_F64] = "__divdf3"; 108 Names[RTLIB::DIV_F80] = "__divxf3"; 109 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 110 Names[RTLIB::REM_F32] = "fmodf"; 111 Names[RTLIB::REM_F64] = "fmod"; 112 Names[RTLIB::REM_F80] = "fmodl"; 113 Names[RTLIB::REM_PPCF128] = "fmodl"; 114 Names[RTLIB::FMA_F32] = "fmaf"; 115 Names[RTLIB::FMA_F64] = "fma"; 116 Names[RTLIB::FMA_F80] = "fmal"; 117 Names[RTLIB::FMA_PPCF128] = "fmal"; 118 Names[RTLIB::POWI_F32] = "__powisf2"; 119 Names[RTLIB::POWI_F64] = "__powidf2"; 120 Names[RTLIB::POWI_F80] = "__powixf2"; 121 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 122 Names[RTLIB::SQRT_F32] = "sqrtf"; 123 Names[RTLIB::SQRT_F64] = "sqrt"; 124 Names[RTLIB::SQRT_F80] = "sqrtl"; 125 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 126 Names[RTLIB::LOG_F32] = "logf"; 127 Names[RTLIB::LOG_F64] = "log"; 128 Names[RTLIB::LOG_F80] = "logl"; 129 Names[RTLIB::LOG_PPCF128] = "logl"; 130 Names[RTLIB::LOG2_F32] = "log2f"; 131 Names[RTLIB::LOG2_F64] = "log2"; 132 Names[RTLIB::LOG2_F80] = "log2l"; 133 Names[RTLIB::LOG2_PPCF128] = "log2l"; 134 Names[RTLIB::LOG10_F32] = "log10f"; 135 Names[RTLIB::LOG10_F64] = "log10"; 136 Names[RTLIB::LOG10_F80] = "log10l"; 137 Names[RTLIB::LOG10_PPCF128] = "log10l"; 138 Names[RTLIB::EXP_F32] = "expf"; 139 Names[RTLIB::EXP_F64] = "exp"; 140 Names[RTLIB::EXP_F80] = "expl"; 141 Names[RTLIB::EXP_PPCF128] = "expl"; 142 Names[RTLIB::EXP2_F32] = "exp2f"; 143 Names[RTLIB::EXP2_F64] = "exp2"; 144 Names[RTLIB::EXP2_F80] = "exp2l"; 145 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 146 Names[RTLIB::SIN_F32] = "sinf"; 147 Names[RTLIB::SIN_F64] = "sin"; 148 Names[RTLIB::SIN_F80] = "sinl"; 149 Names[RTLIB::SIN_PPCF128] = "sinl"; 150 Names[RTLIB::COS_F32] = "cosf"; 151 Names[RTLIB::COS_F64] = "cos"; 152 Names[RTLIB::COS_F80] = "cosl"; 153 Names[RTLIB::COS_PPCF128] = "cosl"; 154 Names[RTLIB::POW_F32] = "powf"; 155 Names[RTLIB::POW_F64] = "pow"; 156 Names[RTLIB::POW_F80] = "powl"; 157 Names[RTLIB::POW_PPCF128] = "powl"; 158 Names[RTLIB::CEIL_F32] = "ceilf"; 159 Names[RTLIB::CEIL_F64] = "ceil"; 160 Names[RTLIB::CEIL_F80] = "ceill"; 161 Names[RTLIB::CEIL_PPCF128] = "ceill"; 162 Names[RTLIB::TRUNC_F32] = "truncf"; 163 Names[RTLIB::TRUNC_F64] = "trunc"; 164 Names[RTLIB::TRUNC_F80] = "truncl"; 165 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 166 Names[RTLIB::RINT_F32] = "rintf"; 167 Names[RTLIB::RINT_F64] = "rint"; 168 Names[RTLIB::RINT_F80] = "rintl"; 169 Names[RTLIB::RINT_PPCF128] = "rintl"; 170 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 171 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 172 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 173 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 174 Names[RTLIB::FLOOR_F32] = "floorf"; 175 Names[RTLIB::FLOOR_F64] = "floor"; 176 Names[RTLIB::FLOOR_F80] = "floorl"; 177 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 178 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 179 Names[RTLIB::COPYSIGN_F64] = "copysign"; 180 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 181 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 182 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 183 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 184 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 185 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 186 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 187 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 188 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 189 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 190 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 191 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 192 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 193 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 194 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 195 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 196 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 197 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 198 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 199 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 200 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 201 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 202 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 203 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 204 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 205 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 206 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 207 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 208 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 209 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 210 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 211 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 212 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 213 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 214 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 215 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 216 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 217 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 218 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 219 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 220 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 221 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 222 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 223 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 224 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 225 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 226 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 227 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 228 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 229 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 230 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 231 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 232 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 233 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 234 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 235 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 236 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 237 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 238 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 239 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 240 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 241 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 242 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 243 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 244 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 245 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 246 Names[RTLIB::OEQ_F32] = "__eqsf2"; 247 Names[RTLIB::OEQ_F64] = "__eqdf2"; 248 Names[RTLIB::UNE_F32] = "__nesf2"; 249 Names[RTLIB::UNE_F64] = "__nedf2"; 250 Names[RTLIB::OGE_F32] = "__gesf2"; 251 Names[RTLIB::OGE_F64] = "__gedf2"; 252 Names[RTLIB::OLT_F32] = "__ltsf2"; 253 Names[RTLIB::OLT_F64] = "__ltdf2"; 254 Names[RTLIB::OLE_F32] = "__lesf2"; 255 Names[RTLIB::OLE_F64] = "__ledf2"; 256 Names[RTLIB::OGT_F32] = "__gtsf2"; 257 Names[RTLIB::OGT_F64] = "__gtdf2"; 258 Names[RTLIB::UO_F32] = "__unordsf2"; 259 Names[RTLIB::UO_F64] = "__unorddf2"; 260 Names[RTLIB::O_F32] = "__unordsf2"; 261 Names[RTLIB::O_F64] = "__unorddf2"; 262 Names[RTLIB::MEMCPY] = "memcpy"; 263 Names[RTLIB::MEMMOVE] = "memmove"; 264 Names[RTLIB::MEMSET] = "memset"; 265 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 268 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 269 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 272 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 273 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 274 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 275 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 276 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 277 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 278 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 279 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 280 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 281 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 282 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 283 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 284 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 285 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 286 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 287 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 288 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 289 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 290 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 291 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 292 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 293 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 294 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 295 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 296 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 297 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 298} 299 300/// InitLibcallCallingConvs - Set default libcall CallingConvs. 301/// 302static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 303 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 304 CCs[i] = CallingConv::C; 305 } 306} 307 308/// getFPEXT - Return the FPEXT_*_* value for the given types, or 309/// UNKNOWN_LIBCALL if there is none. 310RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 311 if (OpVT == MVT::f32) { 312 if (RetVT == MVT::f64) 313 return FPEXT_F32_F64; 314 } 315 316 return UNKNOWN_LIBCALL; 317} 318 319/// getFPROUND - Return the FPROUND_*_* value for the given types, or 320/// UNKNOWN_LIBCALL if there is none. 321RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 322 if (RetVT == MVT::f32) { 323 if (OpVT == MVT::f64) 324 return FPROUND_F64_F32; 325 if (OpVT == MVT::f80) 326 return FPROUND_F80_F32; 327 if (OpVT == MVT::ppcf128) 328 return FPROUND_PPCF128_F32; 329 } else if (RetVT == MVT::f64) { 330 if (OpVT == MVT::f80) 331 return FPROUND_F80_F64; 332 if (OpVT == MVT::ppcf128) 333 return FPROUND_PPCF128_F64; 334 } 335 336 return UNKNOWN_LIBCALL; 337} 338 339/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 340/// UNKNOWN_LIBCALL if there is none. 341RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 342 if (OpVT == MVT::f32) { 343 if (RetVT == MVT::i8) 344 return FPTOSINT_F32_I8; 345 if (RetVT == MVT::i16) 346 return FPTOSINT_F32_I16; 347 if (RetVT == MVT::i32) 348 return FPTOSINT_F32_I32; 349 if (RetVT == MVT::i64) 350 return FPTOSINT_F32_I64; 351 if (RetVT == MVT::i128) 352 return FPTOSINT_F32_I128; 353 } else if (OpVT == MVT::f64) { 354 if (RetVT == MVT::i8) 355 return FPTOSINT_F64_I8; 356 if (RetVT == MVT::i16) 357 return FPTOSINT_F64_I16; 358 if (RetVT == MVT::i32) 359 return FPTOSINT_F64_I32; 360 if (RetVT == MVT::i64) 361 return FPTOSINT_F64_I64; 362 if (RetVT == MVT::i128) 363 return FPTOSINT_F64_I128; 364 } else if (OpVT == MVT::f80) { 365 if (RetVT == MVT::i32) 366 return FPTOSINT_F80_I32; 367 if (RetVT == MVT::i64) 368 return FPTOSINT_F80_I64; 369 if (RetVT == MVT::i128) 370 return FPTOSINT_F80_I128; 371 } else if (OpVT == MVT::ppcf128) { 372 if (RetVT == MVT::i32) 373 return FPTOSINT_PPCF128_I32; 374 if (RetVT == MVT::i64) 375 return FPTOSINT_PPCF128_I64; 376 if (RetVT == MVT::i128) 377 return FPTOSINT_PPCF128_I128; 378 } 379 return UNKNOWN_LIBCALL; 380} 381 382/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 383/// UNKNOWN_LIBCALL if there is none. 384RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 385 if (OpVT == MVT::f32) { 386 if (RetVT == MVT::i8) 387 return FPTOUINT_F32_I8; 388 if (RetVT == MVT::i16) 389 return FPTOUINT_F32_I16; 390 if (RetVT == MVT::i32) 391 return FPTOUINT_F32_I32; 392 if (RetVT == MVT::i64) 393 return FPTOUINT_F32_I64; 394 if (RetVT == MVT::i128) 395 return FPTOUINT_F32_I128; 396 } else if (OpVT == MVT::f64) { 397 if (RetVT == MVT::i8) 398 return FPTOUINT_F64_I8; 399 if (RetVT == MVT::i16) 400 return FPTOUINT_F64_I16; 401 if (RetVT == MVT::i32) 402 return FPTOUINT_F64_I32; 403 if (RetVT == MVT::i64) 404 return FPTOUINT_F64_I64; 405 if (RetVT == MVT::i128) 406 return FPTOUINT_F64_I128; 407 } else if (OpVT == MVT::f80) { 408 if (RetVT == MVT::i32) 409 return FPTOUINT_F80_I32; 410 if (RetVT == MVT::i64) 411 return FPTOUINT_F80_I64; 412 if (RetVT == MVT::i128) 413 return FPTOUINT_F80_I128; 414 } else if (OpVT == MVT::ppcf128) { 415 if (RetVT == MVT::i32) 416 return FPTOUINT_PPCF128_I32; 417 if (RetVT == MVT::i64) 418 return FPTOUINT_PPCF128_I64; 419 if (RetVT == MVT::i128) 420 return FPTOUINT_PPCF128_I128; 421 } 422 return UNKNOWN_LIBCALL; 423} 424 425/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 426/// UNKNOWN_LIBCALL if there is none. 427RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 428 if (OpVT == MVT::i32) { 429 if (RetVT == MVT::f32) 430 return SINTTOFP_I32_F32; 431 if (RetVT == MVT::f64) 432 return SINTTOFP_I32_F64; 433 if (RetVT == MVT::f80) 434 return SINTTOFP_I32_F80; 435 if (RetVT == MVT::ppcf128) 436 return SINTTOFP_I32_PPCF128; 437 } else if (OpVT == MVT::i64) { 438 if (RetVT == MVT::f32) 439 return SINTTOFP_I64_F32; 440 if (RetVT == MVT::f64) 441 return SINTTOFP_I64_F64; 442 if (RetVT == MVT::f80) 443 return SINTTOFP_I64_F80; 444 if (RetVT == MVT::ppcf128) 445 return SINTTOFP_I64_PPCF128; 446 } else if (OpVT == MVT::i128) { 447 if (RetVT == MVT::f32) 448 return SINTTOFP_I128_F32; 449 if (RetVT == MVT::f64) 450 return SINTTOFP_I128_F64; 451 if (RetVT == MVT::f80) 452 return SINTTOFP_I128_F80; 453 if (RetVT == MVT::ppcf128) 454 return SINTTOFP_I128_PPCF128; 455 } 456 return UNKNOWN_LIBCALL; 457} 458 459/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 460/// UNKNOWN_LIBCALL if there is none. 461RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 462 if (OpVT == MVT::i32) { 463 if (RetVT == MVT::f32) 464 return UINTTOFP_I32_F32; 465 if (RetVT == MVT::f64) 466 return UINTTOFP_I32_F64; 467 if (RetVT == MVT::f80) 468 return UINTTOFP_I32_F80; 469 if (RetVT == MVT::ppcf128) 470 return UINTTOFP_I32_PPCF128; 471 } else if (OpVT == MVT::i64) { 472 if (RetVT == MVT::f32) 473 return UINTTOFP_I64_F32; 474 if (RetVT == MVT::f64) 475 return UINTTOFP_I64_F64; 476 if (RetVT == MVT::f80) 477 return UINTTOFP_I64_F80; 478 if (RetVT == MVT::ppcf128) 479 return UINTTOFP_I64_PPCF128; 480 } else if (OpVT == MVT::i128) { 481 if (RetVT == MVT::f32) 482 return UINTTOFP_I128_F32; 483 if (RetVT == MVT::f64) 484 return UINTTOFP_I128_F64; 485 if (RetVT == MVT::f80) 486 return UINTTOFP_I128_F80; 487 if (RetVT == MVT::ppcf128) 488 return UINTTOFP_I128_PPCF128; 489 } 490 return UNKNOWN_LIBCALL; 491} 492 493/// InitCmpLibcallCCs - Set default comparison libcall CC. 494/// 495static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 496 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 497 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 498 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 499 CCs[RTLIB::UNE_F32] = ISD::SETNE; 500 CCs[RTLIB::UNE_F64] = ISD::SETNE; 501 CCs[RTLIB::OGE_F32] = ISD::SETGE; 502 CCs[RTLIB::OGE_F64] = ISD::SETGE; 503 CCs[RTLIB::OLT_F32] = ISD::SETLT; 504 CCs[RTLIB::OLT_F64] = ISD::SETLT; 505 CCs[RTLIB::OLE_F32] = ISD::SETLE; 506 CCs[RTLIB::OLE_F64] = ISD::SETLE; 507 CCs[RTLIB::OGT_F32] = ISD::SETGT; 508 CCs[RTLIB::OGT_F64] = ISD::SETGT; 509 CCs[RTLIB::UO_F32] = ISD::SETNE; 510 CCs[RTLIB::UO_F64] = ISD::SETNE; 511 CCs[RTLIB::O_F32] = ISD::SETEQ; 512 CCs[RTLIB::O_F64] = ISD::SETEQ; 513} 514 515/// NOTE: The constructor takes ownership of TLOF. 516TargetLowering::TargetLowering(const TargetMachine &tm, 517 const TargetLoweringObjectFile *tlof) 518 : TM(tm), TD(TM.getDataLayout()), TLOF(*tlof) { 519 // All operations default to being supported. 520 memset(OpActions, 0, sizeof(OpActions)); 521 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 522 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 523 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 524 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 525 526 // Set default actions for various operations. 527 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 528 // Default all indexed load / store to expand. 529 for (unsigned IM = (unsigned)ISD::PRE_INC; 530 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 531 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 532 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 533 } 534 535 // These operations default to expand. 536 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 537 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 538 } 539 540 // Most targets ignore the @llvm.prefetch intrinsic. 541 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 542 543 // ConstantFP nodes default to expand. Targets can either change this to 544 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 545 // to optimize expansions for certain constants. 546 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 547 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 548 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 549 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 550 551 // These library functions default to expand. 552 setOperationAction(ISD::FLOG , MVT::f16, Expand); 553 setOperationAction(ISD::FLOG2, MVT::f16, Expand); 554 setOperationAction(ISD::FLOG10, MVT::f16, Expand); 555 setOperationAction(ISD::FEXP , MVT::f16, Expand); 556 setOperationAction(ISD::FEXP2, MVT::f16, Expand); 557 setOperationAction(ISD::FFLOOR, MVT::f16, Expand); 558 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand); 559 setOperationAction(ISD::FCEIL, MVT::f16, Expand); 560 setOperationAction(ISD::FRINT, MVT::f16, Expand); 561 setOperationAction(ISD::FTRUNC, MVT::f16, Expand); 562 setOperationAction(ISD::FLOG , MVT::f32, Expand); 563 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 564 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 565 setOperationAction(ISD::FEXP , MVT::f32, Expand); 566 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 567 setOperationAction(ISD::FFLOOR, MVT::f32, Expand); 568 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand); 569 setOperationAction(ISD::FCEIL, MVT::f32, Expand); 570 setOperationAction(ISD::FRINT, MVT::f32, Expand); 571 setOperationAction(ISD::FTRUNC, MVT::f32, Expand); 572 setOperationAction(ISD::FLOG , MVT::f64, Expand); 573 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 574 setOperationAction(ISD::FLOG10, MVT::f64, Expand); 575 setOperationAction(ISD::FEXP , MVT::f64, Expand); 576 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 577 setOperationAction(ISD::FFLOOR, MVT::f64, Expand); 578 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); 579 setOperationAction(ISD::FCEIL, MVT::f64, Expand); 580 setOperationAction(ISD::FRINT, MVT::f64, Expand); 581 setOperationAction(ISD::FTRUNC, MVT::f64, Expand); 582 583 // Default ISD::TRAP to expand (which turns it into abort). 584 setOperationAction(ISD::TRAP, MVT::Other, Expand); 585 586 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 587 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 588 // 589 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 590 591 IsLittleEndian = TD->isLittleEndian(); 592 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize(0)); 593 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 594 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 595 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 596 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize 597 = maxStoresPerMemmoveOptSize = 4; 598 benefitFromCodePlacementOpt = false; 599 UseUnderscoreSetJmp = false; 600 UseUnderscoreLongJmp = false; 601 SelectIsExpensive = false; 602 IntDivIsCheap = false; 603 Pow2DivIsCheap = false; 604 JumpIsExpensive = false; 605 predictableSelectIsExpensive = false; 606 StackPointerRegisterToSaveRestore = 0; 607 ExceptionPointerRegister = 0; 608 ExceptionSelectorRegister = 0; 609 BooleanContents = UndefinedBooleanContent; 610 BooleanVectorContents = UndefinedBooleanContent; 611 SchedPreferenceInfo = Sched::ILP; 612 JumpBufSize = 0; 613 JumpBufAlignment = 0; 614 MinFunctionAlignment = 0; 615 PrefFunctionAlignment = 0; 616 PrefLoopAlignment = 0; 617 MinStackArgumentAlignment = 1; 618 ShouldFoldAtomicFences = false; 619 InsertFencesForAtomic = false; 620 SupportJumpTables = true; 621 MinimumJumpTableEntries = 4; 622 623 InitLibcallNames(LibcallRoutineNames); 624 InitCmpLibcallCCs(CmpLibcallCCs); 625 InitLibcallCallingConvs(LibcallCallingConvs); 626} 627 628TargetLowering::~TargetLowering() { 629 delete &TLOF; 630} 631 632MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const { 633 return MVT::getIntegerVT(8*TD->getPointerSize(0)); 634} 635 636/// canOpTrap - Returns true if the operation can trap for the value type. 637/// VT must be a legal type. 638bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 639 assert(isTypeLegal(VT)); 640 switch (Op) { 641 default: 642 return false; 643 case ISD::FDIV: 644 case ISD::FREM: 645 case ISD::SDIV: 646 case ISD::UDIV: 647 case ISD::SREM: 648 case ISD::UREM: 649 return true; 650 } 651} 652 653 654static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 655 unsigned &NumIntermediates, 656 EVT &RegisterVT, 657 TargetLowering *TLI) { 658 // Figure out the right, legal destination reg to copy into. 659 unsigned NumElts = VT.getVectorNumElements(); 660 MVT EltTy = VT.getVectorElementType(); 661 662 unsigned NumVectorRegs = 1; 663 664 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 665 // could break down into LHS/RHS like LegalizeDAG does. 666 if (!isPowerOf2_32(NumElts)) { 667 NumVectorRegs = NumElts; 668 NumElts = 1; 669 } 670 671 // Divide the input until we get to a supported size. This will always 672 // end with a scalar if the target doesn't support vectors. 673 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 674 NumElts >>= 1; 675 NumVectorRegs <<= 1; 676 } 677 678 NumIntermediates = NumVectorRegs; 679 680 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 681 if (!TLI->isTypeLegal(NewVT)) 682 NewVT = EltTy; 683 IntermediateVT = NewVT; 684 685 unsigned NewVTSize = NewVT.getSizeInBits(); 686 687 // Convert sizes such as i33 to i64. 688 if (!isPowerOf2_32(NewVTSize)) 689 NewVTSize = NextPowerOf2(NewVTSize); 690 691 EVT DestVT = TLI->getRegisterType(NewVT); 692 RegisterVT = DestVT; 693 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 694 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 695 696 // Otherwise, promotion or legal types use the same number of registers as 697 // the vector decimated to the appropriate level. 698 return NumVectorRegs; 699} 700 701/// isLegalRC - Return true if the value types that can be represented by the 702/// specified register class are all legal. 703bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const { 704 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 705 I != E; ++I) { 706 if (isTypeLegal(*I)) 707 return true; 708 } 709 return false; 710} 711 712/// findRepresentativeClass - Return the largest legal super-reg register class 713/// of the register class for the specified type and its associated "cost". 714std::pair<const TargetRegisterClass*, uint8_t> 715TargetLowering::findRepresentativeClass(MVT VT) const { 716 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 717 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 718 if (!RC) 719 return std::make_pair(RC, 0); 720 721 // Compute the set of all super-register classes. 722 BitVector SuperRegRC(TRI->getNumRegClasses()); 723 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 724 SuperRegRC.setBitsInMask(RCI.getMask()); 725 726 // Find the first legal register class with the largest spill size. 727 const TargetRegisterClass *BestRC = RC; 728 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 729 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 730 // We want the largest possible spill size. 731 if (SuperRC->getSize() <= BestRC->getSize()) 732 continue; 733 if (!isLegalRC(SuperRC)) 734 continue; 735 BestRC = SuperRC; 736 } 737 return std::make_pair(BestRC, 1); 738} 739 740/// computeRegisterProperties - Once all of the register classes are added, 741/// this allows us to compute derived properties we expose. 742void TargetLowering::computeRegisterProperties() { 743 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 744 "Too many value types for ValueTypeActions to hold!"); 745 746 // Everything defaults to needing one register. 747 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 748 NumRegistersForVT[i] = 1; 749 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 750 } 751 // ...except isVoid, which doesn't need any registers. 752 NumRegistersForVT[MVT::isVoid] = 0; 753 754 // Find the largest integer register class. 755 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 756 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 757 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 758 759 // Every integer value type larger than this largest register takes twice as 760 // many registers to represent as the previous ValueType. 761 for (unsigned ExpandedReg = LargestIntReg + 1; 762 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 763 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 764 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 765 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 766 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 767 TypeExpandInteger); 768 } 769 770 // Inspect all of the ValueType's smaller than the largest integer 771 // register to see which ones need promotion. 772 unsigned LegalIntReg = LargestIntReg; 773 for (unsigned IntReg = LargestIntReg - 1; 774 IntReg >= (unsigned)MVT::i1; --IntReg) { 775 MVT IVT = (MVT::SimpleValueType)IntReg; 776 if (isTypeLegal(IVT)) { 777 LegalIntReg = IntReg; 778 } else { 779 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 780 (const MVT::SimpleValueType)LegalIntReg; 781 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 782 } 783 } 784 785 // ppcf128 type is really two f64's. 786 if (!isTypeLegal(MVT::ppcf128)) { 787 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 788 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 789 TransformToType[MVT::ppcf128] = MVT::f64; 790 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 791 } 792 793 // Decide how to handle f64. If the target does not have native f64 support, 794 // expand it to i64 and we will be generating soft float library calls. 795 if (!isTypeLegal(MVT::f64)) { 796 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 797 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 798 TransformToType[MVT::f64] = MVT::i64; 799 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 800 } 801 802 // Decide how to handle f32. If the target does not have native support for 803 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 804 if (!isTypeLegal(MVT::f32)) { 805 if (isTypeLegal(MVT::f64)) { 806 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 807 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 808 TransformToType[MVT::f32] = MVT::f64; 809 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger); 810 } else { 811 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 812 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 813 TransformToType[MVT::f32] = MVT::i32; 814 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 815 } 816 } 817 818 // Loop over all of the vector value types to see which need transformations. 819 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 820 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 821 MVT VT = (MVT::SimpleValueType)i; 822 if (isTypeLegal(VT)) continue; 823 824 // Determine if there is a legal wider type. If so, we should promote to 825 // that wider vector type. 826 MVT EltVT = VT.getVectorElementType(); 827 unsigned NElts = VT.getVectorNumElements(); 828 if (NElts != 1 && !shouldSplitVectorElementType(EltVT)) { 829 bool IsLegalWiderType = false; 830 // First try to promote the elements of integer vectors. If no legal 831 // promotion was found, fallback to the widen-vector method. 832 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 833 MVT SVT = (MVT::SimpleValueType)nVT; 834 // Promote vectors of integers to vectors with the same number 835 // of elements, with a wider element type. 836 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 837 && SVT.getVectorNumElements() == NElts && 838 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) { 839 TransformToType[i] = SVT; 840 RegisterTypeForVT[i] = SVT; 841 NumRegistersForVT[i] = 1; 842 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 843 IsLegalWiderType = true; 844 break; 845 } 846 } 847 848 if (IsLegalWiderType) continue; 849 850 // Try to widen the vector. 851 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 852 MVT SVT = (MVT::SimpleValueType)nVT; 853 if (SVT.getVectorElementType() == EltVT && 854 SVT.getVectorNumElements() > NElts && 855 isTypeLegal(SVT)) { 856 TransformToType[i] = SVT; 857 RegisterTypeForVT[i] = SVT; 858 NumRegistersForVT[i] = 1; 859 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 860 IsLegalWiderType = true; 861 break; 862 } 863 } 864 if (IsLegalWiderType) continue; 865 } 866 867 MVT IntermediateVT; 868 EVT RegisterVT; 869 unsigned NumIntermediates; 870 NumRegistersForVT[i] = 871 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 872 RegisterVT, this); 873 RegisterTypeForVT[i] = RegisterVT; 874 875 MVT NVT = VT.getPow2VectorType(); 876 if (NVT == VT) { 877 // Type is already a power of 2. The default action is to split. 878 TransformToType[i] = MVT::Other; 879 unsigned NumElts = VT.getVectorNumElements(); 880 ValueTypeActions.setTypeAction(VT, 881 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector); 882 } else { 883 TransformToType[i] = NVT; 884 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 885 } 886 } 887 888 // Determine the 'representative' register class for each value type. 889 // An representative register class is the largest (meaning one which is 890 // not a sub-register class / subreg register class) legal register class for 891 // a group of value types. For example, on i386, i8, i16, and i32 892 // representative would be GR32; while on x86_64 it's GR64. 893 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 894 const TargetRegisterClass* RRC; 895 uint8_t Cost; 896 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 897 RepRegClassForVT[i] = RRC; 898 RepRegClassCostForVT[i] = Cost; 899 } 900} 901 902const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 903 return NULL; 904} 905 906EVT TargetLowering::getSetCCResultType(EVT VT) const { 907 assert(!VT.isVector() && "No default SetCC type for vectors!"); 908 return getPointerTy(0).SimpleTy; 909} 910 911MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 912 return MVT::i32; // return the default value 913} 914 915/// getVectorTypeBreakdown - Vector types are broken down into some number of 916/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 917/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 918/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 919/// 920/// This method returns the number of registers needed, and the VT for each 921/// register. It also returns the VT and quantity of the intermediate values 922/// before they are promoted/expanded. 923/// 924unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 925 EVT &IntermediateVT, 926 unsigned &NumIntermediates, 927 EVT &RegisterVT) const { 928 unsigned NumElts = VT.getVectorNumElements(); 929 930 // If there is a wider vector type with the same element type as this one, 931 // or a promoted vector type that has the same number of elements which 932 // are wider, then we should convert to that legal vector type. 933 // This handles things like <2 x float> -> <4 x float> and 934 // <4 x i1> -> <4 x i32>. 935 LegalizeTypeAction TA = getTypeAction(Context, VT); 936 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 937 RegisterVT = getTypeToTransformTo(Context, VT); 938 if (isTypeLegal(RegisterVT)) { 939 IntermediateVT = RegisterVT; 940 NumIntermediates = 1; 941 return 1; 942 } 943 } 944 945 // Figure out the right, legal destination reg to copy into. 946 EVT EltTy = VT.getVectorElementType(); 947 948 unsigned NumVectorRegs = 1; 949 950 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 951 // could break down into LHS/RHS like LegalizeDAG does. 952 if (!isPowerOf2_32(NumElts)) { 953 NumVectorRegs = NumElts; 954 NumElts = 1; 955 } 956 957 // Divide the input until we get to a supported size. This will always 958 // end with a scalar if the target doesn't support vectors. 959 while (NumElts > 1 && !isTypeLegal( 960 EVT::getVectorVT(Context, EltTy, NumElts))) { 961 NumElts >>= 1; 962 NumVectorRegs <<= 1; 963 } 964 965 NumIntermediates = NumVectorRegs; 966 967 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 968 if (!isTypeLegal(NewVT)) 969 NewVT = EltTy; 970 IntermediateVT = NewVT; 971 972 EVT DestVT = getRegisterType(Context, NewVT); 973 RegisterVT = DestVT; 974 unsigned NewVTSize = NewVT.getSizeInBits(); 975 976 // Convert sizes such as i33 to i64. 977 if (!isPowerOf2_32(NewVTSize)) 978 NewVTSize = NextPowerOf2(NewVTSize); 979 980 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 981 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 982 983 // Otherwise, promotion or legal types use the same number of registers as 984 // the vector decimated to the appropriate level. 985 return NumVectorRegs; 986} 987 988/// Get the EVTs and ArgFlags collections that represent the legalized return 989/// type of the given function. This does not require a DAG or a return value, 990/// and is suitable for use before any DAGs for the function are constructed. 991/// TODO: Move this out of TargetLowering.cpp. 992void llvm::GetReturnInfo(Type* ReturnType, Attribute attr, 993 SmallVectorImpl<ISD::OutputArg> &Outs, 994 const TargetLowering &TLI) { 995 SmallVector<EVT, 4> ValueVTs; 996 ComputeValueVTs(TLI, ReturnType, ValueVTs); 997 unsigned NumValues = ValueVTs.size(); 998 if (NumValues == 0) return; 999 1000 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1001 EVT VT = ValueVTs[j]; 1002 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1003 1004 if (attr.hasAttribute(Attribute::SExt)) 1005 ExtendKind = ISD::SIGN_EXTEND; 1006 else if (attr.hasAttribute(Attribute::ZExt)) 1007 ExtendKind = ISD::ZERO_EXTEND; 1008 1009 // FIXME: C calling convention requires the return type to be promoted to 1010 // at least 32-bit. But this is not necessary for non-C calling 1011 // conventions. The frontend should mark functions whose return values 1012 // require promoting with signext or zeroext attributes. 1013 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1014 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1015 if (VT.bitsLT(MinVT)) 1016 VT = MinVT; 1017 } 1018 1019 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1020 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1021 1022 // 'inreg' on function refers to return value 1023 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1024 if (attr.hasAttribute(Attribute::InReg)) 1025 Flags.setInReg(); 1026 1027 // Propagate extension type if any 1028 if (attr.hasAttribute(Attribute::SExt)) 1029 Flags.setSExt(); 1030 else if (attr.hasAttribute(Attribute::ZExt)) 1031 Flags.setZExt(); 1032 1033 for (unsigned i = 0; i < NumParts; ++i) 1034 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true, 0, 0)); 1035 } 1036} 1037 1038/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1039/// function arguments in the caller parameter area. This is the actual 1040/// alignment, not its logarithm. 1041unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const { 1042 return TD->getCallFrameTypeAlignment(Ty); 1043} 1044 1045/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1046/// current function. The returned value is a member of the 1047/// MachineJumpTableInfo::JTEntryKind enum. 1048unsigned TargetLowering::getJumpTableEncoding() const { 1049 // In non-pic modes, just use the address of a block. 1050 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 1051 return MachineJumpTableInfo::EK_BlockAddress; 1052 1053 // In PIC mode, if the target supports a GPRel32 directive, use it. 1054 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 1055 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 1056 1057 // Otherwise, use a label difference. 1058 return MachineJumpTableInfo::EK_LabelDifference32; 1059} 1060 1061SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1062 SelectionDAG &DAG) const { 1063 // If our PIC model is GP relative, use the global offset table as the base. 1064 unsigned JTEncoding = getJumpTableEncoding(); 1065 1066 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) || 1067 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress)) 1068 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0)); 1069 1070 return Table; 1071} 1072 1073/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1074/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1075/// MCExpr. 1076const MCExpr * 1077TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1078 unsigned JTI,MCContext &Ctx) const{ 1079 // The normal PIC reloc base is the label at the start of the jump table. 1080 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 1081} 1082 1083bool 1084TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1085 // Assume that everything is safe in static mode. 1086 if (getTargetMachine().getRelocationModel() == Reloc::Static) 1087 return true; 1088 1089 // In dynamic-no-pic mode, assume that known defined values are safe. 1090 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 1091 GA && 1092 !GA->getGlobal()->isDeclaration() && 1093 !GA->getGlobal()->isWeakForLinker()) 1094 return true; 1095 1096 // Otherwise assume nothing is safe. 1097 return false; 1098} 1099 1100//===----------------------------------------------------------------------===// 1101// Optimization Methods 1102//===----------------------------------------------------------------------===// 1103 1104/// ShrinkDemandedConstant - Check to see if the specified operand of the 1105/// specified instruction is a constant integer. If so, check to see if there 1106/// are any bits set in the constant that are not demanded. If so, shrink the 1107/// constant and return true. 1108bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 1109 const APInt &Demanded) { 1110 DebugLoc dl = Op.getDebugLoc(); 1111 1112 // FIXME: ISD::SELECT, ISD::SELECT_CC 1113 switch (Op.getOpcode()) { 1114 default: break; 1115 case ISD::XOR: 1116 case ISD::AND: 1117 case ISD::OR: { 1118 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1119 if (!C) return false; 1120 1121 if (Op.getOpcode() == ISD::XOR && 1122 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 1123 return false; 1124 1125 // if we can expand it to have all bits set, do it 1126 if (C->getAPIntValue().intersects(~Demanded)) { 1127 EVT VT = Op.getValueType(); 1128 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 1129 DAG.getConstant(Demanded & 1130 C->getAPIntValue(), 1131 VT)); 1132 return CombineTo(Op, New); 1133 } 1134 1135 break; 1136 } 1137 } 1138 1139 return false; 1140} 1141 1142/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 1143/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 1144/// cast, but it could be generalized for targets with other types of 1145/// implicit widening casts. 1146bool 1147TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 1148 unsigned BitWidth, 1149 const APInt &Demanded, 1150 DebugLoc dl) { 1151 assert(Op.getNumOperands() == 2 && 1152 "ShrinkDemandedOp only supports binary operators!"); 1153 assert(Op.getNode()->getNumValues() == 1 && 1154 "ShrinkDemandedOp only supports nodes with one result!"); 1155 1156 // Don't do this if the node has another user, which may require the 1157 // full value. 1158 if (!Op.getNode()->hasOneUse()) 1159 return false; 1160 1161 // Search for the smallest integer type with free casts to and from 1162 // Op's type. For expedience, just check power-of-2 integer types. 1163 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1164 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros(); 1165 unsigned SmallVTBits = DemandedSize; 1166 if (!isPowerOf2_32(SmallVTBits)) 1167 SmallVTBits = NextPowerOf2(SmallVTBits); 1168 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 1169 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 1170 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 1171 TLI.isZExtFree(SmallVT, Op.getValueType())) { 1172 // We found a type with free casts. 1173 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 1174 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1175 Op.getNode()->getOperand(0)), 1176 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1177 Op.getNode()->getOperand(1))); 1178 bool NeedZext = DemandedSize > SmallVTBits; 1179 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND, 1180 dl, Op.getValueType(), X); 1181 return CombineTo(Op, Z); 1182 } 1183 } 1184 return false; 1185} 1186 1187/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1188/// DemandedMask bits of the result of Op are ever used downstream. If we can 1189/// use this information to simplify Op, create a new simplified DAG node and 1190/// return true, returning the original and new nodes in Old and New. Otherwise, 1191/// analyze the expression and return a mask of KnownOne and KnownZero bits for 1192/// the expression (used to simplify the caller). The KnownZero/One bits may 1193/// only be accurate for those bits in the DemandedMask. 1194bool TargetLowering::SimplifyDemandedBits(SDValue Op, 1195 const APInt &DemandedMask, 1196 APInt &KnownZero, 1197 APInt &KnownOne, 1198 TargetLoweringOpt &TLO, 1199 unsigned Depth) const { 1200 unsigned BitWidth = DemandedMask.getBitWidth(); 1201 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 1202 "Mask size mismatches value type size!"); 1203 APInt NewMask = DemandedMask; 1204 DebugLoc dl = Op.getDebugLoc(); 1205 1206 // Don't know anything. 1207 KnownZero = KnownOne = APInt(BitWidth, 0); 1208 1209 // Other users may use these bits. 1210 if (!Op.getNode()->hasOneUse()) { 1211 if (Depth != 0) { 1212 // If not at the root, Just compute the KnownZero/KnownOne bits to 1213 // simplify things downstream. 1214 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); 1215 return false; 1216 } 1217 // If this is the root being simplified, allow it to have multiple uses, 1218 // just set the NewMask to all bits. 1219 NewMask = APInt::getAllOnesValue(BitWidth); 1220 } else if (DemandedMask == 0) { 1221 // Not demanding any bits from Op. 1222 if (Op.getOpcode() != ISD::UNDEF) 1223 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 1224 return false; 1225 } else if (Depth == 6) { // Limit search depth. 1226 return false; 1227 } 1228 1229 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1230 switch (Op.getOpcode()) { 1231 case ISD::Constant: 1232 // We know all of the bits for a constant! 1233 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue(); 1234 KnownZero = ~KnownOne; 1235 return false; // Don't fall through, will infinitely loop. 1236 case ISD::AND: 1237 // If the RHS is a constant, check to see if the LHS would be zero without 1238 // using the bits from the RHS. Below, we use knowledge about the RHS to 1239 // simplify the LHS, here we're using information from the LHS to simplify 1240 // the RHS. 1241 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1242 APInt LHSZero, LHSOne; 1243 // Do not increment Depth here; that can cause an infinite loop. 1244 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth); 1245 // If the LHS already has zeros where RHSC does, this and is dead. 1246 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1247 return TLO.CombineTo(Op, Op.getOperand(0)); 1248 // If any of the set bits in the RHS are known zero on the LHS, shrink 1249 // the constant. 1250 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1251 return true; 1252 } 1253 1254 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1255 KnownOne, TLO, Depth+1)) 1256 return true; 1257 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1258 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1259 KnownZero2, KnownOne2, TLO, Depth+1)) 1260 return true; 1261 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1262 1263 // If all of the demanded bits are known one on one side, return the other. 1264 // These bits cannot contribute to the result of the 'and'. 1265 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1266 return TLO.CombineTo(Op, Op.getOperand(0)); 1267 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1268 return TLO.CombineTo(Op, Op.getOperand(1)); 1269 // If all of the demanded bits in the inputs are known zeros, return zero. 1270 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1271 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1272 // If the RHS is a constant, see if we can simplify it. 1273 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1274 return true; 1275 // If the operation can be done in a smaller type, do so. 1276 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1277 return true; 1278 1279 // Output known-1 bits are only known if set in both the LHS & RHS. 1280 KnownOne &= KnownOne2; 1281 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1282 KnownZero |= KnownZero2; 1283 break; 1284 case ISD::OR: 1285 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1286 KnownOne, TLO, Depth+1)) 1287 return true; 1288 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1289 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1290 KnownZero2, KnownOne2, TLO, Depth+1)) 1291 return true; 1292 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1293 1294 // If all of the demanded bits are known zero on one side, return the other. 1295 // These bits cannot contribute to the result of the 'or'. 1296 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1297 return TLO.CombineTo(Op, Op.getOperand(0)); 1298 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1299 return TLO.CombineTo(Op, Op.getOperand(1)); 1300 // If all of the potentially set bits on one side are known to be set on 1301 // the other side, just use the 'other' side. 1302 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1303 return TLO.CombineTo(Op, Op.getOperand(0)); 1304 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1305 return TLO.CombineTo(Op, Op.getOperand(1)); 1306 // If the RHS is a constant, see if we can simplify it. 1307 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1308 return true; 1309 // If the operation can be done in a smaller type, do so. 1310 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1311 return true; 1312 1313 // Output known-0 bits are only known if clear in both the LHS & RHS. 1314 KnownZero &= KnownZero2; 1315 // Output known-1 are known to be set if set in either the LHS | RHS. 1316 KnownOne |= KnownOne2; 1317 break; 1318 case ISD::XOR: 1319 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1320 KnownOne, TLO, Depth+1)) 1321 return true; 1322 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1323 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1324 KnownOne2, TLO, Depth+1)) 1325 return true; 1326 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1327 1328 // If all of the demanded bits are known zero on one side, return the other. 1329 // These bits cannot contribute to the result of the 'xor'. 1330 if ((KnownZero & NewMask) == NewMask) 1331 return TLO.CombineTo(Op, Op.getOperand(0)); 1332 if ((KnownZero2 & NewMask) == NewMask) 1333 return TLO.CombineTo(Op, Op.getOperand(1)); 1334 // If the operation can be done in a smaller type, do so. 1335 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1336 return true; 1337 1338 // If all of the unknown bits are known to be zero on one side or the other 1339 // (but not both) turn this into an *inclusive* or. 1340 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1341 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1342 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1343 Op.getOperand(0), 1344 Op.getOperand(1))); 1345 1346 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1347 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1348 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1349 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1350 1351 // If all of the demanded bits on one side are known, and all of the set 1352 // bits on that side are also known to be set on the other side, turn this 1353 // into an AND, as we know the bits will be cleared. 1354 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1355 // NB: it is okay if more bits are known than are requested 1356 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side 1357 if (KnownOne == KnownOne2) { // set bits are the same on both sides 1358 EVT VT = Op.getValueType(); 1359 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1360 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1361 Op.getOperand(0), ANDC)); 1362 } 1363 } 1364 1365 // If the RHS is a constant, see if we can simplify it. 1366 // for XOR, we prefer to force bits to 1 if they will make a -1. 1367 // if we can't force bits, try to shrink constant 1368 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1369 APInt Expanded = C->getAPIntValue() | (~NewMask); 1370 // if we can expand it to have all bits set, do it 1371 if (Expanded.isAllOnesValue()) { 1372 if (Expanded != C->getAPIntValue()) { 1373 EVT VT = Op.getValueType(); 1374 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1375 TLO.DAG.getConstant(Expanded, VT)); 1376 return TLO.CombineTo(Op, New); 1377 } 1378 // if it already has all the bits set, nothing to change 1379 // but don't shrink either! 1380 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1381 return true; 1382 } 1383 } 1384 1385 KnownZero = KnownZeroOut; 1386 KnownOne = KnownOneOut; 1387 break; 1388 case ISD::SELECT: 1389 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1390 KnownOne, TLO, Depth+1)) 1391 return true; 1392 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1393 KnownOne2, TLO, Depth+1)) 1394 return true; 1395 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1396 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1397 1398 // If the operands are constants, see if we can simplify them. 1399 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1400 return true; 1401 1402 // Only known if known in both the LHS and RHS. 1403 KnownOne &= KnownOne2; 1404 KnownZero &= KnownZero2; 1405 break; 1406 case ISD::SELECT_CC: 1407 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1408 KnownOne, TLO, Depth+1)) 1409 return true; 1410 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1411 KnownOne2, TLO, Depth+1)) 1412 return true; 1413 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1414 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1415 1416 // If the operands are constants, see if we can simplify them. 1417 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1418 return true; 1419 1420 // Only known if known in both the LHS and RHS. 1421 KnownOne &= KnownOne2; 1422 KnownZero &= KnownZero2; 1423 break; 1424 case ISD::SHL: 1425 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1426 unsigned ShAmt = SA->getZExtValue(); 1427 SDValue InOp = Op.getOperand(0); 1428 1429 // If the shift count is an invalid immediate, don't do anything. 1430 if (ShAmt >= BitWidth) 1431 break; 1432 1433 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1434 // single shift. We can do this if the bottom bits (which are shifted 1435 // out) are never demanded. 1436 if (InOp.getOpcode() == ISD::SRL && 1437 isa<ConstantSDNode>(InOp.getOperand(1))) { 1438 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1439 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1440 unsigned Opc = ISD::SHL; 1441 int Diff = ShAmt-C1; 1442 if (Diff < 0) { 1443 Diff = -Diff; 1444 Opc = ISD::SRL; 1445 } 1446 1447 SDValue NewSA = 1448 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1449 EVT VT = Op.getValueType(); 1450 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1451 InOp.getOperand(0), NewSA)); 1452 } 1453 } 1454 1455 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), 1456 KnownZero, KnownOne, TLO, Depth+1)) 1457 return true; 1458 1459 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 1460 // are not demanded. This will likely allow the anyext to be folded away. 1461 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { 1462 SDValue InnerOp = InOp.getNode()->getOperand(0); 1463 EVT InnerVT = InnerOp.getValueType(); 1464 unsigned InnerBits = InnerVT.getSizeInBits(); 1465 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 && 1466 isTypeDesirableForOp(ISD::SHL, InnerVT)) { 1467 EVT ShTy = getShiftAmountTy(InnerVT); 1468 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) 1469 ShTy = InnerVT; 1470 SDValue NarrowShl = 1471 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 1472 TLO.DAG.getConstant(ShAmt, ShTy)); 1473 return 1474 TLO.CombineTo(Op, 1475 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), 1476 NarrowShl)); 1477 } 1478 } 1479 1480 KnownZero <<= SA->getZExtValue(); 1481 KnownOne <<= SA->getZExtValue(); 1482 // low bits known zero. 1483 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1484 } 1485 break; 1486 case ISD::SRL: 1487 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1488 EVT VT = Op.getValueType(); 1489 unsigned ShAmt = SA->getZExtValue(); 1490 unsigned VTSize = VT.getSizeInBits(); 1491 SDValue InOp = Op.getOperand(0); 1492 1493 // If the shift count is an invalid immediate, don't do anything. 1494 if (ShAmt >= BitWidth) 1495 break; 1496 1497 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1498 // single shift. We can do this if the top bits (which are shifted out) 1499 // are never demanded. 1500 if (InOp.getOpcode() == ISD::SHL && 1501 isa<ConstantSDNode>(InOp.getOperand(1))) { 1502 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1503 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1504 unsigned Opc = ISD::SRL; 1505 int Diff = ShAmt-C1; 1506 if (Diff < 0) { 1507 Diff = -Diff; 1508 Opc = ISD::SHL; 1509 } 1510 1511 SDValue NewSA = 1512 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1513 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1514 InOp.getOperand(0), NewSA)); 1515 } 1516 } 1517 1518 // Compute the new bits that are at the top now. 1519 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1520 KnownZero, KnownOne, TLO, Depth+1)) 1521 return true; 1522 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1523 KnownZero = KnownZero.lshr(ShAmt); 1524 KnownOne = KnownOne.lshr(ShAmt); 1525 1526 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1527 KnownZero |= HighBits; // High bits known zero. 1528 } 1529 break; 1530 case ISD::SRA: 1531 // If this is an arithmetic shift right and only the low-bit is set, we can 1532 // always convert this into a logical shr, even if the shift amount is 1533 // variable. The low bit of the shift cannot be an input sign bit unless 1534 // the shift amount is >= the size of the datatype, which is undefined. 1535 if (NewMask == 1) 1536 return TLO.CombineTo(Op, 1537 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1538 Op.getOperand(0), Op.getOperand(1))); 1539 1540 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1541 EVT VT = Op.getValueType(); 1542 unsigned ShAmt = SA->getZExtValue(); 1543 1544 // If the shift count is an invalid immediate, don't do anything. 1545 if (ShAmt >= BitWidth) 1546 break; 1547 1548 APInt InDemandedMask = (NewMask << ShAmt); 1549 1550 // If any of the demanded bits are produced by the sign extension, we also 1551 // demand the input sign bit. 1552 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1553 if (HighBits.intersects(NewMask)) 1554 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1555 1556 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1557 KnownZero, KnownOne, TLO, Depth+1)) 1558 return true; 1559 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1560 KnownZero = KnownZero.lshr(ShAmt); 1561 KnownOne = KnownOne.lshr(ShAmt); 1562 1563 // Handle the sign bit, adjusted to where it is now in the mask. 1564 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1565 1566 // If the input sign bit is known to be zero, or if none of the top bits 1567 // are demanded, turn this into an unsigned shift right. 1568 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1569 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1570 Op.getOperand(0), 1571 Op.getOperand(1))); 1572 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1573 KnownOne |= HighBits; 1574 } 1575 } 1576 break; 1577 case ISD::SIGN_EXTEND_INREG: { 1578 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1579 1580 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1); 1581 // If we only care about the highest bit, don't bother shifting right. 1582 if (MsbMask == DemandedMask) { 1583 unsigned ShAmt = ExVT.getScalarType().getSizeInBits(); 1584 SDValue InOp = Op.getOperand(0); 1585 1586 // Compute the correct shift amount type, which must be getShiftAmountTy 1587 // for scalar types after legalization. 1588 EVT ShiftAmtTy = Op.getValueType(); 1589 if (TLO.LegalTypes() && !ShiftAmtTy.isVector()) 1590 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy); 1591 1592 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy); 1593 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1594 Op.getValueType(), InOp, ShiftAmt)); 1595 } 1596 1597 // Sign extension. Compute the demanded bits in the result that are not 1598 // present in the input. 1599 APInt NewBits = 1600 APInt::getHighBitsSet(BitWidth, 1601 BitWidth - ExVT.getScalarType().getSizeInBits()); 1602 1603 // If none of the extended bits are demanded, eliminate the sextinreg. 1604 if ((NewBits & NewMask) == 0) 1605 return TLO.CombineTo(Op, Op.getOperand(0)); 1606 1607 APInt InSignBit = 1608 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth); 1609 APInt InputDemandedBits = 1610 APInt::getLowBitsSet(BitWidth, 1611 ExVT.getScalarType().getSizeInBits()) & 1612 NewMask; 1613 1614 // Since the sign extended bits are demanded, we know that the sign 1615 // bit is demanded. 1616 InputDemandedBits |= InSignBit; 1617 1618 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1619 KnownZero, KnownOne, TLO, Depth+1)) 1620 return true; 1621 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1622 1623 // If the sign bit of the input is known set or clear, then we know the 1624 // top bits of the result. 1625 1626 // If the input sign bit is known zero, convert this into a zero extension. 1627 if (KnownZero.intersects(InSignBit)) 1628 return TLO.CombineTo(Op, 1629 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT)); 1630 1631 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1632 KnownOne |= NewBits; 1633 KnownZero &= ~NewBits; 1634 } else { // Input sign bit unknown 1635 KnownZero &= ~NewBits; 1636 KnownOne &= ~NewBits; 1637 } 1638 break; 1639 } 1640 case ISD::ZERO_EXTEND: { 1641 unsigned OperandBitWidth = 1642 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1643 APInt InMask = NewMask.trunc(OperandBitWidth); 1644 1645 // If none of the top bits are demanded, convert this into an any_extend. 1646 APInt NewBits = 1647 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1648 if (!NewBits.intersects(NewMask)) 1649 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1650 Op.getValueType(), 1651 Op.getOperand(0))); 1652 1653 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1654 KnownZero, KnownOne, TLO, Depth+1)) 1655 return true; 1656 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1657 KnownZero = KnownZero.zext(BitWidth); 1658 KnownOne = KnownOne.zext(BitWidth); 1659 KnownZero |= NewBits; 1660 break; 1661 } 1662 case ISD::SIGN_EXTEND: { 1663 EVT InVT = Op.getOperand(0).getValueType(); 1664 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1665 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1666 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1667 APInt NewBits = ~InMask & NewMask; 1668 1669 // If none of the top bits are demanded, convert this into an any_extend. 1670 if (NewBits == 0) 1671 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1672 Op.getValueType(), 1673 Op.getOperand(0))); 1674 1675 // Since some of the sign extended bits are demanded, we know that the sign 1676 // bit is demanded. 1677 APInt InDemandedBits = InMask & NewMask; 1678 InDemandedBits |= InSignBit; 1679 InDemandedBits = InDemandedBits.trunc(InBits); 1680 1681 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1682 KnownOne, TLO, Depth+1)) 1683 return true; 1684 KnownZero = KnownZero.zext(BitWidth); 1685 KnownOne = KnownOne.zext(BitWidth); 1686 1687 // If the sign bit is known zero, convert this to a zero extend. 1688 if (KnownZero.intersects(InSignBit)) 1689 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1690 Op.getValueType(), 1691 Op.getOperand(0))); 1692 1693 // If the sign bit is known one, the top bits match. 1694 if (KnownOne.intersects(InSignBit)) { 1695 KnownOne |= NewBits; 1696 assert((KnownZero & NewBits) == 0); 1697 } else { // Otherwise, top bits aren't known. 1698 assert((KnownOne & NewBits) == 0); 1699 assert((KnownZero & NewBits) == 0); 1700 } 1701 break; 1702 } 1703 case ISD::ANY_EXTEND: { 1704 unsigned OperandBitWidth = 1705 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1706 APInt InMask = NewMask.trunc(OperandBitWidth); 1707 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1708 KnownZero, KnownOne, TLO, Depth+1)) 1709 return true; 1710 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1711 KnownZero = KnownZero.zext(BitWidth); 1712 KnownOne = KnownOne.zext(BitWidth); 1713 break; 1714 } 1715 case ISD::TRUNCATE: { 1716 // Simplify the input, using demanded bit information, and compute the known 1717 // zero/one bits live out. 1718 unsigned OperandBitWidth = 1719 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1720 APInt TruncMask = NewMask.zext(OperandBitWidth); 1721 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1722 KnownZero, KnownOne, TLO, Depth+1)) 1723 return true; 1724 KnownZero = KnownZero.trunc(BitWidth); 1725 KnownOne = KnownOne.trunc(BitWidth); 1726 1727 // If the input is only used by this truncate, see if we can shrink it based 1728 // on the known demanded bits. 1729 if (Op.getOperand(0).getNode()->hasOneUse()) { 1730 SDValue In = Op.getOperand(0); 1731 switch (In.getOpcode()) { 1732 default: break; 1733 case ISD::SRL: 1734 // Shrink SRL by a constant if none of the high bits shifted in are 1735 // demanded. 1736 if (TLO.LegalTypes() && 1737 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1738 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1739 // undesirable. 1740 break; 1741 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1742 if (!ShAmt) 1743 break; 1744 SDValue Shift = In.getOperand(1); 1745 if (TLO.LegalTypes()) { 1746 uint64_t ShVal = ShAmt->getZExtValue(); 1747 Shift = 1748 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType())); 1749 } 1750 1751 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1752 OperandBitWidth - BitWidth); 1753 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth); 1754 1755 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1756 // None of the shifted in bits are needed. Add a truncate of the 1757 // shift input, then shift it. 1758 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1759 Op.getValueType(), 1760 In.getOperand(0)); 1761 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1762 Op.getValueType(), 1763 NewTrunc, 1764 Shift)); 1765 } 1766 break; 1767 } 1768 } 1769 1770 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1771 break; 1772 } 1773 case ISD::AssertZext: { 1774 // AssertZext demands all of the high bits, plus any of the low bits 1775 // demanded by its users. 1776 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1777 APInt InMask = APInt::getLowBitsSet(BitWidth, 1778 VT.getSizeInBits()); 1779 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask, 1780 KnownZero, KnownOne, TLO, Depth+1)) 1781 return true; 1782 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1783 1784 KnownZero |= ~InMask & NewMask; 1785 break; 1786 } 1787 case ISD::BITCAST: 1788 // If this is an FP->Int bitcast and if the sign bit is the only 1789 // thing demanded, turn this into a FGETSIGN. 1790 if (!TLO.LegalOperations() && 1791 !Op.getValueType().isVector() && 1792 !Op.getOperand(0).getValueType().isVector() && 1793 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && 1794 Op.getOperand(0).getValueType().isFloatingPoint()) { 1795 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); 1796 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); 1797 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) { 1798 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32; 1799 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1800 // place. We expect the SHL to be eliminated by other optimizations. 1801 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); 1802 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits(); 1803 if (!OpVTLegal && OpVTSizeInBits > 32) 1804 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); 1805 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1806 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); 1807 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1808 Op.getValueType(), 1809 Sign, ShAmt)); 1810 } 1811 } 1812 break; 1813 case ISD::ADD: 1814 case ISD::MUL: 1815 case ISD::SUB: { 1816 // Add, Sub, and Mul don't demand any bits in positions beyond that 1817 // of the highest bit demanded of them. 1818 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1819 BitWidth - NewMask.countLeadingZeros()); 1820 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1821 KnownOne2, TLO, Depth+1)) 1822 return true; 1823 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1824 KnownOne2, TLO, Depth+1)) 1825 return true; 1826 // See if the operation should be performed at a smaller bit width. 1827 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1828 return true; 1829 } 1830 // FALL THROUGH 1831 default: 1832 // Just use ComputeMaskedBits to compute output bits. 1833 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); 1834 break; 1835 } 1836 1837 // If we know the value of all of the demanded bits, return this as a 1838 // constant. 1839 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1840 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1841 1842 return false; 1843} 1844 1845/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1846/// in Mask are known to be either zero or one and return them in the 1847/// KnownZero/KnownOne bitsets. 1848void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1849 APInt &KnownZero, 1850 APInt &KnownOne, 1851 const SelectionDAG &DAG, 1852 unsigned Depth) const { 1853 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1854 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1855 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1856 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1857 "Should use MaskedValueIsZero if you don't know whether Op" 1858 " is a target node!"); 1859 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); 1860} 1861 1862/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1863/// targets that want to expose additional information about sign bits to the 1864/// DAG Combiner. 1865unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1866 unsigned Depth) const { 1867 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1868 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1869 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1870 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1871 "Should use ComputeNumSignBits if you don't know whether Op" 1872 " is a target node!"); 1873 return 1; 1874} 1875 1876/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1877/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1878/// determine which bit is set. 1879/// 1880static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1881 // A left-shift of a constant one will have exactly one bit set, because 1882 // shifting the bit off the end is undefined. 1883 if (Val.getOpcode() == ISD::SHL) 1884 if (ConstantSDNode *C = 1885 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1886 if (C->getAPIntValue() == 1) 1887 return true; 1888 1889 // Similarly, a right-shift of a constant sign-bit will have exactly 1890 // one bit set. 1891 if (Val.getOpcode() == ISD::SRL) 1892 if (ConstantSDNode *C = 1893 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1894 if (C->getAPIntValue().isSignBit()) 1895 return true; 1896 1897 // More could be done here, though the above checks are enough 1898 // to handle some common cases. 1899 1900 // Fall back to ComputeMaskedBits to catch other known cases. 1901 EVT OpVT = Val.getValueType(); 1902 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1903 APInt KnownZero, KnownOne; 1904 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne); 1905 return (KnownZero.countPopulation() == BitWidth - 1) && 1906 (KnownOne.countPopulation() == 1); 1907} 1908 1909/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1910/// and cc. If it is unable to simplify it, return a null SDValue. 1911SDValue 1912TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1913 ISD::CondCode Cond, bool foldBooleans, 1914 DAGCombinerInfo &DCI, DebugLoc dl) const { 1915 SelectionDAG &DAG = DCI.DAG; 1916 1917 // These setcc operations always fold. 1918 switch (Cond) { 1919 default: break; 1920 case ISD::SETFALSE: 1921 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1922 case ISD::SETTRUE: 1923 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1924 } 1925 1926 // Ensure that the constant occurs on the RHS, and fold constant 1927 // comparisons. 1928 if (isa<ConstantSDNode>(N0.getNode())) 1929 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1930 1931 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1932 const APInt &C1 = N1C->getAPIntValue(); 1933 1934 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1935 // equality comparison, then we're just comparing whether X itself is 1936 // zero. 1937 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1938 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1939 N0.getOperand(1).getOpcode() == ISD::Constant) { 1940 const APInt &ShAmt 1941 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1942 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1943 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1944 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1945 // (srl (ctlz x), 5) == 0 -> X != 0 1946 // (srl (ctlz x), 5) != 1 -> X != 0 1947 Cond = ISD::SETNE; 1948 } else { 1949 // (srl (ctlz x), 5) != 0 -> X == 0 1950 // (srl (ctlz x), 5) == 1 -> X == 0 1951 Cond = ISD::SETEQ; 1952 } 1953 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1954 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1955 Zero, Cond); 1956 } 1957 } 1958 1959 SDValue CTPOP = N0; 1960 // Look through truncs that don't change the value of a ctpop. 1961 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) 1962 CTPOP = N0.getOperand(0); 1963 1964 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP && 1965 (N0 == CTPOP || N0.getValueType().getSizeInBits() > 1966 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) { 1967 EVT CTVT = CTPOP.getValueType(); 1968 SDValue CTOp = CTPOP.getOperand(0); 1969 1970 // (ctpop x) u< 2 -> (x & x-1) == 0 1971 // (ctpop x) u> 1 -> (x & x-1) != 0 1972 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ 1973 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, 1974 DAG.getConstant(1, CTVT)); 1975 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub); 1976 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; 1977 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC); 1978 } 1979 1980 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal. 1981 } 1982 1983 // (zext x) == C --> x == (trunc C) 1984 if (DCI.isBeforeLegalize() && N0->hasOneUse() && 1985 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1986 unsigned MinBits = N0.getValueSizeInBits(); 1987 SDValue PreZExt; 1988 if (N0->getOpcode() == ISD::ZERO_EXTEND) { 1989 // ZExt 1990 MinBits = N0->getOperand(0).getValueSizeInBits(); 1991 PreZExt = N0->getOperand(0); 1992 } else if (N0->getOpcode() == ISD::AND) { 1993 // DAGCombine turns costly ZExts into ANDs 1994 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) 1995 if ((C->getAPIntValue()+1).isPowerOf2()) { 1996 MinBits = C->getAPIntValue().countTrailingOnes(); 1997 PreZExt = N0->getOperand(0); 1998 } 1999 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) { 2000 // ZEXTLOAD 2001 if (LN0->getExtensionType() == ISD::ZEXTLOAD) { 2002 MinBits = LN0->getMemoryVT().getSizeInBits(); 2003 PreZExt = N0; 2004 } 2005 } 2006 2007 // Make sure we're not losing bits from the constant. 2008 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) { 2009 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); 2010 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { 2011 // Will get folded away. 2012 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt); 2013 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT); 2014 return DAG.getSetCC(dl, VT, Trunc, C, Cond); 2015 } 2016 } 2017 } 2018 2019 // If the LHS is '(and load, const)', the RHS is 0, 2020 // the test is for equality or unsigned, and all 1 bits of the const are 2021 // in the same partial word, see if we can shorten the load. 2022 if (DCI.isBeforeLegalize() && 2023 N0.getOpcode() == ISD::AND && C1 == 0 && 2024 N0.getNode()->hasOneUse() && 2025 isa<LoadSDNode>(N0.getOperand(0)) && 2026 N0.getOperand(0).getNode()->hasOneUse() && 2027 isa<ConstantSDNode>(N0.getOperand(1))) { 2028 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 2029 APInt bestMask; 2030 unsigned bestWidth = 0, bestOffset = 0; 2031 if (!Lod->isVolatile() && Lod->isUnindexed()) { 2032 unsigned origWidth = N0.getValueType().getSizeInBits(); 2033 unsigned maskWidth = origWidth; 2034 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 2035 // 8 bits, but have to be careful... 2036 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 2037 origWidth = Lod->getMemoryVT().getSizeInBits(); 2038 const APInt &Mask = 2039 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2040 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 2041 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 2042 for (unsigned offset=0; offset<origWidth/width; offset++) { 2043 if ((newMask & Mask) == Mask) { 2044 if (!TD->isLittleEndian()) 2045 bestOffset = (origWidth/width - offset - 1) * (width/8); 2046 else 2047 bestOffset = (uint64_t)offset * (width/8); 2048 bestMask = Mask.lshr(offset * (width/8) * 8); 2049 bestWidth = width; 2050 break; 2051 } 2052 newMask = newMask << width; 2053 } 2054 } 2055 } 2056 if (bestWidth) { 2057 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth); 2058 if (newVT.isRound()) { 2059 EVT PtrType = Lod->getOperand(1).getValueType(); 2060 SDValue Ptr = Lod->getBasePtr(); 2061 if (bestOffset != 0) 2062 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 2063 DAG.getConstant(bestOffset, PtrType)); 2064 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 2065 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 2066 Lod->getPointerInfo().getWithOffset(bestOffset), 2067 false, false, false, NewAlign); 2068 return DAG.getSetCC(dl, VT, 2069 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 2070 DAG.getConstant(bestMask.trunc(bestWidth), 2071 newVT)), 2072 DAG.getConstant(0LL, newVT), Cond); 2073 } 2074 } 2075 } 2076 2077 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 2078 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 2079 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 2080 2081 // If the comparison constant has bits in the upper part, the 2082 // zero-extended value could never match. 2083 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 2084 C1.getBitWidth() - InSize))) { 2085 switch (Cond) { 2086 case ISD::SETUGT: 2087 case ISD::SETUGE: 2088 case ISD::SETEQ: return DAG.getConstant(0, VT); 2089 case ISD::SETULT: 2090 case ISD::SETULE: 2091 case ISD::SETNE: return DAG.getConstant(1, VT); 2092 case ISD::SETGT: 2093 case ISD::SETGE: 2094 // True if the sign bit of C1 is set. 2095 return DAG.getConstant(C1.isNegative(), VT); 2096 case ISD::SETLT: 2097 case ISD::SETLE: 2098 // True if the sign bit of C1 isn't set. 2099 return DAG.getConstant(C1.isNonNegative(), VT); 2100 default: 2101 break; 2102 } 2103 } 2104 2105 // Otherwise, we can perform the comparison with the low bits. 2106 switch (Cond) { 2107 case ISD::SETEQ: 2108 case ISD::SETNE: 2109 case ISD::SETUGT: 2110 case ISD::SETUGE: 2111 case ISD::SETULT: 2112 case ISD::SETULE: { 2113 EVT newVT = N0.getOperand(0).getValueType(); 2114 if (DCI.isBeforeLegalizeOps() || 2115 (isOperationLegal(ISD::SETCC, newVT) && 2116 getCondCodeAction(Cond, newVT.getSimpleVT())==Legal)) 2117 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2118 DAG.getConstant(C1.trunc(InSize), newVT), 2119 Cond); 2120 break; 2121 } 2122 default: 2123 break; // todo, be more careful with signed comparisons 2124 } 2125 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2126 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2127 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2128 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 2129 EVT ExtDstTy = N0.getValueType(); 2130 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 2131 2132 // If the constant doesn't fit into the number of bits for the source of 2133 // the sign extension, it is impossible for both sides to be equal. 2134 if (C1.getMinSignedBits() > ExtSrcTyBits) 2135 return DAG.getConstant(Cond == ISD::SETNE, VT); 2136 2137 SDValue ZextOp; 2138 EVT Op0Ty = N0.getOperand(0).getValueType(); 2139 if (Op0Ty == ExtSrcTy) { 2140 ZextOp = N0.getOperand(0); 2141 } else { 2142 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 2143 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 2144 DAG.getConstant(Imm, Op0Ty)); 2145 } 2146 if (!DCI.isCalledByLegalizer()) 2147 DCI.AddToWorklist(ZextOp.getNode()); 2148 // Otherwise, make this a use of a zext. 2149 return DAG.getSetCC(dl, VT, ZextOp, 2150 DAG.getConstant(C1 & APInt::getLowBitsSet( 2151 ExtDstTyBits, 2152 ExtSrcTyBits), 2153 ExtDstTy), 2154 Cond); 2155 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 2156 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2157 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 2158 if (N0.getOpcode() == ISD::SETCC && 2159 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 2160 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 2161 if (TrueWhenTrue) 2162 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 2163 // Invert the condition. 2164 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 2165 CC = ISD::getSetCCInverse(CC, 2166 N0.getOperand(0).getValueType().isInteger()); 2167 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 2168 } 2169 2170 if ((N0.getOpcode() == ISD::XOR || 2171 (N0.getOpcode() == ISD::AND && 2172 N0.getOperand(0).getOpcode() == ISD::XOR && 2173 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 2174 isa<ConstantSDNode>(N0.getOperand(1)) && 2175 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 2176 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 2177 // can only do this if the top bits are known zero. 2178 unsigned BitWidth = N0.getValueSizeInBits(); 2179 if (DAG.MaskedValueIsZero(N0, 2180 APInt::getHighBitsSet(BitWidth, 2181 BitWidth-1))) { 2182 // Okay, get the un-inverted input value. 2183 SDValue Val; 2184 if (N0.getOpcode() == ISD::XOR) 2185 Val = N0.getOperand(0); 2186 else { 2187 assert(N0.getOpcode() == ISD::AND && 2188 N0.getOperand(0).getOpcode() == ISD::XOR); 2189 // ((X^1)&1)^1 -> X & 1 2190 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 2191 N0.getOperand(0).getOperand(0), 2192 N0.getOperand(1)); 2193 } 2194 2195 return DAG.getSetCC(dl, VT, Val, N1, 2196 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2197 } 2198 } else if (N1C->getAPIntValue() == 1 && 2199 (VT == MVT::i1 || 2200 getBooleanContents(false) == ZeroOrOneBooleanContent)) { 2201 SDValue Op0 = N0; 2202 if (Op0.getOpcode() == ISD::TRUNCATE) 2203 Op0 = Op0.getOperand(0); 2204 2205 if ((Op0.getOpcode() == ISD::XOR) && 2206 Op0.getOperand(0).getOpcode() == ISD::SETCC && 2207 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 2208 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 2209 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 2210 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 2211 Cond); 2212 } 2213 if (Op0.getOpcode() == ISD::AND && 2214 isa<ConstantSDNode>(Op0.getOperand(1)) && 2215 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 2216 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 2217 if (Op0.getValueType().bitsGT(VT)) 2218 Op0 = DAG.getNode(ISD::AND, dl, VT, 2219 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 2220 DAG.getConstant(1, VT)); 2221 else if (Op0.getValueType().bitsLT(VT)) 2222 Op0 = DAG.getNode(ISD::AND, dl, VT, 2223 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 2224 DAG.getConstant(1, VT)); 2225 2226 return DAG.getSetCC(dl, VT, Op0, 2227 DAG.getConstant(0, Op0.getValueType()), 2228 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2229 } 2230 if (Op0.getOpcode() == ISD::AssertZext && 2231 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1) 2232 return DAG.getSetCC(dl, VT, Op0, 2233 DAG.getConstant(0, Op0.getValueType()), 2234 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2235 } 2236 } 2237 2238 APInt MinVal, MaxVal; 2239 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 2240 if (ISD::isSignedIntSetCC(Cond)) { 2241 MinVal = APInt::getSignedMinValue(OperandBitSize); 2242 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 2243 } else { 2244 MinVal = APInt::getMinValue(OperandBitSize); 2245 MaxVal = APInt::getMaxValue(OperandBitSize); 2246 } 2247 2248 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2249 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2250 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2251 // X >= C0 --> X > (C0-1) 2252 return DAG.getSetCC(dl, VT, N0, 2253 DAG.getConstant(C1-1, N1.getValueType()), 2254 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2255 } 2256 2257 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2258 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2259 // X <= C0 --> X < (C0+1) 2260 return DAG.getSetCC(dl, VT, N0, 2261 DAG.getConstant(C1+1, N1.getValueType()), 2262 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2263 } 2264 2265 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2266 return DAG.getConstant(0, VT); // X < MIN --> false 2267 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 2268 return DAG.getConstant(1, VT); // X >= MIN --> true 2269 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 2270 return DAG.getConstant(0, VT); // X > MAX --> false 2271 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 2272 return DAG.getConstant(1, VT); // X <= MAX --> true 2273 2274 // Canonicalize setgt X, Min --> setne X, Min 2275 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2276 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2277 // Canonicalize setlt X, Max --> setne X, Max 2278 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2279 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2280 2281 // If we have setult X, 1, turn it into seteq X, 0 2282 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2283 return DAG.getSetCC(dl, VT, N0, 2284 DAG.getConstant(MinVal, N0.getValueType()), 2285 ISD::SETEQ); 2286 // If we have setugt X, Max-1, turn it into seteq X, Max 2287 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2288 return DAG.getSetCC(dl, VT, N0, 2289 DAG.getConstant(MaxVal, N0.getValueType()), 2290 ISD::SETEQ); 2291 2292 // If we have "setcc X, C0", check to see if we can shrink the immediate 2293 // by changing cc. 2294 2295 // SETUGT X, SINTMAX -> SETLT X, 0 2296 if (Cond == ISD::SETUGT && 2297 C1 == APInt::getSignedMaxValue(OperandBitSize)) 2298 return DAG.getSetCC(dl, VT, N0, 2299 DAG.getConstant(0, N1.getValueType()), 2300 ISD::SETLT); 2301 2302 // SETULT X, SINTMIN -> SETGT X, -1 2303 if (Cond == ISD::SETULT && 2304 C1 == APInt::getSignedMinValue(OperandBitSize)) { 2305 SDValue ConstMinusOne = 2306 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 2307 N1.getValueType()); 2308 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 2309 } 2310 2311 // Fold bit comparisons when we can. 2312 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2313 (VT == N0.getValueType() || 2314 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 2315 N0.getOpcode() == ISD::AND) 2316 if (ConstantSDNode *AndRHS = 2317 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2318 EVT ShiftTy = DCI.isBeforeLegalizeOps() ? 2319 getPointerTy() : getShiftAmountTy(N0.getValueType()); 2320 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2321 // Perform the xform if the AND RHS is a single bit. 2322 if (AndRHS->getAPIntValue().isPowerOf2()) { 2323 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2324 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2325 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 2326 } 2327 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 2328 // (X & 8) == 8 --> (X & 8) >> 3 2329 // Perform the xform if C1 is a single bit. 2330 if (C1.isPowerOf2()) { 2331 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2332 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2333 DAG.getConstant(C1.logBase2(), ShiftTy))); 2334 } 2335 } 2336 } 2337 2338 if (C1.getMinSignedBits() <= 64 && 2339 !isLegalICmpImmediate(C1.getSExtValue())) { 2340 // (X & -256) == 256 -> (X >> 8) == 1 2341 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2342 N0.getOpcode() == ISD::AND && N0.hasOneUse()) { 2343 if (ConstantSDNode *AndRHS = 2344 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2345 const APInt &AndRHSC = AndRHS->getAPIntValue(); 2346 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) { 2347 unsigned ShiftBits = AndRHSC.countTrailingZeros(); 2348 EVT ShiftTy = DCI.isBeforeLegalizeOps() ? 2349 getPointerTy() : getShiftAmountTy(N0.getValueType()); 2350 EVT CmpTy = N0.getValueType(); 2351 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0), 2352 DAG.getConstant(ShiftBits, ShiftTy)); 2353 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy); 2354 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond); 2355 } 2356 } 2357 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || 2358 Cond == ISD::SETULE || Cond == ISD::SETUGT) { 2359 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); 2360 // X < 0x100000000 -> (X >> 32) < 1 2361 // X >= 0x100000000 -> (X >> 32) >= 1 2362 // X <= 0x0ffffffff -> (X >> 32) < 1 2363 // X > 0x0ffffffff -> (X >> 32) >= 1 2364 unsigned ShiftBits; 2365 APInt NewC = C1; 2366 ISD::CondCode NewCond = Cond; 2367 if (AdjOne) { 2368 ShiftBits = C1.countTrailingOnes(); 2369 NewC = NewC + 1; 2370 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 2371 } else { 2372 ShiftBits = C1.countTrailingZeros(); 2373 } 2374 NewC = NewC.lshr(ShiftBits); 2375 if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) { 2376 EVT ShiftTy = DCI.isBeforeLegalizeOps() ? 2377 getPointerTy() : getShiftAmountTy(N0.getValueType()); 2378 EVT CmpTy = N0.getValueType(); 2379 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0, 2380 DAG.getConstant(ShiftBits, ShiftTy)); 2381 SDValue CmpRHS = DAG.getConstant(NewC, CmpTy); 2382 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond); 2383 } 2384 } 2385 } 2386 } 2387 2388 if (isa<ConstantFPSDNode>(N0.getNode())) { 2389 // Constant fold or commute setcc. 2390 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2391 if (O.getNode()) return O; 2392 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2393 // If the RHS of an FP comparison is a constant, simplify it away in 2394 // some cases. 2395 if (CFP->getValueAPF().isNaN()) { 2396 // If an operand is known to be a nan, we can fold it. 2397 switch (ISD::getUnorderedFlavor(Cond)) { 2398 default: llvm_unreachable("Unknown flavor!"); 2399 case 0: // Known false. 2400 return DAG.getConstant(0, VT); 2401 case 1: // Known true. 2402 return DAG.getConstant(1, VT); 2403 case 2: // Undefined. 2404 return DAG.getUNDEF(VT); 2405 } 2406 } 2407 2408 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2409 // constant if knowing that the operand is non-nan is enough. We prefer to 2410 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2411 // materialize 0.0. 2412 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2413 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2414 2415 // If the condition is not legal, see if we can find an equivalent one 2416 // which is legal. 2417 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) { 2418 // If the comparison was an awkward floating-point == or != and one of 2419 // the comparison operands is infinity or negative infinity, convert the 2420 // condition to a less-awkward <= or >=. 2421 if (CFP->getValueAPF().isInfinity()) { 2422 if (CFP->getValueAPF().isNegative()) { 2423 if (Cond == ISD::SETOEQ && 2424 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) 2425 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2426 if (Cond == ISD::SETUEQ && 2427 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) 2428 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2429 if (Cond == ISD::SETUNE && 2430 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType())) 2431 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2432 if (Cond == ISD::SETONE && 2433 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType())) 2434 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2435 } else { 2436 if (Cond == ISD::SETOEQ && 2437 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) 2438 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2439 if (Cond == ISD::SETUEQ && 2440 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) 2441 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2442 if (Cond == ISD::SETUNE && 2443 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType())) 2444 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2445 if (Cond == ISD::SETONE && 2446 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType())) 2447 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2448 } 2449 } 2450 } 2451 } 2452 2453 if (N0 == N1) { 2454 // The sext(setcc()) => setcc() optimization relies on the appropriate 2455 // constant being emitted. 2456 uint64_t EqVal = 0; 2457 switch (getBooleanContents(N0.getValueType().isVector())) { 2458 case UndefinedBooleanContent: 2459 case ZeroOrOneBooleanContent: 2460 EqVal = ISD::isTrueWhenEqual(Cond); 2461 break; 2462 case ZeroOrNegativeOneBooleanContent: 2463 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0; 2464 break; 2465 } 2466 2467 // We can always fold X == X for integer setcc's. 2468 if (N0.getValueType().isInteger()) { 2469 return DAG.getConstant(EqVal, VT); 2470 } 2471 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2472 if (UOF == 2) // FP operators that are undefined on NaNs. 2473 return DAG.getConstant(EqVal, VT); 2474 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2475 return DAG.getConstant(EqVal, VT); 2476 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2477 // if it is not already. 2478 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2479 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() || 2480 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal)) 2481 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2482 } 2483 2484 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2485 N0.getValueType().isInteger()) { 2486 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2487 N0.getOpcode() == ISD::XOR) { 2488 // Simplify (X+Y) == (X+Z) --> Y == Z 2489 if (N0.getOpcode() == N1.getOpcode()) { 2490 if (N0.getOperand(0) == N1.getOperand(0)) 2491 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2492 if (N0.getOperand(1) == N1.getOperand(1)) 2493 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2494 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2495 // If X op Y == Y op X, try other combinations. 2496 if (N0.getOperand(0) == N1.getOperand(1)) 2497 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2498 Cond); 2499 if (N0.getOperand(1) == N1.getOperand(0)) 2500 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2501 Cond); 2502 } 2503 } 2504 2505 // If RHS is a legal immediate value for a compare instruction, we need 2506 // to be careful about increasing register pressure needlessly. 2507 bool LegalRHSImm = false; 2508 2509 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2510 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2511 // Turn (X+C1) == C2 --> X == C2-C1 2512 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2513 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2514 DAG.getConstant(RHSC->getAPIntValue()- 2515 LHSR->getAPIntValue(), 2516 N0.getValueType()), Cond); 2517 } 2518 2519 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2520 if (N0.getOpcode() == ISD::XOR) 2521 // If we know that all of the inverted bits are zero, don't bother 2522 // performing the inversion. 2523 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2524 return 2525 DAG.getSetCC(dl, VT, N0.getOperand(0), 2526 DAG.getConstant(LHSR->getAPIntValue() ^ 2527 RHSC->getAPIntValue(), 2528 N0.getValueType()), 2529 Cond); 2530 } 2531 2532 // Turn (C1-X) == C2 --> X == C1-C2 2533 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2534 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2535 return 2536 DAG.getSetCC(dl, VT, N0.getOperand(1), 2537 DAG.getConstant(SUBC->getAPIntValue() - 2538 RHSC->getAPIntValue(), 2539 N0.getValueType()), 2540 Cond); 2541 } 2542 } 2543 2544 // Could RHSC fold directly into a compare? 2545 if (RHSC->getValueType(0).getSizeInBits() <= 64) 2546 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue()); 2547 } 2548 2549 // Simplify (X+Z) == X --> Z == 0 2550 // Don't do this if X is an immediate that can fold into a cmp 2551 // instruction and X+Z has other uses. It could be an induction variable 2552 // chain, and the transform would increase register pressure. 2553 if (!LegalRHSImm || N0.getNode()->hasOneUse()) { 2554 if (N0.getOperand(0) == N1) 2555 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2556 DAG.getConstant(0, N0.getValueType()), Cond); 2557 if (N0.getOperand(1) == N1) { 2558 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2559 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2560 DAG.getConstant(0, N0.getValueType()), Cond); 2561 if (N0.getNode()->hasOneUse()) { 2562 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2563 // (Z-X) == X --> Z == X<<1 2564 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1, 2565 DAG.getConstant(1, getShiftAmountTy(N1.getValueType()))); 2566 if (!DCI.isCalledByLegalizer()) 2567 DCI.AddToWorklist(SH.getNode()); 2568 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2569 } 2570 } 2571 } 2572 } 2573 2574 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2575 N1.getOpcode() == ISD::XOR) { 2576 // Simplify X == (X+Z) --> Z == 0 2577 if (N1.getOperand(0) == N0) 2578 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2579 DAG.getConstant(0, N1.getValueType()), Cond); 2580 if (N1.getOperand(1) == N0) { 2581 if (DAG.isCommutativeBinOp(N1.getOpcode())) 2582 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2583 DAG.getConstant(0, N1.getValueType()), Cond); 2584 if (N1.getNode()->hasOneUse()) { 2585 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2586 // X == (Z-X) --> X<<1 == Z 2587 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2588 DAG.getConstant(1, getShiftAmountTy(N0.getValueType()))); 2589 if (!DCI.isCalledByLegalizer()) 2590 DCI.AddToWorklist(SH.getNode()); 2591 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2592 } 2593 } 2594 } 2595 2596 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2597 // Note that where y is variable and is known to have at most 2598 // one bit set (for example, if it is z&1) we cannot do this; 2599 // the expressions are not equivalent when y==0. 2600 if (N0.getOpcode() == ISD::AND) 2601 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2602 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2603 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2604 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2605 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2606 } 2607 } 2608 if (N1.getOpcode() == ISD::AND) 2609 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2610 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2611 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2612 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2613 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2614 } 2615 } 2616 } 2617 2618 // Fold away ALL boolean setcc's. 2619 SDValue Temp; 2620 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2621 switch (Cond) { 2622 default: llvm_unreachable("Unknown integer setcc!"); 2623 case ISD::SETEQ: // X == Y -> ~(X^Y) 2624 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2625 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2626 if (!DCI.isCalledByLegalizer()) 2627 DCI.AddToWorklist(Temp.getNode()); 2628 break; 2629 case ISD::SETNE: // X != Y --> (X^Y) 2630 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2631 break; 2632 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2633 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2634 Temp = DAG.getNOT(dl, N0, MVT::i1); 2635 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2636 if (!DCI.isCalledByLegalizer()) 2637 DCI.AddToWorklist(Temp.getNode()); 2638 break; 2639 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2640 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2641 Temp = DAG.getNOT(dl, N1, MVT::i1); 2642 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2643 if (!DCI.isCalledByLegalizer()) 2644 DCI.AddToWorklist(Temp.getNode()); 2645 break; 2646 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2647 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2648 Temp = DAG.getNOT(dl, N0, MVT::i1); 2649 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2650 if (!DCI.isCalledByLegalizer()) 2651 DCI.AddToWorklist(Temp.getNode()); 2652 break; 2653 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2654 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2655 Temp = DAG.getNOT(dl, N1, MVT::i1); 2656 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2657 break; 2658 } 2659 if (VT != MVT::i1) { 2660 if (!DCI.isCalledByLegalizer()) 2661 DCI.AddToWorklist(N0.getNode()); 2662 // FIXME: If running after legalize, we probably can't do this. 2663 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2664 } 2665 return N0; 2666 } 2667 2668 // Could not fold it. 2669 return SDValue(); 2670} 2671 2672/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2673/// node is a GlobalAddress + offset. 2674bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA, 2675 int64_t &Offset) const { 2676 if (isa<GlobalAddressSDNode>(N)) { 2677 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2678 GA = GASD->getGlobal(); 2679 Offset += GASD->getOffset(); 2680 return true; 2681 } 2682 2683 if (N->getOpcode() == ISD::ADD) { 2684 SDValue N1 = N->getOperand(0); 2685 SDValue N2 = N->getOperand(1); 2686 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2687 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2688 if (V) { 2689 Offset += V->getSExtValue(); 2690 return true; 2691 } 2692 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2693 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2694 if (V) { 2695 Offset += V->getSExtValue(); 2696 return true; 2697 } 2698 } 2699 } 2700 2701 return false; 2702} 2703 2704 2705SDValue TargetLowering:: 2706PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2707 // Default implementation: no optimization. 2708 return SDValue(); 2709} 2710 2711//===----------------------------------------------------------------------===// 2712// Inline Assembler Implementation Methods 2713//===----------------------------------------------------------------------===// 2714 2715 2716TargetLowering::ConstraintType 2717TargetLowering::getConstraintType(const std::string &Constraint) const { 2718 if (Constraint.size() == 1) { 2719 switch (Constraint[0]) { 2720 default: break; 2721 case 'r': return C_RegisterClass; 2722 case 'm': // memory 2723 case 'o': // offsetable 2724 case 'V': // not offsetable 2725 return C_Memory; 2726 case 'i': // Simple Integer or Relocatable Constant 2727 case 'n': // Simple Integer 2728 case 'E': // Floating Point Constant 2729 case 'F': // Floating Point Constant 2730 case 's': // Relocatable Constant 2731 case 'p': // Address. 2732 case 'X': // Allow ANY value. 2733 case 'I': // Target registers. 2734 case 'J': 2735 case 'K': 2736 case 'L': 2737 case 'M': 2738 case 'N': 2739 case 'O': 2740 case 'P': 2741 case '<': 2742 case '>': 2743 return C_Other; 2744 } 2745 } 2746 2747 if (Constraint.size() > 1 && Constraint[0] == '{' && 2748 Constraint[Constraint.size()-1] == '}') 2749 return C_Register; 2750 return C_Unknown; 2751} 2752 2753/// LowerXConstraint - try to replace an X constraint, which matches anything, 2754/// with another that has more specific requirements based on the type of the 2755/// corresponding operand. 2756const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2757 if (ConstraintVT.isInteger()) 2758 return "r"; 2759 if (ConstraintVT.isFloatingPoint()) 2760 return "f"; // works for many targets 2761 return 0; 2762} 2763 2764/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2765/// vector. If it is invalid, don't add anything to Ops. 2766void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2767 std::string &Constraint, 2768 std::vector<SDValue> &Ops, 2769 SelectionDAG &DAG) const { 2770 2771 if (Constraint.length() > 1) return; 2772 2773 char ConstraintLetter = Constraint[0]; 2774 switch (ConstraintLetter) { 2775 default: break; 2776 case 'X': // Allows any operand; labels (basic block) use this. 2777 if (Op.getOpcode() == ISD::BasicBlock) { 2778 Ops.push_back(Op); 2779 return; 2780 } 2781 // fall through 2782 case 'i': // Simple Integer or Relocatable Constant 2783 case 'n': // Simple Integer 2784 case 's': { // Relocatable Constant 2785 // These operands are interested in values of the form (GV+C), where C may 2786 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2787 // is possible and fine if either GV or C are missing. 2788 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2789 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2790 2791 // If we have "(add GV, C)", pull out GV/C 2792 if (Op.getOpcode() == ISD::ADD) { 2793 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2794 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2795 if (C == 0 || GA == 0) { 2796 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2797 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2798 } 2799 if (C == 0 || GA == 0) 2800 C = 0, GA = 0; 2801 } 2802 2803 // If we find a valid operand, map to the TargetXXX version so that the 2804 // value itself doesn't get selected. 2805 if (GA) { // Either &GV or &GV+C 2806 if (ConstraintLetter != 'n') { 2807 int64_t Offs = GA->getOffset(); 2808 if (C) Offs += C->getZExtValue(); 2809 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2810 C ? C->getDebugLoc() : DebugLoc(), 2811 Op.getValueType(), Offs)); 2812 return; 2813 } 2814 } 2815 if (C) { // just C, no GV. 2816 // Simple constants are not allowed for 's'. 2817 if (ConstraintLetter != 's') { 2818 // gcc prints these as sign extended. Sign extend value to 64 bits 2819 // now; without this it would get ZExt'd later in 2820 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2821 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2822 MVT::i64)); 2823 return; 2824 } 2825 } 2826 break; 2827 } 2828 } 2829} 2830 2831std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2832getRegForInlineAsmConstraint(const std::string &Constraint, 2833 EVT VT) const { 2834 if (Constraint[0] != '{') 2835 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2836 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2837 2838 // Remove the braces from around the name. 2839 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2840 2841 std::pair<unsigned, const TargetRegisterClass*> R = 2842 std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2843 2844 // Figure out which register class contains this reg. 2845 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2846 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2847 E = RI->regclass_end(); RCI != E; ++RCI) { 2848 const TargetRegisterClass *RC = *RCI; 2849 2850 // If none of the value types for this register class are valid, we 2851 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2852 if (!isLegalRC(RC)) 2853 continue; 2854 2855 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2856 I != E; ++I) { 2857 if (RegName.equals_lower(RI->getName(*I))) { 2858 std::pair<unsigned, const TargetRegisterClass*> S = 2859 std::make_pair(*I, RC); 2860 2861 // If this register class has the requested value type, return it, 2862 // otherwise keep searching and return the first class found 2863 // if no other is found which explicitly has the requested type. 2864 if (RC->hasType(VT)) 2865 return S; 2866 else if (!R.second) 2867 R = S; 2868 } 2869 } 2870 } 2871 2872 return R; 2873} 2874 2875//===----------------------------------------------------------------------===// 2876// Constraint Selection. 2877 2878/// isMatchingInputConstraint - Return true of this is an input operand that is 2879/// a matching constraint like "4". 2880bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2881 assert(!ConstraintCode.empty() && "No known constraint!"); 2882 return isdigit(ConstraintCode[0]); 2883} 2884 2885/// getMatchedOperand - If this is an input matching constraint, this method 2886/// returns the output operand it matches. 2887unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2888 assert(!ConstraintCode.empty() && "No known constraint!"); 2889 return atoi(ConstraintCode.c_str()); 2890} 2891 2892 2893/// ParseConstraints - Split up the constraint string from the inline 2894/// assembly value into the specific constraints and their prefixes, 2895/// and also tie in the associated operand values. 2896/// If this returns an empty vector, and if the constraint string itself 2897/// isn't empty, there was an error parsing. 2898TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints( 2899 ImmutableCallSite CS) const { 2900 /// ConstraintOperands - Information about all of the constraints. 2901 AsmOperandInfoVector ConstraintOperands; 2902 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 2903 unsigned maCount = 0; // Largest number of multiple alternative constraints. 2904 2905 // Do a prepass over the constraints, canonicalizing them, and building up the 2906 // ConstraintOperands list. 2907 InlineAsm::ConstraintInfoVector 2908 ConstraintInfos = IA->ParseConstraints(); 2909 2910 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 2911 unsigned ResNo = 0; // ResNo - The result number of the next output. 2912 2913 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 2914 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 2915 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 2916 2917 // Update multiple alternative constraint count. 2918 if (OpInfo.multipleAlternatives.size() > maCount) 2919 maCount = OpInfo.multipleAlternatives.size(); 2920 2921 OpInfo.ConstraintVT = MVT::Other; 2922 2923 // Compute the value type for each operand. 2924 switch (OpInfo.Type) { 2925 case InlineAsm::isOutput: 2926 // Indirect outputs just consume an argument. 2927 if (OpInfo.isIndirect) { 2928 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2929 break; 2930 } 2931 2932 // The return value of the call is this value. As such, there is no 2933 // corresponding argument. 2934 assert(!CS.getType()->isVoidTy() && 2935 "Bad inline asm!"); 2936 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 2937 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo)); 2938 } else { 2939 assert(ResNo == 0 && "Asm only has one result!"); 2940 OpInfo.ConstraintVT = getValueType(CS.getType()); 2941 } 2942 ++ResNo; 2943 break; 2944 case InlineAsm::isInput: 2945 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2946 break; 2947 case InlineAsm::isClobber: 2948 // Nothing to do. 2949 break; 2950 } 2951 2952 if (OpInfo.CallOperandVal) { 2953 llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); 2954 if (OpInfo.isIndirect) { 2955 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 2956 if (!PtrTy) 2957 report_fatal_error("Indirect operand for inline asm not a pointer!"); 2958 OpTy = PtrTy->getElementType(); 2959 } 2960 2961 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 2962 if (StructType *STy = dyn_cast<StructType>(OpTy)) 2963 if (STy->getNumElements() == 1) 2964 OpTy = STy->getElementType(0); 2965 2966 // If OpTy is not a single value, it may be a struct/union that we 2967 // can tile with integers. 2968 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 2969 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 2970 switch (BitSize) { 2971 default: break; 2972 case 1: 2973 case 8: 2974 case 16: 2975 case 32: 2976 case 64: 2977 case 128: 2978 OpInfo.ConstraintVT = 2979 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true); 2980 break; 2981 } 2982 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) { 2983 OpInfo.ConstraintVT = MVT::getIntegerVT( 2984 8*TD->getPointerSize(PT->getAddressSpace())); 2985 } else { 2986 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true); 2987 } 2988 } 2989 } 2990 2991 // If we have multiple alternative constraints, select the best alternative. 2992 if (ConstraintInfos.size()) { 2993 if (maCount) { 2994 unsigned bestMAIndex = 0; 2995 int bestWeight = -1; 2996 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. 2997 int weight = -1; 2998 unsigned maIndex; 2999 // Compute the sums of the weights for each alternative, keeping track 3000 // of the best (highest weight) one so far. 3001 for (maIndex = 0; maIndex < maCount; ++maIndex) { 3002 int weightSum = 0; 3003 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 3004 cIndex != eIndex; ++cIndex) { 3005 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 3006 if (OpInfo.Type == InlineAsm::isClobber) 3007 continue; 3008 3009 // If this is an output operand with a matching input operand, 3010 // look up the matching input. If their types mismatch, e.g. one 3011 // is an integer, the other is floating point, or their sizes are 3012 // different, flag it as an maCantMatch. 3013 if (OpInfo.hasMatchingInput()) { 3014 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 3015 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 3016 if ((OpInfo.ConstraintVT.isInteger() != 3017 Input.ConstraintVT.isInteger()) || 3018 (OpInfo.ConstraintVT.getSizeInBits() != 3019 Input.ConstraintVT.getSizeInBits())) { 3020 weightSum = -1; // Can't match. 3021 break; 3022 } 3023 } 3024 } 3025 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); 3026 if (weight == -1) { 3027 weightSum = -1; 3028 break; 3029 } 3030 weightSum += weight; 3031 } 3032 // Update best. 3033 if (weightSum > bestWeight) { 3034 bestWeight = weightSum; 3035 bestMAIndex = maIndex; 3036 } 3037 } 3038 3039 // Now select chosen alternative in each constraint. 3040 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 3041 cIndex != eIndex; ++cIndex) { 3042 AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; 3043 if (cInfo.Type == InlineAsm::isClobber) 3044 continue; 3045 cInfo.selectAlternative(bestMAIndex); 3046 } 3047 } 3048 } 3049 3050 // Check and hook up tied operands, choose constraint code to use. 3051 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 3052 cIndex != eIndex; ++cIndex) { 3053 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 3054 3055 // If this is an output operand with a matching input operand, look up the 3056 // matching input. If their types mismatch, e.g. one is an integer, the 3057 // other is floating point, or their sizes are different, flag it as an 3058 // error. 3059 if (OpInfo.hasMatchingInput()) { 3060 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 3061 3062 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 3063 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 3064 getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3065 OpInfo.ConstraintVT); 3066 std::pair<unsigned, const TargetRegisterClass*> InputRC = 3067 getRegForInlineAsmConstraint(Input.ConstraintCode, 3068 Input.ConstraintVT); 3069 if ((OpInfo.ConstraintVT.isInteger() != 3070 Input.ConstraintVT.isInteger()) || 3071 (MatchRC.second != InputRC.second)) { 3072 report_fatal_error("Unsupported asm: input constraint" 3073 " with a matching output constraint of" 3074 " incompatible type!"); 3075 } 3076 } 3077 3078 } 3079 } 3080 3081 return ConstraintOperands; 3082} 3083 3084 3085/// getConstraintGenerality - Return an integer indicating how general CT 3086/// is. 3087static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3088 switch (CT) { 3089 case TargetLowering::C_Other: 3090 case TargetLowering::C_Unknown: 3091 return 0; 3092 case TargetLowering::C_Register: 3093 return 1; 3094 case TargetLowering::C_RegisterClass: 3095 return 2; 3096 case TargetLowering::C_Memory: 3097 return 3; 3098 } 3099 llvm_unreachable("Invalid constraint type"); 3100} 3101 3102/// Examine constraint type and operand type and determine a weight value. 3103/// This object must already have been set up with the operand type 3104/// and the current alternative constraint selected. 3105TargetLowering::ConstraintWeight 3106 TargetLowering::getMultipleConstraintMatchWeight( 3107 AsmOperandInfo &info, int maIndex) const { 3108 InlineAsm::ConstraintCodeVector *rCodes; 3109 if (maIndex >= (int)info.multipleAlternatives.size()) 3110 rCodes = &info.Codes; 3111 else 3112 rCodes = &info.multipleAlternatives[maIndex].Codes; 3113 ConstraintWeight BestWeight = CW_Invalid; 3114 3115 // Loop over the options, keeping track of the most general one. 3116 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { 3117 ConstraintWeight weight = 3118 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); 3119 if (weight > BestWeight) 3120 BestWeight = weight; 3121 } 3122 3123 return BestWeight; 3124} 3125 3126/// Examine constraint type and operand type and determine a weight value. 3127/// This object must already have been set up with the operand type 3128/// and the current alternative constraint selected. 3129TargetLowering::ConstraintWeight 3130 TargetLowering::getSingleConstraintMatchWeight( 3131 AsmOperandInfo &info, const char *constraint) const { 3132 ConstraintWeight weight = CW_Invalid; 3133 Value *CallOperandVal = info.CallOperandVal; 3134 // If we don't have a value, we can't do a match, 3135 // but allow it at the lowest weight. 3136 if (CallOperandVal == NULL) 3137 return CW_Default; 3138 // Look at the constraint type. 3139 switch (*constraint) { 3140 case 'i': // immediate integer. 3141 case 'n': // immediate integer with a known value. 3142 if (isa<ConstantInt>(CallOperandVal)) 3143 weight = CW_Constant; 3144 break; 3145 case 's': // non-explicit intregal immediate. 3146 if (isa<GlobalValue>(CallOperandVal)) 3147 weight = CW_Constant; 3148 break; 3149 case 'E': // immediate float if host format. 3150 case 'F': // immediate float. 3151 if (isa<ConstantFP>(CallOperandVal)) 3152 weight = CW_Constant; 3153 break; 3154 case '<': // memory operand with autodecrement. 3155 case '>': // memory operand with autoincrement. 3156 case 'm': // memory operand. 3157 case 'o': // offsettable memory operand 3158 case 'V': // non-offsettable memory operand 3159 weight = CW_Memory; 3160 break; 3161 case 'r': // general register. 3162 case 'g': // general register, memory operand or immediate integer. 3163 // note: Clang converts "g" to "imr". 3164 if (CallOperandVal->getType()->isIntegerTy()) 3165 weight = CW_Register; 3166 break; 3167 case 'X': // any operand. 3168 default: 3169 weight = CW_Default; 3170 break; 3171 } 3172 return weight; 3173} 3174 3175/// ChooseConstraint - If there are multiple different constraints that we 3176/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 3177/// This is somewhat tricky: constraints fall into four classes: 3178/// Other -> immediates and magic values 3179/// Register -> one specific register 3180/// RegisterClass -> a group of regs 3181/// Memory -> memory 3182/// Ideally, we would pick the most specific constraint possible: if we have 3183/// something that fits into a register, we would pick it. The problem here 3184/// is that if we have something that could either be in a register or in 3185/// memory that use of the register could cause selection of *other* 3186/// operands to fail: they might only succeed if we pick memory. Because of 3187/// this the heuristic we use is: 3188/// 3189/// 1) If there is an 'other' constraint, and if the operand is valid for 3190/// that constraint, use it. This makes us take advantage of 'i' 3191/// constraints when available. 3192/// 2) Otherwise, pick the most general constraint present. This prefers 3193/// 'm' over 'r', for example. 3194/// 3195static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 3196 const TargetLowering &TLI, 3197 SDValue Op, SelectionDAG *DAG) { 3198 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 3199 unsigned BestIdx = 0; 3200 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 3201 int BestGenerality = -1; 3202 3203 // Loop over the options, keeping track of the most general one. 3204 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 3205 TargetLowering::ConstraintType CType = 3206 TLI.getConstraintType(OpInfo.Codes[i]); 3207 3208 // If this is an 'other' constraint, see if the operand is valid for it. 3209 // For example, on X86 we might have an 'rI' constraint. If the operand 3210 // is an integer in the range [0..31] we want to use I (saving a load 3211 // of a register), otherwise we must use 'r'. 3212 if (CType == TargetLowering::C_Other && Op.getNode()) { 3213 assert(OpInfo.Codes[i].size() == 1 && 3214 "Unhandled multi-letter 'other' constraint"); 3215 std::vector<SDValue> ResultOps; 3216 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], 3217 ResultOps, *DAG); 3218 if (!ResultOps.empty()) { 3219 BestType = CType; 3220 BestIdx = i; 3221 break; 3222 } 3223 } 3224 3225 // Things with matching constraints can only be registers, per gcc 3226 // documentation. This mainly affects "g" constraints. 3227 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 3228 continue; 3229 3230 // This constraint letter is more general than the previous one, use it. 3231 int Generality = getConstraintGenerality(CType); 3232 if (Generality > BestGenerality) { 3233 BestType = CType; 3234 BestIdx = i; 3235 BestGenerality = Generality; 3236 } 3237 } 3238 3239 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 3240 OpInfo.ConstraintType = BestType; 3241} 3242 3243/// ComputeConstraintToUse - Determines the constraint code and constraint 3244/// type to use for the specific AsmOperandInfo, setting 3245/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 3246void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 3247 SDValue Op, 3248 SelectionDAG *DAG) const { 3249 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 3250 3251 // Single-letter constraints ('r') are very common. 3252 if (OpInfo.Codes.size() == 1) { 3253 OpInfo.ConstraintCode = OpInfo.Codes[0]; 3254 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3255 } else { 3256 ChooseConstraint(OpInfo, *this, Op, DAG); 3257 } 3258 3259 // 'X' matches anything. 3260 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 3261 // Labels and constants are handled elsewhere ('X' is the only thing 3262 // that matches labels). For Functions, the type here is the type of 3263 // the result, which is not what we want to look at; leave them alone. 3264 Value *v = OpInfo.CallOperandVal; 3265 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 3266 OpInfo.CallOperandVal = v; 3267 return; 3268 } 3269 3270 // Otherwise, try to resolve it to something we know about by looking at 3271 // the actual operand type. 3272 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 3273 OpInfo.ConstraintCode = Repl; 3274 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3275 } 3276 } 3277} 3278 3279//===----------------------------------------------------------------------===// 3280// Loop Strength Reduction hooks 3281//===----------------------------------------------------------------------===// 3282 3283/// isLegalAddressingMode - Return true if the addressing mode represented 3284/// by AM is legal for this target, for a load/store of the specified type. 3285bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 3286 Type *Ty) const { 3287 // The default implementation of this implements a conservative RISCy, r+r and 3288 // r+i addr mode. 3289 3290 // Allows a sign-extended 16-bit immediate field. 3291 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3292 return false; 3293 3294 // No global is ever allowed as a base. 3295 if (AM.BaseGV) 3296 return false; 3297 3298 // Only support r+r, 3299 switch (AM.Scale) { 3300 case 0: // "r+i" or just "i", depending on HasBaseReg. 3301 break; 3302 case 1: 3303 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3304 return false; 3305 // Otherwise we have r+r or r+i. 3306 break; 3307 case 2: 3308 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3309 return false; 3310 // Allow 2*r as r+r. 3311 break; 3312 } 3313 3314 return true; 3315} 3316 3317/// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication 3318/// with the multiplicative inverse of the constant. 3319SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl, 3320 SelectionDAG &DAG) const { 3321 ConstantSDNode *C = cast<ConstantSDNode>(Op2); 3322 APInt d = C->getAPIntValue(); 3323 assert(d != 0 && "Division by zero!"); 3324 3325 // Shift the value upfront if it is even, so the LSB is one. 3326 unsigned ShAmt = d.countTrailingZeros(); 3327 if (ShAmt) { 3328 // TODO: For UDIV use SRL instead of SRA. 3329 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType())); 3330 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt); 3331 d = d.ashr(ShAmt); 3332 } 3333 3334 // Calculate the multiplicative inverse, using Newton's method. 3335 APInt t, xn = d; 3336 while ((t = d*xn) != 1) 3337 xn *= APInt(d.getBitWidth(), 2) - t; 3338 3339 Op2 = DAG.getConstant(xn, Op1.getValueType()); 3340 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2); 3341} 3342 3343/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3344/// return a DAG expression to select that will generate the same value by 3345/// multiplying by a magic number. See: 3346/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3347SDValue TargetLowering:: 3348BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 3349 std::vector<SDNode*> *Created) const { 3350 EVT VT = N->getValueType(0); 3351 DebugLoc dl= N->getDebugLoc(); 3352 3353 // Check to see if we can do this. 3354 // FIXME: We should be more aggressive here. 3355 if (!isTypeLegal(VT)) 3356 return SDValue(); 3357 3358 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3359 APInt::ms magics = d.magic(); 3360 3361 // Multiply the numerator (operand 0) by the magic value 3362 // FIXME: We should support doing a MUL in a wider type 3363 SDValue Q; 3364 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : 3365 isOperationLegalOrCustom(ISD::MULHS, VT)) 3366 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 3367 DAG.getConstant(magics.m, VT)); 3368 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : 3369 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 3370 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 3371 N->getOperand(0), 3372 DAG.getConstant(magics.m, VT)).getNode(), 1); 3373 else 3374 return SDValue(); // No mulhs or equvialent 3375 // If d > 0 and m < 0, add the numerator 3376 if (d.isStrictlyPositive() && magics.m.isNegative()) { 3377 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 3378 if (Created) 3379 Created->push_back(Q.getNode()); 3380 } 3381 // If d < 0 and m > 0, subtract the numerator. 3382 if (d.isNegative() && magics.m.isStrictlyPositive()) { 3383 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 3384 if (Created) 3385 Created->push_back(Q.getNode()); 3386 } 3387 // Shift right algebraic if shift value is nonzero 3388 if (magics.s > 0) { 3389 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 3390 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 3391 if (Created) 3392 Created->push_back(Q.getNode()); 3393 } 3394 // Extract the sign bit and add it to the quotient 3395 SDValue T = 3396 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 3397 getShiftAmountTy(Q.getValueType()))); 3398 if (Created) 3399 Created->push_back(T.getNode()); 3400 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 3401} 3402 3403/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3404/// return a DAG expression to select that will generate the same value by 3405/// multiplying by a magic number. See: 3406/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3407SDValue TargetLowering:: 3408BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 3409 std::vector<SDNode*> *Created) const { 3410 EVT VT = N->getValueType(0); 3411 DebugLoc dl = N->getDebugLoc(); 3412 3413 // Check to see if we can do this. 3414 // FIXME: We should be more aggressive here. 3415 if (!isTypeLegal(VT)) 3416 return SDValue(); 3417 3418 // FIXME: We should use a narrower constant when the upper 3419 // bits are known to be zero. 3420 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3421 APInt::mu magics = N1C.magicu(); 3422 3423 SDValue Q = N->getOperand(0); 3424 3425 // If the divisor is even, we can avoid using the expensive fixup by shifting 3426 // the divided value upfront. 3427 if (magics.a != 0 && !N1C[0]) { 3428 unsigned Shift = N1C.countTrailingZeros(); 3429 Q = DAG.getNode(ISD::SRL, dl, VT, Q, 3430 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType()))); 3431 if (Created) 3432 Created->push_back(Q.getNode()); 3433 3434 // Get magic number for the shifted divisor. 3435 magics = N1C.lshr(Shift).magicu(Shift); 3436 assert(magics.a == 0 && "Should use cheap fixup now"); 3437 } 3438 3439 // Multiply the numerator (operand 0) by the magic value 3440 // FIXME: We should support doing a MUL in a wider type 3441 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : 3442 isOperationLegalOrCustom(ISD::MULHU, VT)) 3443 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT)); 3444 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : 3445 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 3446 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q, 3447 DAG.getConstant(magics.m, VT)).getNode(), 1); 3448 else 3449 return SDValue(); // No mulhu or equvialent 3450 if (Created) 3451 Created->push_back(Q.getNode()); 3452 3453 if (magics.a == 0) { 3454 assert(magics.s < N1C.getBitWidth() && 3455 "We shouldn't generate an undefined shift!"); 3456 return DAG.getNode(ISD::SRL, dl, VT, Q, 3457 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 3458 } else { 3459 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 3460 if (Created) 3461 Created->push_back(NPQ.getNode()); 3462 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 3463 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType()))); 3464 if (Created) 3465 Created->push_back(NPQ.getNode()); 3466 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 3467 if (Created) 3468 Created->push_back(NPQ.getNode()); 3469 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 3470 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType()))); 3471 } 3472} 3473