Host.cpp revision c97db8dfdd854430c28db74825a6bb7593b5ec05 
1//===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//  This header file implements the operating system Host concept.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Support/Host.h"
15#include "llvm/ADT/SmallVector.h"
16#include "llvm/ADT/StringRef.h"
17#include "llvm/ADT/StringSwitch.h"
18#include "llvm/ADT/Triple.h"
19#include "llvm/Config/config.h"
20#include "llvm/Support/DataStream.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Support/raw_ostream.h"
23#include <string.h>
24
25// Include the platform-specific parts of this class.
26#ifdef LLVM_ON_UNIX
27#include "Unix/Host.inc"
28#endif
29#ifdef LLVM_ON_WIN32
30#include "Windows/Host.inc"
31#endif
32#ifdef _MSC_VER
33#include <intrin.h>
34#endif
35#if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
36#include <mach/mach.h>
37#include <mach/mach_host.h>
38#include <mach/host_info.h>
39#include <mach/machine.h>
40#endif
41
42//===----------------------------------------------------------------------===//
43//
44//  Implementations of the CPU detection routines
45//
46//===----------------------------------------------------------------------===//
47
48using namespace llvm;
49
50#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
51 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
52
53/// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
54/// specified arguments.  If we can't run cpuid on the host, return true.
55static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
56                               unsigned *rECX, unsigned *rEDX) {
57#if defined(_MSC_VER)
58  // The MSVC intrinsic is portable across x86 and x64.
59  int registers[4];
60  __cpuid(registers, value);
61  *rEAX = registers[0];
62  *rEBX = registers[1];
63  *rECX = registers[2];
64  *rEDX = registers[3];
65  return false;
66#elif defined(__GNUC__)
67  #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
68    // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
69    asm ("movq\t%%rbx, %%rsi\n\t"
70         "cpuid\n\t"
71         "xchgq\t%%rbx, %%rsi\n\t"
72         : "=a" (*rEAX),
73           "=S" (*rEBX),
74           "=c" (*rECX),
75           "=d" (*rEDX)
76         :  "a" (value));
77    return false;
78  #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
79    asm ("movl\t%%ebx, %%esi\n\t"
80         "cpuid\n\t"
81         "xchgl\t%%ebx, %%esi\n\t"
82         : "=a" (*rEAX),
83           "=S" (*rEBX),
84           "=c" (*rECX),
85           "=d" (*rEDX)
86         :  "a" (value));
87    return false;
88// pedantic #else returns to appease -Wunreachable-code (so we don't generate
89// postprocessed code that looks like "return true; return false;")
90  #else
91    return true;
92  #endif
93#else
94  return true;
95#endif
96}
97
98static bool OSHasAVXSupport() {
99#if defined(__GNUC__)
100  // Check xgetbv; this uses a .byte sequence instead of the instruction
101  // directly because older assemblers do not include support for xgetbv and
102  // there is no easy way to conditionally compile based on the assembler used.
103  int rEAX, rEDX;
104  __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
105#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
106  unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
107#else
108  int rEAX = 0; // Ensures we return false
109#endif
110  return (rEAX & 6) == 6;
111}
112
113static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
114                                 unsigned &Model) {
115  Family = (EAX >> 8) & 0xf; // Bits 8 - 11
116  Model  = (EAX >> 4) & 0xf; // Bits 4 - 7
117  if (Family == 6 || Family == 0xf) {
118    if (Family == 0xf)
119      // Examine extended family ID if family ID is F.
120      Family += (EAX >> 20) & 0xff;    // Bits 20 - 27
121    // Examine extended model ID if family ID is 6 or F.
122    Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
123  }
124}
125
126std::string sys::getHostCPUName() {
127  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
128  if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
129    return "generic";
130  unsigned Family = 0;
131  unsigned Model  = 0;
132  DetectX86FamilyModel(EAX, Family, Model);
133
134  bool HasSSE3 = (ECX & 0x1);
135  bool HasSSE41 = (ECX & 0x80000);
136  // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
137  // indicates that the AVX registers will be saved and restored on context
138  // switch, then we have full AVX support.
139  const unsigned AVXBits = (1 << 27) | (1 << 28);
140  bool HasAVX = ((ECX & AVXBits) == AVXBits) && OSHasAVXSupport();
141  GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
142  bool Em64T = (EDX >> 29) & 0x1;
143
144  union {
145    unsigned u[3];
146    char     c[12];
147  } text;
148
149  GetX86CpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
150  if (memcmp(text.c, "GenuineIntel", 12) == 0) {
151    switch (Family) {
152    case 3:
153      return "i386";
154    case 4:
155      switch (Model) {
156      case 0: // Intel486 DX processors
157      case 1: // Intel486 DX processors
158      case 2: // Intel486 SX processors
159      case 3: // Intel487 processors, IntelDX2 OverDrive processors,
160              // IntelDX2 processors
161      case 4: // Intel486 SL processor
162      case 5: // IntelSX2 processors
163      case 7: // Write-Back Enhanced IntelDX2 processors
164      case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
165      default: return "i486";
166      }
167    case 5:
168      switch (Model) {
169      case  1: // Pentium OverDrive processor for Pentium processor (60, 66),
170               // Pentium processors (60, 66)
171      case  2: // Pentium OverDrive processor for Pentium processor (75, 90,
172               // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
173               // 150, 166, 200)
174      case  3: // Pentium OverDrive processors for Intel486 processor-based
175               // systems
176        return "pentium";
177
178      case  4: // Pentium OverDrive processor with MMX technology for Pentium
179               // processor (75, 90, 100, 120, 133), Pentium processor with
180               // MMX technology (166, 200)
181        return "pentium-mmx";
182
183      default: return "pentium";
184      }
185    case 6:
186      switch (Model) {
187      case  1: // Pentium Pro processor
188        return "pentiumpro";
189
190      case  3: // Intel Pentium II OverDrive processor, Pentium II processor,
191               // model 03
192      case  5: // Pentium II processor, model 05, Pentium II Xeon processor,
193               // model 05, and Intel Celeron processor, model 05
194      case  6: // Celeron processor, model 06
195        return "pentium2";
196
197      case  7: // Pentium III processor, model 07, and Pentium III Xeon
198               // processor, model 07
199      case  8: // Pentium III processor, model 08, Pentium III Xeon processor,
200               // model 08, and Celeron processor, model 08
201      case 10: // Pentium III Xeon processor, model 0Ah
202      case 11: // Pentium III processor, model 0Bh
203        return "pentium3";
204
205      case  9: // Intel Pentium M processor, Intel Celeron M processor model 09.
206      case 13: // Intel Pentium M processor, Intel Celeron M processor, model
207               // 0Dh. All processors are manufactured using the 90 nm process.
208        return "pentium-m";
209
210      case 14: // Intel Core Duo processor, Intel Core Solo processor, model
211               // 0Eh. All processors are manufactured using the 65 nm process.
212        return "yonah";
213
214      case 15: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
215               // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
216               // mobile processor, Intel Core 2 Extreme processor, Intel
217               // Pentium Dual-Core processor, Intel Xeon processor, model
218               // 0Fh. All processors are manufactured using the 65 nm process.
219      case 22: // Intel Celeron processor model 16h. All processors are
220               // manufactured using the 65 nm process
221        return "core2";
222
223      case 21: // Intel EP80579 Integrated Processor and Intel EP80579
224               // Integrated Processor with Intel QuickAssist Technology
225        return "i686"; // FIXME: ???
226
227      case 23: // Intel Core 2 Extreme processor, Intel Xeon processor, model
228               // 17h. All processors are manufactured using the 45 nm process.
229               //
230               // 45nm: Penryn , Wolfdale, Yorkfield (XE)
231        // Not all Penryn processors support SSE 4.1 (such as the Pentium brand)
232        return HasSSE41 ? "penryn" : "core2";
233
234      case 26: // Intel Core i7 processor and Intel Xeon processor. All
235               // processors are manufactured using the 45 nm process.
236      case 29: // Intel Xeon processor MP. All processors are manufactured using
237               // the 45 nm process.
238      case 30: // Intel(R) Core(TM) i7 CPU         870  @ 2.93GHz.
239               // As found in a Summer 2010 model iMac.
240      case 37: // Intel Core i7, laptop version.
241      case 44: // Intel Core i7 processor and Intel Xeon processor. All
242               // processors are manufactured using the 32 nm process.
243      case 46: // Nehalem EX
244      case 47: // Westmere EX
245        return "corei7";
246
247      // SandyBridge:
248      case 42: // Intel Core i7 processor. All processors are manufactured
249               // using the 32 nm process.
250      case 45:
251        // Not all Sandy Bridge processors support AVX (such as the Pentium
252        // versions instead of the i7 versions).
253        return HasAVX ? "corei7-avx" : "corei7";
254
255      // Ivy Bridge:
256      case 58:
257        // Not all Ivy Bridge processors support AVX (such as the Pentium
258        // versions instead of the i7 versions).
259        return HasAVX ? "core-avx-i" : "corei7";
260
261      case 28: // Most 45 nm Intel Atom processors
262      case 38: // 45 nm Atom Lincroft
263      case 39: // 32 nm Atom Medfield
264      case 53: // 32 nm Atom Midview
265      case 54: // 32 nm Atom Midview
266        return "atom";
267
268      default: return (Em64T) ? "x86-64" : "i686";
269      }
270    case 15: {
271      switch (Model) {
272      case  0: // Pentium 4 processor, Intel Xeon processor. All processors are
273               // model 00h and manufactured using the 0.18 micron process.
274      case  1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
275               // processor MP, and Intel Celeron processor. All processors are
276               // model 01h and manufactured using the 0.18 micron process.
277      case  2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
278               // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
279               // processor, and Mobile Intel Celeron processor. All processors
280               // are model 02h and manufactured using the 0.13 micron process.
281        return (Em64T) ? "x86-64" : "pentium4";
282
283      case  3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
284               // processor. All processors are model 03h and manufactured using
285               // the 90 nm process.
286      case  4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
287               // Pentium D processor, Intel Xeon processor, Intel Xeon
288               // processor MP, Intel Celeron D processor. All processors are
289               // model 04h and manufactured using the 90 nm process.
290      case  6: // Pentium 4 processor, Pentium D processor, Pentium processor
291               // Extreme Edition, Intel Xeon processor, Intel Xeon processor
292               // MP, Intel Celeron D processor. All processors are model 06h
293               // and manufactured using the 65 nm process.
294        return (Em64T) ? "nocona" : "prescott";
295
296      default:
297        return (Em64T) ? "x86-64" : "pentium4";
298      }
299    }
300
301    default:
302      return "generic";
303    }
304  } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
305    // FIXME: this poorly matches the generated SubtargetFeatureKV table.  There
306    // appears to be no way to generate the wide variety of AMD-specific targets
307    // from the information returned from CPUID.
308    switch (Family) {
309      case 4:
310        return "i486";
311      case 5:
312        switch (Model) {
313        case 6:
314        case 7:  return "k6";
315        case 8:  return "k6-2";
316        case 9:
317        case 13: return "k6-3";
318        case 10: return "geode";
319        default: return "pentium";
320        }
321      case 6:
322        switch (Model) {
323        case 4:  return "athlon-tbird";
324        case 6:
325        case 7:
326        case 8:  return "athlon-mp";
327        case 10: return "athlon-xp";
328        default: return "athlon";
329        }
330      case 15:
331        if (HasSSE3)
332          return "k8-sse3";
333        switch (Model) {
334        case 1:  return "opteron";
335        case 5:  return "athlon-fx"; // also opteron
336        default: return "athlon64";
337        }
338      case 16:
339        return "amdfam10";
340      case 20:
341        return "btver1";
342      case 21:
343        if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
344          return "btver1";
345        if (Model > 15 && Model <= 31)
346          return "bdver2";
347        return "bdver1";
348      case 22:
349        if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
350          return "btver1";
351        return "btver2";
352    default:
353      return "generic";
354    }
355  }
356  return "generic";
357}
358#elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
359std::string sys::getHostCPUName() {
360  host_basic_info_data_t hostInfo;
361  mach_msg_type_number_t infoCount;
362
363  infoCount = HOST_BASIC_INFO_COUNT;
364  host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
365            &infoCount);
366
367  if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic";
368
369  switch(hostInfo.cpu_subtype) {
370  case CPU_SUBTYPE_POWERPC_601:   return "601";
371  case CPU_SUBTYPE_POWERPC_602:   return "602";
372  case CPU_SUBTYPE_POWERPC_603:   return "603";
373  case CPU_SUBTYPE_POWERPC_603e:  return "603e";
374  case CPU_SUBTYPE_POWERPC_603ev: return "603ev";
375  case CPU_SUBTYPE_POWERPC_604:   return "604";
376  case CPU_SUBTYPE_POWERPC_604e:  return "604e";
377  case CPU_SUBTYPE_POWERPC_620:   return "620";
378  case CPU_SUBTYPE_POWERPC_750:   return "750";
379  case CPU_SUBTYPE_POWERPC_7400:  return "7400";
380  case CPU_SUBTYPE_POWERPC_7450:  return "7450";
381  case CPU_SUBTYPE_POWERPC_970:   return "970";
382  default: ;
383  }
384
385  return "generic";
386}
387#elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
388std::string sys::getHostCPUName() {
389  // Access to the Processor Version Register (PVR) on PowerPC is privileged,
390  // and so we must use an operating-system interface to determine the current
391  // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
392  const char *generic = "generic";
393
394  // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
395  // memory buffer because the 'file' has 0 size (it can be read from only
396  // as a stream).
397
398  std::string Err;
399  DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
400  if (!DS) {
401    DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
402    return generic;
403  }
404
405  // The cpu line is second (after the 'processor: 0' line), so if this
406  // buffer is too small then something has changed (or is wrong).
407  char buffer[1024];
408  size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
409  delete DS;
410
411  const char *CPUInfoStart = buffer;
412  const char *CPUInfoEnd = buffer + CPUInfoSize;
413
414  const char *CIP = CPUInfoStart;
415
416  const char *CPUStart = 0;
417  size_t CPULen = 0;
418
419  // We need to find the first line which starts with cpu, spaces, and a colon.
420  // After the colon, there may be some additional spaces and then the cpu type.
421  while (CIP < CPUInfoEnd && CPUStart == 0) {
422    if (CIP < CPUInfoEnd && *CIP == '\n')
423      ++CIP;
424
425    if (CIP < CPUInfoEnd && *CIP == 'c') {
426      ++CIP;
427      if (CIP < CPUInfoEnd && *CIP == 'p') {
428        ++CIP;
429        if (CIP < CPUInfoEnd && *CIP == 'u') {
430          ++CIP;
431          while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
432            ++CIP;
433
434          if (CIP < CPUInfoEnd && *CIP == ':') {
435            ++CIP;
436            while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
437              ++CIP;
438
439            if (CIP < CPUInfoEnd) {
440              CPUStart = CIP;
441              while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
442                                          *CIP != ',' && *CIP != '\n'))
443                ++CIP;
444              CPULen = CIP - CPUStart;
445            }
446          }
447        }
448      }
449    }
450
451    if (CPUStart == 0)
452      while (CIP < CPUInfoEnd && *CIP != '\n')
453        ++CIP;
454  }
455
456  if (CPUStart == 0)
457    return generic;
458
459  return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
460    .Case("604e", "604e")
461    .Case("604", "604")
462    .Case("7400", "7400")
463    .Case("7410", "7400")
464    .Case("7447", "7400")
465    .Case("7455", "7450")
466    .Case("G4", "g4")
467    .Case("POWER4", "970")
468    .Case("PPC970FX", "970")
469    .Case("PPC970MP", "970")
470    .Case("G5", "g5")
471    .Case("POWER5", "g5")
472    .Case("A2", "a2")
473    .Case("POWER6", "pwr6")
474    .Case("POWER7", "pwr7")
475    .Default(generic);
476}
477#elif defined(__linux__) && defined(__arm__)
478std::string sys::getHostCPUName() {
479  // The cpuid register on arm is not accessible from user space. On Linux,
480  // it is exposed through the /proc/cpuinfo file.
481  // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
482  // memory buffer because the 'file' has 0 size (it can be read from only
483  // as a stream).
484
485  std::string Err;
486  DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
487  if (!DS) {
488    DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
489    return "generic";
490  }
491
492  // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line
493  // in all cases.
494  char buffer[1024];
495  size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
496  delete DS;
497
498  StringRef Str(buffer, CPUInfoSize);
499
500  SmallVector<StringRef, 32> Lines;
501  Str.split(Lines, "\n");
502
503  // Look for the CPU implementer line.
504  StringRef Implementer;
505  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
506    if (Lines[I].startswith("CPU implementer"))
507      Implementer = Lines[I].substr(15).ltrim("\t :");
508
509  if (Implementer == "0x41") // ARM Ltd.
510    // Look for the CPU part line.
511    for (unsigned I = 0, E = Lines.size(); I != E; ++I)
512      if (Lines[I].startswith("CPU part"))
513        // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
514        // values correspond to the "Part number" in the CP15/c0 register. The
515        // contents are specified in the various processor manuals.
516        return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
517          .Case("0x926", "arm926ej-s")
518          .Case("0xb02", "mpcore")
519          .Case("0xb36", "arm1136j-s")
520          .Case("0xb56", "arm1156t2-s")
521          .Case("0xb76", "arm1176jz-s")
522          .Case("0xc08", "cortex-a8")
523          .Case("0xc09", "cortex-a9")
524          .Case("0xc0f", "cortex-a15")
525          .Case("0xc20", "cortex-m0")
526          .Case("0xc23", "cortex-m3")
527          .Case("0xc24", "cortex-m4")
528          .Default("generic");
529
530  return "generic";
531}
532#else
533std::string sys::getHostCPUName() {
534  return "generic";
535}
536#endif
537
538#if defined(__linux__) && defined(__arm__)
539bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
540  std::string Err;
541  DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
542  if (!DS) {
543    DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
544    return false;
545  }
546
547  // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line
548  // in all cases.
549  char buffer[1024];
550  size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
551  delete DS;
552
553  StringRef Str(buffer, CPUInfoSize);
554
555  SmallVector<StringRef, 32> Lines;
556  Str.split(Lines, "\n");
557
558  SmallVector<StringRef, 32> CPUFeatures;
559
560  // Look for the CPU features.
561  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
562    if (Lines[I].startswith("Features")) {
563      Lines[I].split(CPUFeatures, " ");
564      break;
565    }
566
567  for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
568    StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
569      .Case("half", "fp16")
570      .Case("neon", "neon")
571      .Case("vfpv3", "vfp3")
572      .Case("vfpv3d16", "d16")
573      .Case("vfpv4", "vfp4")
574      .Case("idiva", "hwdiv-arm")
575      .Case("idivt", "hwdiv")
576      .Default("");
577
578    if (LLVMFeatureStr != "")
579      Features.GetOrCreateValue(LLVMFeatureStr).setValue(true);
580  }
581
582  return true;
583}
584#else
585bool sys::getHostCPUFeatures(StringMap<bool> &Features){
586  return false;
587}
588#endif
589
590std::string sys::getProcessTriple() {
591  Triple PT(Triple::normalize(LLVM_HOST_TRIPLE));
592
593  if (sizeof(void *) == 8 && PT.isArch32Bit())
594    PT = PT.get64BitArchVariant();
595  if (sizeof(void *) == 4 && PT.isArch64Bit())
596    PT = PT.get32BitArchVariant();
597
598  return PT.str();
599}
600