ARMSubtarget.cpp revision 0b8c9a80f20772c3793201ab5b251d3520b9cea3 
1//===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the ARM specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMSubtarget.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "llvm/IR/GlobalValue.h"
18#include "llvm/Support/CommandLine.h"
19#include "llvm/Target/TargetInstrInfo.h"
20
21#define GET_SUBTARGETINFO_TARGET_DESC
22#define GET_SUBTARGETINFO_CTOR
23#include "ARMGenSubtargetInfo.inc"
24
25using namespace llvm;
26
27static cl::opt<bool>
28ReserveR9("arm-reserve-r9", cl::Hidden,
29          cl::desc("Reserve R9, making it unavailable as GPR"));
30
31static cl::opt<bool>
32DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden);
33
34static cl::opt<bool>
35UseFusedMulOps("arm-use-mulops",
36               cl::init(true), cl::Hidden);
37
38static cl::opt<bool>
39StrictAlign("arm-strict-align", cl::Hidden,
40            cl::desc("Disallow all unaligned memory accesses"));
41
42ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
43                           const std::string &FS)
44  : ARMGenSubtargetInfo(TT, CPU, FS)
45  , ARMProcFamily(Others)
46  , HasV4TOps(false)
47  , HasV5TOps(false)
48  , HasV5TEOps(false)
49  , HasV6Ops(false)
50  , HasV6T2Ops(false)
51  , HasV7Ops(false)
52  , HasVFPv2(false)
53  , HasVFPv3(false)
54  , HasVFPv4(false)
55  , HasNEON(false)
56  , UseNEONForSinglePrecisionFP(false)
57  , UseMulOps(UseFusedMulOps)
58  , SlowFPVMLx(false)
59  , HasVMLxForwarding(false)
60  , SlowFPBrcc(false)
61  , InThumbMode(false)
62  , HasThumb2(false)
63  , IsMClass(false)
64  , NoARM(false)
65  , PostRAScheduler(false)
66  , IsR9Reserved(ReserveR9)
67  , UseMovt(false)
68  , SupportsTailCall(false)
69  , HasFP16(false)
70  , HasD16(false)
71  , HasHardwareDivide(false)
72  , HasHardwareDivideInARM(false)
73  , HasT2ExtractPack(false)
74  , HasDataBarrier(false)
75  , Pref32BitThumb(false)
76  , AvoidCPSRPartialUpdate(false)
77  , AvoidMOVsShifterOperand(false)
78  , HasRAS(false)
79  , HasMPExtension(false)
80  , FPOnlySP(false)
81  , AllowsUnalignedMem(false)
82  , Thumb2DSP(false)
83  , stackAlignment(4)
84  , CPUString(CPU)
85  , TargetTriple(TT)
86  , TargetABI(ARM_ABI_APCS) {
87  // Determine default and user specified characteristics
88  if (CPUString.empty())
89    CPUString = "generic";
90
91  // Insert the architecture feature derived from the target triple into the
92  // feature string. This is important for setting features that are implied
93  // based on the architecture version.
94  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPUString);
95  if (!FS.empty()) {
96    if (!ArchFS.empty())
97      ArchFS = ArchFS + "," + FS;
98    else
99      ArchFS = FS;
100  }
101  ParseSubtargetFeatures(CPUString, ArchFS);
102
103  // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
104  // ARM version or CPU and then remove this.
105  if (!HasV6T2Ops && hasThumb2())
106    HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
107
108  // Keep a pointer to static instruction cost data for the specified CPU.
109  SchedModel = getSchedModelForCPU(CPUString);
110
111  // Initialize scheduling itinerary for the specified CPU.
112  InstrItins = getInstrItineraryForCPU(CPUString);
113
114  if ((TT.find("eabi") != std::string::npos) || (isTargetIOS() && isMClass()))
115    // FIXME: We might want to separate AAPCS and EABI. Some systems, e.g.
116    // Darwin-EABI conforms to AACPS but not the rest of EABI.
117    TargetABI = ARM_ABI_AAPCS;
118
119  if (isAAPCS_ABI())
120    stackAlignment = 8;
121
122  if (!isTargetIOS())
123    UseMovt = hasV6T2Ops();
124  else {
125    IsR9Reserved = ReserveR9 | !HasV6Ops;
126    UseMovt = DarwinUseMOVT && hasV6T2Ops();
127    SupportsTailCall = !getTargetTriple().isOSVersionLT(5, 0);
128  }
129
130  if (!isThumb() || hasThumb2())
131    PostRAScheduler = true;
132
133  // v6+ may or may not support unaligned mem access depending on the system
134  // configuration.
135  if (!StrictAlign && hasV6Ops() && isTargetDarwin())
136    AllowsUnalignedMem = true;
137}
138
139/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
140bool
141ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
142                                 Reloc::Model RelocM) const {
143  if (RelocM == Reloc::Static)
144    return false;
145
146  // Materializable GVs (in JIT lazy compilation mode) do not require an extra
147  // load from stub.
148  bool isDecl = GV->hasAvailableExternallyLinkage();
149  if (GV->isDeclaration() && !GV->isMaterializable())
150    isDecl = true;
151
152  if (!isTargetDarwin()) {
153    // Extra load is needed for all externally visible.
154    if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
155      return false;
156    return true;
157  } else {
158    if (RelocM == Reloc::PIC_) {
159      // If this is a strong reference to a definition, it is definitely not
160      // through a stub.
161      if (!isDecl && !GV->isWeakForLinker())
162        return false;
163
164      // Unless we have a symbol with hidden visibility, we have to go through a
165      // normal $non_lazy_ptr stub because this symbol might be resolved late.
166      if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
167        return true;
168
169      // If symbol visibility is hidden, we have a stub for common symbol
170      // references and external declarations.
171      if (isDecl || GV->hasCommonLinkage())
172        // Hidden $non_lazy_ptr reference.
173        return true;
174
175      return false;
176    } else {
177      // If this is a strong reference to a definition, it is definitely not
178      // through a stub.
179      if (!isDecl && !GV->isWeakForLinker())
180        return false;
181
182      // Unless we have a symbol with hidden visibility, we have to go through a
183      // normal $non_lazy_ptr stub because this symbol might be resolved late.
184      if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
185        return true;
186    }
187  }
188
189  return false;
190}
191
192unsigned ARMSubtarget::getMispredictionPenalty() const {
193  return SchedModel->MispredictPenalty;
194}
195
196bool ARMSubtarget::enablePostRAScheduler(
197           CodeGenOpt::Level OptLevel,
198           TargetSubtargetInfo::AntiDepBreakMode& Mode,
199           RegClassVector& CriticalPathRCs) const {
200  Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
201  CriticalPathRCs.clear();
202  CriticalPathRCs.push_back(&ARM::GPRRegClass);
203  return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
204}
205