ARMSubtarget.cpp revision e127dfd0b175b5a336e61fecaad7fc2aec65d95c 
1//===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the ARM specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMSubtarget.h"
15#include "ARMBaseRegisterInfo.h"
16#include "ARMBaseInstrInfo.h"
17#include "llvm/GlobalValue.h"
18#include "llvm/Target/TargetInstrInfo.h"
19#include "llvm/Support/CommandLine.h"
20
21#define GET_SUBTARGETINFO_TARGET_DESC
22#define GET_SUBTARGETINFO_CTOR
23#include "ARMGenSubtargetInfo.inc"
24
25using namespace llvm;
26
27static cl::opt<bool>
28ReserveR9("arm-reserve-r9", cl::Hidden,
29          cl::desc("Reserve R9, making it unavailable as GPR"));
30
31static cl::opt<bool>
32DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden);
33
34static cl::opt<bool>
35StrictAlign("arm-strict-align", cl::Hidden,
36            cl::desc("Disallow all unaligned memory accesses"));
37
38ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
39                           const std::string &FS)
40  : ARMGenSubtargetInfo(TT, CPU, FS)
41  , ARMProcFamily(Others)
42  , HasV4TOps(false)
43  , HasV5TOps(false)
44  , HasV5TEOps(false)
45  , HasV6Ops(false)
46  , HasV6T2Ops(false)
47  , HasV7Ops(false)
48  , HasVFPv2(false)
49  , HasVFPv3(false)
50  , HasVFPv4(false)
51  , HasNEON(false)
52  , UseNEONForSinglePrecisionFP(false)
53  , SlowFPVMLx(false)
54  , HasVMLxForwarding(false)
55  , SlowFPBrcc(false)
56  , InThumbMode(false)
57  , HasThumb2(false)
58  , IsMClass(false)
59  , NoARM(false)
60  , PostRAScheduler(false)
61  , IsR9Reserved(ReserveR9)
62  , UseMovt(false)
63  , SupportsTailCall(false)
64  , HasFP16(false)
65  , HasD16(false)
66  , HasHardwareDivide(false)
67  , HasT2ExtractPack(false)
68  , HasDataBarrier(false)
69  , Pref32BitThumb(false)
70  , AvoidCPSRPartialUpdate(false)
71  , HasRAS(false)
72  , HasMPExtension(false)
73  , FPOnlySP(false)
74  , AllowsUnalignedMem(false)
75  , Thumb2DSP(false)
76  , stackAlignment(4)
77  , CPUString(CPU)
78  , TargetTriple(TT)
79  , TargetABI(ARM_ABI_APCS) {
80  // Determine default and user specified characteristics
81  if (CPUString.empty())
82    CPUString = "generic";
83
84  // Insert the architecture feature derived from the target triple into the
85  // feature string. This is important for setting features that are implied
86  // based on the architecture version.
87  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPUString);
88  if (!FS.empty()) {
89    if (!ArchFS.empty())
90      ArchFS = ArchFS + "," + FS;
91    else
92      ArchFS = FS;
93  }
94  ParseSubtargetFeatures(CPUString, ArchFS);
95
96  // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
97  // ARM version or CPU and then remove this.
98  if (!HasV6T2Ops && hasThumb2())
99    HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
100
101  // Keep a pointer to static instruction cost data for the specified CPU.
102  SchedModel = getSchedModelForCPU(CPUString);
103
104  // Initialize scheduling itinerary for the specified CPU.
105  InstrItins = getInstrItineraryForCPU(CPUString);
106
107  if ((TT.find("eabi") != std::string::npos) || (isTargetIOS() && isMClass()))
108    // FIXME: We might want to separate AAPCS and EABI. Some systems, e.g.
109    // Darwin-EABI conforms to AACPS but not the rest of EABI.
110    TargetABI = ARM_ABI_AAPCS;
111
112  if (isAAPCS_ABI())
113    stackAlignment = 8;
114
115  if (!isTargetIOS())
116    UseMovt = hasV6T2Ops();
117  else {
118    IsR9Reserved = ReserveR9 | !HasV6Ops;
119    UseMovt = DarwinUseMOVT && hasV6T2Ops();
120    SupportsTailCall = !getTargetTriple().isOSVersionLT(5, 0);
121  }
122
123  if (!isThumb() || hasThumb2())
124    PostRAScheduler = true;
125
126  // v6+ may or may not support unaligned mem access depending on the system
127  // configuration.
128  if (!StrictAlign && hasV6Ops() && isTargetDarwin())
129    AllowsUnalignedMem = true;
130}
131
132/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
133bool
134ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
135                                 Reloc::Model RelocM) const {
136  if (RelocM == Reloc::Static)
137    return false;
138
139  // Materializable GVs (in JIT lazy compilation mode) do not require an extra
140  // load from stub.
141  bool isDecl = GV->hasAvailableExternallyLinkage();
142  if (GV->isDeclaration() && !GV->isMaterializable())
143    isDecl = true;
144
145  if (!isTargetDarwin()) {
146    // Extra load is needed for all externally visible.
147    if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
148      return false;
149    return true;
150  } else {
151    if (RelocM == Reloc::PIC_) {
152      // If this is a strong reference to a definition, it is definitely not
153      // through a stub.
154      if (!isDecl && !GV->isWeakForLinker())
155        return false;
156
157      // Unless we have a symbol with hidden visibility, we have to go through a
158      // normal $non_lazy_ptr stub because this symbol might be resolved late.
159      if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
160        return true;
161
162      // If symbol visibility is hidden, we have a stub for common symbol
163      // references and external declarations.
164      if (isDecl || GV->hasCommonLinkage())
165        // Hidden $non_lazy_ptr reference.
166        return true;
167
168      return false;
169    } else {
170      // If this is a strong reference to a definition, it is definitely not
171      // through a stub.
172      if (!isDecl && !GV->isWeakForLinker())
173        return false;
174
175      // Unless we have a symbol with hidden visibility, we have to go through a
176      // normal $non_lazy_ptr stub because this symbol might be resolved late.
177      if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
178        return true;
179    }
180  }
181
182  return false;
183}
184
185unsigned ARMSubtarget::getMispredictionPenalty() const {
186  return SchedModel->MispredictPenalty;
187}
188
189bool ARMSubtarget::enablePostRAScheduler(
190           CodeGenOpt::Level OptLevel,
191           TargetSubtargetInfo::AntiDepBreakMode& Mode,
192           RegClassVector& CriticalPathRCs) const {
193  Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
194  CriticalPathRCs.clear();
195  CriticalPathRCs.push_back(&ARM::GPRRegClass);
196  return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
197}
198