ARMSubtarget.cpp revision fc8475bde993cc0fa6101427e73e8a9cf7d1c3a4 
1//===-- ARMSubtarget.cpp - ARM Subtarget Information ------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the ARM specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMSubtarget.h"
15#include "ARMGenSubtarget.inc"
16#include "ARMBaseRegisterInfo.h"
17#include "llvm/GlobalValue.h"
18#include "llvm/Target/TargetOptions.h"
19#include "llvm/Support/CommandLine.h"
20#include "llvm/ADT/SmallVector.h"
21using namespace llvm;
22
23static cl::opt<bool>
24ReserveR9("arm-reserve-r9", cl::Hidden,
25          cl::desc("Reserve R9, making it unavailable as GPR"));
26
27static cl::opt<bool>
28UseMOVT("arm-darwin-use-movt", cl::init(false), cl::Hidden);
29
30static cl::opt<bool>
31StrictAlign("arm-strict-align", cl::Hidden,
32            cl::desc("Disallow all unaligned memory accesses"));
33
34ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
35                           bool isT)
36  : ARMArchVersion(V4)
37  , ARMProcFamily(Others)
38  , ARMFPUType(None)
39  , UseNEONForSinglePrecisionFP(false)
40  , SlowFPVMLx(false)
41  , SlowFPBrcc(false)
42  , IsThumb(isT)
43  , ThumbMode(Thumb1)
44  , NoARM(false)
45  , PostRAScheduler(false)
46  , IsR9Reserved(ReserveR9)
47  , UseMovt(false)
48  , HasFP16(false)
49  , HasD16(false)
50  , HasHardwareDivide(false)
51  , HasT2ExtractPack(false)
52  , HasDataBarrier(false)
53  , Pref32BitThumb(false)
54  , HasMPExtension(false)
55  , FPOnlySP(false)
56  , AllowsUnalignedMem(false)
57  , stackAlignment(4)
58  , CPUString("generic")
59  , TargetTriple(TT)
60  , TargetABI(ARM_ABI_APCS) {
61  // Default to soft float ABI
62  if (FloatABIType == FloatABI::Default)
63    FloatABIType = FloatABI::Soft;
64
65  // Determine default and user specified characteristics
66
67  // When no arch is specified either by CPU or by attributes, make the default
68  // ARMv4T.
69  const char *ARMArchFeature = "";
70  if (CPUString == "generic" && (FS.empty() || FS == "generic")) {
71    ARMArchVersion = V4T;
72    ARMArchFeature = ",+v4t";
73  }
74
75  // Set the boolean corresponding to the current target triple, or the default
76  // if one cannot be determined, to true.
77  unsigned Len = TT.length();
78  unsigned Idx = 0;
79
80  if (Len >= 5 && TT.substr(0, 4) == "armv")
81    Idx = 4;
82  else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
83    IsThumb = true;
84    if (Len >= 7 && TT[5] == 'v')
85      Idx = 6;
86  }
87  if (Idx) {
88    unsigned SubVer = TT[Idx];
89    if (SubVer >= '7' && SubVer <= '9') {
90      ARMArchVersion = V7A;
91      ARMArchFeature = ",+v7a";
92      if (Len >= Idx+2 && TT[Idx+1] == 'm') {
93        ARMArchVersion = V7M;
94        ARMArchFeature = ",+v7m";
95      }
96    } else if (SubVer == '6') {
97      ARMArchVersion = V6;
98      ARMArchFeature = ",+v6";
99      if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') {
100        ARMArchVersion = V6T2;
101        ARMArchFeature = ",+v6t2";
102      }
103    } else if (SubVer == '5') {
104      ARMArchVersion = V5T;
105      ARMArchFeature = ",+v5t";
106      if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') {
107        ARMArchVersion = V5TE;
108        ARMArchFeature = ",+v5te";
109      }
110    } else if (SubVer == '4') {
111      if (Len >= Idx+2 && TT[Idx+1] == 't') {
112        ARMArchVersion = V4T;
113        ARMArchFeature = ",+v4t";
114      } else {
115        ARMArchVersion = V4;
116        ARMArchFeature = "";
117      }
118    }
119  }
120
121  if (TT.find("eabi") != std::string::npos)
122    TargetABI = ARM_ABI_AAPCS;
123
124  // Parse features string.  If the first entry in FS (the CPU) is missing,
125  // insert the architecture feature derived from the target triple.  This is
126  // important for setting features that are implied based on the architecture
127  // version.
128  std::string FSWithArch;
129  if (FS.empty())
130    FSWithArch = std::string(ARMArchFeature);
131  else if (FS.find(',') == 0)
132    FSWithArch = std::string(ARMArchFeature) + FS;
133  else
134    FSWithArch = FS;
135  CPUString = ParseSubtargetFeatures(FSWithArch, CPUString);
136
137  // After parsing Itineraries, set ItinData.IssueWidth.
138  computeIssueWidth();
139
140  // Thumb2 implies at least V6T2.
141  if (ARMArchVersion >= V6T2)
142    ThumbMode = Thumb2;
143  else if (ThumbMode >= Thumb2)
144    ARMArchVersion = V6T2;
145
146  if (isAAPCS_ABI())
147    stackAlignment = 8;
148
149  if (!isTargetDarwin())
150    UseMovt = hasV6T2Ops();
151  else {
152    IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
153    if (UseMOVT && hasV6T2Ops()) {
154      unsigned Maj, Min, Rev;
155      TargetTriple.getDarwinNumber(Maj, Min, Rev);
156      UseMovt = Maj > 4;
157    }
158  }
159
160  if (!isThumb() || hasThumb2())
161    PostRAScheduler = true;
162
163  // v6+ may or may not support unaligned mem access depending on the system
164  // configuration.
165  if (!StrictAlign && hasV6Ops() && isTargetDarwin())
166    AllowsUnalignedMem = true;
167}
168
169/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
170bool
171ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
172                                 Reloc::Model RelocM) const {
173  if (RelocM == Reloc::Static)
174    return false;
175
176  // Materializable GVs (in JIT lazy compilation mode) do not require an extra
177  // load from stub.
178  bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
179
180  if (!isTargetDarwin()) {
181    // Extra load is needed for all externally visible.
182    if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
183      return false;
184    return true;
185  } else {
186    if (RelocM == Reloc::PIC_) {
187      // If this is a strong reference to a definition, it is definitely not
188      // through a stub.
189      if (!isDecl && !GV->isWeakForLinker())
190        return false;
191
192      // Unless we have a symbol with hidden visibility, we have to go through a
193      // normal $non_lazy_ptr stub because this symbol might be resolved late.
194      if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
195        return true;
196
197      // If symbol visibility is hidden, we have a stub for common symbol
198      // references and external declarations.
199      if (isDecl || GV->hasCommonLinkage())
200        // Hidden $non_lazy_ptr reference.
201        return true;
202
203      return false;
204    } else {
205      // If this is a strong reference to a definition, it is definitely not
206      // through a stub.
207      if (!isDecl && !GV->isWeakForLinker())
208        return false;
209
210      // Unless we have a symbol with hidden visibility, we have to go through a
211      // normal $non_lazy_ptr stub because this symbol might be resolved late.
212      if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
213        return true;
214    }
215  }
216
217  return false;
218}
219
220unsigned ARMSubtarget::getMispredictionPenalty() const {
221  // If we have a reasonable estimate of the pipeline depth, then we can
222  // estimate the penalty of a misprediction based on that.
223  if (isCortexA8())
224    return 13;
225  else if (isCortexA9())
226    return 8;
227
228  // Otherwise, just return a sensible default.
229  return 10;
230}
231
232void ARMSubtarget::computeIssueWidth() {
233  unsigned allStage1Units = 0;
234  for (const InstrItinerary *itin = InstrItins.Itineraries;
235       itin->FirstStage != ~0U; ++itin) {
236    const InstrStage *IS = InstrItins.Stages + itin->FirstStage;
237    allStage1Units |= IS->getUnits();
238  }
239  InstrItins.IssueWidth = 0;
240  while (allStage1Units) {
241    ++InstrItins.IssueWidth;
242    // clear the lowest bit
243    allStage1Units ^= allStage1Units & ~(allStage1Units - 1);
244  }
245  assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units");
246}
247
248bool ARMSubtarget::enablePostRAScheduler(
249           CodeGenOpt::Level OptLevel,
250           TargetSubtarget::AntiDepBreakMode& Mode,
251           RegClassVector& CriticalPathRCs) const {
252  Mode = TargetSubtarget::ANTIDEP_CRITICAL;
253  CriticalPathRCs.clear();
254  CriticalPathRCs.push_back(&ARM::GPRRegClass);
255  return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
256}
257