ARMSubtarget.cpp revision fcba5e6b645df89ae6b93911fe0f80b08fa6b44c 
1//===-- ARMSubtarget.cpp - ARM Subtarget Information ------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the ARM specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMSubtarget.h"
15#include "ARMGenSubtarget.inc"
16#include "llvm/GlobalValue.h"
17#include "llvm/Target/TargetOptions.h"
18#include "llvm/Support/CommandLine.h"
19#include "llvm/ADT/SmallVector.h"
20using namespace llvm;
21
22static cl::opt<bool>
23ReserveR9("arm-reserve-r9", cl::Hidden,
24          cl::desc("Reserve R9, making it unavailable as GPR"));
25
26static cl::opt<bool>
27UseMOVT("arm-use-movt",
28        cl::init(true), cl::Hidden);
29
30ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
31                           bool isT)
32  : ARMArchVersion(V4)
33  , ARMFPUType(None)
34  , UseNEONForSinglePrecisionFP(false)
35  , SlowVMLx(false)
36  , SlowFPBrcc(false)
37  , IsThumb(isT)
38  , ThumbMode(Thumb1)
39  , NoARM(false)
40  , PostRAScheduler(false)
41  , IsR9Reserved(ReserveR9)
42  , UseMovt(UseMOVT)
43  , HasFP16(false)
44  , HasHardwareDivide(false)
45  , HasT2ExtractPack(false)
46  , HasDataBarrier(false)
47  , Pref32BitThumb(false)
48  , FPOnlySP(false)
49  , stackAlignment(4)
50  , CPUString("generic")
51  , TargetType(isELF) // Default to ELF unless otherwise specified.
52  , TargetABI(ARM_ABI_APCS) {
53  // default to soft float ABI
54  if (FloatABIType == FloatABI::Default)
55    FloatABIType = FloatABI::Soft;
56
57  // Determine default and user specified characteristics
58
59  // Parse features string.
60  CPUString = ParseSubtargetFeatures(FS, CPUString);
61
62  // When no arch is specified either by CPU or by attributes, make the default
63  // ARMv4T.
64  if (CPUString == "generic" && (FS.empty() || FS == "generic"))
65    ARMArchVersion = V4T;
66
67  // Set the boolean corresponding to the current target triple, or the default
68  // if one cannot be determined, to true.
69  unsigned Len = TT.length();
70  unsigned Idx = 0;
71
72  if (Len >= 5 && TT.substr(0, 4) == "armv")
73    Idx = 4;
74  else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
75    IsThumb = true;
76    if (Len >= 7 && TT[5] == 'v')
77      Idx = 6;
78  }
79  if (Idx) {
80    unsigned SubVer = TT[Idx];
81    if (SubVer >= '7' && SubVer <= '9') {
82      ARMArchVersion = V7A;
83      if (Len >= Idx+2 && TT[Idx+1] == 'm')
84        ARMArchVersion = V7M;
85    } else if (SubVer == '6') {
86      ARMArchVersion = V6;
87      if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
88        ARMArchVersion = V6T2;
89    } else if (SubVer == '5') {
90      ARMArchVersion = V5T;
91      if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
92        ARMArchVersion = V5TE;
93    } else if (SubVer == '4') {
94      if (Len >= Idx+2 && TT[Idx+1] == 't')
95        ARMArchVersion = V4T;
96      else
97        ARMArchVersion = V4;
98    }
99  }
100
101  // Thumb2 implies at least V6T2.
102  if (ARMArchVersion >= V6T2)
103    ThumbMode = Thumb2;
104  else if (ThumbMode >= Thumb2)
105    ARMArchVersion = V6T2;
106
107  if (Len >= 10) {
108    if (TT.find("-darwin") != std::string::npos)
109      // arm-darwin
110      TargetType = isDarwin;
111  }
112
113  if (TT.find("eabi") != std::string::npos)
114    TargetABI = ARM_ABI_AAPCS;
115
116  if (isAAPCS_ABI())
117    stackAlignment = 8;
118
119  if (isTargetDarwin())
120    IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
121
122  if (!isThumb() || hasThumb2())
123    PostRAScheduler = true;
124}
125
126/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
127bool
128ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
129                                 Reloc::Model RelocM) const {
130  if (RelocM == Reloc::Static)
131    return false;
132
133  // Materializable GVs (in JIT lazy compilation mode) do not require an extra
134  // load from stub.
135  bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
136
137  if (!isTargetDarwin()) {
138    // Extra load is needed for all externally visible.
139    if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
140      return false;
141    return true;
142  } else {
143    if (RelocM == Reloc::PIC_) {
144      // If this is a strong reference to a definition, it is definitely not
145      // through a stub.
146      if (!isDecl && !GV->isWeakForLinker())
147        return false;
148
149      // Unless we have a symbol with hidden visibility, we have to go through a
150      // normal $non_lazy_ptr stub because this symbol might be resolved late.
151      if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
152        return true;
153
154      // If symbol visibility is hidden, we have a stub for common symbol
155      // references and external declarations.
156      if (isDecl || GV->hasCommonLinkage())
157        // Hidden $non_lazy_ptr reference.
158        return true;
159
160      return false;
161    } else {
162      // If this is a strong reference to a definition, it is definitely not
163      // through a stub.
164      if (!isDecl && !GV->isWeakForLinker())
165        return false;
166
167      // Unless we have a symbol with hidden visibility, we have to go through a
168      // normal $non_lazy_ptr stub because this symbol might be resolved late.
169      if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
170        return true;
171    }
172  }
173
174  return false;
175}
176
177bool ARMSubtarget::enablePostRAScheduler(
178           CodeGenOpt::Level OptLevel,
179           TargetSubtarget::AntiDepBreakMode& Mode,
180           RegClassVector& CriticalPathRCs) const {
181  Mode = TargetSubtarget::ANTIDEP_CRITICAL;
182  CriticalPathRCs.clear();
183  CriticalPathRCs.push_back(&ARM::GPRRegClass);
184  return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
185}
186