ARMAsmParser.cpp revision 02265382929b0275d7b7b334eab5e2fd34e1b9fe 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "llvm/MC/MCTargetAsmParser.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMBaseInfo.h"
13#include "MCTargetDesc/ARMMCExpr.h"
14#include "llvm/ADT/BitVector.h"
15#include "llvm/ADT/OwningPtr.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/ADT/Twine.h"
20#include "llvm/MC/MCAsmInfo.h"
21#include "llvm/MC/MCAssembler.h"
22#include "llvm/MC/MCContext.h"
23#include "llvm/MC/MCELFStreamer.h"
24#include "llvm/MC/MCExpr.h"
25#include "llvm/MC/MCInst.h"
26#include "llvm/MC/MCInstrDesc.h"
27#include "llvm/MC/MCParser/MCAsmLexer.h"
28#include "llvm/MC/MCParser/MCAsmParser.h"
29#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
30#include "llvm/MC/MCRegisterInfo.h"
31#include "llvm/MC/MCStreamer.h"
32#include "llvm/MC/MCSubtargetInfo.h"
33#include "llvm/Support/ELF.h"
34#include "llvm/Support/MathExtras.h"
35#include "llvm/Support/SourceMgr.h"
36#include "llvm/Support/TargetRegistry.h"
37#include "llvm/Support/raw_ostream.h"
38
39using namespace llvm;
40
41namespace {
42
43class ARMOperand;
44
45enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
46
47class ARMAsmParser : public MCTargetAsmParser {
48  MCSubtargetInfo &STI;
49  MCAsmParser &Parser;
50  const MCRegisterInfo *MRI;
51
52  // Unwind directives state
53  SMLoc FnStartLoc;
54  SMLoc CantUnwindLoc;
55  SMLoc PersonalityLoc;
56  SMLoc HandlerDataLoc;
57  int FPReg;
58  void resetUnwindDirectiveParserState() {
59    FnStartLoc = SMLoc();
60    CantUnwindLoc = SMLoc();
61    PersonalityLoc = SMLoc();
62    HandlerDataLoc = SMLoc();
63    FPReg = -1;
64  }
65
66  // Map of register aliases registers via the .req directive.
67  StringMap<unsigned> RegisterReqs;
68
69  struct {
70    ARMCC::CondCodes Cond;    // Condition for IT block.
71    unsigned Mask:4;          // Condition mask for instructions.
72                              // Starting at first 1 (from lsb).
73                              //   '1'  condition as indicated in IT.
74                              //   '0'  inverse of condition (else).
75                              // Count of instructions in IT block is
76                              // 4 - trailingzeroes(mask)
77
78    bool FirstCond;           // Explicit flag for when we're parsing the
79                              // First instruction in the IT block. It's
80                              // implied in the mask, so needs special
81                              // handling.
82
83    unsigned CurPosition;     // Current position in parsing of IT
84                              // block. In range [0,3]. Initialized
85                              // according to count of instructions in block.
86                              // ~0U if no active IT block.
87  } ITState;
88  bool inITBlock() { return ITState.CurPosition != ~0U;}
89  void forwardITPosition() {
90    if (!inITBlock()) return;
91    // Move to the next instruction in the IT block, if there is one. If not,
92    // mark the block as done.
93    unsigned TZ = countTrailingZeros(ITState.Mask);
94    if (++ITState.CurPosition == 5 - TZ)
95      ITState.CurPosition = ~0U; // Done with the IT block after this.
96  }
97
98
99  MCAsmParser &getParser() const { return Parser; }
100  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
101
102  bool Warning(SMLoc L, const Twine &Msg,
103               ArrayRef<SMRange> Ranges = None) {
104    return Parser.Warning(L, Msg, Ranges);
105  }
106  bool Error(SMLoc L, const Twine &Msg,
107             ArrayRef<SMRange> Ranges = None) {
108    return Parser.Error(L, Msg, Ranges);
109  }
110
111  int tryParseRegister();
112  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
113  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
114  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
115  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
116  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
117  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
118  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
119                              unsigned &ShiftAmount);
120  bool parseDirectiveWord(unsigned Size, SMLoc L);
121  bool parseDirectiveThumb(SMLoc L);
122  bool parseDirectiveARM(SMLoc L);
123  bool parseDirectiveThumbFunc(SMLoc L);
124  bool parseDirectiveCode(SMLoc L);
125  bool parseDirectiveSyntax(SMLoc L);
126  bool parseDirectiveReq(StringRef Name, SMLoc L);
127  bool parseDirectiveUnreq(SMLoc L);
128  bool parseDirectiveArch(SMLoc L);
129  bool parseDirectiveEabiAttr(SMLoc L);
130  bool parseDirectiveFnStart(SMLoc L);
131  bool parseDirectiveFnEnd(SMLoc L);
132  bool parseDirectiveCantUnwind(SMLoc L);
133  bool parseDirectivePersonality(SMLoc L);
134  bool parseDirectiveHandlerData(SMLoc L);
135  bool parseDirectiveSetFP(SMLoc L);
136  bool parseDirectivePad(SMLoc L);
137  bool parseDirectiveRegSave(SMLoc L, bool IsVector);
138
139  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
140                          bool &CarrySetting, unsigned &ProcessorIMod,
141                          StringRef &ITMask);
142  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
143                             bool &CanAcceptPredicationCode);
144
145  bool isThumb() const {
146    // FIXME: Can tablegen auto-generate this?
147    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
148  }
149  bool isThumbOne() const {
150    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
151  }
152  bool isThumbTwo() const {
153    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
154  }
155  bool hasThumb() const {
156    return STI.getFeatureBits() & ARM::HasV4TOps;
157  }
158  bool hasV6Ops() const {
159    return STI.getFeatureBits() & ARM::HasV6Ops;
160  }
161  bool hasV7Ops() const {
162    return STI.getFeatureBits() & ARM::HasV7Ops;
163  }
164  bool hasV8Ops() const {
165    return STI.getFeatureBits() & ARM::HasV8Ops;
166  }
167  bool hasARM() const {
168    return !(STI.getFeatureBits() & ARM::FeatureNoARM);
169  }
170
171  void SwitchMode() {
172    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
173    setAvailableFeatures(FB);
174  }
175  bool isMClass() const {
176    return STI.getFeatureBits() & ARM::FeatureMClass;
177  }
178
179  /// @name Auto-generated Match Functions
180  /// {
181
182#define GET_ASSEMBLER_HEADER
183#include "ARMGenAsmMatcher.inc"
184
185  /// }
186
187  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
188  OperandMatchResultTy parseCoprocNumOperand(
189    SmallVectorImpl<MCParsedAsmOperand*>&);
190  OperandMatchResultTy parseCoprocRegOperand(
191    SmallVectorImpl<MCParsedAsmOperand*>&);
192  OperandMatchResultTy parseCoprocOptionOperand(
193    SmallVectorImpl<MCParsedAsmOperand*>&);
194  OperandMatchResultTy parseMemBarrierOptOperand(
195    SmallVectorImpl<MCParsedAsmOperand*>&);
196  OperandMatchResultTy parseInstSyncBarrierOptOperand(
197    SmallVectorImpl<MCParsedAsmOperand*>&);
198  OperandMatchResultTy parseProcIFlagsOperand(
199    SmallVectorImpl<MCParsedAsmOperand*>&);
200  OperandMatchResultTy parseMSRMaskOperand(
201    SmallVectorImpl<MCParsedAsmOperand*>&);
202  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
203                                   StringRef Op, int Low, int High);
204  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
205    return parsePKHImm(O, "lsl", 0, 31);
206  }
207  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
208    return parsePKHImm(O, "asr", 1, 32);
209  }
210  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
211  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
212  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
213  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
214  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
215  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
216  OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
217  OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
218  OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
219                                       SMLoc &EndLoc);
220
221  // Asm Match Converter Methods
222  void cvtThumbMultiply(MCInst &Inst,
223                        const SmallVectorImpl<MCParsedAsmOperand*> &);
224  bool validateInstruction(MCInst &Inst,
225                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
226  bool processInstruction(MCInst &Inst,
227                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
228  bool shouldOmitCCOutOperand(StringRef Mnemonic,
229                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
230  bool shouldOmitPredicateOperand(StringRef Mnemonic,
231                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
232
233public:
234  enum ARMMatchResultTy {
235    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
236    Match_RequiresNotITBlock,
237    Match_RequiresV6,
238    Match_RequiresThumb2,
239#define GET_OPERAND_DIAGNOSTIC_TYPES
240#include "ARMGenAsmMatcher.inc"
241
242  };
243
244  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
245    : MCTargetAsmParser(), STI(_STI), Parser(_Parser), FPReg(-1) {
246    MCAsmParserExtension::Initialize(_Parser);
247
248    // Cache the MCRegisterInfo.
249    MRI = getContext().getRegisterInfo();
250
251    // Initialize the set of available features.
252    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
253
254    // Not in an ITBlock to start with.
255    ITState.CurPosition = ~0U;
256
257    // Set ELF header flags.
258    // FIXME: This should eventually end up somewhere else where more
259    // intelligent flag decisions can be made. For now we are just maintaining
260    // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default.
261    if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&Parser.getStreamer()))
262      MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
263  }
264
265  // Implementation of the MCTargetAsmParser interface:
266  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
267  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
268                        SMLoc NameLoc,
269                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
270  bool ParseDirective(AsmToken DirectiveID);
271
272  unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
273  unsigned checkTargetMatchPredicate(MCInst &Inst);
274
275  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
276                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
277                               MCStreamer &Out, unsigned &ErrorInfo,
278                               bool MatchingInlineAsm);
279};
280} // end anonymous namespace
281
282namespace {
283
284/// ARMOperand - Instances of this class represent a parsed ARM machine
285/// operand.
286class ARMOperand : public MCParsedAsmOperand {
287  enum KindTy {
288    k_CondCode,
289    k_CCOut,
290    k_ITCondMask,
291    k_CoprocNum,
292    k_CoprocReg,
293    k_CoprocOption,
294    k_Immediate,
295    k_MemBarrierOpt,
296    k_InstSyncBarrierOpt,
297    k_Memory,
298    k_PostIndexRegister,
299    k_MSRMask,
300    k_ProcIFlags,
301    k_VectorIndex,
302    k_Register,
303    k_RegisterList,
304    k_DPRRegisterList,
305    k_SPRRegisterList,
306    k_VectorList,
307    k_VectorListAllLanes,
308    k_VectorListIndexed,
309    k_ShiftedRegister,
310    k_ShiftedImmediate,
311    k_ShifterImmediate,
312    k_RotateImmediate,
313    k_BitfieldDescriptor,
314    k_Token
315  } Kind;
316
317  SMLoc StartLoc, EndLoc;
318  SmallVector<unsigned, 8> Registers;
319
320  struct CCOp {
321    ARMCC::CondCodes Val;
322  };
323
324  struct CopOp {
325    unsigned Val;
326  };
327
328  struct CoprocOptionOp {
329    unsigned Val;
330  };
331
332  struct ITMaskOp {
333    unsigned Mask:4;
334  };
335
336  struct MBOptOp {
337    ARM_MB::MemBOpt Val;
338  };
339
340  struct ISBOptOp {
341    ARM_ISB::InstSyncBOpt Val;
342  };
343
344  struct IFlagsOp {
345    ARM_PROC::IFlags Val;
346  };
347
348  struct MMaskOp {
349    unsigned Val;
350  };
351
352  struct TokOp {
353    const char *Data;
354    unsigned Length;
355  };
356
357  struct RegOp {
358    unsigned RegNum;
359  };
360
361  // A vector register list is a sequential list of 1 to 4 registers.
362  struct VectorListOp {
363    unsigned RegNum;
364    unsigned Count;
365    unsigned LaneIndex;
366    bool isDoubleSpaced;
367  };
368
369  struct VectorIndexOp {
370    unsigned Val;
371  };
372
373  struct ImmOp {
374    const MCExpr *Val;
375  };
376
377  /// Combined record for all forms of ARM address expressions.
378  struct MemoryOp {
379    unsigned BaseRegNum;
380    // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
381    // was specified.
382    const MCConstantExpr *OffsetImm;  // Offset immediate value
383    unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
384    ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
385    unsigned ShiftImm;        // shift for OffsetReg.
386    unsigned Alignment;       // 0 = no alignment specified
387    // n = alignment in bytes (2, 4, 8, 16, or 32)
388    unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
389  };
390
391  struct PostIdxRegOp {
392    unsigned RegNum;
393    bool isAdd;
394    ARM_AM::ShiftOpc ShiftTy;
395    unsigned ShiftImm;
396  };
397
398  struct ShifterImmOp {
399    bool isASR;
400    unsigned Imm;
401  };
402
403  struct RegShiftedRegOp {
404    ARM_AM::ShiftOpc ShiftTy;
405    unsigned SrcReg;
406    unsigned ShiftReg;
407    unsigned ShiftImm;
408  };
409
410  struct RegShiftedImmOp {
411    ARM_AM::ShiftOpc ShiftTy;
412    unsigned SrcReg;
413    unsigned ShiftImm;
414  };
415
416  struct RotImmOp {
417    unsigned Imm;
418  };
419
420  struct BitfieldOp {
421    unsigned LSB;
422    unsigned Width;
423  };
424
425  union {
426    struct CCOp CC;
427    struct CopOp Cop;
428    struct CoprocOptionOp CoprocOption;
429    struct MBOptOp MBOpt;
430    struct ISBOptOp ISBOpt;
431    struct ITMaskOp ITMask;
432    struct IFlagsOp IFlags;
433    struct MMaskOp MMask;
434    struct TokOp Tok;
435    struct RegOp Reg;
436    struct VectorListOp VectorList;
437    struct VectorIndexOp VectorIndex;
438    struct ImmOp Imm;
439    struct MemoryOp Memory;
440    struct PostIdxRegOp PostIdxReg;
441    struct ShifterImmOp ShifterImm;
442    struct RegShiftedRegOp RegShiftedReg;
443    struct RegShiftedImmOp RegShiftedImm;
444    struct RotImmOp RotImm;
445    struct BitfieldOp Bitfield;
446  };
447
448  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
449public:
450  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
451    Kind = o.Kind;
452    StartLoc = o.StartLoc;
453    EndLoc = o.EndLoc;
454    switch (Kind) {
455    case k_CondCode:
456      CC = o.CC;
457      break;
458    case k_ITCondMask:
459      ITMask = o.ITMask;
460      break;
461    case k_Token:
462      Tok = o.Tok;
463      break;
464    case k_CCOut:
465    case k_Register:
466      Reg = o.Reg;
467      break;
468    case k_RegisterList:
469    case k_DPRRegisterList:
470    case k_SPRRegisterList:
471      Registers = o.Registers;
472      break;
473    case k_VectorList:
474    case k_VectorListAllLanes:
475    case k_VectorListIndexed:
476      VectorList = o.VectorList;
477      break;
478    case k_CoprocNum:
479    case k_CoprocReg:
480      Cop = o.Cop;
481      break;
482    case k_CoprocOption:
483      CoprocOption = o.CoprocOption;
484      break;
485    case k_Immediate:
486      Imm = o.Imm;
487      break;
488    case k_MemBarrierOpt:
489      MBOpt = o.MBOpt;
490      break;
491    case k_InstSyncBarrierOpt:
492      ISBOpt = o.ISBOpt;
493    case k_Memory:
494      Memory = o.Memory;
495      break;
496    case k_PostIndexRegister:
497      PostIdxReg = o.PostIdxReg;
498      break;
499    case k_MSRMask:
500      MMask = o.MMask;
501      break;
502    case k_ProcIFlags:
503      IFlags = o.IFlags;
504      break;
505    case k_ShifterImmediate:
506      ShifterImm = o.ShifterImm;
507      break;
508    case k_ShiftedRegister:
509      RegShiftedReg = o.RegShiftedReg;
510      break;
511    case k_ShiftedImmediate:
512      RegShiftedImm = o.RegShiftedImm;
513      break;
514    case k_RotateImmediate:
515      RotImm = o.RotImm;
516      break;
517    case k_BitfieldDescriptor:
518      Bitfield = o.Bitfield;
519      break;
520    case k_VectorIndex:
521      VectorIndex = o.VectorIndex;
522      break;
523    }
524  }
525
526  /// getStartLoc - Get the location of the first token of this operand.
527  SMLoc getStartLoc() const { return StartLoc; }
528  /// getEndLoc - Get the location of the last token of this operand.
529  SMLoc getEndLoc() const { return EndLoc; }
530  /// getLocRange - Get the range between the first and last token of this
531  /// operand.
532  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
533
534  ARMCC::CondCodes getCondCode() const {
535    assert(Kind == k_CondCode && "Invalid access!");
536    return CC.Val;
537  }
538
539  unsigned getCoproc() const {
540    assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
541    return Cop.Val;
542  }
543
544  StringRef getToken() const {
545    assert(Kind == k_Token && "Invalid access!");
546    return StringRef(Tok.Data, Tok.Length);
547  }
548
549  unsigned getReg() const {
550    assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
551    return Reg.RegNum;
552  }
553
554  const SmallVectorImpl<unsigned> &getRegList() const {
555    assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
556            Kind == k_SPRRegisterList) && "Invalid access!");
557    return Registers;
558  }
559
560  const MCExpr *getImm() const {
561    assert(isImm() && "Invalid access!");
562    return Imm.Val;
563  }
564
565  unsigned getVectorIndex() const {
566    assert(Kind == k_VectorIndex && "Invalid access!");
567    return VectorIndex.Val;
568  }
569
570  ARM_MB::MemBOpt getMemBarrierOpt() const {
571    assert(Kind == k_MemBarrierOpt && "Invalid access!");
572    return MBOpt.Val;
573  }
574
575  ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
576    assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
577    return ISBOpt.Val;
578  }
579
580  ARM_PROC::IFlags getProcIFlags() const {
581    assert(Kind == k_ProcIFlags && "Invalid access!");
582    return IFlags.Val;
583  }
584
585  unsigned getMSRMask() const {
586    assert(Kind == k_MSRMask && "Invalid access!");
587    return MMask.Val;
588  }
589
590  bool isCoprocNum() const { return Kind == k_CoprocNum; }
591  bool isCoprocReg() const { return Kind == k_CoprocReg; }
592  bool isCoprocOption() const { return Kind == k_CoprocOption; }
593  bool isCondCode() const { return Kind == k_CondCode; }
594  bool isCCOut() const { return Kind == k_CCOut; }
595  bool isITMask() const { return Kind == k_ITCondMask; }
596  bool isITCondCode() const { return Kind == k_CondCode; }
597  bool isImm() const { return Kind == k_Immediate; }
598  // checks whether this operand is an unsigned offset which fits is a field
599  // of specified width and scaled by a specific number of bits
600  template<unsigned width, unsigned scale>
601  bool isUnsignedOffset() const {
602    if (!isImm()) return false;
603    if (dyn_cast<MCSymbolRefExpr>(Imm.Val)) return true;
604    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
605      int64_t Val = CE->getValue();
606      int64_t Align = 1LL << scale;
607      int64_t Max = Align * ((1LL << width) - 1);
608      return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
609    }
610    return false;
611  }
612  // checks whether this operand is a memory operand computed as an offset
613  // applied to PC. the offset may have 8 bits of magnitude and is represented
614  // with two bits of shift. textually it may be either [pc, #imm], #imm or
615  // relocable expression...
616  bool isThumbMemPC() const {
617    int64_t Val = 0;
618    if (isImm()) {
619      if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
620      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
621      if (!CE) return false;
622      Val = CE->getValue();
623    }
624    else if (isMem()) {
625      if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
626      if(Memory.BaseRegNum != ARM::PC) return false;
627      Val = Memory.OffsetImm->getValue();
628    }
629    else return false;
630    return ((Val % 4) == 0) && (Val >= -1020) && (Val <= 1020);
631  }
632  bool isFPImm() const {
633    if (!isImm()) return false;
634    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
635    if (!CE) return false;
636    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
637    return Val != -1;
638  }
639  bool isFBits16() const {
640    if (!isImm()) return false;
641    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
642    if (!CE) return false;
643    int64_t Value = CE->getValue();
644    return Value >= 0 && Value <= 16;
645  }
646  bool isFBits32() const {
647    if (!isImm()) return false;
648    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
649    if (!CE) return false;
650    int64_t Value = CE->getValue();
651    return Value >= 1 && Value <= 32;
652  }
653  bool isImm8s4() const {
654    if (!isImm()) return false;
655    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
656    if (!CE) return false;
657    int64_t Value = CE->getValue();
658    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
659  }
660  bool isImm0_4() const {
661    if (!isImm()) return false;
662    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
663    if (!CE) return false;
664    int64_t Value = CE->getValue();
665    return Value >= 0 && Value < 5;
666  }
667  bool isImm0_1020s4() const {
668    if (!isImm()) return false;
669    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
670    if (!CE) return false;
671    int64_t Value = CE->getValue();
672    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
673  }
674  bool isImm0_508s4() const {
675    if (!isImm()) return false;
676    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
677    if (!CE) return false;
678    int64_t Value = CE->getValue();
679    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
680  }
681  bool isImm0_508s4Neg() const {
682    if (!isImm()) return false;
683    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
684    if (!CE) return false;
685    int64_t Value = -CE->getValue();
686    // explicitly exclude zero. we want that to use the normal 0_508 version.
687    return ((Value & 3) == 0) && Value > 0 && Value <= 508;
688  }
689  bool isImm0_255() const {
690    if (!isImm()) return false;
691    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
692    if (!CE) return false;
693    int64_t Value = CE->getValue();
694    return Value >= 0 && Value < 256;
695  }
696  bool isImm0_4095() const {
697    if (!isImm()) return false;
698    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
699    if (!CE) return false;
700    int64_t Value = CE->getValue();
701    return Value >= 0 && Value < 4096;
702  }
703  bool isImm0_4095Neg() const {
704    if (!isImm()) return false;
705    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
706    if (!CE) return false;
707    int64_t Value = -CE->getValue();
708    return Value > 0 && Value < 4096;
709  }
710  bool isImm0_1() const {
711    if (!isImm()) return false;
712    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
713    if (!CE) return false;
714    int64_t Value = CE->getValue();
715    return Value >= 0 && Value < 2;
716  }
717  bool isImm0_3() const {
718    if (!isImm()) return false;
719    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
720    if (!CE) return false;
721    int64_t Value = CE->getValue();
722    return Value >= 0 && Value < 4;
723  }
724  bool isImm0_7() const {
725    if (!isImm()) return false;
726    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
727    if (!CE) return false;
728    int64_t Value = CE->getValue();
729    return Value >= 0 && Value < 8;
730  }
731  bool isImm0_15() const {
732    if (!isImm()) return false;
733    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
734    if (!CE) return false;
735    int64_t Value = CE->getValue();
736    return Value >= 0 && Value < 16;
737  }
738  bool isImm0_31() const {
739    if (!isImm()) return false;
740    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
741    if (!CE) return false;
742    int64_t Value = CE->getValue();
743    return Value >= 0 && Value < 32;
744  }
745  bool isImm0_63() const {
746    if (!isImm()) return false;
747    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
748    if (!CE) return false;
749    int64_t Value = CE->getValue();
750    return Value >= 0 && Value < 64;
751  }
752  bool isImm8() const {
753    if (!isImm()) return false;
754    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
755    if (!CE) return false;
756    int64_t Value = CE->getValue();
757    return Value == 8;
758  }
759  bool isImm16() const {
760    if (!isImm()) return false;
761    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
762    if (!CE) return false;
763    int64_t Value = CE->getValue();
764    return Value == 16;
765  }
766  bool isImm32() const {
767    if (!isImm()) return false;
768    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
769    if (!CE) return false;
770    int64_t Value = CE->getValue();
771    return Value == 32;
772  }
773  bool isShrImm8() const {
774    if (!isImm()) return false;
775    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
776    if (!CE) return false;
777    int64_t Value = CE->getValue();
778    return Value > 0 && Value <= 8;
779  }
780  bool isShrImm16() const {
781    if (!isImm()) return false;
782    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
783    if (!CE) return false;
784    int64_t Value = CE->getValue();
785    return Value > 0 && Value <= 16;
786  }
787  bool isShrImm32() const {
788    if (!isImm()) return false;
789    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
790    if (!CE) return false;
791    int64_t Value = CE->getValue();
792    return Value > 0 && Value <= 32;
793  }
794  bool isShrImm64() const {
795    if (!isImm()) return false;
796    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
797    if (!CE) return false;
798    int64_t Value = CE->getValue();
799    return Value > 0 && Value <= 64;
800  }
801  bool isImm1_7() const {
802    if (!isImm()) return false;
803    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
804    if (!CE) return false;
805    int64_t Value = CE->getValue();
806    return Value > 0 && Value < 8;
807  }
808  bool isImm1_15() const {
809    if (!isImm()) return false;
810    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
811    if (!CE) return false;
812    int64_t Value = CE->getValue();
813    return Value > 0 && Value < 16;
814  }
815  bool isImm1_31() const {
816    if (!isImm()) return false;
817    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
818    if (!CE) return false;
819    int64_t Value = CE->getValue();
820    return Value > 0 && Value < 32;
821  }
822  bool isImm1_16() const {
823    if (!isImm()) return false;
824    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
825    if (!CE) return false;
826    int64_t Value = CE->getValue();
827    return Value > 0 && Value < 17;
828  }
829  bool isImm1_32() const {
830    if (!isImm()) return false;
831    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
832    if (!CE) return false;
833    int64_t Value = CE->getValue();
834    return Value > 0 && Value < 33;
835  }
836  bool isImm0_32() const {
837    if (!isImm()) return false;
838    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
839    if (!CE) return false;
840    int64_t Value = CE->getValue();
841    return Value >= 0 && Value < 33;
842  }
843  bool isImm0_65535() const {
844    if (!isImm()) return false;
845    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
846    if (!CE) return false;
847    int64_t Value = CE->getValue();
848    return Value >= 0 && Value < 65536;
849  }
850  bool isImm0_65535Expr() const {
851    if (!isImm()) return false;
852    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
853    // If it's not a constant expression, it'll generate a fixup and be
854    // handled later.
855    if (!CE) return true;
856    int64_t Value = CE->getValue();
857    return Value >= 0 && Value < 65536;
858  }
859  bool isImm24bit() const {
860    if (!isImm()) return false;
861    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
862    if (!CE) return false;
863    int64_t Value = CE->getValue();
864    return Value >= 0 && Value <= 0xffffff;
865  }
866  bool isImmThumbSR() const {
867    if (!isImm()) return false;
868    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
869    if (!CE) return false;
870    int64_t Value = CE->getValue();
871    return Value > 0 && Value < 33;
872  }
873  bool isPKHLSLImm() const {
874    if (!isImm()) return false;
875    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
876    if (!CE) return false;
877    int64_t Value = CE->getValue();
878    return Value >= 0 && Value < 32;
879  }
880  bool isPKHASRImm() const {
881    if (!isImm()) return false;
882    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
883    if (!CE) return false;
884    int64_t Value = CE->getValue();
885    return Value > 0 && Value <= 32;
886  }
887  bool isAdrLabel() const {
888    // If we have an immediate that's not a constant, treat it as a label
889    // reference needing a fixup. If it is a constant, but it can't fit
890    // into shift immediate encoding, we reject it.
891    if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
892    else return (isARMSOImm() || isARMSOImmNeg());
893  }
894  bool isARMSOImm() const {
895    if (!isImm()) return false;
896    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
897    if (!CE) return false;
898    int64_t Value = CE->getValue();
899    return ARM_AM::getSOImmVal(Value) != -1;
900  }
901  bool isARMSOImmNot() const {
902    if (!isImm()) return false;
903    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
904    if (!CE) return false;
905    int64_t Value = CE->getValue();
906    return ARM_AM::getSOImmVal(~Value) != -1;
907  }
908  bool isARMSOImmNeg() const {
909    if (!isImm()) return false;
910    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
911    if (!CE) return false;
912    int64_t Value = CE->getValue();
913    // Only use this when not representable as a plain so_imm.
914    return ARM_AM::getSOImmVal(Value) == -1 &&
915      ARM_AM::getSOImmVal(-Value) != -1;
916  }
917  bool isT2SOImm() const {
918    if (!isImm()) return false;
919    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
920    if (!CE) return false;
921    int64_t Value = CE->getValue();
922    return ARM_AM::getT2SOImmVal(Value) != -1;
923  }
924  bool isT2SOImmNot() const {
925    if (!isImm()) return false;
926    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
927    if (!CE) return false;
928    int64_t Value = CE->getValue();
929    return ARM_AM::getT2SOImmVal(~Value) != -1;
930  }
931  bool isT2SOImmNeg() const {
932    if (!isImm()) return false;
933    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
934    if (!CE) return false;
935    int64_t Value = CE->getValue();
936    // Only use this when not representable as a plain so_imm.
937    return ARM_AM::getT2SOImmVal(Value) == -1 &&
938      ARM_AM::getT2SOImmVal(-Value) != -1;
939  }
940  bool isSetEndImm() const {
941    if (!isImm()) return false;
942    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
943    if (!CE) return false;
944    int64_t Value = CE->getValue();
945    return Value == 1 || Value == 0;
946  }
947  bool isReg() const { return Kind == k_Register; }
948  bool isRegList() const { return Kind == k_RegisterList; }
949  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
950  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
951  bool isToken() const { return Kind == k_Token; }
952  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
953  bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
954  bool isMem() const { return Kind == k_Memory; }
955  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
956  bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
957  bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
958  bool isRotImm() const { return Kind == k_RotateImmediate; }
959  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
960  bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
961  bool isPostIdxReg() const {
962    return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
963  }
964  bool isMemNoOffset(bool alignOK = false) const {
965    if (!isMem())
966      return false;
967    // No offset of any kind.
968    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
969     (alignOK || Memory.Alignment == 0);
970  }
971  bool isMemPCRelImm12() const {
972    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
973      return false;
974    // Base register must be PC.
975    if (Memory.BaseRegNum != ARM::PC)
976      return false;
977    // Immediate offset in range [-4095, 4095].
978    if (!Memory.OffsetImm) return true;
979    int64_t Val = Memory.OffsetImm->getValue();
980    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
981  }
982  bool isAlignedMemory() const {
983    return isMemNoOffset(true);
984  }
985  bool isAddrMode2() const {
986    if (!isMem() || Memory.Alignment != 0) return false;
987    // Check for register offset.
988    if (Memory.OffsetRegNum) return true;
989    // Immediate offset in range [-4095, 4095].
990    if (!Memory.OffsetImm) return true;
991    int64_t Val = Memory.OffsetImm->getValue();
992    return Val > -4096 && Val < 4096;
993  }
994  bool isAM2OffsetImm() const {
995    if (!isImm()) return false;
996    // Immediate offset in range [-4095, 4095].
997    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
998    if (!CE) return false;
999    int64_t Val = CE->getValue();
1000    return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1001  }
1002  bool isAddrMode3() const {
1003    // If we have an immediate that's not a constant, treat it as a label
1004    // reference needing a fixup. If it is a constant, it's something else
1005    // and we reject it.
1006    if (isImm() && !isa<MCConstantExpr>(getImm()))
1007      return true;
1008    if (!isMem() || Memory.Alignment != 0) return false;
1009    // No shifts are legal for AM3.
1010    if (Memory.ShiftType != ARM_AM::no_shift) return false;
1011    // Check for register offset.
1012    if (Memory.OffsetRegNum) return true;
1013    // Immediate offset in range [-255, 255].
1014    if (!Memory.OffsetImm) return true;
1015    int64_t Val = Memory.OffsetImm->getValue();
1016    // The #-0 offset is encoded as INT32_MIN, and we have to check
1017    // for this too.
1018    return (Val > -256 && Val < 256) || Val == INT32_MIN;
1019  }
1020  bool isAM3Offset() const {
1021    if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1022      return false;
1023    if (Kind == k_PostIndexRegister)
1024      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1025    // Immediate offset in range [-255, 255].
1026    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1027    if (!CE) return false;
1028    int64_t Val = CE->getValue();
1029    // Special case, #-0 is INT32_MIN.
1030    return (Val > -256 && Val < 256) || Val == INT32_MIN;
1031  }
1032  bool isAddrMode5() const {
1033    // If we have an immediate that's not a constant, treat it as a label
1034    // reference needing a fixup. If it is a constant, it's something else
1035    // and we reject it.
1036    if (isImm() && !isa<MCConstantExpr>(getImm()))
1037      return true;
1038    if (!isMem() || Memory.Alignment != 0) return false;
1039    // Check for register offset.
1040    if (Memory.OffsetRegNum) return false;
1041    // Immediate offset in range [-1020, 1020] and a multiple of 4.
1042    if (!Memory.OffsetImm) return true;
1043    int64_t Val = Memory.OffsetImm->getValue();
1044    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1045      Val == INT32_MIN;
1046  }
1047  bool isMemTBB() const {
1048    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1049        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1050      return false;
1051    return true;
1052  }
1053  bool isMemTBH() const {
1054    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1055        Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1056        Memory.Alignment != 0 )
1057      return false;
1058    return true;
1059  }
1060  bool isMemRegOffset() const {
1061    if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1062      return false;
1063    return true;
1064  }
1065  bool isT2MemRegOffset() const {
1066    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1067        Memory.Alignment != 0)
1068      return false;
1069    // Only lsl #{0, 1, 2, 3} allowed.
1070    if (Memory.ShiftType == ARM_AM::no_shift)
1071      return true;
1072    if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1073      return false;
1074    return true;
1075  }
1076  bool isMemThumbRR() const {
1077    // Thumb reg+reg addressing is simple. Just two registers, a base and
1078    // an offset. No shifts, negations or any other complicating factors.
1079    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1080        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1081      return false;
1082    return isARMLowRegister(Memory.BaseRegNum) &&
1083      (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1084  }
1085  bool isMemThumbRIs4() const {
1086    if (!isMem() || Memory.OffsetRegNum != 0 ||
1087        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1088      return false;
1089    // Immediate offset, multiple of 4 in range [0, 124].
1090    if (!Memory.OffsetImm) return true;
1091    int64_t Val = Memory.OffsetImm->getValue();
1092    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1093  }
1094  bool isMemThumbRIs2() const {
1095    if (!isMem() || Memory.OffsetRegNum != 0 ||
1096        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1097      return false;
1098    // Immediate offset, multiple of 4 in range [0, 62].
1099    if (!Memory.OffsetImm) return true;
1100    int64_t Val = Memory.OffsetImm->getValue();
1101    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1102  }
1103  bool isMemThumbRIs1() const {
1104    if (!isMem() || Memory.OffsetRegNum != 0 ||
1105        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1106      return false;
1107    // Immediate offset in range [0, 31].
1108    if (!Memory.OffsetImm) return true;
1109    int64_t Val = Memory.OffsetImm->getValue();
1110    return Val >= 0 && Val <= 31;
1111  }
1112  bool isMemThumbSPI() const {
1113    if (!isMem() || Memory.OffsetRegNum != 0 ||
1114        Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1115      return false;
1116    // Immediate offset, multiple of 4 in range [0, 1020].
1117    if (!Memory.OffsetImm) return true;
1118    int64_t Val = Memory.OffsetImm->getValue();
1119    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1120  }
1121  bool isMemImm8s4Offset() const {
1122    // If we have an immediate that's not a constant, treat it as a label
1123    // reference needing a fixup. If it is a constant, it's something else
1124    // and we reject it.
1125    if (isImm() && !isa<MCConstantExpr>(getImm()))
1126      return true;
1127    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1128      return false;
1129    // Immediate offset a multiple of 4 in range [-1020, 1020].
1130    if (!Memory.OffsetImm) return true;
1131    int64_t Val = Memory.OffsetImm->getValue();
1132    // Special case, #-0 is INT32_MIN.
1133    return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1134  }
1135  bool isMemImm0_1020s4Offset() const {
1136    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1137      return false;
1138    // Immediate offset a multiple of 4 in range [0, 1020].
1139    if (!Memory.OffsetImm) return true;
1140    int64_t Val = Memory.OffsetImm->getValue();
1141    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1142  }
1143  bool isMemImm8Offset() const {
1144    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1145      return false;
1146    // Base reg of PC isn't allowed for these encodings.
1147    if (Memory.BaseRegNum == ARM::PC) return false;
1148    // Immediate offset in range [-255, 255].
1149    if (!Memory.OffsetImm) return true;
1150    int64_t Val = Memory.OffsetImm->getValue();
1151    return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1152  }
1153  bool isMemPosImm8Offset() const {
1154    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1155      return false;
1156    // Immediate offset in range [0, 255].
1157    if (!Memory.OffsetImm) return true;
1158    int64_t Val = Memory.OffsetImm->getValue();
1159    return Val >= 0 && Val < 256;
1160  }
1161  bool isMemNegImm8Offset() const {
1162    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1163      return false;
1164    // Base reg of PC isn't allowed for these encodings.
1165    if (Memory.BaseRegNum == ARM::PC) return false;
1166    // Immediate offset in range [-255, -1].
1167    if (!Memory.OffsetImm) return false;
1168    int64_t Val = Memory.OffsetImm->getValue();
1169    return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1170  }
1171  bool isMemUImm12Offset() const {
1172    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1173      return false;
1174    // Immediate offset in range [0, 4095].
1175    if (!Memory.OffsetImm) return true;
1176    int64_t Val = Memory.OffsetImm->getValue();
1177    return (Val >= 0 && Val < 4096);
1178  }
1179  bool isMemImm12Offset() const {
1180    // If we have an immediate that's not a constant, treat it as a label
1181    // reference needing a fixup. If it is a constant, it's something else
1182    // and we reject it.
1183    if (isImm() && !isa<MCConstantExpr>(getImm()))
1184      return true;
1185
1186    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1187      return false;
1188    // Immediate offset in range [-4095, 4095].
1189    if (!Memory.OffsetImm) return true;
1190    int64_t Val = Memory.OffsetImm->getValue();
1191    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1192  }
1193  bool isPostIdxImm8() const {
1194    if (!isImm()) return false;
1195    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1196    if (!CE) return false;
1197    int64_t Val = CE->getValue();
1198    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1199  }
1200  bool isPostIdxImm8s4() const {
1201    if (!isImm()) return false;
1202    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1203    if (!CE) return false;
1204    int64_t Val = CE->getValue();
1205    return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1206      (Val == INT32_MIN);
1207  }
1208
1209  bool isMSRMask() const { return Kind == k_MSRMask; }
1210  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1211
1212  // NEON operands.
1213  bool isSingleSpacedVectorList() const {
1214    return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1215  }
1216  bool isDoubleSpacedVectorList() const {
1217    return Kind == k_VectorList && VectorList.isDoubleSpaced;
1218  }
1219  bool isVecListOneD() const {
1220    if (!isSingleSpacedVectorList()) return false;
1221    return VectorList.Count == 1;
1222  }
1223
1224  bool isVecListDPair() const {
1225    if (!isSingleSpacedVectorList()) return false;
1226    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1227              .contains(VectorList.RegNum));
1228  }
1229
1230  bool isVecListThreeD() const {
1231    if (!isSingleSpacedVectorList()) return false;
1232    return VectorList.Count == 3;
1233  }
1234
1235  bool isVecListFourD() const {
1236    if (!isSingleSpacedVectorList()) return false;
1237    return VectorList.Count == 4;
1238  }
1239
1240  bool isVecListDPairSpaced() const {
1241    if (isSingleSpacedVectorList()) return false;
1242    return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1243              .contains(VectorList.RegNum));
1244  }
1245
1246  bool isVecListThreeQ() const {
1247    if (!isDoubleSpacedVectorList()) return false;
1248    return VectorList.Count == 3;
1249  }
1250
1251  bool isVecListFourQ() const {
1252    if (!isDoubleSpacedVectorList()) return false;
1253    return VectorList.Count == 4;
1254  }
1255
1256  bool isSingleSpacedVectorAllLanes() const {
1257    return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1258  }
1259  bool isDoubleSpacedVectorAllLanes() const {
1260    return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1261  }
1262  bool isVecListOneDAllLanes() const {
1263    if (!isSingleSpacedVectorAllLanes()) return false;
1264    return VectorList.Count == 1;
1265  }
1266
1267  bool isVecListDPairAllLanes() const {
1268    if (!isSingleSpacedVectorAllLanes()) return false;
1269    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1270              .contains(VectorList.RegNum));
1271  }
1272
1273  bool isVecListDPairSpacedAllLanes() const {
1274    if (!isDoubleSpacedVectorAllLanes()) return false;
1275    return VectorList.Count == 2;
1276  }
1277
1278  bool isVecListThreeDAllLanes() const {
1279    if (!isSingleSpacedVectorAllLanes()) return false;
1280    return VectorList.Count == 3;
1281  }
1282
1283  bool isVecListThreeQAllLanes() const {
1284    if (!isDoubleSpacedVectorAllLanes()) return false;
1285    return VectorList.Count == 3;
1286  }
1287
1288  bool isVecListFourDAllLanes() const {
1289    if (!isSingleSpacedVectorAllLanes()) return false;
1290    return VectorList.Count == 4;
1291  }
1292
1293  bool isVecListFourQAllLanes() const {
1294    if (!isDoubleSpacedVectorAllLanes()) return false;
1295    return VectorList.Count == 4;
1296  }
1297
1298  bool isSingleSpacedVectorIndexed() const {
1299    return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1300  }
1301  bool isDoubleSpacedVectorIndexed() const {
1302    return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1303  }
1304  bool isVecListOneDByteIndexed() const {
1305    if (!isSingleSpacedVectorIndexed()) return false;
1306    return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1307  }
1308
1309  bool isVecListOneDHWordIndexed() const {
1310    if (!isSingleSpacedVectorIndexed()) return false;
1311    return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1312  }
1313
1314  bool isVecListOneDWordIndexed() const {
1315    if (!isSingleSpacedVectorIndexed()) return false;
1316    return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1317  }
1318
1319  bool isVecListTwoDByteIndexed() const {
1320    if (!isSingleSpacedVectorIndexed()) return false;
1321    return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1322  }
1323
1324  bool isVecListTwoDHWordIndexed() const {
1325    if (!isSingleSpacedVectorIndexed()) return false;
1326    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1327  }
1328
1329  bool isVecListTwoQWordIndexed() const {
1330    if (!isDoubleSpacedVectorIndexed()) return false;
1331    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1332  }
1333
1334  bool isVecListTwoQHWordIndexed() const {
1335    if (!isDoubleSpacedVectorIndexed()) return false;
1336    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1337  }
1338
1339  bool isVecListTwoDWordIndexed() const {
1340    if (!isSingleSpacedVectorIndexed()) return false;
1341    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1342  }
1343
1344  bool isVecListThreeDByteIndexed() const {
1345    if (!isSingleSpacedVectorIndexed()) return false;
1346    return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1347  }
1348
1349  bool isVecListThreeDHWordIndexed() const {
1350    if (!isSingleSpacedVectorIndexed()) return false;
1351    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1352  }
1353
1354  bool isVecListThreeQWordIndexed() const {
1355    if (!isDoubleSpacedVectorIndexed()) return false;
1356    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1357  }
1358
1359  bool isVecListThreeQHWordIndexed() const {
1360    if (!isDoubleSpacedVectorIndexed()) return false;
1361    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1362  }
1363
1364  bool isVecListThreeDWordIndexed() const {
1365    if (!isSingleSpacedVectorIndexed()) return false;
1366    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1367  }
1368
1369  bool isVecListFourDByteIndexed() const {
1370    if (!isSingleSpacedVectorIndexed()) return false;
1371    return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1372  }
1373
1374  bool isVecListFourDHWordIndexed() const {
1375    if (!isSingleSpacedVectorIndexed()) return false;
1376    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1377  }
1378
1379  bool isVecListFourQWordIndexed() const {
1380    if (!isDoubleSpacedVectorIndexed()) return false;
1381    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1382  }
1383
1384  bool isVecListFourQHWordIndexed() const {
1385    if (!isDoubleSpacedVectorIndexed()) return false;
1386    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1387  }
1388
1389  bool isVecListFourDWordIndexed() const {
1390    if (!isSingleSpacedVectorIndexed()) return false;
1391    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1392  }
1393
1394  bool isVectorIndex8() const {
1395    if (Kind != k_VectorIndex) return false;
1396    return VectorIndex.Val < 8;
1397  }
1398  bool isVectorIndex16() const {
1399    if (Kind != k_VectorIndex) return false;
1400    return VectorIndex.Val < 4;
1401  }
1402  bool isVectorIndex32() const {
1403    if (Kind != k_VectorIndex) return false;
1404    return VectorIndex.Val < 2;
1405  }
1406
1407  bool isNEONi8splat() const {
1408    if (!isImm()) return false;
1409    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1410    // Must be a constant.
1411    if (!CE) return false;
1412    int64_t Value = CE->getValue();
1413    // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1414    // value.
1415    return Value >= 0 && Value < 256;
1416  }
1417
1418  bool isNEONi16splat() const {
1419    if (!isImm()) return false;
1420    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1421    // Must be a constant.
1422    if (!CE) return false;
1423    int64_t Value = CE->getValue();
1424    // i16 value in the range [0,255] or [0x0100, 0xff00]
1425    return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1426  }
1427
1428  bool isNEONi32splat() const {
1429    if (!isImm()) return false;
1430    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1431    // Must be a constant.
1432    if (!CE) return false;
1433    int64_t Value = CE->getValue();
1434    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1435    return (Value >= 0 && Value < 256) ||
1436      (Value >= 0x0100 && Value <= 0xff00) ||
1437      (Value >= 0x010000 && Value <= 0xff0000) ||
1438      (Value >= 0x01000000 && Value <= 0xff000000);
1439  }
1440
1441  bool isNEONi32vmov() const {
1442    if (!isImm()) return false;
1443    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1444    // Must be a constant.
1445    if (!CE) return false;
1446    int64_t Value = CE->getValue();
1447    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1448    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1449    return (Value >= 0 && Value < 256) ||
1450      (Value >= 0x0100 && Value <= 0xff00) ||
1451      (Value >= 0x010000 && Value <= 0xff0000) ||
1452      (Value >= 0x01000000 && Value <= 0xff000000) ||
1453      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1454      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1455  }
1456  bool isNEONi32vmovNeg() const {
1457    if (!isImm()) return false;
1458    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1459    // Must be a constant.
1460    if (!CE) return false;
1461    int64_t Value = ~CE->getValue();
1462    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1463    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1464    return (Value >= 0 && Value < 256) ||
1465      (Value >= 0x0100 && Value <= 0xff00) ||
1466      (Value >= 0x010000 && Value <= 0xff0000) ||
1467      (Value >= 0x01000000 && Value <= 0xff000000) ||
1468      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1469      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1470  }
1471
1472  bool isNEONi64splat() const {
1473    if (!isImm()) return false;
1474    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1475    // Must be a constant.
1476    if (!CE) return false;
1477    uint64_t Value = CE->getValue();
1478    // i64 value with each byte being either 0 or 0xff.
1479    for (unsigned i = 0; i < 8; ++i)
1480      if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1481    return true;
1482  }
1483
1484  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1485    // Add as immediates when possible.  Null MCExpr = 0.
1486    if (Expr == 0)
1487      Inst.addOperand(MCOperand::CreateImm(0));
1488    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1489      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1490    else
1491      Inst.addOperand(MCOperand::CreateExpr(Expr));
1492  }
1493
1494  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1495    assert(N == 2 && "Invalid number of operands!");
1496    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1497    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1498    Inst.addOperand(MCOperand::CreateReg(RegNum));
1499  }
1500
1501  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1502    assert(N == 1 && "Invalid number of operands!");
1503    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1504  }
1505
1506  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1507    assert(N == 1 && "Invalid number of operands!");
1508    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1509  }
1510
1511  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1512    assert(N == 1 && "Invalid number of operands!");
1513    Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1514  }
1515
1516  void addITMaskOperands(MCInst &Inst, unsigned N) const {
1517    assert(N == 1 && "Invalid number of operands!");
1518    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1519  }
1520
1521  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1522    assert(N == 1 && "Invalid number of operands!");
1523    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1524  }
1525
1526  void addCCOutOperands(MCInst &Inst, unsigned N) const {
1527    assert(N == 1 && "Invalid number of operands!");
1528    Inst.addOperand(MCOperand::CreateReg(getReg()));
1529  }
1530
1531  void addRegOperands(MCInst &Inst, unsigned N) const {
1532    assert(N == 1 && "Invalid number of operands!");
1533    Inst.addOperand(MCOperand::CreateReg(getReg()));
1534  }
1535
1536  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1537    assert(N == 3 && "Invalid number of operands!");
1538    assert(isRegShiftedReg() &&
1539           "addRegShiftedRegOperands() on non RegShiftedReg!");
1540    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1541    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1542    Inst.addOperand(MCOperand::CreateImm(
1543      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1544  }
1545
1546  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1547    assert(N == 2 && "Invalid number of operands!");
1548    assert(isRegShiftedImm() &&
1549           "addRegShiftedImmOperands() on non RegShiftedImm!");
1550    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1551    // Shift of #32 is encoded as 0 where permitted
1552    unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1553    Inst.addOperand(MCOperand::CreateImm(
1554      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1555  }
1556
1557  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1558    assert(N == 1 && "Invalid number of operands!");
1559    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1560                                         ShifterImm.Imm));
1561  }
1562
1563  void addRegListOperands(MCInst &Inst, unsigned N) const {
1564    assert(N == 1 && "Invalid number of operands!");
1565    const SmallVectorImpl<unsigned> &RegList = getRegList();
1566    for (SmallVectorImpl<unsigned>::const_iterator
1567           I = RegList.begin(), E = RegList.end(); I != E; ++I)
1568      Inst.addOperand(MCOperand::CreateReg(*I));
1569  }
1570
1571  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1572    addRegListOperands(Inst, N);
1573  }
1574
1575  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1576    addRegListOperands(Inst, N);
1577  }
1578
1579  void addRotImmOperands(MCInst &Inst, unsigned N) const {
1580    assert(N == 1 && "Invalid number of operands!");
1581    // Encoded as val>>3. The printer handles display as 8, 16, 24.
1582    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1583  }
1584
1585  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1586    assert(N == 1 && "Invalid number of operands!");
1587    // Munge the lsb/width into a bitfield mask.
1588    unsigned lsb = Bitfield.LSB;
1589    unsigned width = Bitfield.Width;
1590    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1591    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1592                      (32 - (lsb + width)));
1593    Inst.addOperand(MCOperand::CreateImm(Mask));
1594  }
1595
1596  void addImmOperands(MCInst &Inst, unsigned N) const {
1597    assert(N == 1 && "Invalid number of operands!");
1598    addExpr(Inst, getImm());
1599  }
1600
1601  void addFBits16Operands(MCInst &Inst, unsigned N) const {
1602    assert(N == 1 && "Invalid number of operands!");
1603    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1604    Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1605  }
1606
1607  void addFBits32Operands(MCInst &Inst, unsigned N) const {
1608    assert(N == 1 && "Invalid number of operands!");
1609    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1610    Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1611  }
1612
1613  void addFPImmOperands(MCInst &Inst, unsigned N) const {
1614    assert(N == 1 && "Invalid number of operands!");
1615    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1616    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1617    Inst.addOperand(MCOperand::CreateImm(Val));
1618  }
1619
1620  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1621    assert(N == 1 && "Invalid number of operands!");
1622    // FIXME: We really want to scale the value here, but the LDRD/STRD
1623    // instruction don't encode operands that way yet.
1624    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1625    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1626  }
1627
1628  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1629    assert(N == 1 && "Invalid number of operands!");
1630    // The immediate is scaled by four in the encoding and is stored
1631    // in the MCInst as such. Lop off the low two bits here.
1632    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1633    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1634  }
1635
1636  void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1637    assert(N == 1 && "Invalid number of operands!");
1638    // The immediate is scaled by four in the encoding and is stored
1639    // in the MCInst as such. Lop off the low two bits here.
1640    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1641    Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1642  }
1643
1644  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1645    assert(N == 1 && "Invalid number of operands!");
1646    // The immediate is scaled by four in the encoding and is stored
1647    // in the MCInst as such. Lop off the low two bits here.
1648    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1649    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1650  }
1651
1652  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1653    assert(N == 1 && "Invalid number of operands!");
1654    // The constant encodes as the immediate-1, and we store in the instruction
1655    // the bits as encoded, so subtract off one here.
1656    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1657    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1658  }
1659
1660  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1661    assert(N == 1 && "Invalid number of operands!");
1662    // The constant encodes as the immediate-1, and we store in the instruction
1663    // the bits as encoded, so subtract off one here.
1664    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1665    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1666  }
1667
1668  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1669    assert(N == 1 && "Invalid number of operands!");
1670    // The constant encodes as the immediate, except for 32, which encodes as
1671    // zero.
1672    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1673    unsigned Imm = CE->getValue();
1674    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1675  }
1676
1677  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1678    assert(N == 1 && "Invalid number of operands!");
1679    // An ASR value of 32 encodes as 0, so that's how we want to add it to
1680    // the instruction as well.
1681    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1682    int Val = CE->getValue();
1683    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1684  }
1685
1686  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1687    assert(N == 1 && "Invalid number of operands!");
1688    // The operand is actually a t2_so_imm, but we have its bitwise
1689    // negation in the assembly source, so twiddle it here.
1690    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1691    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1692  }
1693
1694  void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1695    assert(N == 1 && "Invalid number of operands!");
1696    // The operand is actually a t2_so_imm, but we have its
1697    // negation in the assembly source, so twiddle it here.
1698    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1699    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1700  }
1701
1702  void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1703    assert(N == 1 && "Invalid number of operands!");
1704    // The operand is actually an imm0_4095, but we have its
1705    // negation in the assembly source, so twiddle it here.
1706    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1707    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1708  }
1709
1710  void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1711    if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1712      Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1713      return;
1714    }
1715
1716    const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1717    assert(SR && "Unknown value type!");
1718    Inst.addOperand(MCOperand::CreateExpr(SR));
1719  }
1720
1721  void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1722    assert(N == 1 && "Invalid number of operands!");
1723    if (isImm()) {
1724      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1725      if (CE) {
1726        Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1727        return;
1728      }
1729
1730      const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1731      assert(SR && "Unknown value type!");
1732      Inst.addOperand(MCOperand::CreateExpr(SR));
1733      return;
1734    }
1735
1736    assert(isMem()  && "Unknown value type!");
1737    assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1738    Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1739  }
1740
1741  void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1742    assert(N == 1 && "Invalid number of operands!");
1743    // The operand is actually a so_imm, but we have its bitwise
1744    // negation in the assembly source, so twiddle it here.
1745    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1746    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1747  }
1748
1749  void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1750    assert(N == 1 && "Invalid number of operands!");
1751    // The operand is actually a so_imm, but we have its
1752    // negation in the assembly source, so twiddle it here.
1753    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1754    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1755  }
1756
1757  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1758    assert(N == 1 && "Invalid number of operands!");
1759    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1760  }
1761
1762  void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1763    assert(N == 1 && "Invalid number of operands!");
1764    Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1765  }
1766
1767  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1768    assert(N == 1 && "Invalid number of operands!");
1769    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1770  }
1771
1772  void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1773    assert(N == 1 && "Invalid number of operands!");
1774    int32_t Imm = Memory.OffsetImm->getValue();
1775    // FIXME: Handle #-0
1776    if (Imm == INT32_MIN) Imm = 0;
1777    Inst.addOperand(MCOperand::CreateImm(Imm));
1778  }
1779
1780  void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1781    assert(N == 1 && "Invalid number of operands!");
1782    assert(isImm() && "Not an immediate!");
1783
1784    // If we have an immediate that's not a constant, treat it as a label
1785    // reference needing a fixup.
1786    if (!isa<MCConstantExpr>(getImm())) {
1787      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1788      return;
1789    }
1790
1791    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1792    int Val = CE->getValue();
1793    Inst.addOperand(MCOperand::CreateImm(Val));
1794  }
1795
1796  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1797    assert(N == 2 && "Invalid number of operands!");
1798    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1799    Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1800  }
1801
1802  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1803    assert(N == 3 && "Invalid number of operands!");
1804    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1805    if (!Memory.OffsetRegNum) {
1806      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1807      // Special case for #-0
1808      if (Val == INT32_MIN) Val = 0;
1809      if (Val < 0) Val = -Val;
1810      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1811    } else {
1812      // For register offset, we encode the shift type and negation flag
1813      // here.
1814      Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1815                              Memory.ShiftImm, Memory.ShiftType);
1816    }
1817    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1818    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1819    Inst.addOperand(MCOperand::CreateImm(Val));
1820  }
1821
1822  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1823    assert(N == 2 && "Invalid number of operands!");
1824    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1825    assert(CE && "non-constant AM2OffsetImm operand!");
1826    int32_t Val = CE->getValue();
1827    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1828    // Special case for #-0
1829    if (Val == INT32_MIN) Val = 0;
1830    if (Val < 0) Val = -Val;
1831    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1832    Inst.addOperand(MCOperand::CreateReg(0));
1833    Inst.addOperand(MCOperand::CreateImm(Val));
1834  }
1835
1836  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1837    assert(N == 3 && "Invalid number of operands!");
1838    // If we have an immediate that's not a constant, treat it as a label
1839    // reference needing a fixup. If it is a constant, it's something else
1840    // and we reject it.
1841    if (isImm()) {
1842      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1843      Inst.addOperand(MCOperand::CreateReg(0));
1844      Inst.addOperand(MCOperand::CreateImm(0));
1845      return;
1846    }
1847
1848    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1849    if (!Memory.OffsetRegNum) {
1850      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1851      // Special case for #-0
1852      if (Val == INT32_MIN) Val = 0;
1853      if (Val < 0) Val = -Val;
1854      Val = ARM_AM::getAM3Opc(AddSub, Val);
1855    } else {
1856      // For register offset, we encode the shift type and negation flag
1857      // here.
1858      Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1859    }
1860    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1861    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1862    Inst.addOperand(MCOperand::CreateImm(Val));
1863  }
1864
1865  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1866    assert(N == 2 && "Invalid number of operands!");
1867    if (Kind == k_PostIndexRegister) {
1868      int32_t Val =
1869        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1870      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1871      Inst.addOperand(MCOperand::CreateImm(Val));
1872      return;
1873    }
1874
1875    // Constant offset.
1876    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1877    int32_t Val = CE->getValue();
1878    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1879    // Special case for #-0
1880    if (Val == INT32_MIN) Val = 0;
1881    if (Val < 0) Val = -Val;
1882    Val = ARM_AM::getAM3Opc(AddSub, Val);
1883    Inst.addOperand(MCOperand::CreateReg(0));
1884    Inst.addOperand(MCOperand::CreateImm(Val));
1885  }
1886
1887  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1888    assert(N == 2 && "Invalid number of operands!");
1889    // If we have an immediate that's not a constant, treat it as a label
1890    // reference needing a fixup. If it is a constant, it's something else
1891    // and we reject it.
1892    if (isImm()) {
1893      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1894      Inst.addOperand(MCOperand::CreateImm(0));
1895      return;
1896    }
1897
1898    // The lower two bits are always zero and as such are not encoded.
1899    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1900    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1901    // Special case for #-0
1902    if (Val == INT32_MIN) Val = 0;
1903    if (Val < 0) Val = -Val;
1904    Val = ARM_AM::getAM5Opc(AddSub, Val);
1905    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1906    Inst.addOperand(MCOperand::CreateImm(Val));
1907  }
1908
1909  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1910    assert(N == 2 && "Invalid number of operands!");
1911    // If we have an immediate that's not a constant, treat it as a label
1912    // reference needing a fixup. If it is a constant, it's something else
1913    // and we reject it.
1914    if (isImm()) {
1915      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1916      Inst.addOperand(MCOperand::CreateImm(0));
1917      return;
1918    }
1919
1920    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1921    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1922    Inst.addOperand(MCOperand::CreateImm(Val));
1923  }
1924
1925  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1926    assert(N == 2 && "Invalid number of operands!");
1927    // The lower two bits are always zero and as such are not encoded.
1928    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1929    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1930    Inst.addOperand(MCOperand::CreateImm(Val));
1931  }
1932
1933  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1934    assert(N == 2 && "Invalid number of operands!");
1935    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1936    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1937    Inst.addOperand(MCOperand::CreateImm(Val));
1938  }
1939
1940  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1941    addMemImm8OffsetOperands(Inst, N);
1942  }
1943
1944  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1945    addMemImm8OffsetOperands(Inst, N);
1946  }
1947
1948  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1949    assert(N == 2 && "Invalid number of operands!");
1950    // If this is an immediate, it's a label reference.
1951    if (isImm()) {
1952      addExpr(Inst, getImm());
1953      Inst.addOperand(MCOperand::CreateImm(0));
1954      return;
1955    }
1956
1957    // Otherwise, it's a normal memory reg+offset.
1958    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1959    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1960    Inst.addOperand(MCOperand::CreateImm(Val));
1961  }
1962
1963  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1964    assert(N == 2 && "Invalid number of operands!");
1965    // If this is an immediate, it's a label reference.
1966    if (isImm()) {
1967      addExpr(Inst, getImm());
1968      Inst.addOperand(MCOperand::CreateImm(0));
1969      return;
1970    }
1971
1972    // Otherwise, it's a normal memory reg+offset.
1973    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1974    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1975    Inst.addOperand(MCOperand::CreateImm(Val));
1976  }
1977
1978  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1979    assert(N == 2 && "Invalid number of operands!");
1980    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1981    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1982  }
1983
1984  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1985    assert(N == 2 && "Invalid number of operands!");
1986    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1987    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1988  }
1989
1990  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1991    assert(N == 3 && "Invalid number of operands!");
1992    unsigned Val =
1993      ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1994                        Memory.ShiftImm, Memory.ShiftType);
1995    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1996    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1997    Inst.addOperand(MCOperand::CreateImm(Val));
1998  }
1999
2000  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2001    assert(N == 3 && "Invalid number of operands!");
2002    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2003    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2004    Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2005  }
2006
2007  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2008    assert(N == 2 && "Invalid number of operands!");
2009    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2010    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2011  }
2012
2013  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2014    assert(N == 2 && "Invalid number of operands!");
2015    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2016    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2017    Inst.addOperand(MCOperand::CreateImm(Val));
2018  }
2019
2020  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2021    assert(N == 2 && "Invalid number of operands!");
2022    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2023    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2024    Inst.addOperand(MCOperand::CreateImm(Val));
2025  }
2026
2027  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2028    assert(N == 2 && "Invalid number of operands!");
2029    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2030    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2031    Inst.addOperand(MCOperand::CreateImm(Val));
2032  }
2033
2034  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2035    assert(N == 2 && "Invalid number of operands!");
2036    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2037    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2038    Inst.addOperand(MCOperand::CreateImm(Val));
2039  }
2040
2041  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2042    assert(N == 1 && "Invalid number of operands!");
2043    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2044    assert(CE && "non-constant post-idx-imm8 operand!");
2045    int Imm = CE->getValue();
2046    bool isAdd = Imm >= 0;
2047    if (Imm == INT32_MIN) Imm = 0;
2048    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2049    Inst.addOperand(MCOperand::CreateImm(Imm));
2050  }
2051
2052  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2053    assert(N == 1 && "Invalid number of operands!");
2054    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2055    assert(CE && "non-constant post-idx-imm8s4 operand!");
2056    int Imm = CE->getValue();
2057    bool isAdd = Imm >= 0;
2058    if (Imm == INT32_MIN) Imm = 0;
2059    // Immediate is scaled by 4.
2060    Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2061    Inst.addOperand(MCOperand::CreateImm(Imm));
2062  }
2063
2064  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2065    assert(N == 2 && "Invalid number of operands!");
2066    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2067    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2068  }
2069
2070  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2071    assert(N == 2 && "Invalid number of operands!");
2072    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2073    // The sign, shift type, and shift amount are encoded in a single operand
2074    // using the AM2 encoding helpers.
2075    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2076    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2077                                     PostIdxReg.ShiftTy);
2078    Inst.addOperand(MCOperand::CreateImm(Imm));
2079  }
2080
2081  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2082    assert(N == 1 && "Invalid number of operands!");
2083    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2084  }
2085
2086  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2087    assert(N == 1 && "Invalid number of operands!");
2088    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2089  }
2090
2091  void addVecListOperands(MCInst &Inst, unsigned N) const {
2092    assert(N == 1 && "Invalid number of operands!");
2093    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2094  }
2095
2096  void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2097    assert(N == 2 && "Invalid number of operands!");
2098    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2099    Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2100  }
2101
2102  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2103    assert(N == 1 && "Invalid number of operands!");
2104    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2105  }
2106
2107  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2108    assert(N == 1 && "Invalid number of operands!");
2109    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2110  }
2111
2112  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2113    assert(N == 1 && "Invalid number of operands!");
2114    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2115  }
2116
2117  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2118    assert(N == 1 && "Invalid number of operands!");
2119    // The immediate encodes the type of constant as well as the value.
2120    // Mask in that this is an i8 splat.
2121    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2122    Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2123  }
2124
2125  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2126    assert(N == 1 && "Invalid number of operands!");
2127    // The immediate encodes the type of constant as well as the value.
2128    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2129    unsigned Value = CE->getValue();
2130    if (Value >= 256)
2131      Value = (Value >> 8) | 0xa00;
2132    else
2133      Value |= 0x800;
2134    Inst.addOperand(MCOperand::CreateImm(Value));
2135  }
2136
2137  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2138    assert(N == 1 && "Invalid number of operands!");
2139    // The immediate encodes the type of constant as well as the value.
2140    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2141    unsigned Value = CE->getValue();
2142    if (Value >= 256 && Value <= 0xff00)
2143      Value = (Value >> 8) | 0x200;
2144    else if (Value > 0xffff && Value <= 0xff0000)
2145      Value = (Value >> 16) | 0x400;
2146    else if (Value > 0xffffff)
2147      Value = (Value >> 24) | 0x600;
2148    Inst.addOperand(MCOperand::CreateImm(Value));
2149  }
2150
2151  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2152    assert(N == 1 && "Invalid number of operands!");
2153    // The immediate encodes the type of constant as well as the value.
2154    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2155    unsigned Value = CE->getValue();
2156    if (Value >= 256 && Value <= 0xffff)
2157      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2158    else if (Value > 0xffff && Value <= 0xffffff)
2159      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2160    else if (Value > 0xffffff)
2161      Value = (Value >> 24) | 0x600;
2162    Inst.addOperand(MCOperand::CreateImm(Value));
2163  }
2164
2165  void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2166    assert(N == 1 && "Invalid number of operands!");
2167    // The immediate encodes the type of constant as well as the value.
2168    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2169    unsigned Value = ~CE->getValue();
2170    if (Value >= 256 && Value <= 0xffff)
2171      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2172    else if (Value > 0xffff && Value <= 0xffffff)
2173      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2174    else if (Value > 0xffffff)
2175      Value = (Value >> 24) | 0x600;
2176    Inst.addOperand(MCOperand::CreateImm(Value));
2177  }
2178
2179  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2180    assert(N == 1 && "Invalid number of operands!");
2181    // The immediate encodes the type of constant as well as the value.
2182    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2183    uint64_t Value = CE->getValue();
2184    unsigned Imm = 0;
2185    for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2186      Imm |= (Value & 1) << i;
2187    }
2188    Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2189  }
2190
2191  virtual void print(raw_ostream &OS) const;
2192
2193  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2194    ARMOperand *Op = new ARMOperand(k_ITCondMask);
2195    Op->ITMask.Mask = Mask;
2196    Op->StartLoc = S;
2197    Op->EndLoc = S;
2198    return Op;
2199  }
2200
2201  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2202    ARMOperand *Op = new ARMOperand(k_CondCode);
2203    Op->CC.Val = CC;
2204    Op->StartLoc = S;
2205    Op->EndLoc = S;
2206    return Op;
2207  }
2208
2209  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2210    ARMOperand *Op = new ARMOperand(k_CoprocNum);
2211    Op->Cop.Val = CopVal;
2212    Op->StartLoc = S;
2213    Op->EndLoc = S;
2214    return Op;
2215  }
2216
2217  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2218    ARMOperand *Op = new ARMOperand(k_CoprocReg);
2219    Op->Cop.Val = CopVal;
2220    Op->StartLoc = S;
2221    Op->EndLoc = S;
2222    return Op;
2223  }
2224
2225  static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2226    ARMOperand *Op = new ARMOperand(k_CoprocOption);
2227    Op->Cop.Val = Val;
2228    Op->StartLoc = S;
2229    Op->EndLoc = E;
2230    return Op;
2231  }
2232
2233  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2234    ARMOperand *Op = new ARMOperand(k_CCOut);
2235    Op->Reg.RegNum = RegNum;
2236    Op->StartLoc = S;
2237    Op->EndLoc = S;
2238    return Op;
2239  }
2240
2241  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2242    ARMOperand *Op = new ARMOperand(k_Token);
2243    Op->Tok.Data = Str.data();
2244    Op->Tok.Length = Str.size();
2245    Op->StartLoc = S;
2246    Op->EndLoc = S;
2247    return Op;
2248  }
2249
2250  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2251    ARMOperand *Op = new ARMOperand(k_Register);
2252    Op->Reg.RegNum = RegNum;
2253    Op->StartLoc = S;
2254    Op->EndLoc = E;
2255    return Op;
2256  }
2257
2258  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2259                                           unsigned SrcReg,
2260                                           unsigned ShiftReg,
2261                                           unsigned ShiftImm,
2262                                           SMLoc S, SMLoc E) {
2263    ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2264    Op->RegShiftedReg.ShiftTy = ShTy;
2265    Op->RegShiftedReg.SrcReg = SrcReg;
2266    Op->RegShiftedReg.ShiftReg = ShiftReg;
2267    Op->RegShiftedReg.ShiftImm = ShiftImm;
2268    Op->StartLoc = S;
2269    Op->EndLoc = E;
2270    return Op;
2271  }
2272
2273  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2274                                            unsigned SrcReg,
2275                                            unsigned ShiftImm,
2276                                            SMLoc S, SMLoc E) {
2277    ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2278    Op->RegShiftedImm.ShiftTy = ShTy;
2279    Op->RegShiftedImm.SrcReg = SrcReg;
2280    Op->RegShiftedImm.ShiftImm = ShiftImm;
2281    Op->StartLoc = S;
2282    Op->EndLoc = E;
2283    return Op;
2284  }
2285
2286  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2287                                   SMLoc S, SMLoc E) {
2288    ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2289    Op->ShifterImm.isASR = isASR;
2290    Op->ShifterImm.Imm = Imm;
2291    Op->StartLoc = S;
2292    Op->EndLoc = E;
2293    return Op;
2294  }
2295
2296  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2297    ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2298    Op->RotImm.Imm = Imm;
2299    Op->StartLoc = S;
2300    Op->EndLoc = E;
2301    return Op;
2302  }
2303
2304  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2305                                    SMLoc S, SMLoc E) {
2306    ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2307    Op->Bitfield.LSB = LSB;
2308    Op->Bitfield.Width = Width;
2309    Op->StartLoc = S;
2310    Op->EndLoc = E;
2311    return Op;
2312  }
2313
2314  static ARMOperand *
2315  CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2316                SMLoc StartLoc, SMLoc EndLoc) {
2317    assert (Regs.size() > 0 && "RegList contains no registers?");
2318    KindTy Kind = k_RegisterList;
2319
2320    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2321      Kind = k_DPRRegisterList;
2322    else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2323             contains(Regs.front().second))
2324      Kind = k_SPRRegisterList;
2325
2326    // Sort based on the register encoding values.
2327    array_pod_sort(Regs.begin(), Regs.end());
2328
2329    ARMOperand *Op = new ARMOperand(Kind);
2330    for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2331           I = Regs.begin(), E = Regs.end(); I != E; ++I)
2332      Op->Registers.push_back(I->second);
2333    Op->StartLoc = StartLoc;
2334    Op->EndLoc = EndLoc;
2335    return Op;
2336  }
2337
2338  static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2339                                      bool isDoubleSpaced, SMLoc S, SMLoc E) {
2340    ARMOperand *Op = new ARMOperand(k_VectorList);
2341    Op->VectorList.RegNum = RegNum;
2342    Op->VectorList.Count = Count;
2343    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2344    Op->StartLoc = S;
2345    Op->EndLoc = E;
2346    return Op;
2347  }
2348
2349  static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2350                                              bool isDoubleSpaced,
2351                                              SMLoc S, SMLoc E) {
2352    ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2353    Op->VectorList.RegNum = RegNum;
2354    Op->VectorList.Count = Count;
2355    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2356    Op->StartLoc = S;
2357    Op->EndLoc = E;
2358    return Op;
2359  }
2360
2361  static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2362                                             unsigned Index,
2363                                             bool isDoubleSpaced,
2364                                             SMLoc S, SMLoc E) {
2365    ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2366    Op->VectorList.RegNum = RegNum;
2367    Op->VectorList.Count = Count;
2368    Op->VectorList.LaneIndex = Index;
2369    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2370    Op->StartLoc = S;
2371    Op->EndLoc = E;
2372    return Op;
2373  }
2374
2375  static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2376                                       MCContext &Ctx) {
2377    ARMOperand *Op = new ARMOperand(k_VectorIndex);
2378    Op->VectorIndex.Val = Idx;
2379    Op->StartLoc = S;
2380    Op->EndLoc = E;
2381    return Op;
2382  }
2383
2384  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2385    ARMOperand *Op = new ARMOperand(k_Immediate);
2386    Op->Imm.Val = Val;
2387    Op->StartLoc = S;
2388    Op->EndLoc = E;
2389    return Op;
2390  }
2391
2392  static ARMOperand *CreateMem(unsigned BaseRegNum,
2393                               const MCConstantExpr *OffsetImm,
2394                               unsigned OffsetRegNum,
2395                               ARM_AM::ShiftOpc ShiftType,
2396                               unsigned ShiftImm,
2397                               unsigned Alignment,
2398                               bool isNegative,
2399                               SMLoc S, SMLoc E) {
2400    ARMOperand *Op = new ARMOperand(k_Memory);
2401    Op->Memory.BaseRegNum = BaseRegNum;
2402    Op->Memory.OffsetImm = OffsetImm;
2403    Op->Memory.OffsetRegNum = OffsetRegNum;
2404    Op->Memory.ShiftType = ShiftType;
2405    Op->Memory.ShiftImm = ShiftImm;
2406    Op->Memory.Alignment = Alignment;
2407    Op->Memory.isNegative = isNegative;
2408    Op->StartLoc = S;
2409    Op->EndLoc = E;
2410    return Op;
2411  }
2412
2413  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2414                                      ARM_AM::ShiftOpc ShiftTy,
2415                                      unsigned ShiftImm,
2416                                      SMLoc S, SMLoc E) {
2417    ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2418    Op->PostIdxReg.RegNum = RegNum;
2419    Op->PostIdxReg.isAdd = isAdd;
2420    Op->PostIdxReg.ShiftTy = ShiftTy;
2421    Op->PostIdxReg.ShiftImm = ShiftImm;
2422    Op->StartLoc = S;
2423    Op->EndLoc = E;
2424    return Op;
2425  }
2426
2427  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2428    ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2429    Op->MBOpt.Val = Opt;
2430    Op->StartLoc = S;
2431    Op->EndLoc = S;
2432    return Op;
2433  }
2434
2435  static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2436                                              SMLoc S) {
2437    ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2438    Op->ISBOpt.Val = Opt;
2439    Op->StartLoc = S;
2440    Op->EndLoc = S;
2441    return Op;
2442  }
2443
2444  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2445    ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2446    Op->IFlags.Val = IFlags;
2447    Op->StartLoc = S;
2448    Op->EndLoc = S;
2449    return Op;
2450  }
2451
2452  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2453    ARMOperand *Op = new ARMOperand(k_MSRMask);
2454    Op->MMask.Val = MMask;
2455    Op->StartLoc = S;
2456    Op->EndLoc = S;
2457    return Op;
2458  }
2459};
2460
2461} // end anonymous namespace.
2462
2463void ARMOperand::print(raw_ostream &OS) const {
2464  switch (Kind) {
2465  case k_CondCode:
2466    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2467    break;
2468  case k_CCOut:
2469    OS << "<ccout " << getReg() << ">";
2470    break;
2471  case k_ITCondMask: {
2472    static const char *const MaskStr[] = {
2473      "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2474      "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2475    };
2476    assert((ITMask.Mask & 0xf) == ITMask.Mask);
2477    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2478    break;
2479  }
2480  case k_CoprocNum:
2481    OS << "<coprocessor number: " << getCoproc() << ">";
2482    break;
2483  case k_CoprocReg:
2484    OS << "<coprocessor register: " << getCoproc() << ">";
2485    break;
2486  case k_CoprocOption:
2487    OS << "<coprocessor option: " << CoprocOption.Val << ">";
2488    break;
2489  case k_MSRMask:
2490    OS << "<mask: " << getMSRMask() << ">";
2491    break;
2492  case k_Immediate:
2493    getImm()->print(OS);
2494    break;
2495  case k_MemBarrierOpt:
2496    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2497    break;
2498  case k_InstSyncBarrierOpt:
2499    OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2500    break;
2501  case k_Memory:
2502    OS << "<memory "
2503       << " base:" << Memory.BaseRegNum;
2504    OS << ">";
2505    break;
2506  case k_PostIndexRegister:
2507    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2508       << PostIdxReg.RegNum;
2509    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2510      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2511         << PostIdxReg.ShiftImm;
2512    OS << ">";
2513    break;
2514  case k_ProcIFlags: {
2515    OS << "<ARM_PROC::";
2516    unsigned IFlags = getProcIFlags();
2517    for (int i=2; i >= 0; --i)
2518      if (IFlags & (1 << i))
2519        OS << ARM_PROC::IFlagsToString(1 << i);
2520    OS << ">";
2521    break;
2522  }
2523  case k_Register:
2524    OS << "<register " << getReg() << ">";
2525    break;
2526  case k_ShifterImmediate:
2527    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2528       << " #" << ShifterImm.Imm << ">";
2529    break;
2530  case k_ShiftedRegister:
2531    OS << "<so_reg_reg "
2532       << RegShiftedReg.SrcReg << " "
2533       << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2534       << " " << RegShiftedReg.ShiftReg << ">";
2535    break;
2536  case k_ShiftedImmediate:
2537    OS << "<so_reg_imm "
2538       << RegShiftedImm.SrcReg << " "
2539       << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2540       << " #" << RegShiftedImm.ShiftImm << ">";
2541    break;
2542  case k_RotateImmediate:
2543    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2544    break;
2545  case k_BitfieldDescriptor:
2546    OS << "<bitfield " << "lsb: " << Bitfield.LSB
2547       << ", width: " << Bitfield.Width << ">";
2548    break;
2549  case k_RegisterList:
2550  case k_DPRRegisterList:
2551  case k_SPRRegisterList: {
2552    OS << "<register_list ";
2553
2554    const SmallVectorImpl<unsigned> &RegList = getRegList();
2555    for (SmallVectorImpl<unsigned>::const_iterator
2556           I = RegList.begin(), E = RegList.end(); I != E; ) {
2557      OS << *I;
2558      if (++I < E) OS << ", ";
2559    }
2560
2561    OS << ">";
2562    break;
2563  }
2564  case k_VectorList:
2565    OS << "<vector_list " << VectorList.Count << " * "
2566       << VectorList.RegNum << ">";
2567    break;
2568  case k_VectorListAllLanes:
2569    OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2570       << VectorList.RegNum << ">";
2571    break;
2572  case k_VectorListIndexed:
2573    OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2574       << VectorList.Count << " * " << VectorList.RegNum << ">";
2575    break;
2576  case k_Token:
2577    OS << "'" << getToken() << "'";
2578    break;
2579  case k_VectorIndex:
2580    OS << "<vectorindex " << getVectorIndex() << ">";
2581    break;
2582  }
2583}
2584
2585/// @name Auto-generated Match Functions
2586/// {
2587
2588static unsigned MatchRegisterName(StringRef Name);
2589
2590/// }
2591
2592bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2593                                 SMLoc &StartLoc, SMLoc &EndLoc) {
2594  StartLoc = Parser.getTok().getLoc();
2595  EndLoc = Parser.getTok().getEndLoc();
2596  RegNo = tryParseRegister();
2597
2598  return (RegNo == (unsigned)-1);
2599}
2600
2601/// Try to parse a register name.  The token must be an Identifier when called,
2602/// and if it is a register name the token is eaten and the register number is
2603/// returned.  Otherwise return -1.
2604///
2605int ARMAsmParser::tryParseRegister() {
2606  const AsmToken &Tok = Parser.getTok();
2607  if (Tok.isNot(AsmToken::Identifier)) return -1;
2608
2609  std::string lowerCase = Tok.getString().lower();
2610  unsigned RegNum = MatchRegisterName(lowerCase);
2611  if (!RegNum) {
2612    RegNum = StringSwitch<unsigned>(lowerCase)
2613      .Case("r13", ARM::SP)
2614      .Case("r14", ARM::LR)
2615      .Case("r15", ARM::PC)
2616      .Case("ip", ARM::R12)
2617      // Additional register name aliases for 'gas' compatibility.
2618      .Case("a1", ARM::R0)
2619      .Case("a2", ARM::R1)
2620      .Case("a3", ARM::R2)
2621      .Case("a4", ARM::R3)
2622      .Case("v1", ARM::R4)
2623      .Case("v2", ARM::R5)
2624      .Case("v3", ARM::R6)
2625      .Case("v4", ARM::R7)
2626      .Case("v5", ARM::R8)
2627      .Case("v6", ARM::R9)
2628      .Case("v7", ARM::R10)
2629      .Case("v8", ARM::R11)
2630      .Case("sb", ARM::R9)
2631      .Case("sl", ARM::R10)
2632      .Case("fp", ARM::R11)
2633      .Default(0);
2634  }
2635  if (!RegNum) {
2636    // Check for aliases registered via .req. Canonicalize to lower case.
2637    // That's more consistent since register names are case insensitive, and
2638    // it's how the original entry was passed in from MC/MCParser/AsmParser.
2639    StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2640    // If no match, return failure.
2641    if (Entry == RegisterReqs.end())
2642      return -1;
2643    Parser.Lex(); // Eat identifier token.
2644    return Entry->getValue();
2645  }
2646
2647  Parser.Lex(); // Eat identifier token.
2648
2649  return RegNum;
2650}
2651
2652// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2653// If a recoverable error occurs, return 1. If an irrecoverable error
2654// occurs, return -1. An irrecoverable error is one where tokens have been
2655// consumed in the process of trying to parse the shifter (i.e., when it is
2656// indeed a shifter operand, but malformed).
2657int ARMAsmParser::tryParseShiftRegister(
2658                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2659  SMLoc S = Parser.getTok().getLoc();
2660  const AsmToken &Tok = Parser.getTok();
2661  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2662
2663  std::string lowerCase = Tok.getString().lower();
2664  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2665      .Case("asl", ARM_AM::lsl)
2666      .Case("lsl", ARM_AM::lsl)
2667      .Case("lsr", ARM_AM::lsr)
2668      .Case("asr", ARM_AM::asr)
2669      .Case("ror", ARM_AM::ror)
2670      .Case("rrx", ARM_AM::rrx)
2671      .Default(ARM_AM::no_shift);
2672
2673  if (ShiftTy == ARM_AM::no_shift)
2674    return 1;
2675
2676  Parser.Lex(); // Eat the operator.
2677
2678  // The source register for the shift has already been added to the
2679  // operand list, so we need to pop it off and combine it into the shifted
2680  // register operand instead.
2681  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2682  if (!PrevOp->isReg())
2683    return Error(PrevOp->getStartLoc(), "shift must be of a register");
2684  int SrcReg = PrevOp->getReg();
2685
2686  SMLoc EndLoc;
2687  int64_t Imm = 0;
2688  int ShiftReg = 0;
2689  if (ShiftTy == ARM_AM::rrx) {
2690    // RRX Doesn't have an explicit shift amount. The encoder expects
2691    // the shift register to be the same as the source register. Seems odd,
2692    // but OK.
2693    ShiftReg = SrcReg;
2694  } else {
2695    // Figure out if this is shifted by a constant or a register (for non-RRX).
2696    if (Parser.getTok().is(AsmToken::Hash) ||
2697        Parser.getTok().is(AsmToken::Dollar)) {
2698      Parser.Lex(); // Eat hash.
2699      SMLoc ImmLoc = Parser.getTok().getLoc();
2700      const MCExpr *ShiftExpr = 0;
2701      if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2702        Error(ImmLoc, "invalid immediate shift value");
2703        return -1;
2704      }
2705      // The expression must be evaluatable as an immediate.
2706      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2707      if (!CE) {
2708        Error(ImmLoc, "invalid immediate shift value");
2709        return -1;
2710      }
2711      // Range check the immediate.
2712      // lsl, ror: 0 <= imm <= 31
2713      // lsr, asr: 0 <= imm <= 32
2714      Imm = CE->getValue();
2715      if (Imm < 0 ||
2716          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2717          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2718        Error(ImmLoc, "immediate shift value out of range");
2719        return -1;
2720      }
2721      // shift by zero is a nop. Always send it through as lsl.
2722      // ('as' compatibility)
2723      if (Imm == 0)
2724        ShiftTy = ARM_AM::lsl;
2725    } else if (Parser.getTok().is(AsmToken::Identifier)) {
2726      SMLoc L = Parser.getTok().getLoc();
2727      EndLoc = Parser.getTok().getEndLoc();
2728      ShiftReg = tryParseRegister();
2729      if (ShiftReg == -1) {
2730        Error (L, "expected immediate or register in shift operand");
2731        return -1;
2732      }
2733    } else {
2734      Error (Parser.getTok().getLoc(),
2735                    "expected immediate or register in shift operand");
2736      return -1;
2737    }
2738  }
2739
2740  if (ShiftReg && ShiftTy != ARM_AM::rrx)
2741    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2742                                                         ShiftReg, Imm,
2743                                                         S, EndLoc));
2744  else
2745    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2746                                                          S, EndLoc));
2747
2748  return 0;
2749}
2750
2751
2752/// Try to parse a register name.  The token must be an Identifier when called.
2753/// If it's a register, an AsmOperand is created. Another AsmOperand is created
2754/// if there is a "writeback". 'true' if it's not a register.
2755///
2756/// TODO this is likely to change to allow different register types and or to
2757/// parse for a specific register type.
2758bool ARMAsmParser::
2759tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2760  const AsmToken &RegTok = Parser.getTok();
2761  int RegNo = tryParseRegister();
2762  if (RegNo == -1)
2763    return true;
2764
2765  Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2766                                           RegTok.getEndLoc()));
2767
2768  const AsmToken &ExclaimTok = Parser.getTok();
2769  if (ExclaimTok.is(AsmToken::Exclaim)) {
2770    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2771                                               ExclaimTok.getLoc()));
2772    Parser.Lex(); // Eat exclaim token
2773    return false;
2774  }
2775
2776  // Also check for an index operand. This is only legal for vector registers,
2777  // but that'll get caught OK in operand matching, so we don't need to
2778  // explicitly filter everything else out here.
2779  if (Parser.getTok().is(AsmToken::LBrac)) {
2780    SMLoc SIdx = Parser.getTok().getLoc();
2781    Parser.Lex(); // Eat left bracket token.
2782
2783    const MCExpr *ImmVal;
2784    if (getParser().parseExpression(ImmVal))
2785      return true;
2786    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2787    if (!MCE)
2788      return TokError("immediate value expected for vector index");
2789
2790    if (Parser.getTok().isNot(AsmToken::RBrac))
2791      return Error(Parser.getTok().getLoc(), "']' expected");
2792
2793    SMLoc E = Parser.getTok().getEndLoc();
2794    Parser.Lex(); // Eat right bracket token.
2795
2796    Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2797                                                     SIdx, E,
2798                                                     getContext()));
2799  }
2800
2801  return false;
2802}
2803
2804/// MatchCoprocessorOperandName - Try to parse an coprocessor related
2805/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2806/// "c5", ...
2807static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2808  // Use the same layout as the tablegen'erated register name matcher. Ugly,
2809  // but efficient.
2810  switch (Name.size()) {
2811  default: return -1;
2812  case 2:
2813    if (Name[0] != CoprocOp)
2814      return -1;
2815    switch (Name[1]) {
2816    default:  return -1;
2817    case '0': return 0;
2818    case '1': return 1;
2819    case '2': return 2;
2820    case '3': return 3;
2821    case '4': return 4;
2822    case '5': return 5;
2823    case '6': return 6;
2824    case '7': return 7;
2825    case '8': return 8;
2826    case '9': return 9;
2827    }
2828  case 3:
2829    if (Name[0] != CoprocOp || Name[1] != '1')
2830      return -1;
2831    switch (Name[2]) {
2832    default:  return -1;
2833    case '0': return 10;
2834    case '1': return 11;
2835    case '2': return 12;
2836    case '3': return 13;
2837    case '4': return 14;
2838    case '5': return 15;
2839    }
2840  }
2841}
2842
2843/// parseITCondCode - Try to parse a condition code for an IT instruction.
2844ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2845parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2846  SMLoc S = Parser.getTok().getLoc();
2847  const AsmToken &Tok = Parser.getTok();
2848  if (!Tok.is(AsmToken::Identifier))
2849    return MatchOperand_NoMatch;
2850  unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2851    .Case("eq", ARMCC::EQ)
2852    .Case("ne", ARMCC::NE)
2853    .Case("hs", ARMCC::HS)
2854    .Case("cs", ARMCC::HS)
2855    .Case("lo", ARMCC::LO)
2856    .Case("cc", ARMCC::LO)
2857    .Case("mi", ARMCC::MI)
2858    .Case("pl", ARMCC::PL)
2859    .Case("vs", ARMCC::VS)
2860    .Case("vc", ARMCC::VC)
2861    .Case("hi", ARMCC::HI)
2862    .Case("ls", ARMCC::LS)
2863    .Case("ge", ARMCC::GE)
2864    .Case("lt", ARMCC::LT)
2865    .Case("gt", ARMCC::GT)
2866    .Case("le", ARMCC::LE)
2867    .Case("al", ARMCC::AL)
2868    .Default(~0U);
2869  if (CC == ~0U)
2870    return MatchOperand_NoMatch;
2871  Parser.Lex(); // Eat the token.
2872
2873  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2874
2875  return MatchOperand_Success;
2876}
2877
2878/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2879/// token must be an Identifier when called, and if it is a coprocessor
2880/// number, the token is eaten and the operand is added to the operand list.
2881ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2882parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2883  SMLoc S = Parser.getTok().getLoc();
2884  const AsmToken &Tok = Parser.getTok();
2885  if (Tok.isNot(AsmToken::Identifier))
2886    return MatchOperand_NoMatch;
2887
2888  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2889  if (Num == -1)
2890    return MatchOperand_NoMatch;
2891
2892  Parser.Lex(); // Eat identifier token.
2893  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2894  return MatchOperand_Success;
2895}
2896
2897/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2898/// token must be an Identifier when called, and if it is a coprocessor
2899/// number, the token is eaten and the operand is added to the operand list.
2900ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2901parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2902  SMLoc S = Parser.getTok().getLoc();
2903  const AsmToken &Tok = Parser.getTok();
2904  if (Tok.isNot(AsmToken::Identifier))
2905    return MatchOperand_NoMatch;
2906
2907  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2908  if (Reg == -1)
2909    return MatchOperand_NoMatch;
2910
2911  Parser.Lex(); // Eat identifier token.
2912  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2913  return MatchOperand_Success;
2914}
2915
2916/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2917/// coproc_option : '{' imm0_255 '}'
2918ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2919parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2920  SMLoc S = Parser.getTok().getLoc();
2921
2922  // If this isn't a '{', this isn't a coprocessor immediate operand.
2923  if (Parser.getTok().isNot(AsmToken::LCurly))
2924    return MatchOperand_NoMatch;
2925  Parser.Lex(); // Eat the '{'
2926
2927  const MCExpr *Expr;
2928  SMLoc Loc = Parser.getTok().getLoc();
2929  if (getParser().parseExpression(Expr)) {
2930    Error(Loc, "illegal expression");
2931    return MatchOperand_ParseFail;
2932  }
2933  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2934  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2935    Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2936    return MatchOperand_ParseFail;
2937  }
2938  int Val = CE->getValue();
2939
2940  // Check for and consume the closing '}'
2941  if (Parser.getTok().isNot(AsmToken::RCurly))
2942    return MatchOperand_ParseFail;
2943  SMLoc E = Parser.getTok().getEndLoc();
2944  Parser.Lex(); // Eat the '}'
2945
2946  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2947  return MatchOperand_Success;
2948}
2949
2950// For register list parsing, we need to map from raw GPR register numbering
2951// to the enumeration values. The enumeration values aren't sorted by
2952// register number due to our using "sp", "lr" and "pc" as canonical names.
2953static unsigned getNextRegister(unsigned Reg) {
2954  // If this is a GPR, we need to do it manually, otherwise we can rely
2955  // on the sort ordering of the enumeration since the other reg-classes
2956  // are sane.
2957  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2958    return Reg + 1;
2959  switch(Reg) {
2960  default: llvm_unreachable("Invalid GPR number!");
2961  case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
2962  case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
2963  case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
2964  case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
2965  case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
2966  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2967  case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
2968  case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
2969  }
2970}
2971
2972// Return the low-subreg of a given Q register.
2973static unsigned getDRegFromQReg(unsigned QReg) {
2974  switch (QReg) {
2975  default: llvm_unreachable("expected a Q register!");
2976  case ARM::Q0:  return ARM::D0;
2977  case ARM::Q1:  return ARM::D2;
2978  case ARM::Q2:  return ARM::D4;
2979  case ARM::Q3:  return ARM::D6;
2980  case ARM::Q4:  return ARM::D8;
2981  case ARM::Q5:  return ARM::D10;
2982  case ARM::Q6:  return ARM::D12;
2983  case ARM::Q7:  return ARM::D14;
2984  case ARM::Q8:  return ARM::D16;
2985  case ARM::Q9:  return ARM::D18;
2986  case ARM::Q10: return ARM::D20;
2987  case ARM::Q11: return ARM::D22;
2988  case ARM::Q12: return ARM::D24;
2989  case ARM::Q13: return ARM::D26;
2990  case ARM::Q14: return ARM::D28;
2991  case ARM::Q15: return ARM::D30;
2992  }
2993}
2994
2995/// Parse a register list.
2996bool ARMAsmParser::
2997parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2998  assert(Parser.getTok().is(AsmToken::LCurly) &&
2999         "Token is not a Left Curly Brace");
3000  SMLoc S = Parser.getTok().getLoc();
3001  Parser.Lex(); // Eat '{' token.
3002  SMLoc RegLoc = Parser.getTok().getLoc();
3003
3004  // Check the first register in the list to see what register class
3005  // this is a list of.
3006  int Reg = tryParseRegister();
3007  if (Reg == -1)
3008    return Error(RegLoc, "register expected");
3009
3010  // The reglist instructions have at most 16 registers, so reserve
3011  // space for that many.
3012  int EReg = 0;
3013  SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3014
3015  // Allow Q regs and just interpret them as the two D sub-registers.
3016  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3017    Reg = getDRegFromQReg(Reg);
3018    EReg = MRI->getEncodingValue(Reg);
3019    Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3020    ++Reg;
3021  }
3022  const MCRegisterClass *RC;
3023  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3024    RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3025  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3026    RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3027  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3028    RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3029  else
3030    return Error(RegLoc, "invalid register in register list");
3031
3032  // Store the register.
3033  EReg = MRI->getEncodingValue(Reg);
3034  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3035
3036  // This starts immediately after the first register token in the list,
3037  // so we can see either a comma or a minus (range separator) as a legal
3038  // next token.
3039  while (Parser.getTok().is(AsmToken::Comma) ||
3040         Parser.getTok().is(AsmToken::Minus)) {
3041    if (Parser.getTok().is(AsmToken::Minus)) {
3042      Parser.Lex(); // Eat the minus.
3043      SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3044      int EndReg = tryParseRegister();
3045      if (EndReg == -1)
3046        return Error(AfterMinusLoc, "register expected");
3047      // Allow Q regs and just interpret them as the two D sub-registers.
3048      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3049        EndReg = getDRegFromQReg(EndReg) + 1;
3050      // If the register is the same as the start reg, there's nothing
3051      // more to do.
3052      if (Reg == EndReg)
3053        continue;
3054      // The register must be in the same register class as the first.
3055      if (!RC->contains(EndReg))
3056        return Error(AfterMinusLoc, "invalid register in register list");
3057      // Ranges must go from low to high.
3058      if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3059        return Error(AfterMinusLoc, "bad range in register list");
3060
3061      // Add all the registers in the range to the register list.
3062      while (Reg != EndReg) {
3063        Reg = getNextRegister(Reg);
3064        EReg = MRI->getEncodingValue(Reg);
3065        Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3066      }
3067      continue;
3068    }
3069    Parser.Lex(); // Eat the comma.
3070    RegLoc = Parser.getTok().getLoc();
3071    int OldReg = Reg;
3072    const AsmToken RegTok = Parser.getTok();
3073    Reg = tryParseRegister();
3074    if (Reg == -1)
3075      return Error(RegLoc, "register expected");
3076    // Allow Q regs and just interpret them as the two D sub-registers.
3077    bool isQReg = false;
3078    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3079      Reg = getDRegFromQReg(Reg);
3080      isQReg = true;
3081    }
3082    // The register must be in the same register class as the first.
3083    if (!RC->contains(Reg))
3084      return Error(RegLoc, "invalid register in register list");
3085    // List must be monotonically increasing.
3086    if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3087      if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3088        Warning(RegLoc, "register list not in ascending order");
3089      else
3090        return Error(RegLoc, "register list not in ascending order");
3091    }
3092    if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3093      Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3094              ") in register list");
3095      continue;
3096    }
3097    // VFP register lists must also be contiguous.
3098    if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3099        Reg != OldReg + 1)
3100      return Error(RegLoc, "non-contiguous register range");
3101    EReg = MRI->getEncodingValue(Reg);
3102    Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3103    if (isQReg) {
3104      EReg = MRI->getEncodingValue(++Reg);
3105      Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3106    }
3107  }
3108
3109  if (Parser.getTok().isNot(AsmToken::RCurly))
3110    return Error(Parser.getTok().getLoc(), "'}' expected");
3111  SMLoc E = Parser.getTok().getEndLoc();
3112  Parser.Lex(); // Eat '}' token.
3113
3114  // Push the register list operand.
3115  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3116
3117  // The ARM system instruction variants for LDM/STM have a '^' token here.
3118  if (Parser.getTok().is(AsmToken::Caret)) {
3119    Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3120    Parser.Lex(); // Eat '^' token.
3121  }
3122
3123  return false;
3124}
3125
3126// Helper function to parse the lane index for vector lists.
3127ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3128parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3129  Index = 0; // Always return a defined index value.
3130  if (Parser.getTok().is(AsmToken::LBrac)) {
3131    Parser.Lex(); // Eat the '['.
3132    if (Parser.getTok().is(AsmToken::RBrac)) {
3133      // "Dn[]" is the 'all lanes' syntax.
3134      LaneKind = AllLanes;
3135      EndLoc = Parser.getTok().getEndLoc();
3136      Parser.Lex(); // Eat the ']'.
3137      return MatchOperand_Success;
3138    }
3139
3140    // There's an optional '#' token here. Normally there wouldn't be, but
3141    // inline assemble puts one in, and it's friendly to accept that.
3142    if (Parser.getTok().is(AsmToken::Hash))
3143      Parser.Lex(); // Eat '#' or '$'.
3144
3145    const MCExpr *LaneIndex;
3146    SMLoc Loc = Parser.getTok().getLoc();
3147    if (getParser().parseExpression(LaneIndex)) {
3148      Error(Loc, "illegal expression");
3149      return MatchOperand_ParseFail;
3150    }
3151    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3152    if (!CE) {
3153      Error(Loc, "lane index must be empty or an integer");
3154      return MatchOperand_ParseFail;
3155    }
3156    if (Parser.getTok().isNot(AsmToken::RBrac)) {
3157      Error(Parser.getTok().getLoc(), "']' expected");
3158      return MatchOperand_ParseFail;
3159    }
3160    EndLoc = Parser.getTok().getEndLoc();
3161    Parser.Lex(); // Eat the ']'.
3162    int64_t Val = CE->getValue();
3163
3164    // FIXME: Make this range check context sensitive for .8, .16, .32.
3165    if (Val < 0 || Val > 7) {
3166      Error(Parser.getTok().getLoc(), "lane index out of range");
3167      return MatchOperand_ParseFail;
3168    }
3169    Index = Val;
3170    LaneKind = IndexedLane;
3171    return MatchOperand_Success;
3172  }
3173  LaneKind = NoLanes;
3174  return MatchOperand_Success;
3175}
3176
3177// parse a vector register list
3178ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3179parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3180  VectorLaneTy LaneKind;
3181  unsigned LaneIndex;
3182  SMLoc S = Parser.getTok().getLoc();
3183  // As an extension (to match gas), support a plain D register or Q register
3184  // (without encosing curly braces) as a single or double entry list,
3185  // respectively.
3186  if (Parser.getTok().is(AsmToken::Identifier)) {
3187    SMLoc E = Parser.getTok().getEndLoc();
3188    int Reg = tryParseRegister();
3189    if (Reg == -1)
3190      return MatchOperand_NoMatch;
3191    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3192      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3193      if (Res != MatchOperand_Success)
3194        return Res;
3195      switch (LaneKind) {
3196      case NoLanes:
3197        Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3198        break;
3199      case AllLanes:
3200        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3201                                                                S, E));
3202        break;
3203      case IndexedLane:
3204        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3205                                                               LaneIndex,
3206                                                               false, S, E));
3207        break;
3208      }
3209      return MatchOperand_Success;
3210    }
3211    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3212      Reg = getDRegFromQReg(Reg);
3213      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3214      if (Res != MatchOperand_Success)
3215        return Res;
3216      switch (LaneKind) {
3217      case NoLanes:
3218        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3219                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3220        Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3221        break;
3222      case AllLanes:
3223        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3224                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3225        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3226                                                                S, E));
3227        break;
3228      case IndexedLane:
3229        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3230                                                               LaneIndex,
3231                                                               false, S, E));
3232        break;
3233      }
3234      return MatchOperand_Success;
3235    }
3236    Error(S, "vector register expected");
3237    return MatchOperand_ParseFail;
3238  }
3239
3240  if (Parser.getTok().isNot(AsmToken::LCurly))
3241    return MatchOperand_NoMatch;
3242
3243  Parser.Lex(); // Eat '{' token.
3244  SMLoc RegLoc = Parser.getTok().getLoc();
3245
3246  int Reg = tryParseRegister();
3247  if (Reg == -1) {
3248    Error(RegLoc, "register expected");
3249    return MatchOperand_ParseFail;
3250  }
3251  unsigned Count = 1;
3252  int Spacing = 0;
3253  unsigned FirstReg = Reg;
3254  // The list is of D registers, but we also allow Q regs and just interpret
3255  // them as the two D sub-registers.
3256  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3257    FirstReg = Reg = getDRegFromQReg(Reg);
3258    Spacing = 1; // double-spacing requires explicit D registers, otherwise
3259                 // it's ambiguous with four-register single spaced.
3260    ++Reg;
3261    ++Count;
3262  }
3263
3264  SMLoc E;
3265  if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3266    return MatchOperand_ParseFail;
3267
3268  while (Parser.getTok().is(AsmToken::Comma) ||
3269         Parser.getTok().is(AsmToken::Minus)) {
3270    if (Parser.getTok().is(AsmToken::Minus)) {
3271      if (!Spacing)
3272        Spacing = 1; // Register range implies a single spaced list.
3273      else if (Spacing == 2) {
3274        Error(Parser.getTok().getLoc(),
3275              "sequential registers in double spaced list");
3276        return MatchOperand_ParseFail;
3277      }
3278      Parser.Lex(); // Eat the minus.
3279      SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3280      int EndReg = tryParseRegister();
3281      if (EndReg == -1) {
3282        Error(AfterMinusLoc, "register expected");
3283        return MatchOperand_ParseFail;
3284      }
3285      // Allow Q regs and just interpret them as the two D sub-registers.
3286      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3287        EndReg = getDRegFromQReg(EndReg) + 1;
3288      // If the register is the same as the start reg, there's nothing
3289      // more to do.
3290      if (Reg == EndReg)
3291        continue;
3292      // The register must be in the same register class as the first.
3293      if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3294        Error(AfterMinusLoc, "invalid register in register list");
3295        return MatchOperand_ParseFail;
3296      }
3297      // Ranges must go from low to high.
3298      if (Reg > EndReg) {
3299        Error(AfterMinusLoc, "bad range in register list");
3300        return MatchOperand_ParseFail;
3301      }
3302      // Parse the lane specifier if present.
3303      VectorLaneTy NextLaneKind;
3304      unsigned NextLaneIndex;
3305      if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3306          MatchOperand_Success)
3307        return MatchOperand_ParseFail;
3308      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3309        Error(AfterMinusLoc, "mismatched lane index in register list");
3310        return MatchOperand_ParseFail;
3311      }
3312
3313      // Add all the registers in the range to the register list.
3314      Count += EndReg - Reg;
3315      Reg = EndReg;
3316      continue;
3317    }
3318    Parser.Lex(); // Eat the comma.
3319    RegLoc = Parser.getTok().getLoc();
3320    int OldReg = Reg;
3321    Reg = tryParseRegister();
3322    if (Reg == -1) {
3323      Error(RegLoc, "register expected");
3324      return MatchOperand_ParseFail;
3325    }
3326    // vector register lists must be contiguous.
3327    // It's OK to use the enumeration values directly here rather, as the
3328    // VFP register classes have the enum sorted properly.
3329    //
3330    // The list is of D registers, but we also allow Q regs and just interpret
3331    // them as the two D sub-registers.
3332    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3333      if (!Spacing)
3334        Spacing = 1; // Register range implies a single spaced list.
3335      else if (Spacing == 2) {
3336        Error(RegLoc,
3337              "invalid register in double-spaced list (must be 'D' register')");
3338        return MatchOperand_ParseFail;
3339      }
3340      Reg = getDRegFromQReg(Reg);
3341      if (Reg != OldReg + 1) {
3342        Error(RegLoc, "non-contiguous register range");
3343        return MatchOperand_ParseFail;
3344      }
3345      ++Reg;
3346      Count += 2;
3347      // Parse the lane specifier if present.
3348      VectorLaneTy NextLaneKind;
3349      unsigned NextLaneIndex;
3350      SMLoc LaneLoc = Parser.getTok().getLoc();
3351      if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3352          MatchOperand_Success)
3353        return MatchOperand_ParseFail;
3354      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3355        Error(LaneLoc, "mismatched lane index in register list");
3356        return MatchOperand_ParseFail;
3357      }
3358      continue;
3359    }
3360    // Normal D register.
3361    // Figure out the register spacing (single or double) of the list if
3362    // we don't know it already.
3363    if (!Spacing)
3364      Spacing = 1 + (Reg == OldReg + 2);
3365
3366    // Just check that it's contiguous and keep going.
3367    if (Reg != OldReg + Spacing) {
3368      Error(RegLoc, "non-contiguous register range");
3369      return MatchOperand_ParseFail;
3370    }
3371    ++Count;
3372    // Parse the lane specifier if present.
3373    VectorLaneTy NextLaneKind;
3374    unsigned NextLaneIndex;
3375    SMLoc EndLoc = Parser.getTok().getLoc();
3376    if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3377      return MatchOperand_ParseFail;
3378    if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3379      Error(EndLoc, "mismatched lane index in register list");
3380      return MatchOperand_ParseFail;
3381    }
3382  }
3383
3384  if (Parser.getTok().isNot(AsmToken::RCurly)) {
3385    Error(Parser.getTok().getLoc(), "'}' expected");
3386    return MatchOperand_ParseFail;
3387  }
3388  E = Parser.getTok().getEndLoc();
3389  Parser.Lex(); // Eat '}' token.
3390
3391  switch (LaneKind) {
3392  case NoLanes:
3393    // Two-register operands have been converted to the
3394    // composite register classes.
3395    if (Count == 2) {
3396      const MCRegisterClass *RC = (Spacing == 1) ?
3397        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3398        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3399      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3400    }
3401
3402    Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3403                                                    (Spacing == 2), S, E));
3404    break;
3405  case AllLanes:
3406    // Two-register operands have been converted to the
3407    // composite register classes.
3408    if (Count == 2) {
3409      const MCRegisterClass *RC = (Spacing == 1) ?
3410        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3411        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3412      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3413    }
3414    Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3415                                                            (Spacing == 2),
3416                                                            S, E));
3417    break;
3418  case IndexedLane:
3419    Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3420                                                           LaneIndex,
3421                                                           (Spacing == 2),
3422                                                           S, E));
3423    break;
3424  }
3425  return MatchOperand_Success;
3426}
3427
3428/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3429ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3430parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3431  SMLoc S = Parser.getTok().getLoc();
3432  const AsmToken &Tok = Parser.getTok();
3433  unsigned Opt;
3434
3435  if (Tok.is(AsmToken::Identifier)) {
3436    StringRef OptStr = Tok.getString();
3437
3438    Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3439      .Case("sy",    ARM_MB::SY)
3440      .Case("st",    ARM_MB::ST)
3441      .Case("sh",    ARM_MB::ISH)
3442      .Case("ish",   ARM_MB::ISH)
3443      .Case("shst",  ARM_MB::ISHST)
3444      .Case("ishst", ARM_MB::ISHST)
3445      .Case("nsh",   ARM_MB::NSH)
3446      .Case("un",    ARM_MB::NSH)
3447      .Case("nshst", ARM_MB::NSHST)
3448      .Case("unst",  ARM_MB::NSHST)
3449      .Case("osh",   ARM_MB::OSH)
3450      .Case("oshst", ARM_MB::OSHST)
3451      .Default(~0U);
3452
3453    if (Opt == ~0U)
3454      return MatchOperand_NoMatch;
3455
3456    Parser.Lex(); // Eat identifier token.
3457  } else if (Tok.is(AsmToken::Hash) ||
3458             Tok.is(AsmToken::Dollar) ||
3459             Tok.is(AsmToken::Integer)) {
3460    if (Parser.getTok().isNot(AsmToken::Integer))
3461      Parser.Lex(); // Eat '#' or '$'.
3462    SMLoc Loc = Parser.getTok().getLoc();
3463
3464    const MCExpr *MemBarrierID;
3465    if (getParser().parseExpression(MemBarrierID)) {
3466      Error(Loc, "illegal expression");
3467      return MatchOperand_ParseFail;
3468    }
3469
3470    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3471    if (!CE) {
3472      Error(Loc, "constant expression expected");
3473      return MatchOperand_ParseFail;
3474    }
3475
3476    int Val = CE->getValue();
3477    if (Val & ~0xf) {
3478      Error(Loc, "immediate value out of range");
3479      return MatchOperand_ParseFail;
3480    }
3481
3482    Opt = ARM_MB::RESERVED_0 + Val;
3483  } else
3484    return MatchOperand_ParseFail;
3485
3486  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3487  return MatchOperand_Success;
3488}
3489
3490/// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3491ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3492parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3493  SMLoc S = Parser.getTok().getLoc();
3494  const AsmToken &Tok = Parser.getTok();
3495  unsigned Opt;
3496
3497  if (Tok.is(AsmToken::Identifier)) {
3498    StringRef OptStr = Tok.getString();
3499
3500    if (OptStr.lower() == "sy")
3501      Opt = ARM_ISB::SY;
3502    else
3503      return MatchOperand_NoMatch;
3504
3505    Parser.Lex(); // Eat identifier token.
3506  } else if (Tok.is(AsmToken::Hash) ||
3507             Tok.is(AsmToken::Dollar) ||
3508             Tok.is(AsmToken::Integer)) {
3509    if (Parser.getTok().isNot(AsmToken::Integer))
3510      Parser.Lex(); // Eat '#' or '$'.
3511    SMLoc Loc = Parser.getTok().getLoc();
3512
3513    const MCExpr *ISBarrierID;
3514    if (getParser().parseExpression(ISBarrierID)) {
3515      Error(Loc, "illegal expression");
3516      return MatchOperand_ParseFail;
3517    }
3518
3519    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3520    if (!CE) {
3521      Error(Loc, "constant expression expected");
3522      return MatchOperand_ParseFail;
3523    }
3524
3525    int Val = CE->getValue();
3526    if (Val & ~0xf) {
3527      Error(Loc, "immediate value out of range");
3528      return MatchOperand_ParseFail;
3529    }
3530
3531    Opt = ARM_ISB::RESERVED_0 + Val;
3532  } else
3533    return MatchOperand_ParseFail;
3534
3535  Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3536          (ARM_ISB::InstSyncBOpt)Opt, S));
3537  return MatchOperand_Success;
3538}
3539
3540
3541/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3542ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3543parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3544  SMLoc S = Parser.getTok().getLoc();
3545  const AsmToken &Tok = Parser.getTok();
3546  if (!Tok.is(AsmToken::Identifier))
3547    return MatchOperand_NoMatch;
3548  StringRef IFlagsStr = Tok.getString();
3549
3550  // An iflags string of "none" is interpreted to mean that none of the AIF
3551  // bits are set.  Not a terribly useful instruction, but a valid encoding.
3552  unsigned IFlags = 0;
3553  if (IFlagsStr != "none") {
3554        for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3555      unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3556        .Case("a", ARM_PROC::A)
3557        .Case("i", ARM_PROC::I)
3558        .Case("f", ARM_PROC::F)
3559        .Default(~0U);
3560
3561      // If some specific iflag is already set, it means that some letter is
3562      // present more than once, this is not acceptable.
3563      if (Flag == ~0U || (IFlags & Flag))
3564        return MatchOperand_NoMatch;
3565
3566      IFlags |= Flag;
3567    }
3568  }
3569
3570  Parser.Lex(); // Eat identifier token.
3571  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3572  return MatchOperand_Success;
3573}
3574
3575/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3576ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3577parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3578  SMLoc S = Parser.getTok().getLoc();
3579  const AsmToken &Tok = Parser.getTok();
3580  if (!Tok.is(AsmToken::Identifier))
3581    return MatchOperand_NoMatch;
3582  StringRef Mask = Tok.getString();
3583
3584  if (isMClass()) {
3585    // See ARMv6-M 10.1.1
3586    std::string Name = Mask.lower();
3587    unsigned FlagsVal = StringSwitch<unsigned>(Name)
3588      // Note: in the documentation:
3589      //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3590      //  for MSR APSR_nzcvq.
3591      // but we do make it an alias here.  This is so to get the "mask encoding"
3592      // bits correct on MSR APSR writes.
3593      //
3594      // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3595      // should really only be allowed when writing a special register.  Note
3596      // they get dropped in the MRS instruction reading a special register as
3597      // the SYSm field is only 8 bits.
3598      //
3599      // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3600      // includes the DSP extension but that is not checked.
3601      .Case("apsr", 0x800)
3602      .Case("apsr_nzcvq", 0x800)
3603      .Case("apsr_g", 0x400)
3604      .Case("apsr_nzcvqg", 0xc00)
3605      .Case("iapsr", 0x801)
3606      .Case("iapsr_nzcvq", 0x801)
3607      .Case("iapsr_g", 0x401)
3608      .Case("iapsr_nzcvqg", 0xc01)
3609      .Case("eapsr", 0x802)
3610      .Case("eapsr_nzcvq", 0x802)
3611      .Case("eapsr_g", 0x402)
3612      .Case("eapsr_nzcvqg", 0xc02)
3613      .Case("xpsr", 0x803)
3614      .Case("xpsr_nzcvq", 0x803)
3615      .Case("xpsr_g", 0x403)
3616      .Case("xpsr_nzcvqg", 0xc03)
3617      .Case("ipsr", 0x805)
3618      .Case("epsr", 0x806)
3619      .Case("iepsr", 0x807)
3620      .Case("msp", 0x808)
3621      .Case("psp", 0x809)
3622      .Case("primask", 0x810)
3623      .Case("basepri", 0x811)
3624      .Case("basepri_max", 0x812)
3625      .Case("faultmask", 0x813)
3626      .Case("control", 0x814)
3627      .Default(~0U);
3628
3629    if (FlagsVal == ~0U)
3630      return MatchOperand_NoMatch;
3631
3632    if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3633      // basepri, basepri_max and faultmask only valid for V7m.
3634      return MatchOperand_NoMatch;
3635
3636    Parser.Lex(); // Eat identifier token.
3637    Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3638    return MatchOperand_Success;
3639  }
3640
3641  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3642  size_t Start = 0, Next = Mask.find('_');
3643  StringRef Flags = "";
3644  std::string SpecReg = Mask.slice(Start, Next).lower();
3645  if (Next != StringRef::npos)
3646    Flags = Mask.slice(Next+1, Mask.size());
3647
3648  // FlagsVal contains the complete mask:
3649  // 3-0: Mask
3650  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3651  unsigned FlagsVal = 0;
3652
3653  if (SpecReg == "apsr") {
3654    FlagsVal = StringSwitch<unsigned>(Flags)
3655    .Case("nzcvq",  0x8) // same as CPSR_f
3656    .Case("g",      0x4) // same as CPSR_s
3657    .Case("nzcvqg", 0xc) // same as CPSR_fs
3658    .Default(~0U);
3659
3660    if (FlagsVal == ~0U) {
3661      if (!Flags.empty())
3662        return MatchOperand_NoMatch;
3663      else
3664        FlagsVal = 8; // No flag
3665    }
3666  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3667    // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3668    if (Flags == "all" || Flags == "")
3669      Flags = "fc";
3670    for (int i = 0, e = Flags.size(); i != e; ++i) {
3671      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3672      .Case("c", 1)
3673      .Case("x", 2)
3674      .Case("s", 4)
3675      .Case("f", 8)
3676      .Default(~0U);
3677
3678      // If some specific flag is already set, it means that some letter is
3679      // present more than once, this is not acceptable.
3680      if (FlagsVal == ~0U || (FlagsVal & Flag))
3681        return MatchOperand_NoMatch;
3682      FlagsVal |= Flag;
3683    }
3684  } else // No match for special register.
3685    return MatchOperand_NoMatch;
3686
3687  // Special register without flags is NOT equivalent to "fc" flags.
3688  // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
3689  // two lines would enable gas compatibility at the expense of breaking
3690  // round-tripping.
3691  //
3692  // if (!FlagsVal)
3693  //  FlagsVal = 0x9;
3694
3695  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3696  if (SpecReg == "spsr")
3697    FlagsVal |= 16;
3698
3699  Parser.Lex(); // Eat identifier token.
3700  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3701  return MatchOperand_Success;
3702}
3703
3704ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3705parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3706            int Low, int High) {
3707  const AsmToken &Tok = Parser.getTok();
3708  if (Tok.isNot(AsmToken::Identifier)) {
3709    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3710    return MatchOperand_ParseFail;
3711  }
3712  StringRef ShiftName = Tok.getString();
3713  std::string LowerOp = Op.lower();
3714  std::string UpperOp = Op.upper();
3715  if (ShiftName != LowerOp && ShiftName != UpperOp) {
3716    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3717    return MatchOperand_ParseFail;
3718  }
3719  Parser.Lex(); // Eat shift type token.
3720
3721  // There must be a '#' and a shift amount.
3722  if (Parser.getTok().isNot(AsmToken::Hash) &&
3723      Parser.getTok().isNot(AsmToken::Dollar)) {
3724    Error(Parser.getTok().getLoc(), "'#' expected");
3725    return MatchOperand_ParseFail;
3726  }
3727  Parser.Lex(); // Eat hash token.
3728
3729  const MCExpr *ShiftAmount;
3730  SMLoc Loc = Parser.getTok().getLoc();
3731  SMLoc EndLoc;
3732  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3733    Error(Loc, "illegal expression");
3734    return MatchOperand_ParseFail;
3735  }
3736  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3737  if (!CE) {
3738    Error(Loc, "constant expression expected");
3739    return MatchOperand_ParseFail;
3740  }
3741  int Val = CE->getValue();
3742  if (Val < Low || Val > High) {
3743    Error(Loc, "immediate value out of range");
3744    return MatchOperand_ParseFail;
3745  }
3746
3747  Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3748
3749  return MatchOperand_Success;
3750}
3751
3752ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3753parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3754  const AsmToken &Tok = Parser.getTok();
3755  SMLoc S = Tok.getLoc();
3756  if (Tok.isNot(AsmToken::Identifier)) {
3757    Error(S, "'be' or 'le' operand expected");
3758    return MatchOperand_ParseFail;
3759  }
3760  int Val = StringSwitch<int>(Tok.getString().lower())
3761    .Case("be", 1)
3762    .Case("le", 0)
3763    .Default(-1);
3764  Parser.Lex(); // Eat the token.
3765
3766  if (Val == -1) {
3767    Error(S, "'be' or 'le' operand expected");
3768    return MatchOperand_ParseFail;
3769  }
3770  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3771                                                                  getContext()),
3772                                           S, Tok.getEndLoc()));
3773  return MatchOperand_Success;
3774}
3775
3776/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3777/// instructions. Legal values are:
3778///     lsl #n  'n' in [0,31]
3779///     asr #n  'n' in [1,32]
3780///             n == 32 encoded as n == 0.
3781ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3782parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3783  const AsmToken &Tok = Parser.getTok();
3784  SMLoc S = Tok.getLoc();
3785  if (Tok.isNot(AsmToken::Identifier)) {
3786    Error(S, "shift operator 'asr' or 'lsl' expected");
3787    return MatchOperand_ParseFail;
3788  }
3789  StringRef ShiftName = Tok.getString();
3790  bool isASR;
3791  if (ShiftName == "lsl" || ShiftName == "LSL")
3792    isASR = false;
3793  else if (ShiftName == "asr" || ShiftName == "ASR")
3794    isASR = true;
3795  else {
3796    Error(S, "shift operator 'asr' or 'lsl' expected");
3797    return MatchOperand_ParseFail;
3798  }
3799  Parser.Lex(); // Eat the operator.
3800
3801  // A '#' and a shift amount.
3802  if (Parser.getTok().isNot(AsmToken::Hash) &&
3803      Parser.getTok().isNot(AsmToken::Dollar)) {
3804    Error(Parser.getTok().getLoc(), "'#' expected");
3805    return MatchOperand_ParseFail;
3806  }
3807  Parser.Lex(); // Eat hash token.
3808  SMLoc ExLoc = Parser.getTok().getLoc();
3809
3810  const MCExpr *ShiftAmount;
3811  SMLoc EndLoc;
3812  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3813    Error(ExLoc, "malformed shift expression");
3814    return MatchOperand_ParseFail;
3815  }
3816  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3817  if (!CE) {
3818    Error(ExLoc, "shift amount must be an immediate");
3819    return MatchOperand_ParseFail;
3820  }
3821
3822  int64_t Val = CE->getValue();
3823  if (isASR) {
3824    // Shift amount must be in [1,32]
3825    if (Val < 1 || Val > 32) {
3826      Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3827      return MatchOperand_ParseFail;
3828    }
3829    // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3830    if (isThumb() && Val == 32) {
3831      Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3832      return MatchOperand_ParseFail;
3833    }
3834    if (Val == 32) Val = 0;
3835  } else {
3836    // Shift amount must be in [1,32]
3837    if (Val < 0 || Val > 31) {
3838      Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3839      return MatchOperand_ParseFail;
3840    }
3841  }
3842
3843  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3844
3845  return MatchOperand_Success;
3846}
3847
3848/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3849/// of instructions. Legal values are:
3850///     ror #n  'n' in {0, 8, 16, 24}
3851ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3852parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3853  const AsmToken &Tok = Parser.getTok();
3854  SMLoc S = Tok.getLoc();
3855  if (Tok.isNot(AsmToken::Identifier))
3856    return MatchOperand_NoMatch;
3857  StringRef ShiftName = Tok.getString();
3858  if (ShiftName != "ror" && ShiftName != "ROR")
3859    return MatchOperand_NoMatch;
3860  Parser.Lex(); // Eat the operator.
3861
3862  // A '#' and a rotate amount.
3863  if (Parser.getTok().isNot(AsmToken::Hash) &&
3864      Parser.getTok().isNot(AsmToken::Dollar)) {
3865    Error(Parser.getTok().getLoc(), "'#' expected");
3866    return MatchOperand_ParseFail;
3867  }
3868  Parser.Lex(); // Eat hash token.
3869  SMLoc ExLoc = Parser.getTok().getLoc();
3870
3871  const MCExpr *ShiftAmount;
3872  SMLoc EndLoc;
3873  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3874    Error(ExLoc, "malformed rotate expression");
3875    return MatchOperand_ParseFail;
3876  }
3877  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3878  if (!CE) {
3879    Error(ExLoc, "rotate amount must be an immediate");
3880    return MatchOperand_ParseFail;
3881  }
3882
3883  int64_t Val = CE->getValue();
3884  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3885  // normally, zero is represented in asm by omitting the rotate operand
3886  // entirely.
3887  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3888    Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
3889    return MatchOperand_ParseFail;
3890  }
3891
3892  Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
3893
3894  return MatchOperand_Success;
3895}
3896
3897ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3898parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3899  SMLoc S = Parser.getTok().getLoc();
3900  // The bitfield descriptor is really two operands, the LSB and the width.
3901  if (Parser.getTok().isNot(AsmToken::Hash) &&
3902      Parser.getTok().isNot(AsmToken::Dollar)) {
3903    Error(Parser.getTok().getLoc(), "'#' expected");
3904    return MatchOperand_ParseFail;
3905  }
3906  Parser.Lex(); // Eat hash token.
3907
3908  const MCExpr *LSBExpr;
3909  SMLoc E = Parser.getTok().getLoc();
3910  if (getParser().parseExpression(LSBExpr)) {
3911    Error(E, "malformed immediate expression");
3912    return MatchOperand_ParseFail;
3913  }
3914  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3915  if (!CE) {
3916    Error(E, "'lsb' operand must be an immediate");
3917    return MatchOperand_ParseFail;
3918  }
3919
3920  int64_t LSB = CE->getValue();
3921  // The LSB must be in the range [0,31]
3922  if (LSB < 0 || LSB > 31) {
3923    Error(E, "'lsb' operand must be in the range [0,31]");
3924    return MatchOperand_ParseFail;
3925  }
3926  E = Parser.getTok().getLoc();
3927
3928  // Expect another immediate operand.
3929  if (Parser.getTok().isNot(AsmToken::Comma)) {
3930    Error(Parser.getTok().getLoc(), "too few operands");
3931    return MatchOperand_ParseFail;
3932  }
3933  Parser.Lex(); // Eat hash token.
3934  if (Parser.getTok().isNot(AsmToken::Hash) &&
3935      Parser.getTok().isNot(AsmToken::Dollar)) {
3936    Error(Parser.getTok().getLoc(), "'#' expected");
3937    return MatchOperand_ParseFail;
3938  }
3939  Parser.Lex(); // Eat hash token.
3940
3941  const MCExpr *WidthExpr;
3942  SMLoc EndLoc;
3943  if (getParser().parseExpression(WidthExpr, EndLoc)) {
3944    Error(E, "malformed immediate expression");
3945    return MatchOperand_ParseFail;
3946  }
3947  CE = dyn_cast<MCConstantExpr>(WidthExpr);
3948  if (!CE) {
3949    Error(E, "'width' operand must be an immediate");
3950    return MatchOperand_ParseFail;
3951  }
3952
3953  int64_t Width = CE->getValue();
3954  // The LSB must be in the range [1,32-lsb]
3955  if (Width < 1 || Width > 32 - LSB) {
3956    Error(E, "'width' operand must be in the range [1,32-lsb]");
3957    return MatchOperand_ParseFail;
3958  }
3959
3960  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
3961
3962  return MatchOperand_Success;
3963}
3964
3965ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3966parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3967  // Check for a post-index addressing register operand. Specifically:
3968  // postidx_reg := '+' register {, shift}
3969  //              | '-' register {, shift}
3970  //              | register {, shift}
3971
3972  // This method must return MatchOperand_NoMatch without consuming any tokens
3973  // in the case where there is no match, as other alternatives take other
3974  // parse methods.
3975  AsmToken Tok = Parser.getTok();
3976  SMLoc S = Tok.getLoc();
3977  bool haveEaten = false;
3978  bool isAdd = true;
3979  if (Tok.is(AsmToken::Plus)) {
3980    Parser.Lex(); // Eat the '+' token.
3981    haveEaten = true;
3982  } else if (Tok.is(AsmToken::Minus)) {
3983    Parser.Lex(); // Eat the '-' token.
3984    isAdd = false;
3985    haveEaten = true;
3986  }
3987
3988  SMLoc E = Parser.getTok().getEndLoc();
3989  int Reg = tryParseRegister();
3990  if (Reg == -1) {
3991    if (!haveEaten)
3992      return MatchOperand_NoMatch;
3993    Error(Parser.getTok().getLoc(), "register expected");
3994    return MatchOperand_ParseFail;
3995  }
3996
3997  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3998  unsigned ShiftImm = 0;
3999  if (Parser.getTok().is(AsmToken::Comma)) {
4000    Parser.Lex(); // Eat the ','.
4001    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4002      return MatchOperand_ParseFail;
4003
4004    // FIXME: Only approximates end...may include intervening whitespace.
4005    E = Parser.getTok().getLoc();
4006  }
4007
4008  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4009                                                  ShiftImm, S, E));
4010
4011  return MatchOperand_Success;
4012}
4013
4014ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4015parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4016  // Check for a post-index addressing register operand. Specifically:
4017  // am3offset := '+' register
4018  //              | '-' register
4019  //              | register
4020  //              | # imm
4021  //              | # + imm
4022  //              | # - imm
4023
4024  // This method must return MatchOperand_NoMatch without consuming any tokens
4025  // in the case where there is no match, as other alternatives take other
4026  // parse methods.
4027  AsmToken Tok = Parser.getTok();
4028  SMLoc S = Tok.getLoc();
4029
4030  // Do immediates first, as we always parse those if we have a '#'.
4031  if (Parser.getTok().is(AsmToken::Hash) ||
4032      Parser.getTok().is(AsmToken::Dollar)) {
4033    Parser.Lex(); // Eat '#' or '$'.
4034    // Explicitly look for a '-', as we need to encode negative zero
4035    // differently.
4036    bool isNegative = Parser.getTok().is(AsmToken::Minus);
4037    const MCExpr *Offset;
4038    SMLoc E;
4039    if (getParser().parseExpression(Offset, E))
4040      return MatchOperand_ParseFail;
4041    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4042    if (!CE) {
4043      Error(S, "constant expression expected");
4044      return MatchOperand_ParseFail;
4045    }
4046    // Negative zero is encoded as the flag value INT32_MIN.
4047    int32_t Val = CE->getValue();
4048    if (isNegative && Val == 0)
4049      Val = INT32_MIN;
4050
4051    Operands.push_back(
4052      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4053
4054    return MatchOperand_Success;
4055  }
4056
4057
4058  bool haveEaten = false;
4059  bool isAdd = true;
4060  if (Tok.is(AsmToken::Plus)) {
4061    Parser.Lex(); // Eat the '+' token.
4062    haveEaten = true;
4063  } else if (Tok.is(AsmToken::Minus)) {
4064    Parser.Lex(); // Eat the '-' token.
4065    isAdd = false;
4066    haveEaten = true;
4067  }
4068
4069  Tok = Parser.getTok();
4070  int Reg = tryParseRegister();
4071  if (Reg == -1) {
4072    if (!haveEaten)
4073      return MatchOperand_NoMatch;
4074    Error(Tok.getLoc(), "register expected");
4075    return MatchOperand_ParseFail;
4076  }
4077
4078  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4079                                                  0, S, Tok.getEndLoc()));
4080
4081  return MatchOperand_Success;
4082}
4083
4084/// Convert parsed operands to MCInst.  Needed here because this instruction
4085/// only has two register operands, but multiplication is commutative so
4086/// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4087void ARMAsmParser::
4088cvtThumbMultiply(MCInst &Inst,
4089           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4090  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4091  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4092  // If we have a three-operand form, make sure to set Rn to be the operand
4093  // that isn't the same as Rd.
4094  unsigned RegOp = 4;
4095  if (Operands.size() == 6 &&
4096      ((ARMOperand*)Operands[4])->getReg() ==
4097        ((ARMOperand*)Operands[3])->getReg())
4098    RegOp = 5;
4099  ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4100  Inst.addOperand(Inst.getOperand(0));
4101  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4102}
4103
4104/// Parse an ARM memory expression, return false if successful else return true
4105/// or an error.  The first token must be a '[' when called.
4106bool ARMAsmParser::
4107parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4108  SMLoc S, E;
4109  assert(Parser.getTok().is(AsmToken::LBrac) &&
4110         "Token is not a Left Bracket");
4111  S = Parser.getTok().getLoc();
4112  Parser.Lex(); // Eat left bracket token.
4113
4114  const AsmToken &BaseRegTok = Parser.getTok();
4115  int BaseRegNum = tryParseRegister();
4116  if (BaseRegNum == -1)
4117    return Error(BaseRegTok.getLoc(), "register expected");
4118
4119  // The next token must either be a comma, a colon or a closing bracket.
4120  const AsmToken &Tok = Parser.getTok();
4121  if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4122      !Tok.is(AsmToken::RBrac))
4123    return Error(Tok.getLoc(), "malformed memory operand");
4124
4125  if (Tok.is(AsmToken::RBrac)) {
4126    E = Tok.getEndLoc();
4127    Parser.Lex(); // Eat right bracket token.
4128
4129    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4130                                             0, 0, false, S, E));
4131
4132    // If there's a pre-indexing writeback marker, '!', just add it as a token
4133    // operand. It's rather odd, but syntactically valid.
4134    if (Parser.getTok().is(AsmToken::Exclaim)) {
4135      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4136      Parser.Lex(); // Eat the '!'.
4137    }
4138
4139    return false;
4140  }
4141
4142  assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4143         "Lost colon or comma in memory operand?!");
4144  if (Tok.is(AsmToken::Comma)) {
4145    Parser.Lex(); // Eat the comma.
4146  }
4147
4148  // If we have a ':', it's an alignment specifier.
4149  if (Parser.getTok().is(AsmToken::Colon)) {
4150    Parser.Lex(); // Eat the ':'.
4151    E = Parser.getTok().getLoc();
4152
4153    const MCExpr *Expr;
4154    if (getParser().parseExpression(Expr))
4155     return true;
4156
4157    // The expression has to be a constant. Memory references with relocations
4158    // don't come through here, as they use the <label> forms of the relevant
4159    // instructions.
4160    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4161    if (!CE)
4162      return Error (E, "constant expression expected");
4163
4164    unsigned Align = 0;
4165    switch (CE->getValue()) {
4166    default:
4167      return Error(E,
4168                   "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4169    case 16:  Align = 2; break;
4170    case 32:  Align = 4; break;
4171    case 64:  Align = 8; break;
4172    case 128: Align = 16; break;
4173    case 256: Align = 32; break;
4174    }
4175
4176    // Now we should have the closing ']'
4177    if (Parser.getTok().isNot(AsmToken::RBrac))
4178      return Error(Parser.getTok().getLoc(), "']' expected");
4179    E = Parser.getTok().getEndLoc();
4180    Parser.Lex(); // Eat right bracket token.
4181
4182    // Don't worry about range checking the value here. That's handled by
4183    // the is*() predicates.
4184    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4185                                             ARM_AM::no_shift, 0, Align,
4186                                             false, S, E));
4187
4188    // If there's a pre-indexing writeback marker, '!', just add it as a token
4189    // operand.
4190    if (Parser.getTok().is(AsmToken::Exclaim)) {
4191      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4192      Parser.Lex(); // Eat the '!'.
4193    }
4194
4195    return false;
4196  }
4197
4198  // If we have a '#', it's an immediate offset, else assume it's a register
4199  // offset. Be friendly and also accept a plain integer (without a leading
4200  // hash) for gas compatibility.
4201  if (Parser.getTok().is(AsmToken::Hash) ||
4202      Parser.getTok().is(AsmToken::Dollar) ||
4203      Parser.getTok().is(AsmToken::Integer)) {
4204    if (Parser.getTok().isNot(AsmToken::Integer))
4205      Parser.Lex(); // Eat '#' or '$'.
4206    E = Parser.getTok().getLoc();
4207
4208    bool isNegative = getParser().getTok().is(AsmToken::Minus);
4209    const MCExpr *Offset;
4210    if (getParser().parseExpression(Offset))
4211     return true;
4212
4213    // The expression has to be a constant. Memory references with relocations
4214    // don't come through here, as they use the <label> forms of the relevant
4215    // instructions.
4216    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4217    if (!CE)
4218      return Error (E, "constant expression expected");
4219
4220    // If the constant was #-0, represent it as INT32_MIN.
4221    int32_t Val = CE->getValue();
4222    if (isNegative && Val == 0)
4223      CE = MCConstantExpr::Create(INT32_MIN, getContext());
4224
4225    // Now we should have the closing ']'
4226    if (Parser.getTok().isNot(AsmToken::RBrac))
4227      return Error(Parser.getTok().getLoc(), "']' expected");
4228    E = Parser.getTok().getEndLoc();
4229    Parser.Lex(); // Eat right bracket token.
4230
4231    // Don't worry about range checking the value here. That's handled by
4232    // the is*() predicates.
4233    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4234                                             ARM_AM::no_shift, 0, 0,
4235                                             false, S, E));
4236
4237    // If there's a pre-indexing writeback marker, '!', just add it as a token
4238    // operand.
4239    if (Parser.getTok().is(AsmToken::Exclaim)) {
4240      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4241      Parser.Lex(); // Eat the '!'.
4242    }
4243
4244    return false;
4245  }
4246
4247  // The register offset is optionally preceded by a '+' or '-'
4248  bool isNegative = false;
4249  if (Parser.getTok().is(AsmToken::Minus)) {
4250    isNegative = true;
4251    Parser.Lex(); // Eat the '-'.
4252  } else if (Parser.getTok().is(AsmToken::Plus)) {
4253    // Nothing to do.
4254    Parser.Lex(); // Eat the '+'.
4255  }
4256
4257  E = Parser.getTok().getLoc();
4258  int OffsetRegNum = tryParseRegister();
4259  if (OffsetRegNum == -1)
4260    return Error(E, "register expected");
4261
4262  // If there's a shift operator, handle it.
4263  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4264  unsigned ShiftImm = 0;
4265  if (Parser.getTok().is(AsmToken::Comma)) {
4266    Parser.Lex(); // Eat the ','.
4267    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4268      return true;
4269  }
4270
4271  // Now we should have the closing ']'
4272  if (Parser.getTok().isNot(AsmToken::RBrac))
4273    return Error(Parser.getTok().getLoc(), "']' expected");
4274  E = Parser.getTok().getEndLoc();
4275  Parser.Lex(); // Eat right bracket token.
4276
4277  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4278                                           ShiftType, ShiftImm, 0, isNegative,
4279                                           S, E));
4280
4281  // If there's a pre-indexing writeback marker, '!', just add it as a token
4282  // operand.
4283  if (Parser.getTok().is(AsmToken::Exclaim)) {
4284    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4285    Parser.Lex(); // Eat the '!'.
4286  }
4287
4288  return false;
4289}
4290
4291/// parseMemRegOffsetShift - one of these two:
4292///   ( lsl | lsr | asr | ror ) , # shift_amount
4293///   rrx
4294/// return true if it parses a shift otherwise it returns false.
4295bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4296                                          unsigned &Amount) {
4297  SMLoc Loc = Parser.getTok().getLoc();
4298  const AsmToken &Tok = Parser.getTok();
4299  if (Tok.isNot(AsmToken::Identifier))
4300    return true;
4301  StringRef ShiftName = Tok.getString();
4302  if (ShiftName == "lsl" || ShiftName == "LSL" ||
4303      ShiftName == "asl" || ShiftName == "ASL")
4304    St = ARM_AM::lsl;
4305  else if (ShiftName == "lsr" || ShiftName == "LSR")
4306    St = ARM_AM::lsr;
4307  else if (ShiftName == "asr" || ShiftName == "ASR")
4308    St = ARM_AM::asr;
4309  else if (ShiftName == "ror" || ShiftName == "ROR")
4310    St = ARM_AM::ror;
4311  else if (ShiftName == "rrx" || ShiftName == "RRX")
4312    St = ARM_AM::rrx;
4313  else
4314    return Error(Loc, "illegal shift operator");
4315  Parser.Lex(); // Eat shift type token.
4316
4317  // rrx stands alone.
4318  Amount = 0;
4319  if (St != ARM_AM::rrx) {
4320    Loc = Parser.getTok().getLoc();
4321    // A '#' and a shift amount.
4322    const AsmToken &HashTok = Parser.getTok();
4323    if (HashTok.isNot(AsmToken::Hash) &&
4324        HashTok.isNot(AsmToken::Dollar))
4325      return Error(HashTok.getLoc(), "'#' expected");
4326    Parser.Lex(); // Eat hash token.
4327
4328    const MCExpr *Expr;
4329    if (getParser().parseExpression(Expr))
4330      return true;
4331    // Range check the immediate.
4332    // lsl, ror: 0 <= imm <= 31
4333    // lsr, asr: 0 <= imm <= 32
4334    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4335    if (!CE)
4336      return Error(Loc, "shift amount must be an immediate");
4337    int64_t Imm = CE->getValue();
4338    if (Imm < 0 ||
4339        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4340        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4341      return Error(Loc, "immediate shift value out of range");
4342    // If <ShiftTy> #0, turn it into a no_shift.
4343    if (Imm == 0)
4344      St = ARM_AM::lsl;
4345    // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4346    if (Imm == 32)
4347      Imm = 0;
4348    Amount = Imm;
4349  }
4350
4351  return false;
4352}
4353
4354/// parseFPImm - A floating point immediate expression operand.
4355ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4356parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4357  // Anything that can accept a floating point constant as an operand
4358  // needs to go through here, as the regular parseExpression is
4359  // integer only.
4360  //
4361  // This routine still creates a generic Immediate operand, containing
4362  // a bitcast of the 64-bit floating point value. The various operands
4363  // that accept floats can check whether the value is valid for them
4364  // via the standard is*() predicates.
4365
4366  SMLoc S = Parser.getTok().getLoc();
4367
4368  if (Parser.getTok().isNot(AsmToken::Hash) &&
4369      Parser.getTok().isNot(AsmToken::Dollar))
4370    return MatchOperand_NoMatch;
4371
4372  // Disambiguate the VMOV forms that can accept an FP immediate.
4373  // vmov.f32 <sreg>, #imm
4374  // vmov.f64 <dreg>, #imm
4375  // vmov.f32 <dreg>, #imm  @ vector f32x2
4376  // vmov.f32 <qreg>, #imm  @ vector f32x4
4377  //
4378  // There are also the NEON VMOV instructions which expect an
4379  // integer constant. Make sure we don't try to parse an FPImm
4380  // for these:
4381  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4382  ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4383  if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4384                           TyOp->getToken() != ".f64"))
4385    return MatchOperand_NoMatch;
4386
4387  Parser.Lex(); // Eat '#' or '$'.
4388
4389  // Handle negation, as that still comes through as a separate token.
4390  bool isNegative = false;
4391  if (Parser.getTok().is(AsmToken::Minus)) {
4392    isNegative = true;
4393    Parser.Lex();
4394  }
4395  const AsmToken &Tok = Parser.getTok();
4396  SMLoc Loc = Tok.getLoc();
4397  if (Tok.is(AsmToken::Real)) {
4398    APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4399    uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4400    // If we had a '-' in front, toggle the sign bit.
4401    IntVal ^= (uint64_t)isNegative << 31;
4402    Parser.Lex(); // Eat the token.
4403    Operands.push_back(ARMOperand::CreateImm(
4404          MCConstantExpr::Create(IntVal, getContext()),
4405          S, Parser.getTok().getLoc()));
4406    return MatchOperand_Success;
4407  }
4408  // Also handle plain integers. Instructions which allow floating point
4409  // immediates also allow a raw encoded 8-bit value.
4410  if (Tok.is(AsmToken::Integer)) {
4411    int64_t Val = Tok.getIntVal();
4412    Parser.Lex(); // Eat the token.
4413    if (Val > 255 || Val < 0) {
4414      Error(Loc, "encoded floating point value out of range");
4415      return MatchOperand_ParseFail;
4416    }
4417    double RealVal = ARM_AM::getFPImmFloat(Val);
4418    Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4419    Operands.push_back(ARMOperand::CreateImm(
4420        MCConstantExpr::Create(Val, getContext()), S,
4421        Parser.getTok().getLoc()));
4422    return MatchOperand_Success;
4423  }
4424
4425  Error(Loc, "invalid floating point immediate");
4426  return MatchOperand_ParseFail;
4427}
4428
4429/// Parse a arm instruction operand.  For now this parses the operand regardless
4430/// of the mnemonic.
4431bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4432                                StringRef Mnemonic) {
4433  SMLoc S, E;
4434
4435  // Check if the current operand has a custom associated parser, if so, try to
4436  // custom parse the operand, or fallback to the general approach.
4437  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4438  if (ResTy == MatchOperand_Success)
4439    return false;
4440  // If there wasn't a custom match, try the generic matcher below. Otherwise,
4441  // there was a match, but an error occurred, in which case, just return that
4442  // the operand parsing failed.
4443  if (ResTy == MatchOperand_ParseFail)
4444    return true;
4445
4446  switch (getLexer().getKind()) {
4447  default:
4448    Error(Parser.getTok().getLoc(), "unexpected token in operand");
4449    return true;
4450  case AsmToken::Identifier: {
4451    // If we've seen a branch mnemonic, the next operand must be a label.  This
4452    // is true even if the label is a register name.  So "br r1" means branch to
4453    // label "r1".
4454    bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4455    if (!ExpectLabel) {
4456      if (!tryParseRegisterWithWriteBack(Operands))
4457        return false;
4458      int Res = tryParseShiftRegister(Operands);
4459      if (Res == 0) // success
4460        return false;
4461      else if (Res == -1) // irrecoverable error
4462        return true;
4463      // If this is VMRS, check for the apsr_nzcv operand.
4464      if (Mnemonic == "vmrs" &&
4465          Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4466        S = Parser.getTok().getLoc();
4467        Parser.Lex();
4468        Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4469        return false;
4470      }
4471    }
4472
4473    // Fall though for the Identifier case that is not a register or a
4474    // special name.
4475  }
4476  case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4477  case AsmToken::Integer: // things like 1f and 2b as a branch targets
4478  case AsmToken::String:  // quoted label names.
4479  case AsmToken::Dot: {   // . as a branch target
4480    // This was not a register so parse other operands that start with an
4481    // identifier (like labels) as expressions and create them as immediates.
4482    const MCExpr *IdVal;
4483    S = Parser.getTok().getLoc();
4484    if (getParser().parseExpression(IdVal))
4485      return true;
4486    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4487    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4488    return false;
4489  }
4490  case AsmToken::LBrac:
4491    return parseMemory(Operands);
4492  case AsmToken::LCurly:
4493    return parseRegisterList(Operands);
4494  case AsmToken::Dollar:
4495  case AsmToken::Hash: {
4496    // #42 -> immediate.
4497    S = Parser.getTok().getLoc();
4498    Parser.Lex();
4499
4500    if (Parser.getTok().isNot(AsmToken::Colon)) {
4501      bool isNegative = Parser.getTok().is(AsmToken::Minus);
4502      const MCExpr *ImmVal;
4503      if (getParser().parseExpression(ImmVal))
4504        return true;
4505      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4506      if (CE) {
4507        int32_t Val = CE->getValue();
4508        if (isNegative && Val == 0)
4509          ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4510      }
4511      E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4512      Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4513
4514      // There can be a trailing '!' on operands that we want as a separate
4515      // '!' Token operand. Handle that here. For example, the compatibilty
4516      // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4517      if (Parser.getTok().is(AsmToken::Exclaim)) {
4518        Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4519                                                   Parser.getTok().getLoc()));
4520        Parser.Lex(); // Eat exclaim token
4521      }
4522      return false;
4523    }
4524    // w/ a ':' after the '#', it's just like a plain ':'.
4525    // FALLTHROUGH
4526  }
4527  case AsmToken::Colon: {
4528    // ":lower16:" and ":upper16:" expression prefixes
4529    // FIXME: Check it's an expression prefix,
4530    // e.g. (FOO - :lower16:BAR) isn't legal.
4531    ARMMCExpr::VariantKind RefKind;
4532    if (parsePrefix(RefKind))
4533      return true;
4534
4535    const MCExpr *SubExprVal;
4536    if (getParser().parseExpression(SubExprVal))
4537      return true;
4538
4539    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4540                                              getContext());
4541    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4542    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4543    return false;
4544  }
4545  }
4546}
4547
4548// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4549//  :lower16: and :upper16:.
4550bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4551  RefKind = ARMMCExpr::VK_ARM_None;
4552
4553  // :lower16: and :upper16: modifiers
4554  assert(getLexer().is(AsmToken::Colon) && "expected a :");
4555  Parser.Lex(); // Eat ':'
4556
4557  if (getLexer().isNot(AsmToken::Identifier)) {
4558    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4559    return true;
4560  }
4561
4562  StringRef IDVal = Parser.getTok().getIdentifier();
4563  if (IDVal == "lower16") {
4564    RefKind = ARMMCExpr::VK_ARM_LO16;
4565  } else if (IDVal == "upper16") {
4566    RefKind = ARMMCExpr::VK_ARM_HI16;
4567  } else {
4568    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4569    return true;
4570  }
4571  Parser.Lex();
4572
4573  if (getLexer().isNot(AsmToken::Colon)) {
4574    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4575    return true;
4576  }
4577  Parser.Lex(); // Eat the last ':'
4578  return false;
4579}
4580
4581/// \brief Given a mnemonic, split out possible predication code and carry
4582/// setting letters to form a canonical mnemonic and flags.
4583//
4584// FIXME: Would be nice to autogen this.
4585// FIXME: This is a bit of a maze of special cases.
4586StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4587                                      unsigned &PredicationCode,
4588                                      bool &CarrySetting,
4589                                      unsigned &ProcessorIMod,
4590                                      StringRef &ITMask) {
4591  PredicationCode = ARMCC::AL;
4592  CarrySetting = false;
4593  ProcessorIMod = 0;
4594
4595  // Ignore some mnemonics we know aren't predicated forms.
4596  //
4597  // FIXME: Would be nice to autogen this.
4598  if ((Mnemonic == "movs" && isThumb()) ||
4599      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
4600      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
4601      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
4602      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
4603      Mnemonic == "vaclt" || Mnemonic == "vacle"  ||
4604      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
4605      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
4606      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4607      Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4608      Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
4609      Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4610      Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4611    return Mnemonic;
4612
4613  // First, split out any predication code. Ignore mnemonics we know aren't
4614  // predicated but do have a carry-set and so weren't caught above.
4615  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4616      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4617      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4618      Mnemonic != "sbcs" && Mnemonic != "rscs") {
4619    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4620      .Case("eq", ARMCC::EQ)
4621      .Case("ne", ARMCC::NE)
4622      .Case("hs", ARMCC::HS)
4623      .Case("cs", ARMCC::HS)
4624      .Case("lo", ARMCC::LO)
4625      .Case("cc", ARMCC::LO)
4626      .Case("mi", ARMCC::MI)
4627      .Case("pl", ARMCC::PL)
4628      .Case("vs", ARMCC::VS)
4629      .Case("vc", ARMCC::VC)
4630      .Case("hi", ARMCC::HI)
4631      .Case("ls", ARMCC::LS)
4632      .Case("ge", ARMCC::GE)
4633      .Case("lt", ARMCC::LT)
4634      .Case("gt", ARMCC::GT)
4635      .Case("le", ARMCC::LE)
4636      .Case("al", ARMCC::AL)
4637      .Default(~0U);
4638    if (CC != ~0U) {
4639      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4640      PredicationCode = CC;
4641    }
4642  }
4643
4644  // Next, determine if we have a carry setting bit. We explicitly ignore all
4645  // the instructions we know end in 's'.
4646  if (Mnemonic.endswith("s") &&
4647      !(Mnemonic == "cps" || Mnemonic == "mls" ||
4648        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4649        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4650        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4651        Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4652        Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4653        Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4654        Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4655        Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4656        (Mnemonic == "movs" && isThumb()))) {
4657    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4658    CarrySetting = true;
4659  }
4660
4661  // The "cps" instruction can have a interrupt mode operand which is glued into
4662  // the mnemonic. Check if this is the case, split it and parse the imod op
4663  if (Mnemonic.startswith("cps")) {
4664    // Split out any imod code.
4665    unsigned IMod =
4666      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4667      .Case("ie", ARM_PROC::IE)
4668      .Case("id", ARM_PROC::ID)
4669      .Default(~0U);
4670    if (IMod != ~0U) {
4671      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4672      ProcessorIMod = IMod;
4673    }
4674  }
4675
4676  // The "it" instruction has the condition mask on the end of the mnemonic.
4677  if (Mnemonic.startswith("it")) {
4678    ITMask = Mnemonic.slice(2, Mnemonic.size());
4679    Mnemonic = Mnemonic.slice(0, 2);
4680  }
4681
4682  return Mnemonic;
4683}
4684
4685/// \brief Given a canonical mnemonic, determine if the instruction ever allows
4686/// inclusion of carry set or predication code operands.
4687//
4688// FIXME: It would be nice to autogen this.
4689void ARMAsmParser::
4690getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4691                      bool &CanAcceptPredicationCode) {
4692  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4693      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4694      Mnemonic == "add" || Mnemonic == "adc" ||
4695      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4696      Mnemonic == "orr" || Mnemonic == "mvn" ||
4697      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4698      Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4699      Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4700      (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4701                      Mnemonic == "mla" || Mnemonic == "smlal" ||
4702                      Mnemonic == "umlal" || Mnemonic == "umull"))) {
4703    CanAcceptCarrySet = true;
4704  } else
4705    CanAcceptCarrySet = false;
4706
4707  if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
4708      Mnemonic == "cps" ||  Mnemonic == "it" ||  Mnemonic == "cbz" ||
4709      Mnemonic == "trap" || Mnemonic == "setend" ||
4710      Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
4711      Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
4712      Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
4713      Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
4714      Mnemonic == "vrintm") {
4715    // These mnemonics are never predicable
4716    CanAcceptPredicationCode = false;
4717  } else if (!isThumb()) {
4718    // Some instructions are only predicable in Thumb mode
4719    CanAcceptPredicationCode
4720      = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
4721        Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
4722        Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
4723        Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
4724        Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
4725        Mnemonic != "stc2" && Mnemonic != "stc2l" &&
4726        !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
4727  } else if (isThumbOne()) {
4728    CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
4729  } else
4730    CanAcceptPredicationCode = true;
4731}
4732
4733bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4734                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4735  // FIXME: This is all horribly hacky. We really need a better way to deal
4736  // with optional operands like this in the matcher table.
4737
4738  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4739  // another does not. Specifically, the MOVW instruction does not. So we
4740  // special case it here and remove the defaulted (non-setting) cc_out
4741  // operand if that's the instruction we're trying to match.
4742  //
4743  // We do this as post-processing of the explicit operands rather than just
4744  // conditionally adding the cc_out in the first place because we need
4745  // to check the type of the parsed immediate operand.
4746  if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4747      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4748      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4749      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4750    return true;
4751
4752  // Register-register 'add' for thumb does not have a cc_out operand
4753  // when there are only two register operands.
4754  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4755      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4756      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4757      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4758    return true;
4759  // Register-register 'add' for thumb does not have a cc_out operand
4760  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4761  // have to check the immediate range here since Thumb2 has a variant
4762  // that can handle a different range and has a cc_out operand.
4763  if (((isThumb() && Mnemonic == "add") ||
4764       (isThumbTwo() && Mnemonic == "sub")) &&
4765      Operands.size() == 6 &&
4766      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4767      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4768      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4769      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4770      ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4771       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4772    return true;
4773  // For Thumb2, add/sub immediate does not have a cc_out operand for the
4774  // imm0_4095 variant. That's the least-preferred variant when
4775  // selecting via the generic "add" mnemonic, so to know that we
4776  // should remove the cc_out operand, we have to explicitly check that
4777  // it's not one of the other variants. Ugh.
4778  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4779      Operands.size() == 6 &&
4780      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4781      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4782      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4783    // Nest conditions rather than one big 'if' statement for readability.
4784    //
4785    // If both registers are low, we're in an IT block, and the immediate is
4786    // in range, we should use encoding T1 instead, which has a cc_out.
4787    if (inITBlock() &&
4788        isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4789        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4790        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4791      return false;
4792    // Check against T3. If the second register is the PC, this is an
4793    // alternate form of ADR, which uses encoding T4, so check for that too.
4794    if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4795        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4796      return false;
4797
4798    // Otherwise, we use encoding T4, which does not have a cc_out
4799    // operand.
4800    return true;
4801  }
4802
4803  // The thumb2 multiply instruction doesn't have a CCOut register, so
4804  // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4805  // use the 16-bit encoding or not.
4806  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4807      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4808      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4809      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4810      static_cast<ARMOperand*>(Operands[5])->isReg() &&
4811      // If the registers aren't low regs, the destination reg isn't the
4812      // same as one of the source regs, or the cc_out operand is zero
4813      // outside of an IT block, we have to use the 32-bit encoding, so
4814      // remove the cc_out operand.
4815      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4816       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4817       !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4818       !inITBlock() ||
4819       (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4820        static_cast<ARMOperand*>(Operands[5])->getReg() &&
4821        static_cast<ARMOperand*>(Operands[3])->getReg() !=
4822        static_cast<ARMOperand*>(Operands[4])->getReg())))
4823    return true;
4824
4825  // Also check the 'mul' syntax variant that doesn't specify an explicit
4826  // destination register.
4827  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4828      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4829      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4830      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4831      // If the registers aren't low regs  or the cc_out operand is zero
4832      // outside of an IT block, we have to use the 32-bit encoding, so
4833      // remove the cc_out operand.
4834      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4835       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4836       !inITBlock()))
4837    return true;
4838
4839
4840
4841  // Register-register 'add/sub' for thumb does not have a cc_out operand
4842  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4843  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4844  // right, this will result in better diagnostics (which operand is off)
4845  // anyway.
4846  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4847      (Operands.size() == 5 || Operands.size() == 6) &&
4848      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4849      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4850      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4851      (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4852       (Operands.size() == 6 &&
4853        static_cast<ARMOperand*>(Operands[5])->isImm())))
4854    return true;
4855
4856  return false;
4857}
4858
4859bool ARMAsmParser::shouldOmitPredicateOperand(
4860    StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
4861  // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
4862  unsigned RegIdx = 3;
4863  if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
4864      static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
4865    if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
4866        static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
4867      RegIdx = 4;
4868
4869    if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
4870        (ARMMCRegisterClasses[ARM::DPRRegClassID]
4871             .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
4872         ARMMCRegisterClasses[ARM::QPRRegClassID]
4873             .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
4874      return true;
4875  }
4876  return false;
4877}
4878
4879static bool isDataTypeToken(StringRef Tok) {
4880  return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4881    Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4882    Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4883    Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4884    Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4885    Tok == ".f" || Tok == ".d";
4886}
4887
4888// FIXME: This bit should probably be handled via an explicit match class
4889// in the .td files that matches the suffix instead of having it be
4890// a literal string token the way it is now.
4891static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4892  return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4893}
4894static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
4895                                 unsigned VariantID);
4896/// Parse an arm instruction mnemonic followed by its operands.
4897bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
4898                                    SMLoc NameLoc,
4899                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4900  // Apply mnemonic aliases before doing anything else, as the destination
4901  // mnemnonic may include suffices and we want to handle them normally.
4902  // The generic tblgen'erated code does this later, at the start of
4903  // MatchInstructionImpl(), but that's too late for aliases that include
4904  // any sort of suffix.
4905  unsigned AvailableFeatures = getAvailableFeatures();
4906  unsigned AssemblerDialect = getParser().getAssemblerDialect();
4907  applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
4908
4909  // First check for the ARM-specific .req directive.
4910  if (Parser.getTok().is(AsmToken::Identifier) &&
4911      Parser.getTok().getIdentifier() == ".req") {
4912    parseDirectiveReq(Name, NameLoc);
4913    // We always return 'error' for this, as we're done with this
4914    // statement and don't need to match the 'instruction."
4915    return true;
4916  }
4917
4918  // Create the leading tokens for the mnemonic, split by '.' characters.
4919  size_t Start = 0, Next = Name.find('.');
4920  StringRef Mnemonic = Name.slice(Start, Next);
4921
4922  // Split out the predication code and carry setting flag from the mnemonic.
4923  unsigned PredicationCode;
4924  unsigned ProcessorIMod;
4925  bool CarrySetting;
4926  StringRef ITMask;
4927  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
4928                           ProcessorIMod, ITMask);
4929
4930  // In Thumb1, only the branch (B) instruction can be predicated.
4931  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
4932    Parser.eatToEndOfStatement();
4933    return Error(NameLoc, "conditional execution not supported in Thumb1");
4934  }
4935
4936  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
4937
4938  // Handle the IT instruction ITMask. Convert it to a bitmask. This
4939  // is the mask as it will be for the IT encoding if the conditional
4940  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
4941  // where the conditional bit0 is zero, the instruction post-processing
4942  // will adjust the mask accordingly.
4943  if (Mnemonic == "it") {
4944    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
4945    if (ITMask.size() > 3) {
4946      Parser.eatToEndOfStatement();
4947      return Error(Loc, "too many conditions on IT instruction");
4948    }
4949    unsigned Mask = 8;
4950    for (unsigned i = ITMask.size(); i != 0; --i) {
4951      char pos = ITMask[i - 1];
4952      if (pos != 't' && pos != 'e') {
4953        Parser.eatToEndOfStatement();
4954        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
4955      }
4956      Mask >>= 1;
4957      if (ITMask[i - 1] == 't')
4958        Mask |= 8;
4959    }
4960    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
4961  }
4962
4963  // FIXME: This is all a pretty gross hack. We should automatically handle
4964  // optional operands like this via tblgen.
4965
4966  // Next, add the CCOut and ConditionCode operands, if needed.
4967  //
4968  // For mnemonics which can ever incorporate a carry setting bit or predication
4969  // code, our matching model involves us always generating CCOut and
4970  // ConditionCode operands to match the mnemonic "as written" and then we let
4971  // the matcher deal with finding the right instruction or generating an
4972  // appropriate error.
4973  bool CanAcceptCarrySet, CanAcceptPredicationCode;
4974  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
4975
4976  // If we had a carry-set on an instruction that can't do that, issue an
4977  // error.
4978  if (!CanAcceptCarrySet && CarrySetting) {
4979    Parser.eatToEndOfStatement();
4980    return Error(NameLoc, "instruction '" + Mnemonic +
4981                 "' can not set flags, but 's' suffix specified");
4982  }
4983  // If we had a predication code on an instruction that can't do that, issue an
4984  // error.
4985  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
4986    Parser.eatToEndOfStatement();
4987    return Error(NameLoc, "instruction '" + Mnemonic +
4988                 "' is not predicable, but condition code specified");
4989  }
4990
4991  // Add the carry setting operand, if necessary.
4992  if (CanAcceptCarrySet) {
4993    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
4994    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
4995                                               Loc));
4996  }
4997
4998  // Add the predication code operand, if necessary.
4999  if (CanAcceptPredicationCode) {
5000    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5001                                      CarrySetting);
5002    Operands.push_back(ARMOperand::CreateCondCode(
5003                         ARMCC::CondCodes(PredicationCode), Loc));
5004  }
5005
5006  // Add the processor imod operand, if necessary.
5007  if (ProcessorIMod) {
5008    Operands.push_back(ARMOperand::CreateImm(
5009          MCConstantExpr::Create(ProcessorIMod, getContext()),
5010                                 NameLoc, NameLoc));
5011  }
5012
5013  // Add the remaining tokens in the mnemonic.
5014  while (Next != StringRef::npos) {
5015    Start = Next;
5016    Next = Name.find('.', Start + 1);
5017    StringRef ExtraToken = Name.slice(Start, Next);
5018
5019    // Some NEON instructions have an optional datatype suffix that is
5020    // completely ignored. Check for that.
5021    if (isDataTypeToken(ExtraToken) &&
5022        doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5023      continue;
5024
5025    // For for ARM mode generate an error if the .n qualifier is used.
5026    if (ExtraToken == ".n" && !isThumb()) {
5027      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5028      return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5029                   "arm mode");
5030    }
5031
5032    // The .n qualifier is always discarded as that is what the tables
5033    // and matcher expect.  In ARM mode the .w qualifier has no effect,
5034    // so discard it to avoid errors that can be caused by the matcher.
5035    if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5036      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5037      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5038    }
5039  }
5040
5041  // Read the remaining operands.
5042  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5043    // Read the first operand.
5044    if (parseOperand(Operands, Mnemonic)) {
5045      Parser.eatToEndOfStatement();
5046      return true;
5047    }
5048
5049    while (getLexer().is(AsmToken::Comma)) {
5050      Parser.Lex();  // Eat the comma.
5051
5052      // Parse and remember the operand.
5053      if (parseOperand(Operands, Mnemonic)) {
5054        Parser.eatToEndOfStatement();
5055        return true;
5056      }
5057    }
5058  }
5059
5060  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5061    SMLoc Loc = getLexer().getLoc();
5062    Parser.eatToEndOfStatement();
5063    return Error(Loc, "unexpected token in argument list");
5064  }
5065
5066  Parser.Lex(); // Consume the EndOfStatement
5067
5068  // Some instructions, mostly Thumb, have forms for the same mnemonic that
5069  // do and don't have a cc_out optional-def operand. With some spot-checks
5070  // of the operand list, we can figure out which variant we're trying to
5071  // parse and adjust accordingly before actually matching. We shouldn't ever
5072  // try to remove a cc_out operand that was explicitly set on the the
5073  // mnemonic, of course (CarrySetting == true). Reason number #317 the
5074  // table driven matcher doesn't fit well with the ARM instruction set.
5075  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5076    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5077    Operands.erase(Operands.begin() + 1);
5078    delete Op;
5079  }
5080
5081  // Some instructions have the same mnemonic, but don't always
5082  // have a predicate. Distinguish them here and delete the
5083  // predicate if needed.
5084  if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5085    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5086    Operands.erase(Operands.begin() + 1);
5087    delete Op;
5088  }
5089
5090  // ARM mode 'blx' need special handling, as the register operand version
5091  // is predicable, but the label operand version is not. So, we can't rely
5092  // on the Mnemonic based checking to correctly figure out when to put
5093  // a k_CondCode operand in the list. If we're trying to match the label
5094  // version, remove the k_CondCode operand here.
5095  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5096      static_cast<ARMOperand*>(Operands[2])->isImm()) {
5097    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5098    Operands.erase(Operands.begin() + 1);
5099    delete Op;
5100  }
5101
5102  // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5103  // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5104  // a single GPRPair reg operand is used in the .td file to replace the two
5105  // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5106  // expressed as a GPRPair, so we have to manually merge them.
5107  // FIXME: We would really like to be able to tablegen'erate this.
5108  if (!isThumb() && Operands.size() > 4 &&
5109      (Mnemonic == "ldrexd" || Mnemonic == "strexd")) {
5110    bool isLoad = (Mnemonic == "ldrexd");
5111    unsigned Idx = isLoad ? 2 : 3;
5112    ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5113    ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5114
5115    const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5116    // Adjust only if Op1 and Op2 are GPRs.
5117    if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5118        MRC.contains(Op2->getReg())) {
5119      unsigned Reg1 = Op1->getReg();
5120      unsigned Reg2 = Op2->getReg();
5121      unsigned Rt = MRI->getEncodingValue(Reg1);
5122      unsigned Rt2 = MRI->getEncodingValue(Reg2);
5123
5124      // Rt2 must be Rt + 1 and Rt must be even.
5125      if (Rt + 1 != Rt2 || (Rt & 1)) {
5126        Error(Op2->getStartLoc(), isLoad ?
5127            "destination operands must be sequential" :
5128            "source operands must be sequential");
5129        return true;
5130      }
5131      unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5132          &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5133      Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5134      Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5135            NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5136      delete Op1;
5137      delete Op2;
5138    }
5139  }
5140
5141  return false;
5142}
5143
5144// Validate context-sensitive operand constraints.
5145
5146// return 'true' if register list contains non-low GPR registers,
5147// 'false' otherwise. If Reg is in the register list or is HiReg, set
5148// 'containsReg' to true.
5149static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5150                                 unsigned HiReg, bool &containsReg) {
5151  containsReg = false;
5152  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5153    unsigned OpReg = Inst.getOperand(i).getReg();
5154    if (OpReg == Reg)
5155      containsReg = true;
5156    // Anything other than a low register isn't legal here.
5157    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5158      return true;
5159  }
5160  return false;
5161}
5162
5163// Check if the specified regisgter is in the register list of the inst,
5164// starting at the indicated operand number.
5165static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5166  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5167    unsigned OpReg = Inst.getOperand(i).getReg();
5168    if (OpReg == Reg)
5169      return true;
5170  }
5171  return false;
5172}
5173
5174// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5175// the ARMInsts array) instead. Getting that here requires awkward
5176// API changes, though. Better way?
5177namespace llvm {
5178extern const MCInstrDesc ARMInsts[];
5179}
5180static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5181  return ARMInsts[Opcode];
5182}
5183
5184// FIXME: We would really like to be able to tablegen'erate this.
5185bool ARMAsmParser::
5186validateInstruction(MCInst &Inst,
5187                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5188  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5189  SMLoc Loc = Operands[0]->getStartLoc();
5190  // Check the IT block state first.
5191  // NOTE: BKPT instruction has the interesting property of being
5192  // allowed in IT blocks, but not being predicable.  It just always
5193  // executes.
5194  if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5195      Inst.getOpcode() != ARM::BKPT) {
5196    unsigned bit = 1;
5197    if (ITState.FirstCond)
5198      ITState.FirstCond = false;
5199    else
5200      bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5201    // The instruction must be predicable.
5202    if (!MCID.isPredicable())
5203      return Error(Loc, "instructions in IT block must be predicable");
5204    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5205    unsigned ITCond = bit ? ITState.Cond :
5206      ARMCC::getOppositeCondition(ITState.Cond);
5207    if (Cond != ITCond) {
5208      // Find the condition code Operand to get its SMLoc information.
5209      SMLoc CondLoc;
5210      for (unsigned i = 1; i < Operands.size(); ++i)
5211        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5212          CondLoc = Operands[i]->getStartLoc();
5213      return Error(CondLoc, "incorrect condition in IT block; got '" +
5214                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5215                   "', but expected '" +
5216                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5217    }
5218  // Check for non-'al' condition codes outside of the IT block.
5219  } else if (isThumbTwo() && MCID.isPredicable() &&
5220             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5221             ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5222             Inst.getOpcode() != ARM::t2B)
5223    return Error(Loc, "predicated instructions must be in IT block");
5224
5225  switch (Inst.getOpcode()) {
5226  case ARM::LDRD:
5227  case ARM::LDRD_PRE:
5228  case ARM::LDRD_POST: {
5229    // Rt2 must be Rt + 1.
5230    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5231    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5232    if (Rt2 != Rt + 1)
5233      return Error(Operands[3]->getStartLoc(),
5234                   "destination operands must be sequential");
5235    return false;
5236  }
5237  case ARM::STRD: {
5238    // Rt2 must be Rt + 1.
5239    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5240    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5241    if (Rt2 != Rt + 1)
5242      return Error(Operands[3]->getStartLoc(),
5243                   "source operands must be sequential");
5244    return false;
5245  }
5246  case ARM::STRD_PRE:
5247  case ARM::STRD_POST: {
5248    // Rt2 must be Rt + 1.
5249    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5250    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5251    if (Rt2 != Rt + 1)
5252      return Error(Operands[3]->getStartLoc(),
5253                   "source operands must be sequential");
5254    return false;
5255  }
5256  case ARM::SBFX:
5257  case ARM::UBFX: {
5258    // width must be in range [1, 32-lsb]
5259    unsigned lsb = Inst.getOperand(2).getImm();
5260    unsigned widthm1 = Inst.getOperand(3).getImm();
5261    if (widthm1 >= 32 - lsb)
5262      return Error(Operands[5]->getStartLoc(),
5263                   "bitfield width must be in range [1,32-lsb]");
5264    return false;
5265  }
5266  case ARM::tLDMIA: {
5267    // If we're parsing Thumb2, the .w variant is available and handles
5268    // most cases that are normally illegal for a Thumb1 LDM
5269    // instruction. We'll make the transformation in processInstruction()
5270    // if necessary.
5271    //
5272    // Thumb LDM instructions are writeback iff the base register is not
5273    // in the register list.
5274    unsigned Rn = Inst.getOperand(0).getReg();
5275    bool hasWritebackToken =
5276      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5277       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5278    bool listContainsBase;
5279    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5280      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5281                   "registers must be in range r0-r7");
5282    // If we should have writeback, then there should be a '!' token.
5283    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5284      return Error(Operands[2]->getStartLoc(),
5285                   "writeback operator '!' expected");
5286    // If we should not have writeback, there must not be a '!'. This is
5287    // true even for the 32-bit wide encodings.
5288    if (listContainsBase && hasWritebackToken)
5289      return Error(Operands[3]->getStartLoc(),
5290                   "writeback operator '!' not allowed when base register "
5291                   "in register list");
5292
5293    break;
5294  }
5295  case ARM::t2LDMIA_UPD: {
5296    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5297      return Error(Operands[4]->getStartLoc(),
5298                   "writeback operator '!' not allowed when base register "
5299                   "in register list");
5300    break;
5301  }
5302  case ARM::tMUL: {
5303    // The second source operand must be the same register as the destination
5304    // operand.
5305    //
5306    // In this case, we must directly check the parsed operands because the
5307    // cvtThumbMultiply() function is written in such a way that it guarantees
5308    // this first statement is always true for the new Inst.  Essentially, the
5309    // destination is unconditionally copied into the second source operand
5310    // without checking to see if it matches what we actually parsed.
5311    if (Operands.size() == 6 &&
5312        (((ARMOperand*)Operands[3])->getReg() !=
5313         ((ARMOperand*)Operands[5])->getReg()) &&
5314        (((ARMOperand*)Operands[3])->getReg() !=
5315         ((ARMOperand*)Operands[4])->getReg())) {
5316      return Error(Operands[3]->getStartLoc(),
5317                   "destination register must match source register");
5318    }
5319    break;
5320  }
5321  // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5322  // so only issue a diagnostic for thumb1. The instructions will be
5323  // switched to the t2 encodings in processInstruction() if necessary.
5324  case ARM::tPOP: {
5325    bool listContainsBase;
5326    if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5327        !isThumbTwo())
5328      return Error(Operands[2]->getStartLoc(),
5329                   "registers must be in range r0-r7 or pc");
5330    break;
5331  }
5332  case ARM::tPUSH: {
5333    bool listContainsBase;
5334    if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5335        !isThumbTwo())
5336      return Error(Operands[2]->getStartLoc(),
5337                   "registers must be in range r0-r7 or lr");
5338    break;
5339  }
5340  case ARM::tSTMIA_UPD: {
5341    bool listContainsBase;
5342    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5343      return Error(Operands[4]->getStartLoc(),
5344                   "registers must be in range r0-r7");
5345    break;
5346  }
5347  case ARM::tADDrSP: {
5348    // If the non-SP source operand and the destination operand are not the
5349    // same, we need thumb2 (for the wide encoding), or we have an error.
5350    if (!isThumbTwo() &&
5351        Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5352      return Error(Operands[4]->getStartLoc(),
5353                   "source register must be the same as destination");
5354    }
5355    break;
5356  }
5357  }
5358
5359  return false;
5360}
5361
5362static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5363  switch(Opc) {
5364  default: llvm_unreachable("unexpected opcode!");
5365  // VST1LN
5366  case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5367  case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5368  case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5369  case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5370  case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5371  case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5372  case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
5373  case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5374  case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5375
5376  // VST2LN
5377  case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5378  case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5379  case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5380  case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5381  case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5382
5383  case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5384  case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5385  case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5386  case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5387  case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5388
5389  case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
5390  case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5391  case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5392  case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5393  case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5394
5395  // VST3LN
5396  case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5397  case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5398  case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5399  case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5400  case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5401  case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5402  case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5403  case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5404  case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5405  case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5406  case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
5407  case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5408  case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5409  case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5410  case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5411
5412  // VST3
5413  case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5414  case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5415  case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5416  case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5417  case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5418  case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5419  case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5420  case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5421  case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5422  case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5423  case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5424  case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5425  case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
5426  case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5427  case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5428  case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
5429  case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5430  case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5431
5432  // VST4LN
5433  case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5434  case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5435  case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5436  case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5437  case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5438  case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5439  case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5440  case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5441  case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5442  case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5443  case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
5444  case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5445  case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5446  case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5447  case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5448
5449  // VST4
5450  case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5451  case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5452  case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5453  case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5454  case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5455  case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5456  case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5457  case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5458  case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5459  case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5460  case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5461  case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5462  case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
5463  case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5464  case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5465  case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
5466  case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5467  case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5468  }
5469}
5470
5471static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5472  switch(Opc) {
5473  default: llvm_unreachable("unexpected opcode!");
5474  // VLD1LN
5475  case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5476  case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5477  case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5478  case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5479  case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5480  case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5481  case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
5482  case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5483  case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5484
5485  // VLD2LN
5486  case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5487  case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5488  case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5489  case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5490  case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5491  case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5492  case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5493  case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5494  case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5495  case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5496  case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
5497  case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5498  case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5499  case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5500  case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5501
5502  // VLD3DUP
5503  case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5504  case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5505  case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5506  case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5507  case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5508  case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5509  case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5510  case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5511  case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5512  case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5513  case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5514  case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5515  case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
5516  case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5517  case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5518  case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5519  case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5520  case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5521
5522  // VLD3LN
5523  case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5524  case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5525  case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5526  case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5527  case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5528  case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5529  case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5530  case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5531  case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5532  case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5533  case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
5534  case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5535  case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5536  case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5537  case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5538
5539  // VLD3
5540  case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5541  case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5542  case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5543  case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5544  case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5545  case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5546  case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5547  case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5548  case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5549  case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5550  case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5551  case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5552  case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
5553  case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5554  case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5555  case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
5556  case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5557  case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5558
5559  // VLD4LN
5560  case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5561  case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5562  case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5563  case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5564  case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5565  case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5566  case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5567  case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5568  case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5569  case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5570  case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
5571  case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5572  case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5573  case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5574  case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5575
5576  // VLD4DUP
5577  case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5578  case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5579  case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5580  case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5581  case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5582  case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5583  case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5584  case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5585  case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5586  case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5587  case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5588  case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5589  case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
5590  case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5591  case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5592  case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5593  case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5594  case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5595
5596  // VLD4
5597  case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5598  case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5599  case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5600  case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5601  case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5602  case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5603  case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5604  case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5605  case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5606  case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5607  case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5608  case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5609  case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
5610  case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5611  case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5612  case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
5613  case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5614  case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5615  }
5616}
5617
5618bool ARMAsmParser::
5619processInstruction(MCInst &Inst,
5620                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5621  switch (Inst.getOpcode()) {
5622  // Alias for alternate form of 'ADR Rd, #imm' instruction.
5623  case ARM::ADDri: {
5624    if (Inst.getOperand(1).getReg() != ARM::PC ||
5625        Inst.getOperand(5).getReg() != 0)
5626      return false;
5627    MCInst TmpInst;
5628    TmpInst.setOpcode(ARM::ADR);
5629    TmpInst.addOperand(Inst.getOperand(0));
5630    TmpInst.addOperand(Inst.getOperand(2));
5631    TmpInst.addOperand(Inst.getOperand(3));
5632    TmpInst.addOperand(Inst.getOperand(4));
5633    Inst = TmpInst;
5634    return true;
5635  }
5636  // Aliases for alternate PC+imm syntax of LDR instructions.
5637  case ARM::t2LDRpcrel:
5638    // Select the narrow version if the immediate will fit.
5639    if (Inst.getOperand(1).getImm() > 0 &&
5640        Inst.getOperand(1).getImm() <= 0xff &&
5641        !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
5642         static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
5643      Inst.setOpcode(ARM::tLDRpci);
5644    else
5645      Inst.setOpcode(ARM::t2LDRpci);
5646    return true;
5647  case ARM::t2LDRBpcrel:
5648    Inst.setOpcode(ARM::t2LDRBpci);
5649    return true;
5650  case ARM::t2LDRHpcrel:
5651    Inst.setOpcode(ARM::t2LDRHpci);
5652    return true;
5653  case ARM::t2LDRSBpcrel:
5654    Inst.setOpcode(ARM::t2LDRSBpci);
5655    return true;
5656  case ARM::t2LDRSHpcrel:
5657    Inst.setOpcode(ARM::t2LDRSHpci);
5658    return true;
5659  // Handle NEON VST complex aliases.
5660  case ARM::VST1LNdWB_register_Asm_8:
5661  case ARM::VST1LNdWB_register_Asm_16:
5662  case ARM::VST1LNdWB_register_Asm_32: {
5663    MCInst TmpInst;
5664    // Shuffle the operands around so the lane index operand is in the
5665    // right place.
5666    unsigned Spacing;
5667    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5668    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5669    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5670    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5671    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5672    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5673    TmpInst.addOperand(Inst.getOperand(1)); // lane
5674    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5675    TmpInst.addOperand(Inst.getOperand(6));
5676    Inst = TmpInst;
5677    return true;
5678  }
5679
5680  case ARM::VST2LNdWB_register_Asm_8:
5681  case ARM::VST2LNdWB_register_Asm_16:
5682  case ARM::VST2LNdWB_register_Asm_32:
5683  case ARM::VST2LNqWB_register_Asm_16:
5684  case ARM::VST2LNqWB_register_Asm_32: {
5685    MCInst TmpInst;
5686    // Shuffle the operands around so the lane index operand is in the
5687    // right place.
5688    unsigned Spacing;
5689    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5690    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5691    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5692    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5693    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5694    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5695    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5696                                            Spacing));
5697    TmpInst.addOperand(Inst.getOperand(1)); // lane
5698    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5699    TmpInst.addOperand(Inst.getOperand(6));
5700    Inst = TmpInst;
5701    return true;
5702  }
5703
5704  case ARM::VST3LNdWB_register_Asm_8:
5705  case ARM::VST3LNdWB_register_Asm_16:
5706  case ARM::VST3LNdWB_register_Asm_32:
5707  case ARM::VST3LNqWB_register_Asm_16:
5708  case ARM::VST3LNqWB_register_Asm_32: {
5709    MCInst TmpInst;
5710    // Shuffle the operands around so the lane index operand is in the
5711    // right place.
5712    unsigned Spacing;
5713    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5714    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5715    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5716    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5717    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5718    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5719    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5720                                            Spacing));
5721    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5722                                            Spacing * 2));
5723    TmpInst.addOperand(Inst.getOperand(1)); // lane
5724    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5725    TmpInst.addOperand(Inst.getOperand(6));
5726    Inst = TmpInst;
5727    return true;
5728  }
5729
5730  case ARM::VST4LNdWB_register_Asm_8:
5731  case ARM::VST4LNdWB_register_Asm_16:
5732  case ARM::VST4LNdWB_register_Asm_32:
5733  case ARM::VST4LNqWB_register_Asm_16:
5734  case ARM::VST4LNqWB_register_Asm_32: {
5735    MCInst TmpInst;
5736    // Shuffle the operands around so the lane index operand is in the
5737    // right place.
5738    unsigned Spacing;
5739    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5740    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5741    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5742    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5743    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5744    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5745    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5746                                            Spacing));
5747    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5748                                            Spacing * 2));
5749    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5750                                            Spacing * 3));
5751    TmpInst.addOperand(Inst.getOperand(1)); // lane
5752    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5753    TmpInst.addOperand(Inst.getOperand(6));
5754    Inst = TmpInst;
5755    return true;
5756  }
5757
5758  case ARM::VST1LNdWB_fixed_Asm_8:
5759  case ARM::VST1LNdWB_fixed_Asm_16:
5760  case ARM::VST1LNdWB_fixed_Asm_32: {
5761    MCInst TmpInst;
5762    // Shuffle the operands around so the lane index operand is in the
5763    // right place.
5764    unsigned Spacing;
5765    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5766    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5767    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5768    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5769    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5770    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5771    TmpInst.addOperand(Inst.getOperand(1)); // lane
5772    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5773    TmpInst.addOperand(Inst.getOperand(5));
5774    Inst = TmpInst;
5775    return true;
5776  }
5777
5778  case ARM::VST2LNdWB_fixed_Asm_8:
5779  case ARM::VST2LNdWB_fixed_Asm_16:
5780  case ARM::VST2LNdWB_fixed_Asm_32:
5781  case ARM::VST2LNqWB_fixed_Asm_16:
5782  case ARM::VST2LNqWB_fixed_Asm_32: {
5783    MCInst TmpInst;
5784    // Shuffle the operands around so the lane index operand is in the
5785    // right place.
5786    unsigned Spacing;
5787    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5788    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5789    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5790    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5791    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5792    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5793    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5794                                            Spacing));
5795    TmpInst.addOperand(Inst.getOperand(1)); // lane
5796    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5797    TmpInst.addOperand(Inst.getOperand(5));
5798    Inst = TmpInst;
5799    return true;
5800  }
5801
5802  case ARM::VST3LNdWB_fixed_Asm_8:
5803  case ARM::VST3LNdWB_fixed_Asm_16:
5804  case ARM::VST3LNdWB_fixed_Asm_32:
5805  case ARM::VST3LNqWB_fixed_Asm_16:
5806  case ARM::VST3LNqWB_fixed_Asm_32: {
5807    MCInst TmpInst;
5808    // Shuffle the operands around so the lane index operand is in the
5809    // right place.
5810    unsigned Spacing;
5811    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5812    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5813    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5814    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5815    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5816    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5817    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5818                                            Spacing));
5819    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5820                                            Spacing * 2));
5821    TmpInst.addOperand(Inst.getOperand(1)); // lane
5822    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5823    TmpInst.addOperand(Inst.getOperand(5));
5824    Inst = TmpInst;
5825    return true;
5826  }
5827
5828  case ARM::VST4LNdWB_fixed_Asm_8:
5829  case ARM::VST4LNdWB_fixed_Asm_16:
5830  case ARM::VST4LNdWB_fixed_Asm_32:
5831  case ARM::VST4LNqWB_fixed_Asm_16:
5832  case ARM::VST4LNqWB_fixed_Asm_32: {
5833    MCInst TmpInst;
5834    // Shuffle the operands around so the lane index operand is in the
5835    // right place.
5836    unsigned Spacing;
5837    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5838    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5839    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5840    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5841    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5842    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5843    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5844                                            Spacing));
5845    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5846                                            Spacing * 2));
5847    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5848                                            Spacing * 3));
5849    TmpInst.addOperand(Inst.getOperand(1)); // lane
5850    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5851    TmpInst.addOperand(Inst.getOperand(5));
5852    Inst = TmpInst;
5853    return true;
5854  }
5855
5856  case ARM::VST1LNdAsm_8:
5857  case ARM::VST1LNdAsm_16:
5858  case ARM::VST1LNdAsm_32: {
5859    MCInst TmpInst;
5860    // Shuffle the operands around so the lane index operand is in the
5861    // right place.
5862    unsigned Spacing;
5863    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5864    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5865    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5866    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5867    TmpInst.addOperand(Inst.getOperand(1)); // lane
5868    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5869    TmpInst.addOperand(Inst.getOperand(5));
5870    Inst = TmpInst;
5871    return true;
5872  }
5873
5874  case ARM::VST2LNdAsm_8:
5875  case ARM::VST2LNdAsm_16:
5876  case ARM::VST2LNdAsm_32:
5877  case ARM::VST2LNqAsm_16:
5878  case ARM::VST2LNqAsm_32: {
5879    MCInst TmpInst;
5880    // Shuffle the operands around so the lane index operand is in the
5881    // right place.
5882    unsigned Spacing;
5883    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5884    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5885    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5886    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5887    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5888                                            Spacing));
5889    TmpInst.addOperand(Inst.getOperand(1)); // lane
5890    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5891    TmpInst.addOperand(Inst.getOperand(5));
5892    Inst = TmpInst;
5893    return true;
5894  }
5895
5896  case ARM::VST3LNdAsm_8:
5897  case ARM::VST3LNdAsm_16:
5898  case ARM::VST3LNdAsm_32:
5899  case ARM::VST3LNqAsm_16:
5900  case ARM::VST3LNqAsm_32: {
5901    MCInst TmpInst;
5902    // Shuffle the operands around so the lane index operand is in the
5903    // right place.
5904    unsigned Spacing;
5905    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5906    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5907    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5908    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5909    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5910                                            Spacing));
5911    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5912                                            Spacing * 2));
5913    TmpInst.addOperand(Inst.getOperand(1)); // lane
5914    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5915    TmpInst.addOperand(Inst.getOperand(5));
5916    Inst = TmpInst;
5917    return true;
5918  }
5919
5920  case ARM::VST4LNdAsm_8:
5921  case ARM::VST4LNdAsm_16:
5922  case ARM::VST4LNdAsm_32:
5923  case ARM::VST4LNqAsm_16:
5924  case ARM::VST4LNqAsm_32: {
5925    MCInst TmpInst;
5926    // Shuffle the operands around so the lane index operand is in the
5927    // right place.
5928    unsigned Spacing;
5929    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5930    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5931    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5932    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5933    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5934                                            Spacing));
5935    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5936                                            Spacing * 2));
5937    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5938                                            Spacing * 3));
5939    TmpInst.addOperand(Inst.getOperand(1)); // lane
5940    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5941    TmpInst.addOperand(Inst.getOperand(5));
5942    Inst = TmpInst;
5943    return true;
5944  }
5945
5946  // Handle NEON VLD complex aliases.
5947  case ARM::VLD1LNdWB_register_Asm_8:
5948  case ARM::VLD1LNdWB_register_Asm_16:
5949  case ARM::VLD1LNdWB_register_Asm_32: {
5950    MCInst TmpInst;
5951    // Shuffle the operands around so the lane index operand is in the
5952    // right place.
5953    unsigned Spacing;
5954    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5955    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5956    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5957    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5958    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5959    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5960    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5961    TmpInst.addOperand(Inst.getOperand(1)); // lane
5962    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5963    TmpInst.addOperand(Inst.getOperand(6));
5964    Inst = TmpInst;
5965    return true;
5966  }
5967
5968  case ARM::VLD2LNdWB_register_Asm_8:
5969  case ARM::VLD2LNdWB_register_Asm_16:
5970  case ARM::VLD2LNdWB_register_Asm_32:
5971  case ARM::VLD2LNqWB_register_Asm_16:
5972  case ARM::VLD2LNqWB_register_Asm_32: {
5973    MCInst TmpInst;
5974    // Shuffle the operands around so the lane index operand is in the
5975    // right place.
5976    unsigned Spacing;
5977    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5978    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5979    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5980                                            Spacing));
5981    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5982    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5983    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5984    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5985    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5986    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5987                                            Spacing));
5988    TmpInst.addOperand(Inst.getOperand(1)); // lane
5989    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5990    TmpInst.addOperand(Inst.getOperand(6));
5991    Inst = TmpInst;
5992    return true;
5993  }
5994
5995  case ARM::VLD3LNdWB_register_Asm_8:
5996  case ARM::VLD3LNdWB_register_Asm_16:
5997  case ARM::VLD3LNdWB_register_Asm_32:
5998  case ARM::VLD3LNqWB_register_Asm_16:
5999  case ARM::VLD3LNqWB_register_Asm_32: {
6000    MCInst TmpInst;
6001    // Shuffle the operands around so the lane index operand is in the
6002    // right place.
6003    unsigned Spacing;
6004    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6005    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6006    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6007                                            Spacing));
6008    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6009                                            Spacing * 2));
6010    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6011    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6012    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6013    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6014    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6015    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6016                                            Spacing));
6017    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6018                                            Spacing * 2));
6019    TmpInst.addOperand(Inst.getOperand(1)); // lane
6020    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6021    TmpInst.addOperand(Inst.getOperand(6));
6022    Inst = TmpInst;
6023    return true;
6024  }
6025
6026  case ARM::VLD4LNdWB_register_Asm_8:
6027  case ARM::VLD4LNdWB_register_Asm_16:
6028  case ARM::VLD4LNdWB_register_Asm_32:
6029  case ARM::VLD4LNqWB_register_Asm_16:
6030  case ARM::VLD4LNqWB_register_Asm_32: {
6031    MCInst TmpInst;
6032    // Shuffle the operands around so the lane index operand is in the
6033    // right place.
6034    unsigned Spacing;
6035    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6036    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6037    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6038                                            Spacing));
6039    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6040                                            Spacing * 2));
6041    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6042                                            Spacing * 3));
6043    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6044    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6045    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6046    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6047    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6048    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6049                                            Spacing));
6050    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6051                                            Spacing * 2));
6052    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6053                                            Spacing * 3));
6054    TmpInst.addOperand(Inst.getOperand(1)); // lane
6055    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6056    TmpInst.addOperand(Inst.getOperand(6));
6057    Inst = TmpInst;
6058    return true;
6059  }
6060
6061  case ARM::VLD1LNdWB_fixed_Asm_8:
6062  case ARM::VLD1LNdWB_fixed_Asm_16:
6063  case ARM::VLD1LNdWB_fixed_Asm_32: {
6064    MCInst TmpInst;
6065    // Shuffle the operands around so the lane index operand is in the
6066    // right place.
6067    unsigned Spacing;
6068    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6069    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6070    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6071    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6072    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6073    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6074    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6075    TmpInst.addOperand(Inst.getOperand(1)); // lane
6076    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6077    TmpInst.addOperand(Inst.getOperand(5));
6078    Inst = TmpInst;
6079    return true;
6080  }
6081
6082  case ARM::VLD2LNdWB_fixed_Asm_8:
6083  case ARM::VLD2LNdWB_fixed_Asm_16:
6084  case ARM::VLD2LNdWB_fixed_Asm_32:
6085  case ARM::VLD2LNqWB_fixed_Asm_16:
6086  case ARM::VLD2LNqWB_fixed_Asm_32: {
6087    MCInst TmpInst;
6088    // Shuffle the operands around so the lane index operand is in the
6089    // right place.
6090    unsigned Spacing;
6091    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6092    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6093    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6094                                            Spacing));
6095    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6096    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6097    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6098    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6099    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6100    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6101                                            Spacing));
6102    TmpInst.addOperand(Inst.getOperand(1)); // lane
6103    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6104    TmpInst.addOperand(Inst.getOperand(5));
6105    Inst = TmpInst;
6106    return true;
6107  }
6108
6109  case ARM::VLD3LNdWB_fixed_Asm_8:
6110  case ARM::VLD3LNdWB_fixed_Asm_16:
6111  case ARM::VLD3LNdWB_fixed_Asm_32:
6112  case ARM::VLD3LNqWB_fixed_Asm_16:
6113  case ARM::VLD3LNqWB_fixed_Asm_32: {
6114    MCInst TmpInst;
6115    // Shuffle the operands around so the lane index operand is in the
6116    // right place.
6117    unsigned Spacing;
6118    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6119    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6120    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6121                                            Spacing));
6122    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6123                                            Spacing * 2));
6124    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6125    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6126    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6127    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6128    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6129    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6130                                            Spacing));
6131    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6132                                            Spacing * 2));
6133    TmpInst.addOperand(Inst.getOperand(1)); // lane
6134    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6135    TmpInst.addOperand(Inst.getOperand(5));
6136    Inst = TmpInst;
6137    return true;
6138  }
6139
6140  case ARM::VLD4LNdWB_fixed_Asm_8:
6141  case ARM::VLD4LNdWB_fixed_Asm_16:
6142  case ARM::VLD4LNdWB_fixed_Asm_32:
6143  case ARM::VLD4LNqWB_fixed_Asm_16:
6144  case ARM::VLD4LNqWB_fixed_Asm_32: {
6145    MCInst TmpInst;
6146    // Shuffle the operands around so the lane index operand is in the
6147    // right place.
6148    unsigned Spacing;
6149    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6150    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6151    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6152                                            Spacing));
6153    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6154                                            Spacing * 2));
6155    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6156                                            Spacing * 3));
6157    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6158    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6159    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6160    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6161    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6162    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6163                                            Spacing));
6164    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6165                                            Spacing * 2));
6166    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6167                                            Spacing * 3));
6168    TmpInst.addOperand(Inst.getOperand(1)); // lane
6169    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6170    TmpInst.addOperand(Inst.getOperand(5));
6171    Inst = TmpInst;
6172    return true;
6173  }
6174
6175  case ARM::VLD1LNdAsm_8:
6176  case ARM::VLD1LNdAsm_16:
6177  case ARM::VLD1LNdAsm_32: {
6178    MCInst TmpInst;
6179    // Shuffle the operands around so the lane index operand is in the
6180    // right place.
6181    unsigned Spacing;
6182    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6183    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6184    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6185    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6186    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6187    TmpInst.addOperand(Inst.getOperand(1)); // lane
6188    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6189    TmpInst.addOperand(Inst.getOperand(5));
6190    Inst = TmpInst;
6191    return true;
6192  }
6193
6194  case ARM::VLD2LNdAsm_8:
6195  case ARM::VLD2LNdAsm_16:
6196  case ARM::VLD2LNdAsm_32:
6197  case ARM::VLD2LNqAsm_16:
6198  case ARM::VLD2LNqAsm_32: {
6199    MCInst TmpInst;
6200    // Shuffle the operands around so the lane index operand is in the
6201    // right place.
6202    unsigned Spacing;
6203    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6204    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6205    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6206                                            Spacing));
6207    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6208    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6209    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6210    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6211                                            Spacing));
6212    TmpInst.addOperand(Inst.getOperand(1)); // lane
6213    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6214    TmpInst.addOperand(Inst.getOperand(5));
6215    Inst = TmpInst;
6216    return true;
6217  }
6218
6219  case ARM::VLD3LNdAsm_8:
6220  case ARM::VLD3LNdAsm_16:
6221  case ARM::VLD3LNdAsm_32:
6222  case ARM::VLD3LNqAsm_16:
6223  case ARM::VLD3LNqAsm_32: {
6224    MCInst TmpInst;
6225    // Shuffle the operands around so the lane index operand is in the
6226    // right place.
6227    unsigned Spacing;
6228    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6229    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6230    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6231                                            Spacing));
6232    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6233                                            Spacing * 2));
6234    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6235    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6236    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6237    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6238                                            Spacing));
6239    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6240                                            Spacing * 2));
6241    TmpInst.addOperand(Inst.getOperand(1)); // lane
6242    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6243    TmpInst.addOperand(Inst.getOperand(5));
6244    Inst = TmpInst;
6245    return true;
6246  }
6247
6248  case ARM::VLD4LNdAsm_8:
6249  case ARM::VLD4LNdAsm_16:
6250  case ARM::VLD4LNdAsm_32:
6251  case ARM::VLD4LNqAsm_16:
6252  case ARM::VLD4LNqAsm_32: {
6253    MCInst TmpInst;
6254    // Shuffle the operands around so the lane index operand is in the
6255    // right place.
6256    unsigned Spacing;
6257    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6258    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6259    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6260                                            Spacing));
6261    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6262                                            Spacing * 2));
6263    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6264                                            Spacing * 3));
6265    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6266    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6267    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6268    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6269                                            Spacing));
6270    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6271                                            Spacing * 2));
6272    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6273                                            Spacing * 3));
6274    TmpInst.addOperand(Inst.getOperand(1)); // lane
6275    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6276    TmpInst.addOperand(Inst.getOperand(5));
6277    Inst = TmpInst;
6278    return true;
6279  }
6280
6281  // VLD3DUP single 3-element structure to all lanes instructions.
6282  case ARM::VLD3DUPdAsm_8:
6283  case ARM::VLD3DUPdAsm_16:
6284  case ARM::VLD3DUPdAsm_32:
6285  case ARM::VLD3DUPqAsm_8:
6286  case ARM::VLD3DUPqAsm_16:
6287  case ARM::VLD3DUPqAsm_32: {
6288    MCInst TmpInst;
6289    unsigned Spacing;
6290    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6291    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6292    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6293                                            Spacing));
6294    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6295                                            Spacing * 2));
6296    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6297    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6298    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6299    TmpInst.addOperand(Inst.getOperand(4));
6300    Inst = TmpInst;
6301    return true;
6302  }
6303
6304  case ARM::VLD3DUPdWB_fixed_Asm_8:
6305  case ARM::VLD3DUPdWB_fixed_Asm_16:
6306  case ARM::VLD3DUPdWB_fixed_Asm_32:
6307  case ARM::VLD3DUPqWB_fixed_Asm_8:
6308  case ARM::VLD3DUPqWB_fixed_Asm_16:
6309  case ARM::VLD3DUPqWB_fixed_Asm_32: {
6310    MCInst TmpInst;
6311    unsigned Spacing;
6312    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6313    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6314    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6315                                            Spacing));
6316    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6317                                            Spacing * 2));
6318    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6319    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6320    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6321    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6322    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6323    TmpInst.addOperand(Inst.getOperand(4));
6324    Inst = TmpInst;
6325    return true;
6326  }
6327
6328  case ARM::VLD3DUPdWB_register_Asm_8:
6329  case ARM::VLD3DUPdWB_register_Asm_16:
6330  case ARM::VLD3DUPdWB_register_Asm_32:
6331  case ARM::VLD3DUPqWB_register_Asm_8:
6332  case ARM::VLD3DUPqWB_register_Asm_16:
6333  case ARM::VLD3DUPqWB_register_Asm_32: {
6334    MCInst TmpInst;
6335    unsigned Spacing;
6336    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6337    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6338    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6339                                            Spacing));
6340    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6341                                            Spacing * 2));
6342    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6343    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6344    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6345    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6346    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6347    TmpInst.addOperand(Inst.getOperand(5));
6348    Inst = TmpInst;
6349    return true;
6350  }
6351
6352  // VLD3 multiple 3-element structure instructions.
6353  case ARM::VLD3dAsm_8:
6354  case ARM::VLD3dAsm_16:
6355  case ARM::VLD3dAsm_32:
6356  case ARM::VLD3qAsm_8:
6357  case ARM::VLD3qAsm_16:
6358  case ARM::VLD3qAsm_32: {
6359    MCInst TmpInst;
6360    unsigned Spacing;
6361    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6362    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6363    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6364                                            Spacing));
6365    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6366                                            Spacing * 2));
6367    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6368    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6369    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6370    TmpInst.addOperand(Inst.getOperand(4));
6371    Inst = TmpInst;
6372    return true;
6373  }
6374
6375  case ARM::VLD3dWB_fixed_Asm_8:
6376  case ARM::VLD3dWB_fixed_Asm_16:
6377  case ARM::VLD3dWB_fixed_Asm_32:
6378  case ARM::VLD3qWB_fixed_Asm_8:
6379  case ARM::VLD3qWB_fixed_Asm_16:
6380  case ARM::VLD3qWB_fixed_Asm_32: {
6381    MCInst TmpInst;
6382    unsigned Spacing;
6383    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6384    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6385    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6386                                            Spacing));
6387    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6388                                            Spacing * 2));
6389    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6390    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6391    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6392    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6393    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6394    TmpInst.addOperand(Inst.getOperand(4));
6395    Inst = TmpInst;
6396    return true;
6397  }
6398
6399  case ARM::VLD3dWB_register_Asm_8:
6400  case ARM::VLD3dWB_register_Asm_16:
6401  case ARM::VLD3dWB_register_Asm_32:
6402  case ARM::VLD3qWB_register_Asm_8:
6403  case ARM::VLD3qWB_register_Asm_16:
6404  case ARM::VLD3qWB_register_Asm_32: {
6405    MCInst TmpInst;
6406    unsigned Spacing;
6407    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6408    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6409    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6410                                            Spacing));
6411    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6412                                            Spacing * 2));
6413    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6414    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6415    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6416    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6417    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6418    TmpInst.addOperand(Inst.getOperand(5));
6419    Inst = TmpInst;
6420    return true;
6421  }
6422
6423  // VLD4DUP single 3-element structure to all lanes instructions.
6424  case ARM::VLD4DUPdAsm_8:
6425  case ARM::VLD4DUPdAsm_16:
6426  case ARM::VLD4DUPdAsm_32:
6427  case ARM::VLD4DUPqAsm_8:
6428  case ARM::VLD4DUPqAsm_16:
6429  case ARM::VLD4DUPqAsm_32: {
6430    MCInst TmpInst;
6431    unsigned Spacing;
6432    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6433    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6434    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6435                                            Spacing));
6436    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6437                                            Spacing * 2));
6438    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6439                                            Spacing * 3));
6440    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6441    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6442    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6443    TmpInst.addOperand(Inst.getOperand(4));
6444    Inst = TmpInst;
6445    return true;
6446  }
6447
6448  case ARM::VLD4DUPdWB_fixed_Asm_8:
6449  case ARM::VLD4DUPdWB_fixed_Asm_16:
6450  case ARM::VLD4DUPdWB_fixed_Asm_32:
6451  case ARM::VLD4DUPqWB_fixed_Asm_8:
6452  case ARM::VLD4DUPqWB_fixed_Asm_16:
6453  case ARM::VLD4DUPqWB_fixed_Asm_32: {
6454    MCInst TmpInst;
6455    unsigned Spacing;
6456    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6457    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6458    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6459                                            Spacing));
6460    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6461                                            Spacing * 2));
6462    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6463                                            Spacing * 3));
6464    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6465    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6466    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6467    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6468    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6469    TmpInst.addOperand(Inst.getOperand(4));
6470    Inst = TmpInst;
6471    return true;
6472  }
6473
6474  case ARM::VLD4DUPdWB_register_Asm_8:
6475  case ARM::VLD4DUPdWB_register_Asm_16:
6476  case ARM::VLD4DUPdWB_register_Asm_32:
6477  case ARM::VLD4DUPqWB_register_Asm_8:
6478  case ARM::VLD4DUPqWB_register_Asm_16:
6479  case ARM::VLD4DUPqWB_register_Asm_32: {
6480    MCInst TmpInst;
6481    unsigned Spacing;
6482    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6483    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6484    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6485                                            Spacing));
6486    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6487                                            Spacing * 2));
6488    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6489                                            Spacing * 3));
6490    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6491    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6492    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6493    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6494    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6495    TmpInst.addOperand(Inst.getOperand(5));
6496    Inst = TmpInst;
6497    return true;
6498  }
6499
6500  // VLD4 multiple 4-element structure instructions.
6501  case ARM::VLD4dAsm_8:
6502  case ARM::VLD4dAsm_16:
6503  case ARM::VLD4dAsm_32:
6504  case ARM::VLD4qAsm_8:
6505  case ARM::VLD4qAsm_16:
6506  case ARM::VLD4qAsm_32: {
6507    MCInst TmpInst;
6508    unsigned Spacing;
6509    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6510    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6511    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6512                                            Spacing));
6513    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6514                                            Spacing * 2));
6515    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6516                                            Spacing * 3));
6517    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6518    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6519    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6520    TmpInst.addOperand(Inst.getOperand(4));
6521    Inst = TmpInst;
6522    return true;
6523  }
6524
6525  case ARM::VLD4dWB_fixed_Asm_8:
6526  case ARM::VLD4dWB_fixed_Asm_16:
6527  case ARM::VLD4dWB_fixed_Asm_32:
6528  case ARM::VLD4qWB_fixed_Asm_8:
6529  case ARM::VLD4qWB_fixed_Asm_16:
6530  case ARM::VLD4qWB_fixed_Asm_32: {
6531    MCInst TmpInst;
6532    unsigned Spacing;
6533    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6534    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6535    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6536                                            Spacing));
6537    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6538                                            Spacing * 2));
6539    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6540                                            Spacing * 3));
6541    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6542    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6543    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6544    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6545    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6546    TmpInst.addOperand(Inst.getOperand(4));
6547    Inst = TmpInst;
6548    return true;
6549  }
6550
6551  case ARM::VLD4dWB_register_Asm_8:
6552  case ARM::VLD4dWB_register_Asm_16:
6553  case ARM::VLD4dWB_register_Asm_32:
6554  case ARM::VLD4qWB_register_Asm_8:
6555  case ARM::VLD4qWB_register_Asm_16:
6556  case ARM::VLD4qWB_register_Asm_32: {
6557    MCInst TmpInst;
6558    unsigned Spacing;
6559    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6560    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6561    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6562                                            Spacing));
6563    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6564                                            Spacing * 2));
6565    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6566                                            Spacing * 3));
6567    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6568    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6569    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6570    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6571    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6572    TmpInst.addOperand(Inst.getOperand(5));
6573    Inst = TmpInst;
6574    return true;
6575  }
6576
6577  // VST3 multiple 3-element structure instructions.
6578  case ARM::VST3dAsm_8:
6579  case ARM::VST3dAsm_16:
6580  case ARM::VST3dAsm_32:
6581  case ARM::VST3qAsm_8:
6582  case ARM::VST3qAsm_16:
6583  case ARM::VST3qAsm_32: {
6584    MCInst TmpInst;
6585    unsigned Spacing;
6586    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6587    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6588    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6589    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6590    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6591                                            Spacing));
6592    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6593                                            Spacing * 2));
6594    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6595    TmpInst.addOperand(Inst.getOperand(4));
6596    Inst = TmpInst;
6597    return true;
6598  }
6599
6600  case ARM::VST3dWB_fixed_Asm_8:
6601  case ARM::VST3dWB_fixed_Asm_16:
6602  case ARM::VST3dWB_fixed_Asm_32:
6603  case ARM::VST3qWB_fixed_Asm_8:
6604  case ARM::VST3qWB_fixed_Asm_16:
6605  case ARM::VST3qWB_fixed_Asm_32: {
6606    MCInst TmpInst;
6607    unsigned Spacing;
6608    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6609    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6610    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6611    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6612    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6613    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6614    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6615                                            Spacing));
6616    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6617                                            Spacing * 2));
6618    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6619    TmpInst.addOperand(Inst.getOperand(4));
6620    Inst = TmpInst;
6621    return true;
6622  }
6623
6624  case ARM::VST3dWB_register_Asm_8:
6625  case ARM::VST3dWB_register_Asm_16:
6626  case ARM::VST3dWB_register_Asm_32:
6627  case ARM::VST3qWB_register_Asm_8:
6628  case ARM::VST3qWB_register_Asm_16:
6629  case ARM::VST3qWB_register_Asm_32: {
6630    MCInst TmpInst;
6631    unsigned Spacing;
6632    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6633    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6634    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6635    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6636    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6637    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6638    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6639                                            Spacing));
6640    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6641                                            Spacing * 2));
6642    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6643    TmpInst.addOperand(Inst.getOperand(5));
6644    Inst = TmpInst;
6645    return true;
6646  }
6647
6648  // VST4 multiple 3-element structure instructions.
6649  case ARM::VST4dAsm_8:
6650  case ARM::VST4dAsm_16:
6651  case ARM::VST4dAsm_32:
6652  case ARM::VST4qAsm_8:
6653  case ARM::VST4qAsm_16:
6654  case ARM::VST4qAsm_32: {
6655    MCInst TmpInst;
6656    unsigned Spacing;
6657    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6658    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6659    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6660    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6661    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6662                                            Spacing));
6663    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6664                                            Spacing * 2));
6665    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6666                                            Spacing * 3));
6667    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6668    TmpInst.addOperand(Inst.getOperand(4));
6669    Inst = TmpInst;
6670    return true;
6671  }
6672
6673  case ARM::VST4dWB_fixed_Asm_8:
6674  case ARM::VST4dWB_fixed_Asm_16:
6675  case ARM::VST4dWB_fixed_Asm_32:
6676  case ARM::VST4qWB_fixed_Asm_8:
6677  case ARM::VST4qWB_fixed_Asm_16:
6678  case ARM::VST4qWB_fixed_Asm_32: {
6679    MCInst TmpInst;
6680    unsigned Spacing;
6681    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6682    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6683    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6684    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6685    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6686    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6687    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6688                                            Spacing));
6689    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6690                                            Spacing * 2));
6691    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6692                                            Spacing * 3));
6693    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6694    TmpInst.addOperand(Inst.getOperand(4));
6695    Inst = TmpInst;
6696    return true;
6697  }
6698
6699  case ARM::VST4dWB_register_Asm_8:
6700  case ARM::VST4dWB_register_Asm_16:
6701  case ARM::VST4dWB_register_Asm_32:
6702  case ARM::VST4qWB_register_Asm_8:
6703  case ARM::VST4qWB_register_Asm_16:
6704  case ARM::VST4qWB_register_Asm_32: {
6705    MCInst TmpInst;
6706    unsigned Spacing;
6707    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6708    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6709    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6710    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6711    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6712    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6713    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6714                                            Spacing));
6715    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6716                                            Spacing * 2));
6717    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6718                                            Spacing * 3));
6719    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6720    TmpInst.addOperand(Inst.getOperand(5));
6721    Inst = TmpInst;
6722    return true;
6723  }
6724
6725  // Handle encoding choice for the shift-immediate instructions.
6726  case ARM::t2LSLri:
6727  case ARM::t2LSRri:
6728  case ARM::t2ASRri: {
6729    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6730        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6731        Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6732        !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6733         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6734      unsigned NewOpc;
6735      switch (Inst.getOpcode()) {
6736      default: llvm_unreachable("unexpected opcode");
6737      case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6738      case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6739      case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6740      }
6741      // The Thumb1 operands aren't in the same order. Awesome, eh?
6742      MCInst TmpInst;
6743      TmpInst.setOpcode(NewOpc);
6744      TmpInst.addOperand(Inst.getOperand(0));
6745      TmpInst.addOperand(Inst.getOperand(5));
6746      TmpInst.addOperand(Inst.getOperand(1));
6747      TmpInst.addOperand(Inst.getOperand(2));
6748      TmpInst.addOperand(Inst.getOperand(3));
6749      TmpInst.addOperand(Inst.getOperand(4));
6750      Inst = TmpInst;
6751      return true;
6752    }
6753    return false;
6754  }
6755
6756  // Handle the Thumb2 mode MOV complex aliases.
6757  case ARM::t2MOVsr:
6758  case ARM::t2MOVSsr: {
6759    // Which instruction to expand to depends on the CCOut operand and
6760    // whether we're in an IT block if the register operands are low
6761    // registers.
6762    bool isNarrow = false;
6763    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6764        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6765        isARMLowRegister(Inst.getOperand(2).getReg()) &&
6766        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6767        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6768      isNarrow = true;
6769    MCInst TmpInst;
6770    unsigned newOpc;
6771    switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6772    default: llvm_unreachable("unexpected opcode!");
6773    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6774    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6775    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6776    case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
6777    }
6778    TmpInst.setOpcode(newOpc);
6779    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6780    if (isNarrow)
6781      TmpInst.addOperand(MCOperand::CreateReg(
6782          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6783    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6784    TmpInst.addOperand(Inst.getOperand(2)); // Rm
6785    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6786    TmpInst.addOperand(Inst.getOperand(5));
6787    if (!isNarrow)
6788      TmpInst.addOperand(MCOperand::CreateReg(
6789          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6790    Inst = TmpInst;
6791    return true;
6792  }
6793  case ARM::t2MOVsi:
6794  case ARM::t2MOVSsi: {
6795    // Which instruction to expand to depends on the CCOut operand and
6796    // whether we're in an IT block if the register operands are low
6797    // registers.
6798    bool isNarrow = false;
6799    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6800        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6801        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6802      isNarrow = true;
6803    MCInst TmpInst;
6804    unsigned newOpc;
6805    switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6806    default: llvm_unreachable("unexpected opcode!");
6807    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6808    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6809    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6810    case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6811    case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6812    }
6813    unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6814    if (Amount == 32) Amount = 0;
6815    TmpInst.setOpcode(newOpc);
6816    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6817    if (isNarrow)
6818      TmpInst.addOperand(MCOperand::CreateReg(
6819          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6820    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6821    if (newOpc != ARM::t2RRX)
6822      TmpInst.addOperand(MCOperand::CreateImm(Amount));
6823    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6824    TmpInst.addOperand(Inst.getOperand(4));
6825    if (!isNarrow)
6826      TmpInst.addOperand(MCOperand::CreateReg(
6827          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6828    Inst = TmpInst;
6829    return true;
6830  }
6831  // Handle the ARM mode MOV complex aliases.
6832  case ARM::ASRr:
6833  case ARM::LSRr:
6834  case ARM::LSLr:
6835  case ARM::RORr: {
6836    ARM_AM::ShiftOpc ShiftTy;
6837    switch(Inst.getOpcode()) {
6838    default: llvm_unreachable("unexpected opcode!");
6839    case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6840    case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6841    case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6842    case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6843    }
6844    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6845    MCInst TmpInst;
6846    TmpInst.setOpcode(ARM::MOVsr);
6847    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6848    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6849    TmpInst.addOperand(Inst.getOperand(2)); // Rm
6850    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6851    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6852    TmpInst.addOperand(Inst.getOperand(4));
6853    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6854    Inst = TmpInst;
6855    return true;
6856  }
6857  case ARM::ASRi:
6858  case ARM::LSRi:
6859  case ARM::LSLi:
6860  case ARM::RORi: {
6861    ARM_AM::ShiftOpc ShiftTy;
6862    switch(Inst.getOpcode()) {
6863    default: llvm_unreachable("unexpected opcode!");
6864    case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6865    case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6866    case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
6867    case ARM::RORi: ShiftTy = ARM_AM::ror; break;
6868    }
6869    // A shift by zero is a plain MOVr, not a MOVsi.
6870    unsigned Amt = Inst.getOperand(2).getImm();
6871    unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6872    // A shift by 32 should be encoded as 0 when permitted
6873    if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
6874      Amt = 0;
6875    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
6876    MCInst TmpInst;
6877    TmpInst.setOpcode(Opc);
6878    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6879    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6880    if (Opc == ARM::MOVsi)
6881      TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6882    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6883    TmpInst.addOperand(Inst.getOperand(4));
6884    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6885    Inst = TmpInst;
6886    return true;
6887  }
6888  case ARM::RRXi: {
6889    unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
6890    MCInst TmpInst;
6891    TmpInst.setOpcode(ARM::MOVsi);
6892    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6893    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6894    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6895    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6896    TmpInst.addOperand(Inst.getOperand(3));
6897    TmpInst.addOperand(Inst.getOperand(4)); // cc_out
6898    Inst = TmpInst;
6899    return true;
6900  }
6901  case ARM::t2LDMIA_UPD: {
6902    // If this is a load of a single register, then we should use
6903    // a post-indexed LDR instruction instead, per the ARM ARM.
6904    if (Inst.getNumOperands() != 5)
6905      return false;
6906    MCInst TmpInst;
6907    TmpInst.setOpcode(ARM::t2LDR_POST);
6908    TmpInst.addOperand(Inst.getOperand(4)); // Rt
6909    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6910    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6911    TmpInst.addOperand(MCOperand::CreateImm(4));
6912    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6913    TmpInst.addOperand(Inst.getOperand(3));
6914    Inst = TmpInst;
6915    return true;
6916  }
6917  case ARM::t2STMDB_UPD: {
6918    // If this is a store of a single register, then we should use
6919    // a pre-indexed STR instruction instead, per the ARM ARM.
6920    if (Inst.getNumOperands() != 5)
6921      return false;
6922    MCInst TmpInst;
6923    TmpInst.setOpcode(ARM::t2STR_PRE);
6924    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6925    TmpInst.addOperand(Inst.getOperand(4)); // Rt
6926    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6927    TmpInst.addOperand(MCOperand::CreateImm(-4));
6928    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6929    TmpInst.addOperand(Inst.getOperand(3));
6930    Inst = TmpInst;
6931    return true;
6932  }
6933  case ARM::LDMIA_UPD:
6934    // If this is a load of a single register via a 'pop', then we should use
6935    // a post-indexed LDR instruction instead, per the ARM ARM.
6936    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
6937        Inst.getNumOperands() == 5) {
6938      MCInst TmpInst;
6939      TmpInst.setOpcode(ARM::LDR_POST_IMM);
6940      TmpInst.addOperand(Inst.getOperand(4)); // Rt
6941      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6942      TmpInst.addOperand(Inst.getOperand(1)); // Rn
6943      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
6944      TmpInst.addOperand(MCOperand::CreateImm(4));
6945      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6946      TmpInst.addOperand(Inst.getOperand(3));
6947      Inst = TmpInst;
6948      return true;
6949    }
6950    break;
6951  case ARM::STMDB_UPD:
6952    // If this is a store of a single register via a 'push', then we should use
6953    // a pre-indexed STR instruction instead, per the ARM ARM.
6954    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
6955        Inst.getNumOperands() == 5) {
6956      MCInst TmpInst;
6957      TmpInst.setOpcode(ARM::STR_PRE_IMM);
6958      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6959      TmpInst.addOperand(Inst.getOperand(4)); // Rt
6960      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
6961      TmpInst.addOperand(MCOperand::CreateImm(-4));
6962      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6963      TmpInst.addOperand(Inst.getOperand(3));
6964      Inst = TmpInst;
6965    }
6966    break;
6967  case ARM::t2ADDri12:
6968    // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
6969    // mnemonic was used (not "addw"), encoding T3 is preferred.
6970    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
6971        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
6972      break;
6973    Inst.setOpcode(ARM::t2ADDri);
6974    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
6975    break;
6976  case ARM::t2SUBri12:
6977    // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
6978    // mnemonic was used (not "subw"), encoding T3 is preferred.
6979    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
6980        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
6981      break;
6982    Inst.setOpcode(ARM::t2SUBri);
6983    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
6984    break;
6985  case ARM::tADDi8:
6986    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
6987    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
6988    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
6989    // to encoding T1 if <Rd> is omitted."
6990    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
6991      Inst.setOpcode(ARM::tADDi3);
6992      return true;
6993    }
6994    break;
6995  case ARM::tSUBi8:
6996    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
6997    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
6998    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
6999    // to encoding T1 if <Rd> is omitted."
7000    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7001      Inst.setOpcode(ARM::tSUBi3);
7002      return true;
7003    }
7004    break;
7005  case ARM::t2ADDri:
7006  case ARM::t2SUBri: {
7007    // If the destination and first source operand are the same, and
7008    // the flags are compatible with the current IT status, use encoding T2
7009    // instead of T3. For compatibility with the system 'as'. Make sure the
7010    // wide encoding wasn't explicit.
7011    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7012        !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7013        (unsigned)Inst.getOperand(2).getImm() > 255 ||
7014        ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7015        (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7016        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7017         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7018      break;
7019    MCInst TmpInst;
7020    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7021                      ARM::tADDi8 : ARM::tSUBi8);
7022    TmpInst.addOperand(Inst.getOperand(0));
7023    TmpInst.addOperand(Inst.getOperand(5));
7024    TmpInst.addOperand(Inst.getOperand(0));
7025    TmpInst.addOperand(Inst.getOperand(2));
7026    TmpInst.addOperand(Inst.getOperand(3));
7027    TmpInst.addOperand(Inst.getOperand(4));
7028    Inst = TmpInst;
7029    return true;
7030  }
7031  case ARM::t2ADDrr: {
7032    // If the destination and first source operand are the same, and
7033    // there's no setting of the flags, use encoding T2 instead of T3.
7034    // Note that this is only for ADD, not SUB. This mirrors the system
7035    // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7036    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7037        Inst.getOperand(5).getReg() != 0 ||
7038        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7039         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7040      break;
7041    MCInst TmpInst;
7042    TmpInst.setOpcode(ARM::tADDhirr);
7043    TmpInst.addOperand(Inst.getOperand(0));
7044    TmpInst.addOperand(Inst.getOperand(0));
7045    TmpInst.addOperand(Inst.getOperand(2));
7046    TmpInst.addOperand(Inst.getOperand(3));
7047    TmpInst.addOperand(Inst.getOperand(4));
7048    Inst = TmpInst;
7049    return true;
7050  }
7051  case ARM::tADDrSP: {
7052    // If the non-SP source operand and the destination operand are not the
7053    // same, we need to use the 32-bit encoding if it's available.
7054    if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7055      Inst.setOpcode(ARM::t2ADDrr);
7056      Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7057      return true;
7058    }
7059    break;
7060  }
7061  case ARM::tB:
7062    // A Thumb conditional branch outside of an IT block is a tBcc.
7063    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7064      Inst.setOpcode(ARM::tBcc);
7065      return true;
7066    }
7067    break;
7068  case ARM::t2B:
7069    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7070    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7071      Inst.setOpcode(ARM::t2Bcc);
7072      return true;
7073    }
7074    break;
7075  case ARM::t2Bcc:
7076    // If the conditional is AL or we're in an IT block, we really want t2B.
7077    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7078      Inst.setOpcode(ARM::t2B);
7079      return true;
7080    }
7081    break;
7082  case ARM::tBcc:
7083    // If the conditional is AL, we really want tB.
7084    if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7085      Inst.setOpcode(ARM::tB);
7086      return true;
7087    }
7088    break;
7089  case ARM::tLDMIA: {
7090    // If the register list contains any high registers, or if the writeback
7091    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7092    // instead if we're in Thumb2. Otherwise, this should have generated
7093    // an error in validateInstruction().
7094    unsigned Rn = Inst.getOperand(0).getReg();
7095    bool hasWritebackToken =
7096      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7097       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7098    bool listContainsBase;
7099    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7100        (!listContainsBase && !hasWritebackToken) ||
7101        (listContainsBase && hasWritebackToken)) {
7102      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7103      assert (isThumbTwo());
7104      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7105      // If we're switching to the updating version, we need to insert
7106      // the writeback tied operand.
7107      if (hasWritebackToken)
7108        Inst.insert(Inst.begin(),
7109                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7110      return true;
7111    }
7112    break;
7113  }
7114  case ARM::tSTMIA_UPD: {
7115    // If the register list contains any high registers, we need to use
7116    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7117    // should have generated an error in validateInstruction().
7118    unsigned Rn = Inst.getOperand(0).getReg();
7119    bool listContainsBase;
7120    if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7121      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7122      assert (isThumbTwo());
7123      Inst.setOpcode(ARM::t2STMIA_UPD);
7124      return true;
7125    }
7126    break;
7127  }
7128  case ARM::tPOP: {
7129    bool listContainsBase;
7130    // If the register list contains any high registers, we need to use
7131    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7132    // should have generated an error in validateInstruction().
7133    if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7134      return false;
7135    assert (isThumbTwo());
7136    Inst.setOpcode(ARM::t2LDMIA_UPD);
7137    // Add the base register and writeback operands.
7138    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7139    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7140    return true;
7141  }
7142  case ARM::tPUSH: {
7143    bool listContainsBase;
7144    if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7145      return false;
7146    assert (isThumbTwo());
7147    Inst.setOpcode(ARM::t2STMDB_UPD);
7148    // Add the base register and writeback operands.
7149    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7150    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7151    return true;
7152  }
7153  case ARM::t2MOVi: {
7154    // If we can use the 16-bit encoding and the user didn't explicitly
7155    // request the 32-bit variant, transform it here.
7156    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7157        (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7158        ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7159         Inst.getOperand(4).getReg() == ARM::CPSR) ||
7160        (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7161        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7162         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7163      // The operands aren't in the same order for tMOVi8...
7164      MCInst TmpInst;
7165      TmpInst.setOpcode(ARM::tMOVi8);
7166      TmpInst.addOperand(Inst.getOperand(0));
7167      TmpInst.addOperand(Inst.getOperand(4));
7168      TmpInst.addOperand(Inst.getOperand(1));
7169      TmpInst.addOperand(Inst.getOperand(2));
7170      TmpInst.addOperand(Inst.getOperand(3));
7171      Inst = TmpInst;
7172      return true;
7173    }
7174    break;
7175  }
7176  case ARM::t2MOVr: {
7177    // If we can use the 16-bit encoding and the user didn't explicitly
7178    // request the 32-bit variant, transform it here.
7179    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7180        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7181        Inst.getOperand(2).getImm() == ARMCC::AL &&
7182        Inst.getOperand(4).getReg() == ARM::CPSR &&
7183        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7184         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7185      // The operands aren't the same for tMOV[S]r... (no cc_out)
7186      MCInst TmpInst;
7187      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7188      TmpInst.addOperand(Inst.getOperand(0));
7189      TmpInst.addOperand(Inst.getOperand(1));
7190      TmpInst.addOperand(Inst.getOperand(2));
7191      TmpInst.addOperand(Inst.getOperand(3));
7192      Inst = TmpInst;
7193      return true;
7194    }
7195    break;
7196  }
7197  case ARM::t2SXTH:
7198  case ARM::t2SXTB:
7199  case ARM::t2UXTH:
7200  case ARM::t2UXTB: {
7201    // If we can use the 16-bit encoding and the user didn't explicitly
7202    // request the 32-bit variant, transform it here.
7203    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7204        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7205        Inst.getOperand(2).getImm() == 0 &&
7206        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7207         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7208      unsigned NewOpc;
7209      switch (Inst.getOpcode()) {
7210      default: llvm_unreachable("Illegal opcode!");
7211      case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7212      case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7213      case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7214      case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7215      }
7216      // The operands aren't the same for thumb1 (no rotate operand).
7217      MCInst TmpInst;
7218      TmpInst.setOpcode(NewOpc);
7219      TmpInst.addOperand(Inst.getOperand(0));
7220      TmpInst.addOperand(Inst.getOperand(1));
7221      TmpInst.addOperand(Inst.getOperand(3));
7222      TmpInst.addOperand(Inst.getOperand(4));
7223      Inst = TmpInst;
7224      return true;
7225    }
7226    break;
7227  }
7228  case ARM::MOVsi: {
7229    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7230    // rrx shifts and asr/lsr of #32 is encoded as 0
7231    if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7232      return false;
7233    if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7234      // Shifting by zero is accepted as a vanilla 'MOVr'
7235      MCInst TmpInst;
7236      TmpInst.setOpcode(ARM::MOVr);
7237      TmpInst.addOperand(Inst.getOperand(0));
7238      TmpInst.addOperand(Inst.getOperand(1));
7239      TmpInst.addOperand(Inst.getOperand(3));
7240      TmpInst.addOperand(Inst.getOperand(4));
7241      TmpInst.addOperand(Inst.getOperand(5));
7242      Inst = TmpInst;
7243      return true;
7244    }
7245    return false;
7246  }
7247  case ARM::ANDrsi:
7248  case ARM::ORRrsi:
7249  case ARM::EORrsi:
7250  case ARM::BICrsi:
7251  case ARM::SUBrsi:
7252  case ARM::ADDrsi: {
7253    unsigned newOpc;
7254    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7255    if (SOpc == ARM_AM::rrx) return false;
7256    switch (Inst.getOpcode()) {
7257    default: llvm_unreachable("unexpected opcode!");
7258    case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7259    case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7260    case ARM::EORrsi: newOpc = ARM::EORrr; break;
7261    case ARM::BICrsi: newOpc = ARM::BICrr; break;
7262    case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7263    case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7264    }
7265    // If the shift is by zero, use the non-shifted instruction definition.
7266    // The exception is for right shifts, where 0 == 32
7267    if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7268        !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7269      MCInst TmpInst;
7270      TmpInst.setOpcode(newOpc);
7271      TmpInst.addOperand(Inst.getOperand(0));
7272      TmpInst.addOperand(Inst.getOperand(1));
7273      TmpInst.addOperand(Inst.getOperand(2));
7274      TmpInst.addOperand(Inst.getOperand(4));
7275      TmpInst.addOperand(Inst.getOperand(5));
7276      TmpInst.addOperand(Inst.getOperand(6));
7277      Inst = TmpInst;
7278      return true;
7279    }
7280    return false;
7281  }
7282  case ARM::ITasm:
7283  case ARM::t2IT: {
7284    // The mask bits for all but the first condition are represented as
7285    // the low bit of the condition code value implies 't'. We currently
7286    // always have 1 implies 't', so XOR toggle the bits if the low bit
7287    // of the condition code is zero.
7288    MCOperand &MO = Inst.getOperand(1);
7289    unsigned Mask = MO.getImm();
7290    unsigned OrigMask = Mask;
7291    unsigned TZ = countTrailingZeros(Mask);
7292    if ((Inst.getOperand(0).getImm() & 1) == 0) {
7293      assert(Mask && TZ <= 3 && "illegal IT mask value!");
7294      Mask ^= (0xE << TZ) & 0xF;
7295    }
7296    MO.setImm(Mask);
7297
7298    // Set up the IT block state according to the IT instruction we just
7299    // matched.
7300    assert(!inITBlock() && "nested IT blocks?!");
7301    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7302    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7303    ITState.CurPosition = 0;
7304    ITState.FirstCond = true;
7305    break;
7306  }
7307  case ARM::t2LSLrr:
7308  case ARM::t2LSRrr:
7309  case ARM::t2ASRrr:
7310  case ARM::t2SBCrr:
7311  case ARM::t2RORrr:
7312  case ARM::t2BICrr:
7313  {
7314    // Assemblers should use the narrow encodings of these instructions when permissible.
7315    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7316         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7317        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7318        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7319         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7320        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7321         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7322      unsigned NewOpc;
7323      switch (Inst.getOpcode()) {
7324        default: llvm_unreachable("unexpected opcode");
7325        case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7326        case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7327        case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7328        case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7329        case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7330        case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7331      }
7332      MCInst TmpInst;
7333      TmpInst.setOpcode(NewOpc);
7334      TmpInst.addOperand(Inst.getOperand(0));
7335      TmpInst.addOperand(Inst.getOperand(5));
7336      TmpInst.addOperand(Inst.getOperand(1));
7337      TmpInst.addOperand(Inst.getOperand(2));
7338      TmpInst.addOperand(Inst.getOperand(3));
7339      TmpInst.addOperand(Inst.getOperand(4));
7340      Inst = TmpInst;
7341      return true;
7342    }
7343    return false;
7344  }
7345  case ARM::t2ANDrr:
7346  case ARM::t2EORrr:
7347  case ARM::t2ADCrr:
7348  case ARM::t2ORRrr:
7349  {
7350    // Assemblers should use the narrow encodings of these instructions when permissible.
7351    // These instructions are special in that they are commutable, so shorter encodings
7352    // are available more often.
7353    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7354         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7355        (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7356         Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7357        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7358         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7359        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7360         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7361      unsigned NewOpc;
7362      switch (Inst.getOpcode()) {
7363        default: llvm_unreachable("unexpected opcode");
7364        case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7365        case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7366        case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7367        case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7368      }
7369      MCInst TmpInst;
7370      TmpInst.setOpcode(NewOpc);
7371      TmpInst.addOperand(Inst.getOperand(0));
7372      TmpInst.addOperand(Inst.getOperand(5));
7373      if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7374        TmpInst.addOperand(Inst.getOperand(1));
7375        TmpInst.addOperand(Inst.getOperand(2));
7376      } else {
7377        TmpInst.addOperand(Inst.getOperand(2));
7378        TmpInst.addOperand(Inst.getOperand(1));
7379      }
7380      TmpInst.addOperand(Inst.getOperand(3));
7381      TmpInst.addOperand(Inst.getOperand(4));
7382      Inst = TmpInst;
7383      return true;
7384    }
7385    return false;
7386  }
7387  }
7388  return false;
7389}
7390
7391unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7392  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7393  // suffix depending on whether they're in an IT block or not.
7394  unsigned Opc = Inst.getOpcode();
7395  const MCInstrDesc &MCID = getInstDesc(Opc);
7396  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7397    assert(MCID.hasOptionalDef() &&
7398           "optionally flag setting instruction missing optional def operand");
7399    assert(MCID.NumOperands == Inst.getNumOperands() &&
7400           "operand count mismatch!");
7401    // Find the optional-def operand (cc_out).
7402    unsigned OpNo;
7403    for (OpNo = 0;
7404         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7405         ++OpNo)
7406      ;
7407    // If we're parsing Thumb1, reject it completely.
7408    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7409      return Match_MnemonicFail;
7410    // If we're parsing Thumb2, which form is legal depends on whether we're
7411    // in an IT block.
7412    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7413        !inITBlock())
7414      return Match_RequiresITBlock;
7415    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7416        inITBlock())
7417      return Match_RequiresNotITBlock;
7418  }
7419  // Some high-register supporting Thumb1 encodings only allow both registers
7420  // to be from r0-r7 when in Thumb2.
7421  else if (Opc == ARM::tADDhirr && isThumbOne() &&
7422           isARMLowRegister(Inst.getOperand(1).getReg()) &&
7423           isARMLowRegister(Inst.getOperand(2).getReg()))
7424    return Match_RequiresThumb2;
7425  // Others only require ARMv6 or later.
7426  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7427           isARMLowRegister(Inst.getOperand(0).getReg()) &&
7428           isARMLowRegister(Inst.getOperand(1).getReg()))
7429    return Match_RequiresV6;
7430  return Match_Success;
7431}
7432
7433static const char *getSubtargetFeatureName(unsigned Val);
7434bool ARMAsmParser::
7435MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7436                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7437                        MCStreamer &Out, unsigned &ErrorInfo,
7438                        bool MatchingInlineAsm) {
7439  MCInst Inst;
7440  unsigned MatchResult;
7441
7442  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7443                                     MatchingInlineAsm);
7444  switch (MatchResult) {
7445  default: break;
7446  case Match_Success:
7447    // Context sensitive operand constraints aren't handled by the matcher,
7448    // so check them here.
7449    if (validateInstruction(Inst, Operands)) {
7450      // Still progress the IT block, otherwise one wrong condition causes
7451      // nasty cascading errors.
7452      forwardITPosition();
7453      return true;
7454    }
7455
7456    // Some instructions need post-processing to, for example, tweak which
7457    // encoding is selected. Loop on it while changes happen so the
7458    // individual transformations can chain off each other. E.g.,
7459    // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7460    while (processInstruction(Inst, Operands))
7461      ;
7462
7463    // Only move forward at the very end so that everything in validate
7464    // and process gets a consistent answer about whether we're in an IT
7465    // block.
7466    forwardITPosition();
7467
7468    // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7469    // doesn't actually encode.
7470    if (Inst.getOpcode() == ARM::ITasm)
7471      return false;
7472
7473    Inst.setLoc(IDLoc);
7474    Out.EmitInstruction(Inst);
7475    return false;
7476  case Match_MissingFeature: {
7477    assert(ErrorInfo && "Unknown missing feature!");
7478    // Special case the error message for the very common case where only
7479    // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7480    std::string Msg = "instruction requires:";
7481    unsigned Mask = 1;
7482    for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7483      if (ErrorInfo & Mask) {
7484        Msg += " ";
7485        Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7486      }
7487      Mask <<= 1;
7488    }
7489    return Error(IDLoc, Msg);
7490  }
7491  case Match_InvalidOperand: {
7492    SMLoc ErrorLoc = IDLoc;
7493    if (ErrorInfo != ~0U) {
7494      if (ErrorInfo >= Operands.size())
7495        return Error(IDLoc, "too few operands for instruction");
7496
7497      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7498      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7499    }
7500
7501    return Error(ErrorLoc, "invalid operand for instruction");
7502  }
7503  case Match_MnemonicFail:
7504    return Error(IDLoc, "invalid instruction",
7505                 ((ARMOperand*)Operands[0])->getLocRange());
7506  case Match_RequiresNotITBlock:
7507    return Error(IDLoc, "flag setting instruction only valid outside IT block");
7508  case Match_RequiresITBlock:
7509    return Error(IDLoc, "instruction only valid inside IT block");
7510  case Match_RequiresV6:
7511    return Error(IDLoc, "instruction variant requires ARMv6 or later");
7512  case Match_RequiresThumb2:
7513    return Error(IDLoc, "instruction variant requires Thumb2");
7514  case Match_ImmRange0_4: {
7515    SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7516    if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7517    return Error(ErrorLoc, "immediate operand must be in the range [0,4]");
7518  }
7519  case Match_ImmRange0_15: {
7520    SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7521    if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7522    return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7523  }
7524  }
7525
7526  llvm_unreachable("Implement any new match types added!");
7527}
7528
7529/// parseDirective parses the arm specific directives
7530bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7531  StringRef IDVal = DirectiveID.getIdentifier();
7532  if (IDVal == ".word")
7533    return parseDirectiveWord(4, DirectiveID.getLoc());
7534  else if (IDVal == ".thumb")
7535    return parseDirectiveThumb(DirectiveID.getLoc());
7536  else if (IDVal == ".arm")
7537    return parseDirectiveARM(DirectiveID.getLoc());
7538  else if (IDVal == ".thumb_func")
7539    return parseDirectiveThumbFunc(DirectiveID.getLoc());
7540  else if (IDVal == ".code")
7541    return parseDirectiveCode(DirectiveID.getLoc());
7542  else if (IDVal == ".syntax")
7543    return parseDirectiveSyntax(DirectiveID.getLoc());
7544  else if (IDVal == ".unreq")
7545    return parseDirectiveUnreq(DirectiveID.getLoc());
7546  else if (IDVal == ".arch")
7547    return parseDirectiveArch(DirectiveID.getLoc());
7548  else if (IDVal == ".eabi_attribute")
7549    return parseDirectiveEabiAttr(DirectiveID.getLoc());
7550  else if (IDVal == ".fnstart")
7551    return parseDirectiveFnStart(DirectiveID.getLoc());
7552  else if (IDVal == ".fnend")
7553    return parseDirectiveFnEnd(DirectiveID.getLoc());
7554  else if (IDVal == ".cantunwind")
7555    return parseDirectiveCantUnwind(DirectiveID.getLoc());
7556  else if (IDVal == ".personality")
7557    return parseDirectivePersonality(DirectiveID.getLoc());
7558  else if (IDVal == ".handlerdata")
7559    return parseDirectiveHandlerData(DirectiveID.getLoc());
7560  else if (IDVal == ".setfp")
7561    return parseDirectiveSetFP(DirectiveID.getLoc());
7562  else if (IDVal == ".pad")
7563    return parseDirectivePad(DirectiveID.getLoc());
7564  else if (IDVal == ".save")
7565    return parseDirectiveRegSave(DirectiveID.getLoc(), false);
7566  else if (IDVal == ".vsave")
7567    return parseDirectiveRegSave(DirectiveID.getLoc(), true);
7568  return true;
7569}
7570
7571/// parseDirectiveWord
7572///  ::= .word [ expression (, expression)* ]
7573bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7574  if (getLexer().isNot(AsmToken::EndOfStatement)) {
7575    for (;;) {
7576      const MCExpr *Value;
7577      if (getParser().parseExpression(Value))
7578        return true;
7579
7580      getParser().getStreamer().EmitValue(Value, Size);
7581
7582      if (getLexer().is(AsmToken::EndOfStatement))
7583        break;
7584
7585      // FIXME: Improve diagnostic.
7586      if (getLexer().isNot(AsmToken::Comma))
7587        return Error(L, "unexpected token in directive");
7588      Parser.Lex();
7589    }
7590  }
7591
7592  Parser.Lex();
7593  return false;
7594}
7595
7596/// parseDirectiveThumb
7597///  ::= .thumb
7598bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7599  if (getLexer().isNot(AsmToken::EndOfStatement))
7600    return Error(L, "unexpected token in directive");
7601  Parser.Lex();
7602
7603  if (!hasThumb())
7604    return Error(L, "target does not support Thumb mode");
7605
7606  if (!isThumb())
7607    SwitchMode();
7608  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7609  return false;
7610}
7611
7612/// parseDirectiveARM
7613///  ::= .arm
7614bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7615  if (getLexer().isNot(AsmToken::EndOfStatement))
7616    return Error(L, "unexpected token in directive");
7617  Parser.Lex();
7618
7619  if (!hasARM())
7620    return Error(L, "target does not support ARM mode");
7621
7622  if (isThumb())
7623    SwitchMode();
7624  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7625  return false;
7626}
7627
7628/// parseDirectiveThumbFunc
7629///  ::= .thumbfunc symbol_name
7630bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7631  const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
7632  bool isMachO = MAI->hasSubsectionsViaSymbols();
7633  StringRef Name;
7634  bool needFuncName = true;
7635
7636  // Darwin asm has (optionally) function name after .thumb_func direction
7637  // ELF doesn't
7638  if (isMachO) {
7639    const AsmToken &Tok = Parser.getTok();
7640    if (Tok.isNot(AsmToken::EndOfStatement)) {
7641      if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7642        return Error(L, "unexpected token in .thumb_func directive");
7643      Name = Tok.getIdentifier();
7644      Parser.Lex(); // Consume the identifier token.
7645      needFuncName = false;
7646    }
7647  }
7648
7649  if (getLexer().isNot(AsmToken::EndOfStatement))
7650    return Error(L, "unexpected token in directive");
7651
7652  // Eat the end of statement and any blank lines that follow.
7653  while (getLexer().is(AsmToken::EndOfStatement))
7654    Parser.Lex();
7655
7656  // FIXME: assuming function name will be the line following .thumb_func
7657  // We really should be checking the next symbol definition even if there's
7658  // stuff in between.
7659  if (needFuncName) {
7660    Name = Parser.getTok().getIdentifier();
7661  }
7662
7663  // Mark symbol as a thumb symbol.
7664  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7665  getParser().getStreamer().EmitThumbFunc(Func);
7666  return false;
7667}
7668
7669/// parseDirectiveSyntax
7670///  ::= .syntax unified | divided
7671bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7672  const AsmToken &Tok = Parser.getTok();
7673  if (Tok.isNot(AsmToken::Identifier))
7674    return Error(L, "unexpected token in .syntax directive");
7675  StringRef Mode = Tok.getString();
7676  if (Mode == "unified" || Mode == "UNIFIED")
7677    Parser.Lex();
7678  else if (Mode == "divided" || Mode == "DIVIDED")
7679    return Error(L, "'.syntax divided' arm asssembly not supported");
7680  else
7681    return Error(L, "unrecognized syntax mode in .syntax directive");
7682
7683  if (getLexer().isNot(AsmToken::EndOfStatement))
7684    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7685  Parser.Lex();
7686
7687  // TODO tell the MC streamer the mode
7688  // getParser().getStreamer().Emit???();
7689  return false;
7690}
7691
7692/// parseDirectiveCode
7693///  ::= .code 16 | 32
7694bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7695  const AsmToken &Tok = Parser.getTok();
7696  if (Tok.isNot(AsmToken::Integer))
7697    return Error(L, "unexpected token in .code directive");
7698  int64_t Val = Parser.getTok().getIntVal();
7699  if (Val == 16)
7700    Parser.Lex();
7701  else if (Val == 32)
7702    Parser.Lex();
7703  else
7704    return Error(L, "invalid operand to .code directive");
7705
7706  if (getLexer().isNot(AsmToken::EndOfStatement))
7707    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7708  Parser.Lex();
7709
7710  if (Val == 16) {
7711    if (!hasThumb())
7712      return Error(L, "target does not support Thumb mode");
7713
7714    if (!isThumb())
7715      SwitchMode();
7716    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7717  } else {
7718    if (!hasARM())
7719      return Error(L, "target does not support ARM mode");
7720
7721    if (isThumb())
7722      SwitchMode();
7723    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7724  }
7725
7726  return false;
7727}
7728
7729/// parseDirectiveReq
7730///  ::= name .req registername
7731bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7732  Parser.Lex(); // Eat the '.req' token.
7733  unsigned Reg;
7734  SMLoc SRegLoc, ERegLoc;
7735  if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7736    Parser.eatToEndOfStatement();
7737    return Error(SRegLoc, "register name expected");
7738  }
7739
7740  // Shouldn't be anything else.
7741  if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7742    Parser.eatToEndOfStatement();
7743    return Error(Parser.getTok().getLoc(),
7744                 "unexpected input in .req directive.");
7745  }
7746
7747  Parser.Lex(); // Consume the EndOfStatement
7748
7749  if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7750    return Error(SRegLoc, "redefinition of '" + Name +
7751                          "' does not match original.");
7752
7753  return false;
7754}
7755
7756/// parseDirectiveUneq
7757///  ::= .unreq registername
7758bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7759  if (Parser.getTok().isNot(AsmToken::Identifier)) {
7760    Parser.eatToEndOfStatement();
7761    return Error(L, "unexpected input in .unreq directive.");
7762  }
7763  RegisterReqs.erase(Parser.getTok().getIdentifier());
7764  Parser.Lex(); // Eat the identifier.
7765  return false;
7766}
7767
7768/// parseDirectiveArch
7769///  ::= .arch token
7770bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7771  return true;
7772}
7773
7774/// parseDirectiveEabiAttr
7775///  ::= .eabi_attribute int, int
7776bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7777  return true;
7778}
7779
7780/// parseDirectiveFnStart
7781///  ::= .fnstart
7782bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
7783  if (FnStartLoc.isValid()) {
7784    Error(L, ".fnstart starts before the end of previous one");
7785    Error(FnStartLoc, "previous .fnstart starts here");
7786    return true;
7787  }
7788
7789  FnStartLoc = L;
7790  getParser().getStreamer().EmitFnStart();
7791  return false;
7792}
7793
7794/// parseDirectiveFnEnd
7795///  ::= .fnend
7796bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
7797  // Check the ordering of unwind directives
7798  if (!FnStartLoc.isValid())
7799    return Error(L, ".fnstart must precede .fnend directive");
7800
7801  // Reset the unwind directives parser state
7802  resetUnwindDirectiveParserState();
7803
7804  getParser().getStreamer().EmitFnEnd();
7805  return false;
7806}
7807
7808/// parseDirectiveCantUnwind
7809///  ::= .cantunwind
7810bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
7811  // Check the ordering of unwind directives
7812  CantUnwindLoc = L;
7813  if (!FnStartLoc.isValid())
7814    return Error(L, ".fnstart must precede .cantunwind directive");
7815  if (HandlerDataLoc.isValid()) {
7816    Error(L, ".cantunwind can't be used with .handlerdata directive");
7817    Error(HandlerDataLoc, ".handlerdata was specified here");
7818    return true;
7819  }
7820  if (PersonalityLoc.isValid()) {
7821    Error(L, ".cantunwind can't be used with .personality directive");
7822    Error(PersonalityLoc, ".personality was specified here");
7823    return true;
7824  }
7825
7826  getParser().getStreamer().EmitCantUnwind();
7827  return false;
7828}
7829
7830/// parseDirectivePersonality
7831///  ::= .personality name
7832bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
7833  // Check the ordering of unwind directives
7834  PersonalityLoc = L;
7835  if (!FnStartLoc.isValid())
7836    return Error(L, ".fnstart must precede .personality directive");
7837  if (CantUnwindLoc.isValid()) {
7838    Error(L, ".personality can't be used with .cantunwind directive");
7839    Error(CantUnwindLoc, ".cantunwind was specified here");
7840    return true;
7841  }
7842  if (HandlerDataLoc.isValid()) {
7843    Error(L, ".personality must precede .handlerdata directive");
7844    Error(HandlerDataLoc, ".handlerdata was specified here");
7845    return true;
7846  }
7847
7848  // Parse the name of the personality routine
7849  if (Parser.getTok().isNot(AsmToken::Identifier)) {
7850    Parser.eatToEndOfStatement();
7851    return Error(L, "unexpected input in .personality directive.");
7852  }
7853  StringRef Name(Parser.getTok().getIdentifier());
7854  Parser.Lex();
7855
7856  MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
7857  getParser().getStreamer().EmitPersonality(PR);
7858  return false;
7859}
7860
7861/// parseDirectiveHandlerData
7862///  ::= .handlerdata
7863bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
7864  // Check the ordering of unwind directives
7865  HandlerDataLoc = L;
7866  if (!FnStartLoc.isValid())
7867    return Error(L, ".fnstart must precede .personality directive");
7868  if (CantUnwindLoc.isValid()) {
7869    Error(L, ".handlerdata can't be used with .cantunwind directive");
7870    Error(CantUnwindLoc, ".cantunwind was specified here");
7871    return true;
7872  }
7873
7874  getParser().getStreamer().EmitHandlerData();
7875  return false;
7876}
7877
7878/// parseDirectiveSetFP
7879///  ::= .setfp fpreg, spreg [, offset]
7880bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
7881  // Check the ordering of unwind directives
7882  if (!FnStartLoc.isValid())
7883    return Error(L, ".fnstart must precede .setfp directive");
7884  if (HandlerDataLoc.isValid())
7885    return Error(L, ".setfp must precede .handlerdata directive");
7886
7887  // Parse fpreg
7888  SMLoc NewFPRegLoc = Parser.getTok().getLoc();
7889  int NewFPReg = tryParseRegister();
7890  if (NewFPReg == -1)
7891    return Error(NewFPRegLoc, "frame pointer register expected");
7892
7893  // Consume comma
7894  if (!Parser.getTok().is(AsmToken::Comma))
7895    return Error(Parser.getTok().getLoc(), "comma expected");
7896  Parser.Lex(); // skip comma
7897
7898  // Parse spreg
7899  SMLoc NewSPRegLoc = Parser.getTok().getLoc();
7900  int NewSPReg = tryParseRegister();
7901  if (NewSPReg == -1)
7902    return Error(NewSPRegLoc, "stack pointer register expected");
7903
7904  if (NewSPReg != ARM::SP && NewSPReg != FPReg)
7905    return Error(NewSPRegLoc,
7906                 "register should be either $sp or the latest fp register");
7907
7908  // Update the frame pointer register
7909  FPReg = NewFPReg;
7910
7911  // Parse offset
7912  int64_t Offset = 0;
7913  if (Parser.getTok().is(AsmToken::Comma)) {
7914    Parser.Lex(); // skip comma
7915
7916    if (Parser.getTok().isNot(AsmToken::Hash) &&
7917        Parser.getTok().isNot(AsmToken::Dollar)) {
7918      return Error(Parser.getTok().getLoc(), "'#' expected");
7919    }
7920    Parser.Lex(); // skip hash token.
7921
7922    const MCExpr *OffsetExpr;
7923    SMLoc ExLoc = Parser.getTok().getLoc();
7924    SMLoc EndLoc;
7925    if (getParser().parseExpression(OffsetExpr, EndLoc))
7926      return Error(ExLoc, "malformed setfp offset");
7927    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
7928    if (!CE)
7929      return Error(ExLoc, "setfp offset must be an immediate");
7930
7931    Offset = CE->getValue();
7932  }
7933
7934  getParser().getStreamer().EmitSetFP(static_cast<unsigned>(NewFPReg),
7935                                      static_cast<unsigned>(NewSPReg),
7936                                      Offset);
7937  return false;
7938}
7939
7940/// parseDirective
7941///  ::= .pad offset
7942bool ARMAsmParser::parseDirectivePad(SMLoc L) {
7943  // Check the ordering of unwind directives
7944  if (!FnStartLoc.isValid())
7945    return Error(L, ".fnstart must precede .pad directive");
7946  if (HandlerDataLoc.isValid())
7947    return Error(L, ".pad must precede .handlerdata directive");
7948
7949  // Parse the offset
7950  if (Parser.getTok().isNot(AsmToken::Hash) &&
7951      Parser.getTok().isNot(AsmToken::Dollar)) {
7952    return Error(Parser.getTok().getLoc(), "'#' expected");
7953  }
7954  Parser.Lex(); // skip hash token.
7955
7956  const MCExpr *OffsetExpr;
7957  SMLoc ExLoc = Parser.getTok().getLoc();
7958  SMLoc EndLoc;
7959  if (getParser().parseExpression(OffsetExpr, EndLoc))
7960    return Error(ExLoc, "malformed pad offset");
7961  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
7962  if (!CE)
7963    return Error(ExLoc, "pad offset must be an immediate");
7964
7965  getParser().getStreamer().EmitPad(CE->getValue());
7966  return false;
7967}
7968
7969/// parseDirectiveRegSave
7970///  ::= .save  { registers }
7971///  ::= .vsave { registers }
7972bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
7973  // Check the ordering of unwind directives
7974  if (!FnStartLoc.isValid())
7975    return Error(L, ".fnstart must precede .save or .vsave directives");
7976  if (HandlerDataLoc.isValid())
7977    return Error(L, ".save or .vsave must precede .handlerdata directive");
7978
7979  // Parse the register list
7980  SmallVector<MCParsedAsmOperand*, 1> Operands;
7981  if (parseRegisterList(Operands))
7982    return true;
7983  ARMOperand *Op = (ARMOperand*)Operands[0];
7984  if (!IsVector && !Op->isRegList())
7985    return Error(L, ".save expects GPR registers");
7986  if (IsVector && !Op->isDPRRegList())
7987    return Error(L, ".vsave expects DPR registers");
7988
7989  getParser().getStreamer().EmitRegSave(Op->getRegList(), IsVector);
7990  return false;
7991}
7992
7993/// Force static initialization.
7994extern "C" void LLVMInitializeARMAsmParser() {
7995  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
7996  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
7997}
7998
7999#define GET_REGISTER_MATCHER
8000#define GET_SUBTARGET_FEATURE_NAME
8001#define GET_MATCHER_IMPLEMENTATION
8002#include "ARMGenAsmMatcher.inc"
8003
8004// Define this matcher function after the auto-generated include so we
8005// have the match class enum definitions.
8006unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
8007                                                  unsigned Kind) {
8008  ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
8009  // If the kind is a token for a literal immediate, check if our asm
8010  // operand matches. This is for InstAliases which have a fixed-value
8011  // immediate in the syntax.
8012  if (Kind == MCK__35_0 && Op->isImm()) {
8013    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
8014    if (!CE)
8015      return Match_InvalidOperand;
8016    if (CE->getValue() == 0)
8017      return Match_Success;
8018  }
8019  return Match_InvalidOperand;
8020}
8021