ARMAsmParser.cpp revision 1b332860aef0121cf4591f4377a7201ce0ef8366 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/MCTargetAsmParser.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/SourceMgr.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/ADT/BitVector.h"
30#include "llvm/ADT/OwningPtr.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/StringSwitch.h"
34#include "llvm/ADT/Twine.h"
35
36using namespace llvm;
37
38namespace {
39
40class ARMOperand;
41
42class ARMAsmParser : public MCTargetAsmParser {
43  MCSubtargetInfo &STI;
44  MCAsmParser &Parser;
45
46  struct {
47    ARMCC::CondCodes Cond;    // Condition for IT block.
48    unsigned Mask:4;          // Condition mask for instructions.
49                              // Starting at first 1 (from lsb).
50                              //   '1'  condition as indicated in IT.
51                              //   '0'  inverse of condition (else).
52                              // Count of instructions in IT block is
53                              // 4 - trailingzeroes(mask)
54
55    bool FirstCond;           // Explicit flag for when we're parsing the
56                              // First instruction in the IT block. It's
57                              // implied in the mask, so needs special
58                              // handling.
59
60    unsigned CurPosition;     // Current position in parsing of IT
61                              // block. In range [0,3]. Initialized
62                              // according to count of instructions in block.
63                              // ~0U if no active IT block.
64  } ITState;
65  bool inITBlock() { return ITState.CurPosition != ~0U;}
66  void forwardITPosition() {
67    if (!inITBlock()) return;
68    // Move to the next instruction in the IT block, if there is one. If not,
69    // mark the block as done.
70    unsigned TZ = CountTrailingZeros_32(ITState.Mask);
71    if (++ITState.CurPosition == 5 - TZ)
72      ITState.CurPosition = ~0U; // Done with the IT block after this.
73  }
74
75
76  MCAsmParser &getParser() const { return Parser; }
77  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
78
79  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
80  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
81
82  int tryParseRegister();
83  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
84  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
85  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
86  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
87  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
88  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
89  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
90                              unsigned &ShiftAmount);
91  bool parseDirectiveWord(unsigned Size, SMLoc L);
92  bool parseDirectiveThumb(SMLoc L);
93  bool parseDirectiveThumbFunc(SMLoc L);
94  bool parseDirectiveCode(SMLoc L);
95  bool parseDirectiveSyntax(SMLoc L);
96
97  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
98                          bool &CarrySetting, unsigned &ProcessorIMod,
99                          StringRef &ITMask);
100  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
101                             bool &CanAcceptPredicationCode);
102
103  bool isThumb() const {
104    // FIXME: Can tablegen auto-generate this?
105    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
106  }
107  bool isThumbOne() const {
108    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
109  }
110  bool isThumbTwo() const {
111    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
112  }
113  bool hasV6Ops() const {
114    return STI.getFeatureBits() & ARM::HasV6Ops;
115  }
116  bool hasV7Ops() const {
117    return STI.getFeatureBits() & ARM::HasV7Ops;
118  }
119  void SwitchMode() {
120    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
121    setAvailableFeatures(FB);
122  }
123  bool isMClass() const {
124    return STI.getFeatureBits() & ARM::FeatureMClass;
125  }
126
127  /// @name Auto-generated Match Functions
128  /// {
129
130#define GET_ASSEMBLER_HEADER
131#include "ARMGenAsmMatcher.inc"
132
133  /// }
134
135  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
136  OperandMatchResultTy parseCoprocNumOperand(
137    SmallVectorImpl<MCParsedAsmOperand*>&);
138  OperandMatchResultTy parseCoprocRegOperand(
139    SmallVectorImpl<MCParsedAsmOperand*>&);
140  OperandMatchResultTy parseCoprocOptionOperand(
141    SmallVectorImpl<MCParsedAsmOperand*>&);
142  OperandMatchResultTy parseMemBarrierOptOperand(
143    SmallVectorImpl<MCParsedAsmOperand*>&);
144  OperandMatchResultTy parseProcIFlagsOperand(
145    SmallVectorImpl<MCParsedAsmOperand*>&);
146  OperandMatchResultTy parseMSRMaskOperand(
147    SmallVectorImpl<MCParsedAsmOperand*>&);
148  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
149                                   StringRef Op, int Low, int High);
150  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
151    return parsePKHImm(O, "lsl", 0, 31);
152  }
153  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
154    return parsePKHImm(O, "asr", 1, 32);
155  }
156  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
157  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
158  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
159  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
160  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
161  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
162  OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
163  OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
164
165  // Asm Match Converter Methods
166  bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
167                    const SmallVectorImpl<MCParsedAsmOperand*> &);
168  bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
169                    const SmallVectorImpl<MCParsedAsmOperand*> &);
170  bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
171                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
172  bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
173                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
174  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
175                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
176  bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
177                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
178  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
179                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
180  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
181                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
182  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
183                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
184  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
185                             const SmallVectorImpl<MCParsedAsmOperand*> &);
186  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
187                             const SmallVectorImpl<MCParsedAsmOperand*> &);
188  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
189                             const SmallVectorImpl<MCParsedAsmOperand*> &);
190  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
191                             const SmallVectorImpl<MCParsedAsmOperand*> &);
192  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
193                  const SmallVectorImpl<MCParsedAsmOperand*> &);
194  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
195                  const SmallVectorImpl<MCParsedAsmOperand*> &);
196  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
197                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
198  bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
199                        const SmallVectorImpl<MCParsedAsmOperand*> &);
200  bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
201                     const SmallVectorImpl<MCParsedAsmOperand*> &);
202  bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
203                        const SmallVectorImpl<MCParsedAsmOperand*> &);
204  bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
205                     const SmallVectorImpl<MCParsedAsmOperand*> &);
206  bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
207                        const SmallVectorImpl<MCParsedAsmOperand*> &);
208
209  bool validateInstruction(MCInst &Inst,
210                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
211  void processInstruction(MCInst &Inst,
212                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
213  bool shouldOmitCCOutOperand(StringRef Mnemonic,
214                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
215
216public:
217  enum ARMMatchResultTy {
218    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
219    Match_RequiresNotITBlock,
220    Match_RequiresV6,
221    Match_RequiresThumb2
222  };
223
224  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
225    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
226    MCAsmParserExtension::Initialize(_Parser);
227
228    // Initialize the set of available features.
229    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
230
231    // Not in an ITBlock to start with.
232    ITState.CurPosition = ~0U;
233  }
234
235  // Implementation of the MCTargetAsmParser interface:
236  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
237  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
238                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
239  bool ParseDirective(AsmToken DirectiveID);
240
241  unsigned checkTargetMatchPredicate(MCInst &Inst);
242
243  bool MatchAndEmitInstruction(SMLoc IDLoc,
244                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
245                               MCStreamer &Out);
246};
247} // end anonymous namespace
248
249namespace {
250
251/// ARMOperand - Instances of this class represent a parsed ARM machine
252/// instruction.
253class ARMOperand : public MCParsedAsmOperand {
254  enum KindTy {
255    k_CondCode,
256    k_CCOut,
257    k_ITCondMask,
258    k_CoprocNum,
259    k_CoprocReg,
260    k_CoprocOption,
261    k_Immediate,
262    k_FPImmediate,
263    k_MemBarrierOpt,
264    k_Memory,
265    k_PostIndexRegister,
266    k_MSRMask,
267    k_ProcIFlags,
268    k_VectorIndex,
269    k_Register,
270    k_RegisterList,
271    k_DPRRegisterList,
272    k_SPRRegisterList,
273    k_VectorList,
274    k_ShiftedRegister,
275    k_ShiftedImmediate,
276    k_ShifterImmediate,
277    k_RotateImmediate,
278    k_BitfieldDescriptor,
279    k_Token
280  } Kind;
281
282  SMLoc StartLoc, EndLoc;
283  SmallVector<unsigned, 8> Registers;
284
285  union {
286    struct {
287      ARMCC::CondCodes Val;
288    } CC;
289
290    struct {
291      unsigned Val;
292    } Cop;
293
294    struct {
295      unsigned Val;
296    } CoprocOption;
297
298    struct {
299      unsigned Mask:4;
300    } ITMask;
301
302    struct {
303      ARM_MB::MemBOpt Val;
304    } MBOpt;
305
306    struct {
307      ARM_PROC::IFlags Val;
308    } IFlags;
309
310    struct {
311      unsigned Val;
312    } MMask;
313
314    struct {
315      const char *Data;
316      unsigned Length;
317    } Tok;
318
319    struct {
320      unsigned RegNum;
321    } Reg;
322
323    // A vector register list is a sequential list of 1 to 4 registers.
324    struct {
325      unsigned RegNum;
326      unsigned Count;
327    } VectorList;
328
329    struct {
330      unsigned Val;
331    } VectorIndex;
332
333    struct {
334      const MCExpr *Val;
335    } Imm;
336
337    struct {
338      unsigned Val;       // encoded 8-bit representation
339    } FPImm;
340
341    /// Combined record for all forms of ARM address expressions.
342    struct {
343      unsigned BaseRegNum;
344      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
345      // was specified.
346      const MCConstantExpr *OffsetImm;  // Offset immediate value
347      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
348      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
349      unsigned ShiftImm;        // shift for OffsetReg.
350      unsigned Alignment;       // 0 = no alignment specified
351                                // n = alignment in bytes (8, 16, or 32)
352      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
353    } Memory;
354
355    struct {
356      unsigned RegNum;
357      bool isAdd;
358      ARM_AM::ShiftOpc ShiftTy;
359      unsigned ShiftImm;
360    } PostIdxReg;
361
362    struct {
363      bool isASR;
364      unsigned Imm;
365    } ShifterImm;
366    struct {
367      ARM_AM::ShiftOpc ShiftTy;
368      unsigned SrcReg;
369      unsigned ShiftReg;
370      unsigned ShiftImm;
371    } RegShiftedReg;
372    struct {
373      ARM_AM::ShiftOpc ShiftTy;
374      unsigned SrcReg;
375      unsigned ShiftImm;
376    } RegShiftedImm;
377    struct {
378      unsigned Imm;
379    } RotImm;
380    struct {
381      unsigned LSB;
382      unsigned Width;
383    } Bitfield;
384  };
385
386  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
387public:
388  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
389    Kind = o.Kind;
390    StartLoc = o.StartLoc;
391    EndLoc = o.EndLoc;
392    switch (Kind) {
393    case k_CondCode:
394      CC = o.CC;
395      break;
396    case k_ITCondMask:
397      ITMask = o.ITMask;
398      break;
399    case k_Token:
400      Tok = o.Tok;
401      break;
402    case k_CCOut:
403    case k_Register:
404      Reg = o.Reg;
405      break;
406    case k_RegisterList:
407    case k_DPRRegisterList:
408    case k_SPRRegisterList:
409      Registers = o.Registers;
410      break;
411    case k_VectorList:
412      VectorList = o.VectorList;
413      break;
414    case k_CoprocNum:
415    case k_CoprocReg:
416      Cop = o.Cop;
417      break;
418    case k_CoprocOption:
419      CoprocOption = o.CoprocOption;
420      break;
421    case k_Immediate:
422      Imm = o.Imm;
423      break;
424    case k_FPImmediate:
425      FPImm = o.FPImm;
426      break;
427    case k_MemBarrierOpt:
428      MBOpt = o.MBOpt;
429      break;
430    case k_Memory:
431      Memory = o.Memory;
432      break;
433    case k_PostIndexRegister:
434      PostIdxReg = o.PostIdxReg;
435      break;
436    case k_MSRMask:
437      MMask = o.MMask;
438      break;
439    case k_ProcIFlags:
440      IFlags = o.IFlags;
441      break;
442    case k_ShifterImmediate:
443      ShifterImm = o.ShifterImm;
444      break;
445    case k_ShiftedRegister:
446      RegShiftedReg = o.RegShiftedReg;
447      break;
448    case k_ShiftedImmediate:
449      RegShiftedImm = o.RegShiftedImm;
450      break;
451    case k_RotateImmediate:
452      RotImm = o.RotImm;
453      break;
454    case k_BitfieldDescriptor:
455      Bitfield = o.Bitfield;
456      break;
457    case k_VectorIndex:
458      VectorIndex = o.VectorIndex;
459      break;
460    }
461  }
462
463  /// getStartLoc - Get the location of the first token of this operand.
464  SMLoc getStartLoc() const { return StartLoc; }
465  /// getEndLoc - Get the location of the last token of this operand.
466  SMLoc getEndLoc() const { return EndLoc; }
467
468  ARMCC::CondCodes getCondCode() const {
469    assert(Kind == k_CondCode && "Invalid access!");
470    return CC.Val;
471  }
472
473  unsigned getCoproc() const {
474    assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
475    return Cop.Val;
476  }
477
478  StringRef getToken() const {
479    assert(Kind == k_Token && "Invalid access!");
480    return StringRef(Tok.Data, Tok.Length);
481  }
482
483  unsigned getReg() const {
484    assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
485    return Reg.RegNum;
486  }
487
488  const SmallVectorImpl<unsigned> &getRegList() const {
489    assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
490            Kind == k_SPRRegisterList) && "Invalid access!");
491    return Registers;
492  }
493
494  const MCExpr *getImm() const {
495    assert(Kind == k_Immediate && "Invalid access!");
496    return Imm.Val;
497  }
498
499  unsigned getFPImm() const {
500    assert(Kind == k_FPImmediate && "Invalid access!");
501    return FPImm.Val;
502  }
503
504  unsigned getVectorIndex() const {
505    assert(Kind == k_VectorIndex && "Invalid access!");
506    return VectorIndex.Val;
507  }
508
509  ARM_MB::MemBOpt getMemBarrierOpt() const {
510    assert(Kind == k_MemBarrierOpt && "Invalid access!");
511    return MBOpt.Val;
512  }
513
514  ARM_PROC::IFlags getProcIFlags() const {
515    assert(Kind == k_ProcIFlags && "Invalid access!");
516    return IFlags.Val;
517  }
518
519  unsigned getMSRMask() const {
520    assert(Kind == k_MSRMask && "Invalid access!");
521    return MMask.Val;
522  }
523
524  bool isCoprocNum() const { return Kind == k_CoprocNum; }
525  bool isCoprocReg() const { return Kind == k_CoprocReg; }
526  bool isCoprocOption() const { return Kind == k_CoprocOption; }
527  bool isCondCode() const { return Kind == k_CondCode; }
528  bool isCCOut() const { return Kind == k_CCOut; }
529  bool isITMask() const { return Kind == k_ITCondMask; }
530  bool isITCondCode() const { return Kind == k_CondCode; }
531  bool isImm() const { return Kind == k_Immediate; }
532  bool isFPImm() const { return Kind == k_FPImmediate; }
533  bool isImm8s4() const {
534    if (Kind != k_Immediate)
535      return false;
536    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
537    if (!CE) return false;
538    int64_t Value = CE->getValue();
539    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
540  }
541  bool isImm0_1020s4() const {
542    if (Kind != k_Immediate)
543      return false;
544    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
545    if (!CE) return false;
546    int64_t Value = CE->getValue();
547    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
548  }
549  bool isImm0_508s4() const {
550    if (Kind != k_Immediate)
551      return false;
552    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
553    if (!CE) return false;
554    int64_t Value = CE->getValue();
555    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
556  }
557  bool isImm0_255() const {
558    if (Kind != k_Immediate)
559      return false;
560    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
561    if (!CE) return false;
562    int64_t Value = CE->getValue();
563    return Value >= 0 && Value < 256;
564  }
565  bool isImm0_7() const {
566    if (Kind != k_Immediate)
567      return false;
568    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
569    if (!CE) return false;
570    int64_t Value = CE->getValue();
571    return Value >= 0 && Value < 8;
572  }
573  bool isImm0_15() const {
574    if (Kind != k_Immediate)
575      return false;
576    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
577    if (!CE) return false;
578    int64_t Value = CE->getValue();
579    return Value >= 0 && Value < 16;
580  }
581  bool isImm0_31() const {
582    if (Kind != k_Immediate)
583      return false;
584    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
585    if (!CE) return false;
586    int64_t Value = CE->getValue();
587    return Value >= 0 && Value < 32;
588  }
589  bool isImm1_16() const {
590    if (Kind != k_Immediate)
591      return false;
592    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
593    if (!CE) return false;
594    int64_t Value = CE->getValue();
595    return Value > 0 && Value < 17;
596  }
597  bool isImm1_32() const {
598    if (Kind != k_Immediate)
599      return false;
600    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
601    if (!CE) return false;
602    int64_t Value = CE->getValue();
603    return Value > 0 && Value < 33;
604  }
605  bool isImm0_32() const {
606    if (Kind != k_Immediate)
607      return false;
608    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
609    if (!CE) return false;
610    int64_t Value = CE->getValue();
611    return Value >= 0 && Value < 33;
612  }
613  bool isImm0_65535() const {
614    if (Kind != k_Immediate)
615      return false;
616    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
617    if (!CE) return false;
618    int64_t Value = CE->getValue();
619    return Value >= 0 && Value < 65536;
620  }
621  bool isImm0_65535Expr() const {
622    if (Kind != k_Immediate)
623      return false;
624    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
625    // If it's not a constant expression, it'll generate a fixup and be
626    // handled later.
627    if (!CE) return true;
628    int64_t Value = CE->getValue();
629    return Value >= 0 && Value < 65536;
630  }
631  bool isImm24bit() const {
632    if (Kind != k_Immediate)
633      return false;
634    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
635    if (!CE) return false;
636    int64_t Value = CE->getValue();
637    return Value >= 0 && Value <= 0xffffff;
638  }
639  bool isImmThumbSR() const {
640    if (Kind != k_Immediate)
641      return false;
642    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
643    if (!CE) return false;
644    int64_t Value = CE->getValue();
645    return Value > 0 && Value < 33;
646  }
647  bool isPKHLSLImm() const {
648    if (Kind != k_Immediate)
649      return false;
650    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
651    if (!CE) return false;
652    int64_t Value = CE->getValue();
653    return Value >= 0 && Value < 32;
654  }
655  bool isPKHASRImm() const {
656    if (Kind != k_Immediate)
657      return false;
658    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
659    if (!CE) return false;
660    int64_t Value = CE->getValue();
661    return Value > 0 && Value <= 32;
662  }
663  bool isARMSOImm() const {
664    if (Kind != k_Immediate)
665      return false;
666    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
667    if (!CE) return false;
668    int64_t Value = CE->getValue();
669    return ARM_AM::getSOImmVal(Value) != -1;
670  }
671  bool isARMSOImmNot() const {
672    if (Kind != k_Immediate)
673      return false;
674    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
675    if (!CE) return false;
676    int64_t Value = CE->getValue();
677    return ARM_AM::getSOImmVal(~Value) != -1;
678  }
679  bool isT2SOImm() const {
680    if (Kind != k_Immediate)
681      return false;
682    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
683    if (!CE) return false;
684    int64_t Value = CE->getValue();
685    return ARM_AM::getT2SOImmVal(Value) != -1;
686  }
687  bool isT2SOImmNot() const {
688    if (Kind != k_Immediate)
689      return false;
690    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
691    if (!CE) return false;
692    int64_t Value = CE->getValue();
693    return ARM_AM::getT2SOImmVal(~Value) != -1;
694  }
695  bool isSetEndImm() const {
696    if (Kind != k_Immediate)
697      return false;
698    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
699    if (!CE) return false;
700    int64_t Value = CE->getValue();
701    return Value == 1 || Value == 0;
702  }
703  bool isReg() const { return Kind == k_Register; }
704  bool isRegList() const { return Kind == k_RegisterList; }
705  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
706  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
707  bool isToken() const { return Kind == k_Token; }
708  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
709  bool isMemory() const { return Kind == k_Memory; }
710  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
711  bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
712  bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
713  bool isRotImm() const { return Kind == k_RotateImmediate; }
714  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
715  bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
716  bool isPostIdxReg() const {
717    return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
718  }
719  bool isMemNoOffset(bool alignOK = false) const {
720    if (!isMemory())
721      return false;
722    // No offset of any kind.
723    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
724     (alignOK || Memory.Alignment == 0);
725  }
726  bool isAlignedMemory() const {
727    return isMemNoOffset(true);
728  }
729  bool isAddrMode2() const {
730    if (!isMemory() || Memory.Alignment != 0) return false;
731    // Check for register offset.
732    if (Memory.OffsetRegNum) return true;
733    // Immediate offset in range [-4095, 4095].
734    if (!Memory.OffsetImm) return true;
735    int64_t Val = Memory.OffsetImm->getValue();
736    return Val > -4096 && Val < 4096;
737  }
738  bool isAM2OffsetImm() const {
739    if (Kind != k_Immediate)
740      return false;
741    // Immediate offset in range [-4095, 4095].
742    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
743    if (!CE) return false;
744    int64_t Val = CE->getValue();
745    return Val > -4096 && Val < 4096;
746  }
747  bool isAddrMode3() const {
748    if (!isMemory() || Memory.Alignment != 0) return false;
749    // No shifts are legal for AM3.
750    if (Memory.ShiftType != ARM_AM::no_shift) return false;
751    // Check for register offset.
752    if (Memory.OffsetRegNum) return true;
753    // Immediate offset in range [-255, 255].
754    if (!Memory.OffsetImm) return true;
755    int64_t Val = Memory.OffsetImm->getValue();
756    return Val > -256 && Val < 256;
757  }
758  bool isAM3Offset() const {
759    if (Kind != k_Immediate && Kind != k_PostIndexRegister)
760      return false;
761    if (Kind == k_PostIndexRegister)
762      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
763    // Immediate offset in range [-255, 255].
764    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
765    if (!CE) return false;
766    int64_t Val = CE->getValue();
767    // Special case, #-0 is INT32_MIN.
768    return (Val > -256 && Val < 256) || Val == INT32_MIN;
769  }
770  bool isAddrMode5() const {
771    // If we have an immediate that's not a constant, treat it as a label
772    // reference needing a fixup. If it is a constant, it's something else
773    // and we reject it.
774    if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
775      return true;
776    if (!isMemory() || Memory.Alignment != 0) return false;
777    // Check for register offset.
778    if (Memory.OffsetRegNum) return false;
779    // Immediate offset in range [-1020, 1020] and a multiple of 4.
780    if (!Memory.OffsetImm) return true;
781    int64_t Val = Memory.OffsetImm->getValue();
782    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
783      Val == INT32_MIN;
784  }
785  bool isMemTBB() const {
786    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
787        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
788      return false;
789    return true;
790  }
791  bool isMemTBH() const {
792    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
793        Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
794        Memory.Alignment != 0 )
795      return false;
796    return true;
797  }
798  bool isMemRegOffset() const {
799    if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
800      return false;
801    return true;
802  }
803  bool isT2MemRegOffset() const {
804    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
805        Memory.Alignment != 0)
806      return false;
807    // Only lsl #{0, 1, 2, 3} allowed.
808    if (Memory.ShiftType == ARM_AM::no_shift)
809      return true;
810    if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
811      return false;
812    return true;
813  }
814  bool isMemThumbRR() const {
815    // Thumb reg+reg addressing is simple. Just two registers, a base and
816    // an offset. No shifts, negations or any other complicating factors.
817    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
818        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
819      return false;
820    return isARMLowRegister(Memory.BaseRegNum) &&
821      (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
822  }
823  bool isMemThumbRIs4() const {
824    if (!isMemory() || Memory.OffsetRegNum != 0 ||
825        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
826      return false;
827    // Immediate offset, multiple of 4 in range [0, 124].
828    if (!Memory.OffsetImm) return true;
829    int64_t Val = Memory.OffsetImm->getValue();
830    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
831  }
832  bool isMemThumbRIs2() const {
833    if (!isMemory() || Memory.OffsetRegNum != 0 ||
834        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
835      return false;
836    // Immediate offset, multiple of 4 in range [0, 62].
837    if (!Memory.OffsetImm) return true;
838    int64_t Val = Memory.OffsetImm->getValue();
839    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
840  }
841  bool isMemThumbRIs1() const {
842    if (!isMemory() || Memory.OffsetRegNum != 0 ||
843        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
844      return false;
845    // Immediate offset in range [0, 31].
846    if (!Memory.OffsetImm) return true;
847    int64_t Val = Memory.OffsetImm->getValue();
848    return Val >= 0 && Val <= 31;
849  }
850  bool isMemThumbSPI() const {
851    if (!isMemory() || Memory.OffsetRegNum != 0 ||
852        Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
853      return false;
854    // Immediate offset, multiple of 4 in range [0, 1020].
855    if (!Memory.OffsetImm) return true;
856    int64_t Val = Memory.OffsetImm->getValue();
857    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
858  }
859  bool isMemImm8s4Offset() const {
860    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
861      return false;
862    // Immediate offset a multiple of 4 in range [-1020, 1020].
863    if (!Memory.OffsetImm) return true;
864    int64_t Val = Memory.OffsetImm->getValue();
865    return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
866  }
867  bool isMemImm0_1020s4Offset() const {
868    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
869      return false;
870    // Immediate offset a multiple of 4 in range [0, 1020].
871    if (!Memory.OffsetImm) return true;
872    int64_t Val = Memory.OffsetImm->getValue();
873    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
874  }
875  bool isMemImm8Offset() const {
876    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
877      return false;
878    // Immediate offset in range [-255, 255].
879    if (!Memory.OffsetImm) return true;
880    int64_t Val = Memory.OffsetImm->getValue();
881    return (Val == INT32_MIN) || (Val > -256 && Val < 256);
882  }
883  bool isMemPosImm8Offset() const {
884    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
885      return false;
886    // Immediate offset in range [0, 255].
887    if (!Memory.OffsetImm) return true;
888    int64_t Val = Memory.OffsetImm->getValue();
889    return Val >= 0 && Val < 256;
890  }
891  bool isMemNegImm8Offset() const {
892    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
893      return false;
894    // Immediate offset in range [-255, -1].
895    if (!Memory.OffsetImm) return true;
896    int64_t Val = Memory.OffsetImm->getValue();
897    return Val > -256 && Val < 0;
898  }
899  bool isMemUImm12Offset() const {
900    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
901      return false;
902    // Immediate offset in range [0, 4095].
903    if (!Memory.OffsetImm) return true;
904    int64_t Val = Memory.OffsetImm->getValue();
905    return (Val >= 0 && Val < 4096);
906  }
907  bool isMemImm12Offset() const {
908    // If we have an immediate that's not a constant, treat it as a label
909    // reference needing a fixup. If it is a constant, it's something else
910    // and we reject it.
911    if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
912      return true;
913
914    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
915      return false;
916    // Immediate offset in range [-4095, 4095].
917    if (!Memory.OffsetImm) return true;
918    int64_t Val = Memory.OffsetImm->getValue();
919    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
920  }
921  bool isPostIdxImm8() const {
922    if (Kind != k_Immediate)
923      return false;
924    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
925    if (!CE) return false;
926    int64_t Val = CE->getValue();
927    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
928  }
929  bool isPostIdxImm8s4() const {
930    if (Kind != k_Immediate)
931      return false;
932    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
933    if (!CE) return false;
934    int64_t Val = CE->getValue();
935    return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
936      (Val == INT32_MIN);
937  }
938
939  bool isMSRMask() const { return Kind == k_MSRMask; }
940  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
941
942  // NEON operands.
943  bool isVecListOneD() const {
944    if (Kind != k_VectorList) return false;
945    return VectorList.Count == 1;
946  }
947
948  bool isVecListTwoD() const {
949    if (Kind != k_VectorList) return false;
950    return VectorList.Count == 2;
951  }
952
953  bool isVecListThreeD() const {
954    if (Kind != k_VectorList) return false;
955    return VectorList.Count == 3;
956  }
957
958  bool isVecListFourD() const {
959    if (Kind != k_VectorList) return false;
960    return VectorList.Count == 4;
961  }
962
963  bool isVecListTwoQ() const {
964    if (Kind != k_VectorList) return false;
965    //FIXME: We haven't taught the parser to handle by-two register lists
966    // yet, so don't pretend to know one.
967    return VectorList.Count == 2 && false;
968  }
969
970  bool isVectorIndex8() const {
971    if (Kind != k_VectorIndex) return false;
972    return VectorIndex.Val < 8;
973  }
974  bool isVectorIndex16() const {
975    if (Kind != k_VectorIndex) return false;
976    return VectorIndex.Val < 4;
977  }
978  bool isVectorIndex32() const {
979    if (Kind != k_VectorIndex) return false;
980    return VectorIndex.Val < 2;
981  }
982
983  bool isNEONi8splat() const {
984    if (Kind != k_Immediate)
985      return false;
986    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
987    // Must be a constant.
988    if (!CE) return false;
989    int64_t Value = CE->getValue();
990    // i8 value splatted across 8 bytes. The immediate is just the 8 byte
991    // value.
992    return Value >= 0 && Value < 256;
993  }
994
995  bool isNEONi16splat() const {
996    if (Kind != k_Immediate)
997      return false;
998    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
999    // Must be a constant.
1000    if (!CE) return false;
1001    int64_t Value = CE->getValue();
1002    // i16 value in the range [0,255] or [0x0100, 0xff00]
1003    return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1004  }
1005
1006  bool isNEONi32splat() const {
1007    if (Kind != k_Immediate)
1008      return false;
1009    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1010    // Must be a constant.
1011    if (!CE) return false;
1012    int64_t Value = CE->getValue();
1013    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1014    return (Value >= 0 && Value < 256) ||
1015      (Value >= 0x0100 && Value <= 0xff00) ||
1016      (Value >= 0x010000 && Value <= 0xff0000) ||
1017      (Value >= 0x01000000 && Value <= 0xff000000);
1018  }
1019
1020  bool isNEONi32vmov() const {
1021    if (Kind != k_Immediate)
1022      return false;
1023    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1024    // Must be a constant.
1025    if (!CE) return false;
1026    int64_t Value = CE->getValue();
1027    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1028    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1029    return (Value >= 0 && Value < 256) ||
1030      (Value >= 0x0100 && Value <= 0xff00) ||
1031      (Value >= 0x010000 && Value <= 0xff0000) ||
1032      (Value >= 0x01000000 && Value <= 0xff000000) ||
1033      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1034      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1035  }
1036
1037  bool isNEONi64splat() const {
1038    if (Kind != k_Immediate)
1039      return false;
1040    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1041    // Must be a constant.
1042    if (!CE) return false;
1043    uint64_t Value = CE->getValue();
1044    // i64 value with each byte being either 0 or 0xff.
1045    for (unsigned i = 0; i < 8; ++i)
1046      if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1047    return true;
1048  }
1049
1050  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1051    // Add as immediates when possible.  Null MCExpr = 0.
1052    if (Expr == 0)
1053      Inst.addOperand(MCOperand::CreateImm(0));
1054    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1055      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1056    else
1057      Inst.addOperand(MCOperand::CreateExpr(Expr));
1058  }
1059
1060  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1061    assert(N == 2 && "Invalid number of operands!");
1062    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1063    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1064    Inst.addOperand(MCOperand::CreateReg(RegNum));
1065  }
1066
1067  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1068    assert(N == 1 && "Invalid number of operands!");
1069    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1070  }
1071
1072  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1073    assert(N == 1 && "Invalid number of operands!");
1074    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1075  }
1076
1077  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1078    assert(N == 1 && "Invalid number of operands!");
1079    Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1080  }
1081
1082  void addITMaskOperands(MCInst &Inst, unsigned N) const {
1083    assert(N == 1 && "Invalid number of operands!");
1084    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1085  }
1086
1087  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1088    assert(N == 1 && "Invalid number of operands!");
1089    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1090  }
1091
1092  void addCCOutOperands(MCInst &Inst, unsigned N) const {
1093    assert(N == 1 && "Invalid number of operands!");
1094    Inst.addOperand(MCOperand::CreateReg(getReg()));
1095  }
1096
1097  void addRegOperands(MCInst &Inst, unsigned N) const {
1098    assert(N == 1 && "Invalid number of operands!");
1099    Inst.addOperand(MCOperand::CreateReg(getReg()));
1100  }
1101
1102  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1103    assert(N == 3 && "Invalid number of operands!");
1104    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
1105    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1106    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1107    Inst.addOperand(MCOperand::CreateImm(
1108      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1109  }
1110
1111  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1112    assert(N == 2 && "Invalid number of operands!");
1113    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
1114    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1115    Inst.addOperand(MCOperand::CreateImm(
1116      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
1117  }
1118
1119  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1120    assert(N == 1 && "Invalid number of operands!");
1121    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1122                                         ShifterImm.Imm));
1123  }
1124
1125  void addRegListOperands(MCInst &Inst, unsigned N) const {
1126    assert(N == 1 && "Invalid number of operands!");
1127    const SmallVectorImpl<unsigned> &RegList = getRegList();
1128    for (SmallVectorImpl<unsigned>::const_iterator
1129           I = RegList.begin(), E = RegList.end(); I != E; ++I)
1130      Inst.addOperand(MCOperand::CreateReg(*I));
1131  }
1132
1133  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1134    addRegListOperands(Inst, N);
1135  }
1136
1137  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1138    addRegListOperands(Inst, N);
1139  }
1140
1141  void addRotImmOperands(MCInst &Inst, unsigned N) const {
1142    assert(N == 1 && "Invalid number of operands!");
1143    // Encoded as val>>3. The printer handles display as 8, 16, 24.
1144    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1145  }
1146
1147  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1148    assert(N == 1 && "Invalid number of operands!");
1149    // Munge the lsb/width into a bitfield mask.
1150    unsigned lsb = Bitfield.LSB;
1151    unsigned width = Bitfield.Width;
1152    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1153    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1154                      (32 - (lsb + width)));
1155    Inst.addOperand(MCOperand::CreateImm(Mask));
1156  }
1157
1158  void addImmOperands(MCInst &Inst, unsigned N) const {
1159    assert(N == 1 && "Invalid number of operands!");
1160    addExpr(Inst, getImm());
1161  }
1162
1163  void addFPImmOperands(MCInst &Inst, unsigned N) const {
1164    assert(N == 1 && "Invalid number of operands!");
1165    Inst.addOperand(MCOperand::CreateImm(getFPImm()));
1166  }
1167
1168  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1169    assert(N == 1 && "Invalid number of operands!");
1170    // FIXME: We really want to scale the value here, but the LDRD/STRD
1171    // instruction don't encode operands that way yet.
1172    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1173    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1174  }
1175
1176  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1177    assert(N == 1 && "Invalid number of operands!");
1178    // The immediate is scaled by four in the encoding and is stored
1179    // in the MCInst as such. Lop off the low two bits here.
1180    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1181    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1182  }
1183
1184  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1185    assert(N == 1 && "Invalid number of operands!");
1186    // The immediate is scaled by four in the encoding and is stored
1187    // in the MCInst as such. Lop off the low two bits here.
1188    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1189    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1190  }
1191
1192  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
1193    assert(N == 1 && "Invalid number of operands!");
1194    addExpr(Inst, getImm());
1195  }
1196
1197  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
1198    assert(N == 1 && "Invalid number of operands!");
1199    addExpr(Inst, getImm());
1200  }
1201
1202  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
1203    assert(N == 1 && "Invalid number of operands!");
1204    addExpr(Inst, getImm());
1205  }
1206
1207  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
1208    assert(N == 1 && "Invalid number of operands!");
1209    addExpr(Inst, getImm());
1210  }
1211
1212  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1213    assert(N == 1 && "Invalid number of operands!");
1214    // The constant encodes as the immediate-1, and we store in the instruction
1215    // the bits as encoded, so subtract off one here.
1216    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1217    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1218  }
1219
1220  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1221    assert(N == 1 && "Invalid number of operands!");
1222    // The constant encodes as the immediate-1, and we store in the instruction
1223    // the bits as encoded, so subtract off one here.
1224    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1225    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1226  }
1227
1228  void addImm0_32Operands(MCInst &Inst, unsigned N) const {
1229    assert(N == 1 && "Invalid number of operands!");
1230    addExpr(Inst, getImm());
1231  }
1232
1233  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
1234    assert(N == 1 && "Invalid number of operands!");
1235    addExpr(Inst, getImm());
1236  }
1237
1238  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
1239    assert(N == 1 && "Invalid number of operands!");
1240    addExpr(Inst, getImm());
1241  }
1242
1243  void addImm24bitOperands(MCInst &Inst, unsigned N) const {
1244    assert(N == 1 && "Invalid number of operands!");
1245    addExpr(Inst, getImm());
1246  }
1247
1248  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1249    assert(N == 1 && "Invalid number of operands!");
1250    // The constant encodes as the immediate, except for 32, which encodes as
1251    // zero.
1252    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1253    unsigned Imm = CE->getValue();
1254    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1255  }
1256
1257  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
1258    assert(N == 1 && "Invalid number of operands!");
1259    addExpr(Inst, getImm());
1260  }
1261
1262  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1263    assert(N == 1 && "Invalid number of operands!");
1264    // An ASR value of 32 encodes as 0, so that's how we want to add it to
1265    // the instruction as well.
1266    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1267    int Val = CE->getValue();
1268    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1269  }
1270
1271  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
1272    assert(N == 1 && "Invalid number of operands!");
1273    addExpr(Inst, getImm());
1274  }
1275
1276  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
1277    assert(N == 1 && "Invalid number of operands!");
1278    addExpr(Inst, getImm());
1279  }
1280
1281  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1282    assert(N == 1 && "Invalid number of operands!");
1283    // The operand is actually a t2_so_imm, but we have its bitwise
1284    // negation in the assembly source, so twiddle it here.
1285    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1286    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1287  }
1288
1289  void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1290    assert(N == 1 && "Invalid number of operands!");
1291    // The operand is actually a so_imm, but we have its bitwise
1292    // negation in the assembly source, so twiddle it here.
1293    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1294    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1295  }
1296
1297  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
1298    assert(N == 1 && "Invalid number of operands!");
1299    addExpr(Inst, getImm());
1300  }
1301
1302  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1303    assert(N == 1 && "Invalid number of operands!");
1304    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1305  }
1306
1307  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1308    assert(N == 1 && "Invalid number of operands!");
1309    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1310  }
1311
1312  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1313    assert(N == 2 && "Invalid number of operands!");
1314    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1315    Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1316  }
1317
1318  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1319    assert(N == 3 && "Invalid number of operands!");
1320    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1321    if (!Memory.OffsetRegNum) {
1322      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1323      // Special case for #-0
1324      if (Val == INT32_MIN) Val = 0;
1325      if (Val < 0) Val = -Val;
1326      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1327    } else {
1328      // For register offset, we encode the shift type and negation flag
1329      // here.
1330      Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1331                              Memory.ShiftImm, Memory.ShiftType);
1332    }
1333    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1334    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1335    Inst.addOperand(MCOperand::CreateImm(Val));
1336  }
1337
1338  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1339    assert(N == 2 && "Invalid number of operands!");
1340    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1341    assert(CE && "non-constant AM2OffsetImm operand!");
1342    int32_t Val = CE->getValue();
1343    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1344    // Special case for #-0
1345    if (Val == INT32_MIN) Val = 0;
1346    if (Val < 0) Val = -Val;
1347    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1348    Inst.addOperand(MCOperand::CreateReg(0));
1349    Inst.addOperand(MCOperand::CreateImm(Val));
1350  }
1351
1352  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1353    assert(N == 3 && "Invalid number of operands!");
1354    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1355    if (!Memory.OffsetRegNum) {
1356      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1357      // Special case for #-0
1358      if (Val == INT32_MIN) Val = 0;
1359      if (Val < 0) Val = -Val;
1360      Val = ARM_AM::getAM3Opc(AddSub, Val);
1361    } else {
1362      // For register offset, we encode the shift type and negation flag
1363      // here.
1364      Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1365    }
1366    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1367    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1368    Inst.addOperand(MCOperand::CreateImm(Val));
1369  }
1370
1371  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1372    assert(N == 2 && "Invalid number of operands!");
1373    if (Kind == k_PostIndexRegister) {
1374      int32_t Val =
1375        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1376      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1377      Inst.addOperand(MCOperand::CreateImm(Val));
1378      return;
1379    }
1380
1381    // Constant offset.
1382    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1383    int32_t Val = CE->getValue();
1384    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1385    // Special case for #-0
1386    if (Val == INT32_MIN) Val = 0;
1387    if (Val < 0) Val = -Val;
1388    Val = ARM_AM::getAM3Opc(AddSub, Val);
1389    Inst.addOperand(MCOperand::CreateReg(0));
1390    Inst.addOperand(MCOperand::CreateImm(Val));
1391  }
1392
1393  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1394    assert(N == 2 && "Invalid number of operands!");
1395    // If we have an immediate that's not a constant, treat it as a label
1396    // reference needing a fixup. If it is a constant, it's something else
1397    // and we reject it.
1398    if (isImm()) {
1399      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1400      Inst.addOperand(MCOperand::CreateImm(0));
1401      return;
1402    }
1403
1404    // The lower two bits are always zero and as such are not encoded.
1405    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1406    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1407    // Special case for #-0
1408    if (Val == INT32_MIN) Val = 0;
1409    if (Val < 0) Val = -Val;
1410    Val = ARM_AM::getAM5Opc(AddSub, Val);
1411    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1412    Inst.addOperand(MCOperand::CreateImm(Val));
1413  }
1414
1415  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1416    assert(N == 2 && "Invalid number of operands!");
1417    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1418    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1419    Inst.addOperand(MCOperand::CreateImm(Val));
1420  }
1421
1422  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1423    assert(N == 2 && "Invalid number of operands!");
1424    // The lower two bits are always zero and as such are not encoded.
1425    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1426    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1427    Inst.addOperand(MCOperand::CreateImm(Val));
1428  }
1429
1430  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1431    assert(N == 2 && "Invalid number of operands!");
1432    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1433    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1434    Inst.addOperand(MCOperand::CreateImm(Val));
1435  }
1436
1437  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1438    addMemImm8OffsetOperands(Inst, N);
1439  }
1440
1441  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1442    addMemImm8OffsetOperands(Inst, N);
1443  }
1444
1445  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1446    assert(N == 2 && "Invalid number of operands!");
1447    // If this is an immediate, it's a label reference.
1448    if (Kind == k_Immediate) {
1449      addExpr(Inst, getImm());
1450      Inst.addOperand(MCOperand::CreateImm(0));
1451      return;
1452    }
1453
1454    // Otherwise, it's a normal memory reg+offset.
1455    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1456    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1457    Inst.addOperand(MCOperand::CreateImm(Val));
1458  }
1459
1460  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1461    assert(N == 2 && "Invalid number of operands!");
1462    // If this is an immediate, it's a label reference.
1463    if (Kind == k_Immediate) {
1464      addExpr(Inst, getImm());
1465      Inst.addOperand(MCOperand::CreateImm(0));
1466      return;
1467    }
1468
1469    // Otherwise, it's a normal memory reg+offset.
1470    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1471    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1472    Inst.addOperand(MCOperand::CreateImm(Val));
1473  }
1474
1475  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1476    assert(N == 2 && "Invalid number of operands!");
1477    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1478    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1479  }
1480
1481  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1482    assert(N == 2 && "Invalid number of operands!");
1483    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1484    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1485  }
1486
1487  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1488    assert(N == 3 && "Invalid number of operands!");
1489    unsigned Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1490                                     Memory.ShiftImm, Memory.ShiftType);
1491    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1492    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1493    Inst.addOperand(MCOperand::CreateImm(Val));
1494  }
1495
1496  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1497    assert(N == 3 && "Invalid number of operands!");
1498    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1499    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1500    Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1501  }
1502
1503  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1504    assert(N == 2 && "Invalid number of operands!");
1505    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1506    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1507  }
1508
1509  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1510    assert(N == 2 && "Invalid number of operands!");
1511    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1512    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1513    Inst.addOperand(MCOperand::CreateImm(Val));
1514  }
1515
1516  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1517    assert(N == 2 && "Invalid number of operands!");
1518    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1519    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1520    Inst.addOperand(MCOperand::CreateImm(Val));
1521  }
1522
1523  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1524    assert(N == 2 && "Invalid number of operands!");
1525    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1526    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1527    Inst.addOperand(MCOperand::CreateImm(Val));
1528  }
1529
1530  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1531    assert(N == 2 && "Invalid number of operands!");
1532    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1533    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1534    Inst.addOperand(MCOperand::CreateImm(Val));
1535  }
1536
1537  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1538    assert(N == 1 && "Invalid number of operands!");
1539    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1540    assert(CE && "non-constant post-idx-imm8 operand!");
1541    int Imm = CE->getValue();
1542    bool isAdd = Imm >= 0;
1543    if (Imm == INT32_MIN) Imm = 0;
1544    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1545    Inst.addOperand(MCOperand::CreateImm(Imm));
1546  }
1547
1548  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1549    assert(N == 1 && "Invalid number of operands!");
1550    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1551    assert(CE && "non-constant post-idx-imm8s4 operand!");
1552    int Imm = CE->getValue();
1553    bool isAdd = Imm >= 0;
1554    if (Imm == INT32_MIN) Imm = 0;
1555    // Immediate is scaled by 4.
1556    Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1557    Inst.addOperand(MCOperand::CreateImm(Imm));
1558  }
1559
1560  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1561    assert(N == 2 && "Invalid number of operands!");
1562    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1563    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1564  }
1565
1566  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1567    assert(N == 2 && "Invalid number of operands!");
1568    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1569    // The sign, shift type, and shift amount are encoded in a single operand
1570    // using the AM2 encoding helpers.
1571    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1572    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1573                                     PostIdxReg.ShiftTy);
1574    Inst.addOperand(MCOperand::CreateImm(Imm));
1575  }
1576
1577  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1578    assert(N == 1 && "Invalid number of operands!");
1579    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1580  }
1581
1582  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1583    assert(N == 1 && "Invalid number of operands!");
1584    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1585  }
1586
1587  void addVecListOneDOperands(MCInst &Inst, unsigned N) const {
1588    assert(N == 1 && "Invalid number of operands!");
1589    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1590  }
1591
1592  void addVecListTwoDOperands(MCInst &Inst, unsigned N) const {
1593    assert(N == 1 && "Invalid number of operands!");
1594    // Only the first register actually goes on the instruction. The rest
1595    // are implied by the opcode.
1596    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1597  }
1598
1599  void addVecListThreeDOperands(MCInst &Inst, unsigned N) const {
1600    assert(N == 1 && "Invalid number of operands!");
1601    // Only the first register actually goes on the instruction. The rest
1602    // are implied by the opcode.
1603    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1604  }
1605
1606  void addVecListFourDOperands(MCInst &Inst, unsigned N) const {
1607    assert(N == 1 && "Invalid number of operands!");
1608    // Only the first register actually goes on the instruction. The rest
1609    // are implied by the opcode.
1610    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1611  }
1612
1613  void addVecListTwoQOperands(MCInst &Inst, unsigned N) const {
1614    assert(N == 1 && "Invalid number of operands!");
1615    // Only the first register actually goes on the instruction. The rest
1616    // are implied by the opcode.
1617    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1618  }
1619
1620  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1621    assert(N == 1 && "Invalid number of operands!");
1622    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1623  }
1624
1625  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1626    assert(N == 1 && "Invalid number of operands!");
1627    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1628  }
1629
1630  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1631    assert(N == 1 && "Invalid number of operands!");
1632    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1633  }
1634
1635  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1636    assert(N == 1 && "Invalid number of operands!");
1637    // The immediate encodes the type of constant as well as the value.
1638    // Mask in that this is an i8 splat.
1639    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1640    Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1641  }
1642
1643  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1644    assert(N == 1 && "Invalid number of operands!");
1645    // The immediate encodes the type of constant as well as the value.
1646    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1647    unsigned Value = CE->getValue();
1648    if (Value >= 256)
1649      Value = (Value >> 8) | 0xa00;
1650    else
1651      Value |= 0x800;
1652    Inst.addOperand(MCOperand::CreateImm(Value));
1653  }
1654
1655  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
1656    assert(N == 1 && "Invalid number of operands!");
1657    // The immediate encodes the type of constant as well as the value.
1658    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1659    unsigned Value = CE->getValue();
1660    if (Value >= 256 && Value <= 0xff00)
1661      Value = (Value >> 8) | 0x200;
1662    else if (Value > 0xffff && Value <= 0xff0000)
1663      Value = (Value >> 16) | 0x400;
1664    else if (Value > 0xffffff)
1665      Value = (Value >> 24) | 0x600;
1666    Inst.addOperand(MCOperand::CreateImm(Value));
1667  }
1668
1669  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
1670    assert(N == 1 && "Invalid number of operands!");
1671    // The immediate encodes the type of constant as well as the value.
1672    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1673    unsigned Value = CE->getValue();
1674    if (Value >= 256 && Value <= 0xffff)
1675      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
1676    else if (Value > 0xffff && Value <= 0xffffff)
1677      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
1678    else if (Value > 0xffffff)
1679      Value = (Value >> 24) | 0x600;
1680    Inst.addOperand(MCOperand::CreateImm(Value));
1681  }
1682
1683  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
1684    assert(N == 1 && "Invalid number of operands!");
1685    // The immediate encodes the type of constant as well as the value.
1686    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1687    uint64_t Value = CE->getValue();
1688    unsigned Imm = 0;
1689    for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
1690      Imm |= (Value & 1) << i;
1691    }
1692    Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
1693  }
1694
1695  virtual void print(raw_ostream &OS) const;
1696
1697  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1698    ARMOperand *Op = new ARMOperand(k_ITCondMask);
1699    Op->ITMask.Mask = Mask;
1700    Op->StartLoc = S;
1701    Op->EndLoc = S;
1702    return Op;
1703  }
1704
1705  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1706    ARMOperand *Op = new ARMOperand(k_CondCode);
1707    Op->CC.Val = CC;
1708    Op->StartLoc = S;
1709    Op->EndLoc = S;
1710    return Op;
1711  }
1712
1713  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1714    ARMOperand *Op = new ARMOperand(k_CoprocNum);
1715    Op->Cop.Val = CopVal;
1716    Op->StartLoc = S;
1717    Op->EndLoc = S;
1718    return Op;
1719  }
1720
1721  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1722    ARMOperand *Op = new ARMOperand(k_CoprocReg);
1723    Op->Cop.Val = CopVal;
1724    Op->StartLoc = S;
1725    Op->EndLoc = S;
1726    return Op;
1727  }
1728
1729  static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
1730    ARMOperand *Op = new ARMOperand(k_CoprocOption);
1731    Op->Cop.Val = Val;
1732    Op->StartLoc = S;
1733    Op->EndLoc = E;
1734    return Op;
1735  }
1736
1737  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1738    ARMOperand *Op = new ARMOperand(k_CCOut);
1739    Op->Reg.RegNum = RegNum;
1740    Op->StartLoc = S;
1741    Op->EndLoc = S;
1742    return Op;
1743  }
1744
1745  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1746    ARMOperand *Op = new ARMOperand(k_Token);
1747    Op->Tok.Data = Str.data();
1748    Op->Tok.Length = Str.size();
1749    Op->StartLoc = S;
1750    Op->EndLoc = S;
1751    return Op;
1752  }
1753
1754  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1755    ARMOperand *Op = new ARMOperand(k_Register);
1756    Op->Reg.RegNum = RegNum;
1757    Op->StartLoc = S;
1758    Op->EndLoc = E;
1759    return Op;
1760  }
1761
1762  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1763                                           unsigned SrcReg,
1764                                           unsigned ShiftReg,
1765                                           unsigned ShiftImm,
1766                                           SMLoc S, SMLoc E) {
1767    ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
1768    Op->RegShiftedReg.ShiftTy = ShTy;
1769    Op->RegShiftedReg.SrcReg = SrcReg;
1770    Op->RegShiftedReg.ShiftReg = ShiftReg;
1771    Op->RegShiftedReg.ShiftImm = ShiftImm;
1772    Op->StartLoc = S;
1773    Op->EndLoc = E;
1774    return Op;
1775  }
1776
1777  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1778                                            unsigned SrcReg,
1779                                            unsigned ShiftImm,
1780                                            SMLoc S, SMLoc E) {
1781    ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
1782    Op->RegShiftedImm.ShiftTy = ShTy;
1783    Op->RegShiftedImm.SrcReg = SrcReg;
1784    Op->RegShiftedImm.ShiftImm = ShiftImm;
1785    Op->StartLoc = S;
1786    Op->EndLoc = E;
1787    return Op;
1788  }
1789
1790  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1791                                   SMLoc S, SMLoc E) {
1792    ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
1793    Op->ShifterImm.isASR = isASR;
1794    Op->ShifterImm.Imm = Imm;
1795    Op->StartLoc = S;
1796    Op->EndLoc = E;
1797    return Op;
1798  }
1799
1800  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1801    ARMOperand *Op = new ARMOperand(k_RotateImmediate);
1802    Op->RotImm.Imm = Imm;
1803    Op->StartLoc = S;
1804    Op->EndLoc = E;
1805    return Op;
1806  }
1807
1808  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1809                                    SMLoc S, SMLoc E) {
1810    ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
1811    Op->Bitfield.LSB = LSB;
1812    Op->Bitfield.Width = Width;
1813    Op->StartLoc = S;
1814    Op->EndLoc = E;
1815    return Op;
1816  }
1817
1818  static ARMOperand *
1819  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1820                SMLoc StartLoc, SMLoc EndLoc) {
1821    KindTy Kind = k_RegisterList;
1822
1823    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
1824      Kind = k_DPRRegisterList;
1825    else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
1826             contains(Regs.front().first))
1827      Kind = k_SPRRegisterList;
1828
1829    ARMOperand *Op = new ARMOperand(Kind);
1830    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1831           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1832      Op->Registers.push_back(I->first);
1833    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1834    Op->StartLoc = StartLoc;
1835    Op->EndLoc = EndLoc;
1836    return Op;
1837  }
1838
1839  static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
1840                                      SMLoc S, SMLoc E) {
1841    ARMOperand *Op = new ARMOperand(k_VectorList);
1842    Op->VectorList.RegNum = RegNum;
1843    Op->VectorList.Count = Count;
1844    Op->StartLoc = S;
1845    Op->EndLoc = E;
1846    return Op;
1847  }
1848
1849  static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
1850                                       MCContext &Ctx) {
1851    ARMOperand *Op = new ARMOperand(k_VectorIndex);
1852    Op->VectorIndex.Val = Idx;
1853    Op->StartLoc = S;
1854    Op->EndLoc = E;
1855    return Op;
1856  }
1857
1858  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1859    ARMOperand *Op = new ARMOperand(k_Immediate);
1860    Op->Imm.Val = Val;
1861    Op->StartLoc = S;
1862    Op->EndLoc = E;
1863    return Op;
1864  }
1865
1866  static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) {
1867    ARMOperand *Op = new ARMOperand(k_FPImmediate);
1868    Op->FPImm.Val = Val;
1869    Op->StartLoc = S;
1870    Op->EndLoc = S;
1871    return Op;
1872  }
1873
1874  static ARMOperand *CreateMem(unsigned BaseRegNum,
1875                               const MCConstantExpr *OffsetImm,
1876                               unsigned OffsetRegNum,
1877                               ARM_AM::ShiftOpc ShiftType,
1878                               unsigned ShiftImm,
1879                               unsigned Alignment,
1880                               bool isNegative,
1881                               SMLoc S, SMLoc E) {
1882    ARMOperand *Op = new ARMOperand(k_Memory);
1883    Op->Memory.BaseRegNum = BaseRegNum;
1884    Op->Memory.OffsetImm = OffsetImm;
1885    Op->Memory.OffsetRegNum = OffsetRegNum;
1886    Op->Memory.ShiftType = ShiftType;
1887    Op->Memory.ShiftImm = ShiftImm;
1888    Op->Memory.Alignment = Alignment;
1889    Op->Memory.isNegative = isNegative;
1890    Op->StartLoc = S;
1891    Op->EndLoc = E;
1892    return Op;
1893  }
1894
1895  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1896                                      ARM_AM::ShiftOpc ShiftTy,
1897                                      unsigned ShiftImm,
1898                                      SMLoc S, SMLoc E) {
1899    ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
1900    Op->PostIdxReg.RegNum = RegNum;
1901    Op->PostIdxReg.isAdd = isAdd;
1902    Op->PostIdxReg.ShiftTy = ShiftTy;
1903    Op->PostIdxReg.ShiftImm = ShiftImm;
1904    Op->StartLoc = S;
1905    Op->EndLoc = E;
1906    return Op;
1907  }
1908
1909  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1910    ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
1911    Op->MBOpt.Val = Opt;
1912    Op->StartLoc = S;
1913    Op->EndLoc = S;
1914    return Op;
1915  }
1916
1917  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1918    ARMOperand *Op = new ARMOperand(k_ProcIFlags);
1919    Op->IFlags.Val = IFlags;
1920    Op->StartLoc = S;
1921    Op->EndLoc = S;
1922    return Op;
1923  }
1924
1925  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1926    ARMOperand *Op = new ARMOperand(k_MSRMask);
1927    Op->MMask.Val = MMask;
1928    Op->StartLoc = S;
1929    Op->EndLoc = S;
1930    return Op;
1931  }
1932};
1933
1934} // end anonymous namespace.
1935
1936void ARMOperand::print(raw_ostream &OS) const {
1937  switch (Kind) {
1938  case k_FPImmediate:
1939    OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm())
1940       << ") >";
1941    break;
1942  case k_CondCode:
1943    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1944    break;
1945  case k_CCOut:
1946    OS << "<ccout " << getReg() << ">";
1947    break;
1948  case k_ITCondMask: {
1949    static const char *MaskStr[] = {
1950      "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
1951      "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
1952    };
1953    assert((ITMask.Mask & 0xf) == ITMask.Mask);
1954    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1955    break;
1956  }
1957  case k_CoprocNum:
1958    OS << "<coprocessor number: " << getCoproc() << ">";
1959    break;
1960  case k_CoprocReg:
1961    OS << "<coprocessor register: " << getCoproc() << ">";
1962    break;
1963  case k_CoprocOption:
1964    OS << "<coprocessor option: " << CoprocOption.Val << ">";
1965    break;
1966  case k_MSRMask:
1967    OS << "<mask: " << getMSRMask() << ">";
1968    break;
1969  case k_Immediate:
1970    getImm()->print(OS);
1971    break;
1972  case k_MemBarrierOpt:
1973    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1974    break;
1975  case k_Memory:
1976    OS << "<memory "
1977       << " base:" << Memory.BaseRegNum;
1978    OS << ">";
1979    break;
1980  case k_PostIndexRegister:
1981    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1982       << PostIdxReg.RegNum;
1983    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1984      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1985         << PostIdxReg.ShiftImm;
1986    OS << ">";
1987    break;
1988  case k_ProcIFlags: {
1989    OS << "<ARM_PROC::";
1990    unsigned IFlags = getProcIFlags();
1991    for (int i=2; i >= 0; --i)
1992      if (IFlags & (1 << i))
1993        OS << ARM_PROC::IFlagsToString(1 << i);
1994    OS << ">";
1995    break;
1996  }
1997  case k_Register:
1998    OS << "<register " << getReg() << ">";
1999    break;
2000  case k_ShifterImmediate:
2001    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2002       << " #" << ShifterImm.Imm << ">";
2003    break;
2004  case k_ShiftedRegister:
2005    OS << "<so_reg_reg "
2006       << RegShiftedReg.SrcReg
2007       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
2008       << ", " << RegShiftedReg.ShiftReg << ", "
2009       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
2010       << ">";
2011    break;
2012  case k_ShiftedImmediate:
2013    OS << "<so_reg_imm "
2014       << RegShiftedImm.SrcReg
2015       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
2016       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
2017       << ">";
2018    break;
2019  case k_RotateImmediate:
2020    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2021    break;
2022  case k_BitfieldDescriptor:
2023    OS << "<bitfield " << "lsb: " << Bitfield.LSB
2024       << ", width: " << Bitfield.Width << ">";
2025    break;
2026  case k_RegisterList:
2027  case k_DPRRegisterList:
2028  case k_SPRRegisterList: {
2029    OS << "<register_list ";
2030
2031    const SmallVectorImpl<unsigned> &RegList = getRegList();
2032    for (SmallVectorImpl<unsigned>::const_iterator
2033           I = RegList.begin(), E = RegList.end(); I != E; ) {
2034      OS << *I;
2035      if (++I < E) OS << ", ";
2036    }
2037
2038    OS << ">";
2039    break;
2040  }
2041  case k_VectorList:
2042    OS << "<vector_list " << VectorList.Count << " * "
2043       << VectorList.RegNum << ">";
2044    break;
2045  case k_Token:
2046    OS << "'" << getToken() << "'";
2047    break;
2048  case k_VectorIndex:
2049    OS << "<vectorindex " << getVectorIndex() << ">";
2050    break;
2051  }
2052}
2053
2054/// @name Auto-generated Match Functions
2055/// {
2056
2057static unsigned MatchRegisterName(StringRef Name);
2058
2059/// }
2060
2061bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2062                                 SMLoc &StartLoc, SMLoc &EndLoc) {
2063  RegNo = tryParseRegister();
2064
2065  return (RegNo == (unsigned)-1);
2066}
2067
2068/// Try to parse a register name.  The token must be an Identifier when called,
2069/// and if it is a register name the token is eaten and the register number is
2070/// returned.  Otherwise return -1.
2071///
2072int ARMAsmParser::tryParseRegister() {
2073  const AsmToken &Tok = Parser.getTok();
2074  if (Tok.isNot(AsmToken::Identifier)) return -1;
2075
2076  // FIXME: Validate register for the current architecture; we have to do
2077  // validation later, so maybe there is no need for this here.
2078  std::string lowerCase = Tok.getString().lower();
2079  unsigned RegNum = MatchRegisterName(lowerCase);
2080  if (!RegNum) {
2081    RegNum = StringSwitch<unsigned>(lowerCase)
2082      .Case("r13", ARM::SP)
2083      .Case("r14", ARM::LR)
2084      .Case("r15", ARM::PC)
2085      .Case("ip", ARM::R12)
2086      .Default(0);
2087  }
2088  if (!RegNum) return -1;
2089
2090  Parser.Lex(); // Eat identifier token.
2091
2092  return RegNum;
2093}
2094
2095// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2096// If a recoverable error occurs, return 1. If an irrecoverable error
2097// occurs, return -1. An irrecoverable error is one where tokens have been
2098// consumed in the process of trying to parse the shifter (i.e., when it is
2099// indeed a shifter operand, but malformed).
2100int ARMAsmParser::tryParseShiftRegister(
2101                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2102  SMLoc S = Parser.getTok().getLoc();
2103  const AsmToken &Tok = Parser.getTok();
2104  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2105
2106  std::string lowerCase = Tok.getString().lower();
2107  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2108      .Case("lsl", ARM_AM::lsl)
2109      .Case("lsr", ARM_AM::lsr)
2110      .Case("asr", ARM_AM::asr)
2111      .Case("ror", ARM_AM::ror)
2112      .Case("rrx", ARM_AM::rrx)
2113      .Default(ARM_AM::no_shift);
2114
2115  if (ShiftTy == ARM_AM::no_shift)
2116    return 1;
2117
2118  Parser.Lex(); // Eat the operator.
2119
2120  // The source register for the shift has already been added to the
2121  // operand list, so we need to pop it off and combine it into the shifted
2122  // register operand instead.
2123  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2124  if (!PrevOp->isReg())
2125    return Error(PrevOp->getStartLoc(), "shift must be of a register");
2126  int SrcReg = PrevOp->getReg();
2127  int64_t Imm = 0;
2128  int ShiftReg = 0;
2129  if (ShiftTy == ARM_AM::rrx) {
2130    // RRX Doesn't have an explicit shift amount. The encoder expects
2131    // the shift register to be the same as the source register. Seems odd,
2132    // but OK.
2133    ShiftReg = SrcReg;
2134  } else {
2135    // Figure out if this is shifted by a constant or a register (for non-RRX).
2136    if (Parser.getTok().is(AsmToken::Hash)) {
2137      Parser.Lex(); // Eat hash.
2138      SMLoc ImmLoc = Parser.getTok().getLoc();
2139      const MCExpr *ShiftExpr = 0;
2140      if (getParser().ParseExpression(ShiftExpr)) {
2141        Error(ImmLoc, "invalid immediate shift value");
2142        return -1;
2143      }
2144      // The expression must be evaluatable as an immediate.
2145      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2146      if (!CE) {
2147        Error(ImmLoc, "invalid immediate shift value");
2148        return -1;
2149      }
2150      // Range check the immediate.
2151      // lsl, ror: 0 <= imm <= 31
2152      // lsr, asr: 0 <= imm <= 32
2153      Imm = CE->getValue();
2154      if (Imm < 0 ||
2155          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2156          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2157        Error(ImmLoc, "immediate shift value out of range");
2158        return -1;
2159      }
2160    } else if (Parser.getTok().is(AsmToken::Identifier)) {
2161      ShiftReg = tryParseRegister();
2162      SMLoc L = Parser.getTok().getLoc();
2163      if (ShiftReg == -1) {
2164        Error (L, "expected immediate or register in shift operand");
2165        return -1;
2166      }
2167    } else {
2168      Error (Parser.getTok().getLoc(),
2169                    "expected immediate or register in shift operand");
2170      return -1;
2171    }
2172  }
2173
2174  if (ShiftReg && ShiftTy != ARM_AM::rrx)
2175    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2176                                                         ShiftReg, Imm,
2177                                               S, Parser.getTok().getLoc()));
2178  else
2179    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2180                                               S, Parser.getTok().getLoc()));
2181
2182  return 0;
2183}
2184
2185
2186/// Try to parse a register name.  The token must be an Identifier when called.
2187/// If it's a register, an AsmOperand is created. Another AsmOperand is created
2188/// if there is a "writeback". 'true' if it's not a register.
2189///
2190/// TODO this is likely to change to allow different register types and or to
2191/// parse for a specific register type.
2192bool ARMAsmParser::
2193tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2194  SMLoc S = Parser.getTok().getLoc();
2195  int RegNo = tryParseRegister();
2196  if (RegNo == -1)
2197    return true;
2198
2199  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2200
2201  const AsmToken &ExclaimTok = Parser.getTok();
2202  if (ExclaimTok.is(AsmToken::Exclaim)) {
2203    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2204                                               ExclaimTok.getLoc()));
2205    Parser.Lex(); // Eat exclaim token
2206    return false;
2207  }
2208
2209  // Also check for an index operand. This is only legal for vector registers,
2210  // but that'll get caught OK in operand matching, so we don't need to
2211  // explicitly filter everything else out here.
2212  if (Parser.getTok().is(AsmToken::LBrac)) {
2213    SMLoc SIdx = Parser.getTok().getLoc();
2214    Parser.Lex(); // Eat left bracket token.
2215
2216    const MCExpr *ImmVal;
2217    if (getParser().ParseExpression(ImmVal))
2218      return MatchOperand_ParseFail;
2219    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2220    if (!MCE) {
2221      TokError("immediate value expected for vector index");
2222      return MatchOperand_ParseFail;
2223    }
2224
2225    SMLoc E = Parser.getTok().getLoc();
2226    if (Parser.getTok().isNot(AsmToken::RBrac)) {
2227      Error(E, "']' expected");
2228      return MatchOperand_ParseFail;
2229    }
2230
2231    Parser.Lex(); // Eat right bracket token.
2232
2233    Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2234                                                     SIdx, E,
2235                                                     getContext()));
2236  }
2237
2238  return false;
2239}
2240
2241/// MatchCoprocessorOperandName - Try to parse an coprocessor related
2242/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2243/// "c5", ...
2244static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2245  // Use the same layout as the tablegen'erated register name matcher. Ugly,
2246  // but efficient.
2247  switch (Name.size()) {
2248  default: break;
2249  case 2:
2250    if (Name[0] != CoprocOp)
2251      return -1;
2252    switch (Name[1]) {
2253    default:  return -1;
2254    case '0': return 0;
2255    case '1': return 1;
2256    case '2': return 2;
2257    case '3': return 3;
2258    case '4': return 4;
2259    case '5': return 5;
2260    case '6': return 6;
2261    case '7': return 7;
2262    case '8': return 8;
2263    case '9': return 9;
2264    }
2265    break;
2266  case 3:
2267    if (Name[0] != CoprocOp || Name[1] != '1')
2268      return -1;
2269    switch (Name[2]) {
2270    default:  return -1;
2271    case '0': return 10;
2272    case '1': return 11;
2273    case '2': return 12;
2274    case '3': return 13;
2275    case '4': return 14;
2276    case '5': return 15;
2277    }
2278    break;
2279  }
2280
2281  return -1;
2282}
2283
2284/// parseITCondCode - Try to parse a condition code for an IT instruction.
2285ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2286parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2287  SMLoc S = Parser.getTok().getLoc();
2288  const AsmToken &Tok = Parser.getTok();
2289  if (!Tok.is(AsmToken::Identifier))
2290    return MatchOperand_NoMatch;
2291  unsigned CC = StringSwitch<unsigned>(Tok.getString())
2292    .Case("eq", ARMCC::EQ)
2293    .Case("ne", ARMCC::NE)
2294    .Case("hs", ARMCC::HS)
2295    .Case("cs", ARMCC::HS)
2296    .Case("lo", ARMCC::LO)
2297    .Case("cc", ARMCC::LO)
2298    .Case("mi", ARMCC::MI)
2299    .Case("pl", ARMCC::PL)
2300    .Case("vs", ARMCC::VS)
2301    .Case("vc", ARMCC::VC)
2302    .Case("hi", ARMCC::HI)
2303    .Case("ls", ARMCC::LS)
2304    .Case("ge", ARMCC::GE)
2305    .Case("lt", ARMCC::LT)
2306    .Case("gt", ARMCC::GT)
2307    .Case("le", ARMCC::LE)
2308    .Case("al", ARMCC::AL)
2309    .Default(~0U);
2310  if (CC == ~0U)
2311    return MatchOperand_NoMatch;
2312  Parser.Lex(); // Eat the token.
2313
2314  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2315
2316  return MatchOperand_Success;
2317}
2318
2319/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2320/// token must be an Identifier when called, and if it is a coprocessor
2321/// number, the token is eaten and the operand is added to the operand list.
2322ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2323parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2324  SMLoc S = Parser.getTok().getLoc();
2325  const AsmToken &Tok = Parser.getTok();
2326  if (Tok.isNot(AsmToken::Identifier))
2327    return MatchOperand_NoMatch;
2328
2329  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2330  if (Num == -1)
2331    return MatchOperand_NoMatch;
2332
2333  Parser.Lex(); // Eat identifier token.
2334  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2335  return MatchOperand_Success;
2336}
2337
2338/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2339/// token must be an Identifier when called, and if it is a coprocessor
2340/// number, the token is eaten and the operand is added to the operand list.
2341ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2342parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2343  SMLoc S = Parser.getTok().getLoc();
2344  const AsmToken &Tok = Parser.getTok();
2345  if (Tok.isNot(AsmToken::Identifier))
2346    return MatchOperand_NoMatch;
2347
2348  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2349  if (Reg == -1)
2350    return MatchOperand_NoMatch;
2351
2352  Parser.Lex(); // Eat identifier token.
2353  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2354  return MatchOperand_Success;
2355}
2356
2357/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2358/// coproc_option : '{' imm0_255 '}'
2359ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2360parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2361  SMLoc S = Parser.getTok().getLoc();
2362
2363  // If this isn't a '{', this isn't a coprocessor immediate operand.
2364  if (Parser.getTok().isNot(AsmToken::LCurly))
2365    return MatchOperand_NoMatch;
2366  Parser.Lex(); // Eat the '{'
2367
2368  const MCExpr *Expr;
2369  SMLoc Loc = Parser.getTok().getLoc();
2370  if (getParser().ParseExpression(Expr)) {
2371    Error(Loc, "illegal expression");
2372    return MatchOperand_ParseFail;
2373  }
2374  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2375  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2376    Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2377    return MatchOperand_ParseFail;
2378  }
2379  int Val = CE->getValue();
2380
2381  // Check for and consume the closing '}'
2382  if (Parser.getTok().isNot(AsmToken::RCurly))
2383    return MatchOperand_ParseFail;
2384  SMLoc E = Parser.getTok().getLoc();
2385  Parser.Lex(); // Eat the '}'
2386
2387  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2388  return MatchOperand_Success;
2389}
2390
2391// For register list parsing, we need to map from raw GPR register numbering
2392// to the enumeration values. The enumeration values aren't sorted by
2393// register number due to our using "sp", "lr" and "pc" as canonical names.
2394static unsigned getNextRegister(unsigned Reg) {
2395  // If this is a GPR, we need to do it manually, otherwise we can rely
2396  // on the sort ordering of the enumeration since the other reg-classes
2397  // are sane.
2398  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2399    return Reg + 1;
2400  switch(Reg) {
2401  default: assert(0 && "Invalid GPR number!");
2402  case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
2403  case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
2404  case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
2405  case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
2406  case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
2407  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2408  case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
2409  case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
2410  }
2411}
2412
2413/// Parse a register list.
2414bool ARMAsmParser::
2415parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2416  assert(Parser.getTok().is(AsmToken::LCurly) &&
2417         "Token is not a Left Curly Brace");
2418  SMLoc S = Parser.getTok().getLoc();
2419  Parser.Lex(); // Eat '{' token.
2420  SMLoc RegLoc = Parser.getTok().getLoc();
2421
2422  // Check the first register in the list to see what register class
2423  // this is a list of.
2424  int Reg = tryParseRegister();
2425  if (Reg == -1)
2426    return Error(RegLoc, "register expected");
2427
2428  const MCRegisterClass *RC;
2429  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2430    RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2431  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2432    RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2433  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2434    RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2435  else
2436    return Error(RegLoc, "invalid register in register list");
2437
2438  // The reglist instructions have at most 16 registers, so reserve
2439  // space for that many.
2440  SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2441  // Store the first register.
2442  Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2443
2444  // This starts immediately after the first register token in the list,
2445  // so we can see either a comma or a minus (range separator) as a legal
2446  // next token.
2447  while (Parser.getTok().is(AsmToken::Comma) ||
2448         Parser.getTok().is(AsmToken::Minus)) {
2449    if (Parser.getTok().is(AsmToken::Minus)) {
2450      Parser.Lex(); // Eat the comma.
2451      SMLoc EndLoc = Parser.getTok().getLoc();
2452      int EndReg = tryParseRegister();
2453      if (EndReg == -1)
2454        return Error(EndLoc, "register expected");
2455      // If the register is the same as the start reg, there's nothing
2456      // more to do.
2457      if (Reg == EndReg)
2458        continue;
2459      // The register must be in the same register class as the first.
2460      if (!RC->contains(EndReg))
2461        return Error(EndLoc, "invalid register in register list");
2462      // Ranges must go from low to high.
2463      if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
2464        return Error(EndLoc, "bad range in register list");
2465
2466      // Add all the registers in the range to the register list.
2467      while (Reg != EndReg) {
2468        Reg = getNextRegister(Reg);
2469        Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2470      }
2471      continue;
2472    }
2473    Parser.Lex(); // Eat the comma.
2474    RegLoc = Parser.getTok().getLoc();
2475    int OldReg = Reg;
2476    Reg = tryParseRegister();
2477    if (Reg == -1)
2478      return Error(RegLoc, "register expected");
2479    // The register must be in the same register class as the first.
2480    if (!RC->contains(Reg))
2481      return Error(RegLoc, "invalid register in register list");
2482    // List must be monotonically increasing.
2483    if (getARMRegisterNumbering(Reg) <= getARMRegisterNumbering(OldReg))
2484      return Error(RegLoc, "register list not in ascending order");
2485    // VFP register lists must also be contiguous.
2486    // It's OK to use the enumeration values directly here rather, as the
2487    // VFP register classes have the enum sorted properly.
2488    if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2489        Reg != OldReg + 1)
2490      return Error(RegLoc, "non-contiguous register range");
2491    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2492  }
2493
2494  SMLoc E = Parser.getTok().getLoc();
2495  if (Parser.getTok().isNot(AsmToken::RCurly))
2496    return Error(E, "'}' expected");
2497  Parser.Lex(); // Eat '}' token.
2498
2499  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2500  return false;
2501}
2502
2503// Return the low-subreg of a given Q register.
2504static unsigned getDRegFromQReg(unsigned QReg) {
2505  switch (QReg) {
2506  default: llvm_unreachable("expected a Q register!");
2507  case ARM::Q0:  return ARM::D0;
2508  case ARM::Q1:  return ARM::D2;
2509  case ARM::Q2:  return ARM::D4;
2510  case ARM::Q3:  return ARM::D6;
2511  case ARM::Q4:  return ARM::D8;
2512  case ARM::Q5:  return ARM::D10;
2513  case ARM::Q6:  return ARM::D12;
2514  case ARM::Q7:  return ARM::D14;
2515  case ARM::Q8:  return ARM::D16;
2516  case ARM::Q9:  return ARM::D19;
2517  case ARM::Q10: return ARM::D20;
2518  case ARM::Q11: return ARM::D22;
2519  case ARM::Q12: return ARM::D24;
2520  case ARM::Q13: return ARM::D26;
2521  case ARM::Q14: return ARM::D28;
2522  case ARM::Q15: return ARM::D30;
2523  }
2524}
2525
2526// parse a vector register list
2527ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2528parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2529  if(Parser.getTok().isNot(AsmToken::LCurly))
2530    return MatchOperand_NoMatch;
2531
2532  SMLoc S = Parser.getTok().getLoc();
2533  Parser.Lex(); // Eat '{' token.
2534  SMLoc RegLoc = Parser.getTok().getLoc();
2535
2536  int Reg = tryParseRegister();
2537  if (Reg == -1) {
2538    Error(RegLoc, "register expected");
2539    return MatchOperand_ParseFail;
2540  }
2541  unsigned Count = 1;
2542  unsigned FirstReg = Reg;
2543  // The list is of D registers, but we also allow Q regs and just interpret
2544  // them as the two D sub-registers.
2545  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2546    FirstReg = Reg = getDRegFromQReg(Reg);
2547    ++Reg;
2548    ++Count;
2549  }
2550
2551  while (Parser.getTok().is(AsmToken::Comma)) {
2552    Parser.Lex(); // Eat the comma.
2553    RegLoc = Parser.getTok().getLoc();
2554    int OldReg = Reg;
2555    Reg = tryParseRegister();
2556    if (Reg == -1) {
2557      Error(RegLoc, "register expected");
2558      return MatchOperand_ParseFail;
2559    }
2560    // vector register lists must be contiguous.
2561    // It's OK to use the enumeration values directly here rather, as the
2562    // VFP register classes have the enum sorted properly.
2563    //
2564    // The list is of D registers, but we also allow Q regs and just interpret
2565    // them as the two D sub-registers.
2566    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2567      Reg = getDRegFromQReg(Reg);
2568      if (Reg != OldReg + 1) {
2569        Error(RegLoc, "non-contiguous register range");
2570        return MatchOperand_ParseFail;
2571      }
2572      ++Reg;
2573      Count += 2;
2574      continue;
2575    }
2576    // Normal D register. Just check that it's contiguous and keep going.
2577    if (Reg != OldReg + 1) {
2578      Error(RegLoc, "non-contiguous register range");
2579      return MatchOperand_ParseFail;
2580    }
2581    ++Count;
2582  }
2583
2584  SMLoc E = Parser.getTok().getLoc();
2585  if (Parser.getTok().isNot(AsmToken::RCurly)) {
2586    Error(E, "'}' expected");
2587    return MatchOperand_ParseFail;
2588  }
2589  Parser.Lex(); // Eat '}' token.
2590
2591  Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, S, E));
2592  return MatchOperand_Success;
2593}
2594
2595/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
2596ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2597parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2598  SMLoc S = Parser.getTok().getLoc();
2599  const AsmToken &Tok = Parser.getTok();
2600  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2601  StringRef OptStr = Tok.getString();
2602
2603  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
2604    .Case("sy",    ARM_MB::SY)
2605    .Case("st",    ARM_MB::ST)
2606    .Case("sh",    ARM_MB::ISH)
2607    .Case("ish",   ARM_MB::ISH)
2608    .Case("shst",  ARM_MB::ISHST)
2609    .Case("ishst", ARM_MB::ISHST)
2610    .Case("nsh",   ARM_MB::NSH)
2611    .Case("un",    ARM_MB::NSH)
2612    .Case("nshst", ARM_MB::NSHST)
2613    .Case("unst",  ARM_MB::NSHST)
2614    .Case("osh",   ARM_MB::OSH)
2615    .Case("oshst", ARM_MB::OSHST)
2616    .Default(~0U);
2617
2618  if (Opt == ~0U)
2619    return MatchOperand_NoMatch;
2620
2621  Parser.Lex(); // Eat identifier token.
2622  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
2623  return MatchOperand_Success;
2624}
2625
2626/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
2627ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2628parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2629  SMLoc S = Parser.getTok().getLoc();
2630  const AsmToken &Tok = Parser.getTok();
2631  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2632  StringRef IFlagsStr = Tok.getString();
2633
2634  // An iflags string of "none" is interpreted to mean that none of the AIF
2635  // bits are set.  Not a terribly useful instruction, but a valid encoding.
2636  unsigned IFlags = 0;
2637  if (IFlagsStr != "none") {
2638        for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
2639      unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
2640        .Case("a", ARM_PROC::A)
2641        .Case("i", ARM_PROC::I)
2642        .Case("f", ARM_PROC::F)
2643        .Default(~0U);
2644
2645      // If some specific iflag is already set, it means that some letter is
2646      // present more than once, this is not acceptable.
2647      if (Flag == ~0U || (IFlags & Flag))
2648        return MatchOperand_NoMatch;
2649
2650      IFlags |= Flag;
2651    }
2652  }
2653
2654  Parser.Lex(); // Eat identifier token.
2655  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
2656  return MatchOperand_Success;
2657}
2658
2659/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
2660ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2661parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2662  SMLoc S = Parser.getTok().getLoc();
2663  const AsmToken &Tok = Parser.getTok();
2664  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2665  StringRef Mask = Tok.getString();
2666
2667  if (isMClass()) {
2668    // See ARMv6-M 10.1.1
2669    unsigned FlagsVal = StringSwitch<unsigned>(Mask)
2670      .Case("apsr", 0)
2671      .Case("iapsr", 1)
2672      .Case("eapsr", 2)
2673      .Case("xpsr", 3)
2674      .Case("ipsr", 5)
2675      .Case("epsr", 6)
2676      .Case("iepsr", 7)
2677      .Case("msp", 8)
2678      .Case("psp", 9)
2679      .Case("primask", 16)
2680      .Case("basepri", 17)
2681      .Case("basepri_max", 18)
2682      .Case("faultmask", 19)
2683      .Case("control", 20)
2684      .Default(~0U);
2685
2686    if (FlagsVal == ~0U)
2687      return MatchOperand_NoMatch;
2688
2689    if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
2690      // basepri, basepri_max and faultmask only valid for V7m.
2691      return MatchOperand_NoMatch;
2692
2693    Parser.Lex(); // Eat identifier token.
2694    Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2695    return MatchOperand_Success;
2696  }
2697
2698  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
2699  size_t Start = 0, Next = Mask.find('_');
2700  StringRef Flags = "";
2701  std::string SpecReg = Mask.slice(Start, Next).lower();
2702  if (Next != StringRef::npos)
2703    Flags = Mask.slice(Next+1, Mask.size());
2704
2705  // FlagsVal contains the complete mask:
2706  // 3-0: Mask
2707  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2708  unsigned FlagsVal = 0;
2709
2710  if (SpecReg == "apsr") {
2711    FlagsVal = StringSwitch<unsigned>(Flags)
2712    .Case("nzcvq",  0x8) // same as CPSR_f
2713    .Case("g",      0x4) // same as CPSR_s
2714    .Case("nzcvqg", 0xc) // same as CPSR_fs
2715    .Default(~0U);
2716
2717    if (FlagsVal == ~0U) {
2718      if (!Flags.empty())
2719        return MatchOperand_NoMatch;
2720      else
2721        FlagsVal = 8; // No flag
2722    }
2723  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
2724    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
2725      Flags = "fc";
2726    for (int i = 0, e = Flags.size(); i != e; ++i) {
2727      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
2728      .Case("c", 1)
2729      .Case("x", 2)
2730      .Case("s", 4)
2731      .Case("f", 8)
2732      .Default(~0U);
2733
2734      // If some specific flag is already set, it means that some letter is
2735      // present more than once, this is not acceptable.
2736      if (FlagsVal == ~0U || (FlagsVal & Flag))
2737        return MatchOperand_NoMatch;
2738      FlagsVal |= Flag;
2739    }
2740  } else // No match for special register.
2741    return MatchOperand_NoMatch;
2742
2743  // Special register without flags is NOT equivalent to "fc" flags.
2744  // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
2745  // two lines would enable gas compatibility at the expense of breaking
2746  // round-tripping.
2747  //
2748  // if (!FlagsVal)
2749  //  FlagsVal = 0x9;
2750
2751  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2752  if (SpecReg == "spsr")
2753    FlagsVal |= 16;
2754
2755  Parser.Lex(); // Eat identifier token.
2756  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2757  return MatchOperand_Success;
2758}
2759
2760ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2761parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
2762            int Low, int High) {
2763  const AsmToken &Tok = Parser.getTok();
2764  if (Tok.isNot(AsmToken::Identifier)) {
2765    Error(Parser.getTok().getLoc(), Op + " operand expected.");
2766    return MatchOperand_ParseFail;
2767  }
2768  StringRef ShiftName = Tok.getString();
2769  std::string LowerOp = Op.lower();
2770  std::string UpperOp = Op.upper();
2771  if (ShiftName != LowerOp && ShiftName != UpperOp) {
2772    Error(Parser.getTok().getLoc(), Op + " operand expected.");
2773    return MatchOperand_ParseFail;
2774  }
2775  Parser.Lex(); // Eat shift type token.
2776
2777  // There must be a '#' and a shift amount.
2778  if (Parser.getTok().isNot(AsmToken::Hash)) {
2779    Error(Parser.getTok().getLoc(), "'#' expected");
2780    return MatchOperand_ParseFail;
2781  }
2782  Parser.Lex(); // Eat hash token.
2783
2784  const MCExpr *ShiftAmount;
2785  SMLoc Loc = Parser.getTok().getLoc();
2786  if (getParser().ParseExpression(ShiftAmount)) {
2787    Error(Loc, "illegal expression");
2788    return MatchOperand_ParseFail;
2789  }
2790  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2791  if (!CE) {
2792    Error(Loc, "constant expression expected");
2793    return MatchOperand_ParseFail;
2794  }
2795  int Val = CE->getValue();
2796  if (Val < Low || Val > High) {
2797    Error(Loc, "immediate value out of range");
2798    return MatchOperand_ParseFail;
2799  }
2800
2801  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
2802
2803  return MatchOperand_Success;
2804}
2805
2806ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2807parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2808  const AsmToken &Tok = Parser.getTok();
2809  SMLoc S = Tok.getLoc();
2810  if (Tok.isNot(AsmToken::Identifier)) {
2811    Error(Tok.getLoc(), "'be' or 'le' operand expected");
2812    return MatchOperand_ParseFail;
2813  }
2814  int Val = StringSwitch<int>(Tok.getString())
2815    .Case("be", 1)
2816    .Case("le", 0)
2817    .Default(-1);
2818  Parser.Lex(); // Eat the token.
2819
2820  if (Val == -1) {
2821    Error(Tok.getLoc(), "'be' or 'le' operand expected");
2822    return MatchOperand_ParseFail;
2823  }
2824  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2825                                                                  getContext()),
2826                                           S, Parser.getTok().getLoc()));
2827  return MatchOperand_Success;
2828}
2829
2830/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2831/// instructions. Legal values are:
2832///     lsl #n  'n' in [0,31]
2833///     asr #n  'n' in [1,32]
2834///             n == 32 encoded as n == 0.
2835ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2836parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2837  const AsmToken &Tok = Parser.getTok();
2838  SMLoc S = Tok.getLoc();
2839  if (Tok.isNot(AsmToken::Identifier)) {
2840    Error(S, "shift operator 'asr' or 'lsl' expected");
2841    return MatchOperand_ParseFail;
2842  }
2843  StringRef ShiftName = Tok.getString();
2844  bool isASR;
2845  if (ShiftName == "lsl" || ShiftName == "LSL")
2846    isASR = false;
2847  else if (ShiftName == "asr" || ShiftName == "ASR")
2848    isASR = true;
2849  else {
2850    Error(S, "shift operator 'asr' or 'lsl' expected");
2851    return MatchOperand_ParseFail;
2852  }
2853  Parser.Lex(); // Eat the operator.
2854
2855  // A '#' and a shift amount.
2856  if (Parser.getTok().isNot(AsmToken::Hash)) {
2857    Error(Parser.getTok().getLoc(), "'#' expected");
2858    return MatchOperand_ParseFail;
2859  }
2860  Parser.Lex(); // Eat hash token.
2861
2862  const MCExpr *ShiftAmount;
2863  SMLoc E = Parser.getTok().getLoc();
2864  if (getParser().ParseExpression(ShiftAmount)) {
2865    Error(E, "malformed shift expression");
2866    return MatchOperand_ParseFail;
2867  }
2868  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2869  if (!CE) {
2870    Error(E, "shift amount must be an immediate");
2871    return MatchOperand_ParseFail;
2872  }
2873
2874  int64_t Val = CE->getValue();
2875  if (isASR) {
2876    // Shift amount must be in [1,32]
2877    if (Val < 1 || Val > 32) {
2878      Error(E, "'asr' shift amount must be in range [1,32]");
2879      return MatchOperand_ParseFail;
2880    }
2881    // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
2882    if (isThumb() && Val == 32) {
2883      Error(E, "'asr #32' shift amount not allowed in Thumb mode");
2884      return MatchOperand_ParseFail;
2885    }
2886    if (Val == 32) Val = 0;
2887  } else {
2888    // Shift amount must be in [1,32]
2889    if (Val < 0 || Val > 31) {
2890      Error(E, "'lsr' shift amount must be in range [0,31]");
2891      return MatchOperand_ParseFail;
2892    }
2893  }
2894
2895  E = Parser.getTok().getLoc();
2896  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2897
2898  return MatchOperand_Success;
2899}
2900
2901/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2902/// of instructions. Legal values are:
2903///     ror #n  'n' in {0, 8, 16, 24}
2904ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2905parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2906  const AsmToken &Tok = Parser.getTok();
2907  SMLoc S = Tok.getLoc();
2908  if (Tok.isNot(AsmToken::Identifier))
2909    return MatchOperand_NoMatch;
2910  StringRef ShiftName = Tok.getString();
2911  if (ShiftName != "ror" && ShiftName != "ROR")
2912    return MatchOperand_NoMatch;
2913  Parser.Lex(); // Eat the operator.
2914
2915  // A '#' and a rotate amount.
2916  if (Parser.getTok().isNot(AsmToken::Hash)) {
2917    Error(Parser.getTok().getLoc(), "'#' expected");
2918    return MatchOperand_ParseFail;
2919  }
2920  Parser.Lex(); // Eat hash token.
2921
2922  const MCExpr *ShiftAmount;
2923  SMLoc E = Parser.getTok().getLoc();
2924  if (getParser().ParseExpression(ShiftAmount)) {
2925    Error(E, "malformed rotate expression");
2926    return MatchOperand_ParseFail;
2927  }
2928  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2929  if (!CE) {
2930    Error(E, "rotate amount must be an immediate");
2931    return MatchOperand_ParseFail;
2932  }
2933
2934  int64_t Val = CE->getValue();
2935  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2936  // normally, zero is represented in asm by omitting the rotate operand
2937  // entirely.
2938  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2939    Error(E, "'ror' rotate amount must be 8, 16, or 24");
2940    return MatchOperand_ParseFail;
2941  }
2942
2943  E = Parser.getTok().getLoc();
2944  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2945
2946  return MatchOperand_Success;
2947}
2948
2949ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2950parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2951  SMLoc S = Parser.getTok().getLoc();
2952  // The bitfield descriptor is really two operands, the LSB and the width.
2953  if (Parser.getTok().isNot(AsmToken::Hash)) {
2954    Error(Parser.getTok().getLoc(), "'#' expected");
2955    return MatchOperand_ParseFail;
2956  }
2957  Parser.Lex(); // Eat hash token.
2958
2959  const MCExpr *LSBExpr;
2960  SMLoc E = Parser.getTok().getLoc();
2961  if (getParser().ParseExpression(LSBExpr)) {
2962    Error(E, "malformed immediate expression");
2963    return MatchOperand_ParseFail;
2964  }
2965  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2966  if (!CE) {
2967    Error(E, "'lsb' operand must be an immediate");
2968    return MatchOperand_ParseFail;
2969  }
2970
2971  int64_t LSB = CE->getValue();
2972  // The LSB must be in the range [0,31]
2973  if (LSB < 0 || LSB > 31) {
2974    Error(E, "'lsb' operand must be in the range [0,31]");
2975    return MatchOperand_ParseFail;
2976  }
2977  E = Parser.getTok().getLoc();
2978
2979  // Expect another immediate operand.
2980  if (Parser.getTok().isNot(AsmToken::Comma)) {
2981    Error(Parser.getTok().getLoc(), "too few operands");
2982    return MatchOperand_ParseFail;
2983  }
2984  Parser.Lex(); // Eat hash token.
2985  if (Parser.getTok().isNot(AsmToken::Hash)) {
2986    Error(Parser.getTok().getLoc(), "'#' expected");
2987    return MatchOperand_ParseFail;
2988  }
2989  Parser.Lex(); // Eat hash token.
2990
2991  const MCExpr *WidthExpr;
2992  if (getParser().ParseExpression(WidthExpr)) {
2993    Error(E, "malformed immediate expression");
2994    return MatchOperand_ParseFail;
2995  }
2996  CE = dyn_cast<MCConstantExpr>(WidthExpr);
2997  if (!CE) {
2998    Error(E, "'width' operand must be an immediate");
2999    return MatchOperand_ParseFail;
3000  }
3001
3002  int64_t Width = CE->getValue();
3003  // The LSB must be in the range [1,32-lsb]
3004  if (Width < 1 || Width > 32 - LSB) {
3005    Error(E, "'width' operand must be in the range [1,32-lsb]");
3006    return MatchOperand_ParseFail;
3007  }
3008  E = Parser.getTok().getLoc();
3009
3010  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
3011
3012  return MatchOperand_Success;
3013}
3014
3015ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3016parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3017  // Check for a post-index addressing register operand. Specifically:
3018  // postidx_reg := '+' register {, shift}
3019  //              | '-' register {, shift}
3020  //              | register {, shift}
3021
3022  // This method must return MatchOperand_NoMatch without consuming any tokens
3023  // in the case where there is no match, as other alternatives take other
3024  // parse methods.
3025  AsmToken Tok = Parser.getTok();
3026  SMLoc S = Tok.getLoc();
3027  bool haveEaten = false;
3028  bool isAdd = true;
3029  int Reg = -1;
3030  if (Tok.is(AsmToken::Plus)) {
3031    Parser.Lex(); // Eat the '+' token.
3032    haveEaten = true;
3033  } else if (Tok.is(AsmToken::Minus)) {
3034    Parser.Lex(); // Eat the '-' token.
3035    isAdd = false;
3036    haveEaten = true;
3037  }
3038  if (Parser.getTok().is(AsmToken::Identifier))
3039    Reg = tryParseRegister();
3040  if (Reg == -1) {
3041    if (!haveEaten)
3042      return MatchOperand_NoMatch;
3043    Error(Parser.getTok().getLoc(), "register expected");
3044    return MatchOperand_ParseFail;
3045  }
3046  SMLoc E = Parser.getTok().getLoc();
3047
3048  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3049  unsigned ShiftImm = 0;
3050  if (Parser.getTok().is(AsmToken::Comma)) {
3051    Parser.Lex(); // Eat the ','.
3052    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3053      return MatchOperand_ParseFail;
3054  }
3055
3056  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3057                                                  ShiftImm, S, E));
3058
3059  return MatchOperand_Success;
3060}
3061
3062ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3063parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3064  // Check for a post-index addressing register operand. Specifically:
3065  // am3offset := '+' register
3066  //              | '-' register
3067  //              | register
3068  //              | # imm
3069  //              | # + imm
3070  //              | # - imm
3071
3072  // This method must return MatchOperand_NoMatch without consuming any tokens
3073  // in the case where there is no match, as other alternatives take other
3074  // parse methods.
3075  AsmToken Tok = Parser.getTok();
3076  SMLoc S = Tok.getLoc();
3077
3078  // Do immediates first, as we always parse those if we have a '#'.
3079  if (Parser.getTok().is(AsmToken::Hash)) {
3080    Parser.Lex(); // Eat the '#'.
3081    // Explicitly look for a '-', as we need to encode negative zero
3082    // differently.
3083    bool isNegative = Parser.getTok().is(AsmToken::Minus);
3084    const MCExpr *Offset;
3085    if (getParser().ParseExpression(Offset))
3086      return MatchOperand_ParseFail;
3087    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3088    if (!CE) {
3089      Error(S, "constant expression expected");
3090      return MatchOperand_ParseFail;
3091    }
3092    SMLoc E = Tok.getLoc();
3093    // Negative zero is encoded as the flag value INT32_MIN.
3094    int32_t Val = CE->getValue();
3095    if (isNegative && Val == 0)
3096      Val = INT32_MIN;
3097
3098    Operands.push_back(
3099      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3100
3101    return MatchOperand_Success;
3102  }
3103
3104
3105  bool haveEaten = false;
3106  bool isAdd = true;
3107  int Reg = -1;
3108  if (Tok.is(AsmToken::Plus)) {
3109    Parser.Lex(); // Eat the '+' token.
3110    haveEaten = true;
3111  } else if (Tok.is(AsmToken::Minus)) {
3112    Parser.Lex(); // Eat the '-' token.
3113    isAdd = false;
3114    haveEaten = true;
3115  }
3116  if (Parser.getTok().is(AsmToken::Identifier))
3117    Reg = tryParseRegister();
3118  if (Reg == -1) {
3119    if (!haveEaten)
3120      return MatchOperand_NoMatch;
3121    Error(Parser.getTok().getLoc(), "register expected");
3122    return MatchOperand_ParseFail;
3123  }
3124  SMLoc E = Parser.getTok().getLoc();
3125
3126  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3127                                                  0, S, E));
3128
3129  return MatchOperand_Success;
3130}
3131
3132/// cvtT2LdrdPre - Convert parsed operands to MCInst.
3133/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3134/// when they refer multiple MIOperands inside a single one.
3135bool ARMAsmParser::
3136cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3137             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3138  // Rt, Rt2
3139  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3140  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3141  // Create a writeback register dummy placeholder.
3142  Inst.addOperand(MCOperand::CreateReg(0));
3143  // addr
3144  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3145  // pred
3146  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3147  return true;
3148}
3149
3150/// cvtT2StrdPre - Convert parsed operands to MCInst.
3151/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3152/// when they refer multiple MIOperands inside a single one.
3153bool ARMAsmParser::
3154cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3155             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3156  // Create a writeback register dummy placeholder.
3157  Inst.addOperand(MCOperand::CreateReg(0));
3158  // Rt, Rt2
3159  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3160  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3161  // addr
3162  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3163  // pred
3164  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3165  return true;
3166}
3167
3168/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3169/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3170/// when they refer multiple MIOperands inside a single one.
3171bool ARMAsmParser::
3172cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3173                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3174  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3175
3176  // Create a writeback register dummy placeholder.
3177  Inst.addOperand(MCOperand::CreateImm(0));
3178
3179  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3180  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3181  return true;
3182}
3183
3184/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3185/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3186/// when they refer multiple MIOperands inside a single one.
3187bool ARMAsmParser::
3188cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3189                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3190  // Create a writeback register dummy placeholder.
3191  Inst.addOperand(MCOperand::CreateImm(0));
3192  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3193  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3194  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3195  return true;
3196}
3197
3198/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3199/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3200/// when they refer multiple MIOperands inside a single one.
3201bool ARMAsmParser::
3202cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3203                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3204  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3205
3206  // Create a writeback register dummy placeholder.
3207  Inst.addOperand(MCOperand::CreateImm(0));
3208
3209  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3210  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3211  return true;
3212}
3213
3214/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3215/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3216/// when they refer multiple MIOperands inside a single one.
3217bool ARMAsmParser::
3218cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3219                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3220  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3221
3222  // Create a writeback register dummy placeholder.
3223  Inst.addOperand(MCOperand::CreateImm(0));
3224
3225  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3226  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3227  return true;
3228}
3229
3230
3231/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3232/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3233/// when they refer multiple MIOperands inside a single one.
3234bool ARMAsmParser::
3235cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3236                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3237  // Create a writeback register dummy placeholder.
3238  Inst.addOperand(MCOperand::CreateImm(0));
3239  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3240  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3241  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3242  return true;
3243}
3244
3245/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3246/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3247/// when they refer multiple MIOperands inside a single one.
3248bool ARMAsmParser::
3249cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3250                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3251  // Create a writeback register dummy placeholder.
3252  Inst.addOperand(MCOperand::CreateImm(0));
3253  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3254  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3255  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3256  return true;
3257}
3258
3259/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3260/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3261/// when they refer multiple MIOperands inside a single one.
3262bool ARMAsmParser::
3263cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3264                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3265  // Create a writeback register dummy placeholder.
3266  Inst.addOperand(MCOperand::CreateImm(0));
3267  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3268  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3269  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3270  return true;
3271}
3272
3273/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
3274/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3275/// when they refer multiple MIOperands inside a single one.
3276bool ARMAsmParser::
3277cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3278                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3279  // Rt
3280  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3281  // Create a writeback register dummy placeholder.
3282  Inst.addOperand(MCOperand::CreateImm(0));
3283  // addr
3284  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3285  // offset
3286  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3287  // pred
3288  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3289  return true;
3290}
3291
3292/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
3293/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3294/// when they refer multiple MIOperands inside a single one.
3295bool ARMAsmParser::
3296cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3297                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3298  // Rt
3299  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3300  // Create a writeback register dummy placeholder.
3301  Inst.addOperand(MCOperand::CreateImm(0));
3302  // addr
3303  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3304  // offset
3305  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3306  // pred
3307  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3308  return true;
3309}
3310
3311/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
3312/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3313/// when they refer multiple MIOperands inside a single one.
3314bool ARMAsmParser::
3315cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3316                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3317  // Create a writeback register dummy placeholder.
3318  Inst.addOperand(MCOperand::CreateImm(0));
3319  // Rt
3320  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3321  // addr
3322  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3323  // offset
3324  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3325  // pred
3326  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3327  return true;
3328}
3329
3330/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
3331/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3332/// when they refer multiple MIOperands inside a single one.
3333bool ARMAsmParser::
3334cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3335                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3336  // Create a writeback register dummy placeholder.
3337  Inst.addOperand(MCOperand::CreateImm(0));
3338  // Rt
3339  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3340  // addr
3341  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3342  // offset
3343  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3344  // pred
3345  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3346  return true;
3347}
3348
3349/// cvtLdrdPre - Convert parsed operands to MCInst.
3350/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3351/// when they refer multiple MIOperands inside a single one.
3352bool ARMAsmParser::
3353cvtLdrdPre(MCInst &Inst, unsigned Opcode,
3354           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3355  // Rt, Rt2
3356  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3357  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3358  // Create a writeback register dummy placeholder.
3359  Inst.addOperand(MCOperand::CreateImm(0));
3360  // addr
3361  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3362  // pred
3363  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3364  return true;
3365}
3366
3367/// cvtStrdPre - Convert parsed operands to MCInst.
3368/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3369/// when they refer multiple MIOperands inside a single one.
3370bool ARMAsmParser::
3371cvtStrdPre(MCInst &Inst, unsigned Opcode,
3372           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3373  // Create a writeback register dummy placeholder.
3374  Inst.addOperand(MCOperand::CreateImm(0));
3375  // Rt, Rt2
3376  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3377  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3378  // addr
3379  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3380  // pred
3381  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3382  return true;
3383}
3384
3385/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3386/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3387/// when they refer multiple MIOperands inside a single one.
3388bool ARMAsmParser::
3389cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3390                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3391  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3392  // Create a writeback register dummy placeholder.
3393  Inst.addOperand(MCOperand::CreateImm(0));
3394  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3395  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3396  return true;
3397}
3398
3399/// cvtThumbMultiple- Convert parsed operands to MCInst.
3400/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3401/// when they refer multiple MIOperands inside a single one.
3402bool ARMAsmParser::
3403cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
3404           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3405  // The second source operand must be the same register as the destination
3406  // operand.
3407  if (Operands.size() == 6 &&
3408      (((ARMOperand*)Operands[3])->getReg() !=
3409       ((ARMOperand*)Operands[5])->getReg()) &&
3410      (((ARMOperand*)Operands[3])->getReg() !=
3411       ((ARMOperand*)Operands[4])->getReg())) {
3412    Error(Operands[3]->getStartLoc(),
3413          "destination register must match source register");
3414    return false;
3415  }
3416  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3417  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
3418  // If we have a three-operand form, make sure to set Rn to be the operand
3419  // that isn't the same as Rd.
3420  unsigned RegOp = 4;
3421  if (Operands.size() == 6 &&
3422      ((ARMOperand*)Operands[4])->getReg() ==
3423        ((ARMOperand*)Operands[3])->getReg())
3424    RegOp = 5;
3425  ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
3426  Inst.addOperand(Inst.getOperand(0));
3427  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
3428
3429  return true;
3430}
3431
3432bool ARMAsmParser::
3433cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
3434              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3435  // Vd
3436  ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3437  // Create a writeback register dummy placeholder.
3438  Inst.addOperand(MCOperand::CreateImm(0));
3439  // Vn
3440  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3441  // pred
3442  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3443  return true;
3444}
3445
3446bool ARMAsmParser::
3447cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
3448                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3449  // Vd
3450  ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3451  // Create a writeback register dummy placeholder.
3452  Inst.addOperand(MCOperand::CreateImm(0));
3453  // Vn
3454  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3455  // Vm
3456  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3457  // pred
3458  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3459  return true;
3460}
3461
3462bool ARMAsmParser::
3463cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
3464              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3465  // Create a writeback register dummy placeholder.
3466  Inst.addOperand(MCOperand::CreateImm(0));
3467  // Vn
3468  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3469  // Vt
3470  ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3471  // pred
3472  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3473  return true;
3474}
3475
3476bool ARMAsmParser::
3477cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
3478                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3479  // Create a writeback register dummy placeholder.
3480  Inst.addOperand(MCOperand::CreateImm(0));
3481  // Vn
3482  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3483  // Vm
3484  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3485  // Vt
3486  ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3487  // pred
3488  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3489  return true;
3490}
3491
3492/// Parse an ARM memory expression, return false if successful else return true
3493/// or an error.  The first token must be a '[' when called.
3494bool ARMAsmParser::
3495parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3496  SMLoc S, E;
3497  assert(Parser.getTok().is(AsmToken::LBrac) &&
3498         "Token is not a Left Bracket");
3499  S = Parser.getTok().getLoc();
3500  Parser.Lex(); // Eat left bracket token.
3501
3502  const AsmToken &BaseRegTok = Parser.getTok();
3503  int BaseRegNum = tryParseRegister();
3504  if (BaseRegNum == -1)
3505    return Error(BaseRegTok.getLoc(), "register expected");
3506
3507  // The next token must either be a comma or a closing bracket.
3508  const AsmToken &Tok = Parser.getTok();
3509  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
3510    return Error(Tok.getLoc(), "malformed memory operand");
3511
3512  if (Tok.is(AsmToken::RBrac)) {
3513    E = Tok.getLoc();
3514    Parser.Lex(); // Eat right bracket token.
3515
3516    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
3517                                             0, 0, false, S, E));
3518
3519    // If there's a pre-indexing writeback marker, '!', just add it as a token
3520    // operand. It's rather odd, but syntactically valid.
3521    if (Parser.getTok().is(AsmToken::Exclaim)) {
3522      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3523      Parser.Lex(); // Eat the '!'.
3524    }
3525
3526    return false;
3527  }
3528
3529  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
3530  Parser.Lex(); // Eat the comma.
3531
3532  // If we have a ':', it's an alignment specifier.
3533  if (Parser.getTok().is(AsmToken::Colon)) {
3534    Parser.Lex(); // Eat the ':'.
3535    E = Parser.getTok().getLoc();
3536
3537    const MCExpr *Expr;
3538    if (getParser().ParseExpression(Expr))
3539     return true;
3540
3541    // The expression has to be a constant. Memory references with relocations
3542    // don't come through here, as they use the <label> forms of the relevant
3543    // instructions.
3544    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3545    if (!CE)
3546      return Error (E, "constant expression expected");
3547
3548    unsigned Align = 0;
3549    switch (CE->getValue()) {
3550    default:
3551      return Error(E, "alignment specifier must be 64, 128, or 256 bits");
3552    case 64:  Align = 8; break;
3553    case 128: Align = 16; break;
3554    case 256: Align = 32; break;
3555    }
3556
3557    // Now we should have the closing ']'
3558    E = Parser.getTok().getLoc();
3559    if (Parser.getTok().isNot(AsmToken::RBrac))
3560      return Error(E, "']' expected");
3561    Parser.Lex(); // Eat right bracket token.
3562
3563    // Don't worry about range checking the value here. That's handled by
3564    // the is*() predicates.
3565    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
3566                                             ARM_AM::no_shift, 0, Align,
3567                                             false, S, E));
3568
3569    // If there's a pre-indexing writeback marker, '!', just add it as a token
3570    // operand.
3571    if (Parser.getTok().is(AsmToken::Exclaim)) {
3572      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3573      Parser.Lex(); // Eat the '!'.
3574    }
3575
3576    return false;
3577  }
3578
3579  // If we have a '#', it's an immediate offset, else assume it's a register
3580  // offset.
3581  if (Parser.getTok().is(AsmToken::Hash)) {
3582    Parser.Lex(); // Eat the '#'.
3583    E = Parser.getTok().getLoc();
3584
3585    bool isNegative = getParser().getTok().is(AsmToken::Minus);
3586    const MCExpr *Offset;
3587    if (getParser().ParseExpression(Offset))
3588     return true;
3589
3590    // The expression has to be a constant. Memory references with relocations
3591    // don't come through here, as they use the <label> forms of the relevant
3592    // instructions.
3593    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3594    if (!CE)
3595      return Error (E, "constant expression expected");
3596
3597    // If the constant was #-0, represent it as INT32_MIN.
3598    int32_t Val = CE->getValue();
3599    if (isNegative && Val == 0)
3600      CE = MCConstantExpr::Create(INT32_MIN, getContext());
3601
3602    // Now we should have the closing ']'
3603    E = Parser.getTok().getLoc();
3604    if (Parser.getTok().isNot(AsmToken::RBrac))
3605      return Error(E, "']' expected");
3606    Parser.Lex(); // Eat right bracket token.
3607
3608    // Don't worry about range checking the value here. That's handled by
3609    // the is*() predicates.
3610    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
3611                                             ARM_AM::no_shift, 0, 0,
3612                                             false, S, E));
3613
3614    // If there's a pre-indexing writeback marker, '!', just add it as a token
3615    // operand.
3616    if (Parser.getTok().is(AsmToken::Exclaim)) {
3617      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3618      Parser.Lex(); // Eat the '!'.
3619    }
3620
3621    return false;
3622  }
3623
3624  // The register offset is optionally preceded by a '+' or '-'
3625  bool isNegative = false;
3626  if (Parser.getTok().is(AsmToken::Minus)) {
3627    isNegative = true;
3628    Parser.Lex(); // Eat the '-'.
3629  } else if (Parser.getTok().is(AsmToken::Plus)) {
3630    // Nothing to do.
3631    Parser.Lex(); // Eat the '+'.
3632  }
3633
3634  E = Parser.getTok().getLoc();
3635  int OffsetRegNum = tryParseRegister();
3636  if (OffsetRegNum == -1)
3637    return Error(E, "register expected");
3638
3639  // If there's a shift operator, handle it.
3640  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
3641  unsigned ShiftImm = 0;
3642  if (Parser.getTok().is(AsmToken::Comma)) {
3643    Parser.Lex(); // Eat the ','.
3644    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
3645      return true;
3646  }
3647
3648  // Now we should have the closing ']'
3649  E = Parser.getTok().getLoc();
3650  if (Parser.getTok().isNot(AsmToken::RBrac))
3651    return Error(E, "']' expected");
3652  Parser.Lex(); // Eat right bracket token.
3653
3654  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
3655                                           ShiftType, ShiftImm, 0, isNegative,
3656                                           S, E));
3657
3658  // If there's a pre-indexing writeback marker, '!', just add it as a token
3659  // operand.
3660  if (Parser.getTok().is(AsmToken::Exclaim)) {
3661    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3662    Parser.Lex(); // Eat the '!'.
3663  }
3664
3665  return false;
3666}
3667
3668/// parseMemRegOffsetShift - one of these two:
3669///   ( lsl | lsr | asr | ror ) , # shift_amount
3670///   rrx
3671/// return true if it parses a shift otherwise it returns false.
3672bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
3673                                          unsigned &Amount) {
3674  SMLoc Loc = Parser.getTok().getLoc();
3675  const AsmToken &Tok = Parser.getTok();
3676  if (Tok.isNot(AsmToken::Identifier))
3677    return true;
3678  StringRef ShiftName = Tok.getString();
3679  if (ShiftName == "lsl" || ShiftName == "LSL")
3680    St = ARM_AM::lsl;
3681  else if (ShiftName == "lsr" || ShiftName == "LSR")
3682    St = ARM_AM::lsr;
3683  else if (ShiftName == "asr" || ShiftName == "ASR")
3684    St = ARM_AM::asr;
3685  else if (ShiftName == "ror" || ShiftName == "ROR")
3686    St = ARM_AM::ror;
3687  else if (ShiftName == "rrx" || ShiftName == "RRX")
3688    St = ARM_AM::rrx;
3689  else
3690    return Error(Loc, "illegal shift operator");
3691  Parser.Lex(); // Eat shift type token.
3692
3693  // rrx stands alone.
3694  Amount = 0;
3695  if (St != ARM_AM::rrx) {
3696    Loc = Parser.getTok().getLoc();
3697    // A '#' and a shift amount.
3698    const AsmToken &HashTok = Parser.getTok();
3699    if (HashTok.isNot(AsmToken::Hash))
3700      return Error(HashTok.getLoc(), "'#' expected");
3701    Parser.Lex(); // Eat hash token.
3702
3703    const MCExpr *Expr;
3704    if (getParser().ParseExpression(Expr))
3705      return true;
3706    // Range check the immediate.
3707    // lsl, ror: 0 <= imm <= 31
3708    // lsr, asr: 0 <= imm <= 32
3709    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3710    if (!CE)
3711      return Error(Loc, "shift amount must be an immediate");
3712    int64_t Imm = CE->getValue();
3713    if (Imm < 0 ||
3714        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
3715        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
3716      return Error(Loc, "immediate shift value out of range");
3717    Amount = Imm;
3718  }
3719
3720  return false;
3721}
3722
3723/// parseFPImm - A floating point immediate expression operand.
3724ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3725parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3726  SMLoc S = Parser.getTok().getLoc();
3727
3728  if (Parser.getTok().isNot(AsmToken::Hash))
3729    return MatchOperand_NoMatch;
3730
3731  // Disambiguate the VMOV forms that can accept an FP immediate.
3732  // vmov.f32 <sreg>, #imm
3733  // vmov.f64 <dreg>, #imm
3734  // vmov.f32 <dreg>, #imm  @ vector f32x2
3735  // vmov.f32 <qreg>, #imm  @ vector f32x4
3736  //
3737  // There are also the NEON VMOV instructions which expect an
3738  // integer constant. Make sure we don't try to parse an FPImm
3739  // for these:
3740  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
3741  ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
3742  if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
3743                           TyOp->getToken() != ".f64"))
3744    return MatchOperand_NoMatch;
3745
3746  Parser.Lex(); // Eat the '#'.
3747
3748  // Handle negation, as that still comes through as a separate token.
3749  bool isNegative = false;
3750  if (Parser.getTok().is(AsmToken::Minus)) {
3751    isNegative = true;
3752    Parser.Lex();
3753  }
3754  const AsmToken &Tok = Parser.getTok();
3755  if (Tok.is(AsmToken::Real)) {
3756    APFloat RealVal(APFloat::IEEEdouble, Tok.getString());
3757    uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
3758    // If we had a '-' in front, toggle the sign bit.
3759    IntVal ^= (uint64_t)isNegative << 63;
3760    int Val = ARM_AM::getFP64Imm(APInt(64, IntVal));
3761    Parser.Lex(); // Eat the token.
3762    if (Val == -1) {
3763      TokError("floating point value out of range");
3764      return MatchOperand_ParseFail;
3765    }
3766    Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
3767    return MatchOperand_Success;
3768  }
3769  if (Tok.is(AsmToken::Integer)) {
3770    int64_t Val = Tok.getIntVal();
3771    Parser.Lex(); // Eat the token.
3772    if (Val > 255 || Val < 0) {
3773      TokError("encoded floating point value out of range");
3774      return MatchOperand_ParseFail;
3775    }
3776    Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
3777    return MatchOperand_Success;
3778  }
3779
3780  TokError("invalid floating point immediate");
3781  return MatchOperand_ParseFail;
3782}
3783/// Parse a arm instruction operand.  For now this parses the operand regardless
3784/// of the mnemonic.
3785bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3786                                StringRef Mnemonic) {
3787  SMLoc S, E;
3788
3789  // Check if the current operand has a custom associated parser, if so, try to
3790  // custom parse the operand, or fallback to the general approach.
3791  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
3792  if (ResTy == MatchOperand_Success)
3793    return false;
3794  // If there wasn't a custom match, try the generic matcher below. Otherwise,
3795  // there was a match, but an error occurred, in which case, just return that
3796  // the operand parsing failed.
3797  if (ResTy == MatchOperand_ParseFail)
3798    return true;
3799
3800  switch (getLexer().getKind()) {
3801  default:
3802    Error(Parser.getTok().getLoc(), "unexpected token in operand");
3803    return true;
3804  case AsmToken::Identifier: {
3805    // If this is VMRS, check for the apsr_nzcv operand.
3806    if (!tryParseRegisterWithWriteBack(Operands))
3807      return false;
3808    int Res = tryParseShiftRegister(Operands);
3809    if (Res == 0) // success
3810      return false;
3811    else if (Res == -1) // irrecoverable error
3812      return true;
3813    if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") {
3814      S = Parser.getTok().getLoc();
3815      Parser.Lex();
3816      Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S));
3817      return false;
3818    }
3819
3820    // Fall though for the Identifier case that is not a register or a
3821    // special name.
3822  }
3823  case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
3824  case AsmToken::Integer: // things like 1f and 2b as a branch targets
3825  case AsmToken::String:  // quoted label names.
3826  case AsmToken::Dot: {   // . as a branch target
3827    // This was not a register so parse other operands that start with an
3828    // identifier (like labels) as expressions and create them as immediates.
3829    const MCExpr *IdVal;
3830    S = Parser.getTok().getLoc();
3831    if (getParser().ParseExpression(IdVal))
3832      return true;
3833    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3834    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
3835    return false;
3836  }
3837  case AsmToken::LBrac:
3838    return parseMemory(Operands);
3839  case AsmToken::LCurly:
3840    return parseRegisterList(Operands);
3841  case AsmToken::Hash: {
3842    // #42 -> immediate.
3843    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
3844    S = Parser.getTok().getLoc();
3845    Parser.Lex();
3846    bool isNegative = Parser.getTok().is(AsmToken::Minus);
3847    const MCExpr *ImmVal;
3848    if (getParser().ParseExpression(ImmVal))
3849      return true;
3850    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
3851    if (CE) {
3852      int32_t Val = CE->getValue();
3853      if (isNegative && Val == 0)
3854        ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
3855    }
3856    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3857    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
3858    return false;
3859  }
3860  case AsmToken::Colon: {
3861    // ":lower16:" and ":upper16:" expression prefixes
3862    // FIXME: Check it's an expression prefix,
3863    // e.g. (FOO - :lower16:BAR) isn't legal.
3864    ARMMCExpr::VariantKind RefKind;
3865    if (parsePrefix(RefKind))
3866      return true;
3867
3868    const MCExpr *SubExprVal;
3869    if (getParser().ParseExpression(SubExprVal))
3870      return true;
3871
3872    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
3873                                                   getContext());
3874    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3875    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
3876    return false;
3877  }
3878  }
3879}
3880
3881// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
3882//  :lower16: and :upper16:.
3883bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
3884  RefKind = ARMMCExpr::VK_ARM_None;
3885
3886  // :lower16: and :upper16: modifiers
3887  assert(getLexer().is(AsmToken::Colon) && "expected a :");
3888  Parser.Lex(); // Eat ':'
3889
3890  if (getLexer().isNot(AsmToken::Identifier)) {
3891    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
3892    return true;
3893  }
3894
3895  StringRef IDVal = Parser.getTok().getIdentifier();
3896  if (IDVal == "lower16") {
3897    RefKind = ARMMCExpr::VK_ARM_LO16;
3898  } else if (IDVal == "upper16") {
3899    RefKind = ARMMCExpr::VK_ARM_HI16;
3900  } else {
3901    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
3902    return true;
3903  }
3904  Parser.Lex();
3905
3906  if (getLexer().isNot(AsmToken::Colon)) {
3907    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
3908    return true;
3909  }
3910  Parser.Lex(); // Eat the last ':'
3911  return false;
3912}
3913
3914/// \brief Given a mnemonic, split out possible predication code and carry
3915/// setting letters to form a canonical mnemonic and flags.
3916//
3917// FIXME: Would be nice to autogen this.
3918// FIXME: This is a bit of a maze of special cases.
3919StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
3920                                      unsigned &PredicationCode,
3921                                      bool &CarrySetting,
3922                                      unsigned &ProcessorIMod,
3923                                      StringRef &ITMask) {
3924  PredicationCode = ARMCC::AL;
3925  CarrySetting = false;
3926  ProcessorIMod = 0;
3927
3928  // Ignore some mnemonics we know aren't predicated forms.
3929  //
3930  // FIXME: Would be nice to autogen this.
3931  if ((Mnemonic == "movs" && isThumb()) ||
3932      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
3933      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
3934      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
3935      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
3936      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
3937      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
3938      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
3939    return Mnemonic;
3940
3941  // First, split out any predication code. Ignore mnemonics we know aren't
3942  // predicated but do have a carry-set and so weren't caught above.
3943  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
3944      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
3945      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
3946      Mnemonic != "sbcs" && Mnemonic != "rscs") {
3947    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
3948      .Case("eq", ARMCC::EQ)
3949      .Case("ne", ARMCC::NE)
3950      .Case("hs", ARMCC::HS)
3951      .Case("cs", ARMCC::HS)
3952      .Case("lo", ARMCC::LO)
3953      .Case("cc", ARMCC::LO)
3954      .Case("mi", ARMCC::MI)
3955      .Case("pl", ARMCC::PL)
3956      .Case("vs", ARMCC::VS)
3957      .Case("vc", ARMCC::VC)
3958      .Case("hi", ARMCC::HI)
3959      .Case("ls", ARMCC::LS)
3960      .Case("ge", ARMCC::GE)
3961      .Case("lt", ARMCC::LT)
3962      .Case("gt", ARMCC::GT)
3963      .Case("le", ARMCC::LE)
3964      .Case("al", ARMCC::AL)
3965      .Default(~0U);
3966    if (CC != ~0U) {
3967      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
3968      PredicationCode = CC;
3969    }
3970  }
3971
3972  // Next, determine if we have a carry setting bit. We explicitly ignore all
3973  // the instructions we know end in 's'.
3974  if (Mnemonic.endswith("s") &&
3975      !(Mnemonic == "cps" || Mnemonic == "mls" ||
3976        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
3977        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
3978        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
3979        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
3980        (Mnemonic == "movs" && isThumb()))) {
3981    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
3982    CarrySetting = true;
3983  }
3984
3985  // The "cps" instruction can have a interrupt mode operand which is glued into
3986  // the mnemonic. Check if this is the case, split it and parse the imod op
3987  if (Mnemonic.startswith("cps")) {
3988    // Split out any imod code.
3989    unsigned IMod =
3990      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
3991      .Case("ie", ARM_PROC::IE)
3992      .Case("id", ARM_PROC::ID)
3993      .Default(~0U);
3994    if (IMod != ~0U) {
3995      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
3996      ProcessorIMod = IMod;
3997    }
3998  }
3999
4000  // The "it" instruction has the condition mask on the end of the mnemonic.
4001  if (Mnemonic.startswith("it")) {
4002    ITMask = Mnemonic.slice(2, Mnemonic.size());
4003    Mnemonic = Mnemonic.slice(0, 2);
4004  }
4005
4006  return Mnemonic;
4007}
4008
4009/// \brief Given a canonical mnemonic, determine if the instruction ever allows
4010/// inclusion of carry set or predication code operands.
4011//
4012// FIXME: It would be nice to autogen this.
4013void ARMAsmParser::
4014getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4015                      bool &CanAcceptPredicationCode) {
4016  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4017      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4018      Mnemonic == "add" || Mnemonic == "adc" ||
4019      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4020      Mnemonic == "orr" || Mnemonic == "mvn" ||
4021      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4022      Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4023      (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4024                      Mnemonic == "mla" || Mnemonic == "smlal" ||
4025                      Mnemonic == "umlal" || Mnemonic == "umull"))) {
4026    CanAcceptCarrySet = true;
4027  } else
4028    CanAcceptCarrySet = false;
4029
4030  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4031      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4032      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4033      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4034      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4035      (Mnemonic == "clrex" && !isThumb()) ||
4036      (Mnemonic == "nop" && isThumbOne()) ||
4037      ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4038        Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4039        Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4040      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4041       !isThumb()) ||
4042      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4043    CanAcceptPredicationCode = false;
4044  } else
4045    CanAcceptPredicationCode = true;
4046
4047  if (isThumb()) {
4048    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4049        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4050      CanAcceptPredicationCode = false;
4051  }
4052}
4053
4054bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4055                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4056  // FIXME: This is all horribly hacky. We really need a better way to deal
4057  // with optional operands like this in the matcher table.
4058
4059  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4060  // another does not. Specifically, the MOVW instruction does not. So we
4061  // special case it here and remove the defaulted (non-setting) cc_out
4062  // operand if that's the instruction we're trying to match.
4063  //
4064  // We do this as post-processing of the explicit operands rather than just
4065  // conditionally adding the cc_out in the first place because we need
4066  // to check the type of the parsed immediate operand.
4067  if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4068      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4069      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4070      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4071    return true;
4072
4073  // Register-register 'add' for thumb does not have a cc_out operand
4074  // when there are only two register operands.
4075  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4076      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4077      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4078      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4079    return true;
4080  // Register-register 'add' for thumb does not have a cc_out operand
4081  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4082  // have to check the immediate range here since Thumb2 has a variant
4083  // that can handle a different range and has a cc_out operand.
4084  if (((isThumb() && Mnemonic == "add") ||
4085       (isThumbTwo() && Mnemonic == "sub")) &&
4086      Operands.size() == 6 &&
4087      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4088      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4089      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4090      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4091      (static_cast<ARMOperand*>(Operands[5])->isReg() ||
4092       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4093    return true;
4094  // For Thumb2, add/sub immediate does not have a cc_out operand for the
4095  // imm0_4095 variant. That's the least-preferred variant when
4096  // selecting via the generic "add" mnemonic, so to know that we
4097  // should remove the cc_out operand, we have to explicitly check that
4098  // it's not one of the other variants. Ugh.
4099  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4100      Operands.size() == 6 &&
4101      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4102      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4103      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4104    // Nest conditions rather than one big 'if' statement for readability.
4105    //
4106    // If either register is a high reg, it's either one of the SP
4107    // variants (handled above) or a 32-bit encoding, so we just
4108    // check against T3.
4109    if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4110         !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4111        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4112      return false;
4113    // If both registers are low, we're in an IT block, and the immediate is
4114    // in range, we should use encoding T1 instead, which has a cc_out.
4115    if (inITBlock() &&
4116        isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4117        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4118        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4119      return false;
4120
4121    // Otherwise, we use encoding T4, which does not have a cc_out
4122    // operand.
4123    return true;
4124  }
4125
4126  // The thumb2 multiply instruction doesn't have a CCOut register, so
4127  // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4128  // use the 16-bit encoding or not.
4129  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4130      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4131      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4132      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4133      static_cast<ARMOperand*>(Operands[5])->isReg() &&
4134      // If the registers aren't low regs, the destination reg isn't the
4135      // same as one of the source regs, or the cc_out operand is zero
4136      // outside of an IT block, we have to use the 32-bit encoding, so
4137      // remove the cc_out operand.
4138      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4139       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4140       !inITBlock() ||
4141       (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4142        static_cast<ARMOperand*>(Operands[5])->getReg() &&
4143        static_cast<ARMOperand*>(Operands[3])->getReg() !=
4144        static_cast<ARMOperand*>(Operands[4])->getReg())))
4145    return true;
4146
4147
4148
4149  // Register-register 'add/sub' for thumb does not have a cc_out operand
4150  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4151  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4152  // right, this will result in better diagnostics (which operand is off)
4153  // anyway.
4154  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4155      (Operands.size() == 5 || Operands.size() == 6) &&
4156      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4157      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4158      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4159    return true;
4160
4161  return false;
4162}
4163
4164/// Parse an arm instruction mnemonic followed by its operands.
4165bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4166                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4167  // Create the leading tokens for the mnemonic, split by '.' characters.
4168  size_t Start = 0, Next = Name.find('.');
4169  StringRef Mnemonic = Name.slice(Start, Next);
4170
4171  // Split out the predication code and carry setting flag from the mnemonic.
4172  unsigned PredicationCode;
4173  unsigned ProcessorIMod;
4174  bool CarrySetting;
4175  StringRef ITMask;
4176  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
4177                           ProcessorIMod, ITMask);
4178
4179  // In Thumb1, only the branch (B) instruction can be predicated.
4180  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
4181    Parser.EatToEndOfStatement();
4182    return Error(NameLoc, "conditional execution not supported in Thumb1");
4183  }
4184
4185  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
4186
4187  // Handle the IT instruction ITMask. Convert it to a bitmask. This
4188  // is the mask as it will be for the IT encoding if the conditional
4189  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
4190  // where the conditional bit0 is zero, the instruction post-processing
4191  // will adjust the mask accordingly.
4192  if (Mnemonic == "it") {
4193    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
4194    if (ITMask.size() > 3) {
4195      Parser.EatToEndOfStatement();
4196      return Error(Loc, "too many conditions on IT instruction");
4197    }
4198    unsigned Mask = 8;
4199    for (unsigned i = ITMask.size(); i != 0; --i) {
4200      char pos = ITMask[i - 1];
4201      if (pos != 't' && pos != 'e') {
4202        Parser.EatToEndOfStatement();
4203        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
4204      }
4205      Mask >>= 1;
4206      if (ITMask[i - 1] == 't')
4207        Mask |= 8;
4208    }
4209    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
4210  }
4211
4212  // FIXME: This is all a pretty gross hack. We should automatically handle
4213  // optional operands like this via tblgen.
4214
4215  // Next, add the CCOut and ConditionCode operands, if needed.
4216  //
4217  // For mnemonics which can ever incorporate a carry setting bit or predication
4218  // code, our matching model involves us always generating CCOut and
4219  // ConditionCode operands to match the mnemonic "as written" and then we let
4220  // the matcher deal with finding the right instruction or generating an
4221  // appropriate error.
4222  bool CanAcceptCarrySet, CanAcceptPredicationCode;
4223  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
4224
4225  // If we had a carry-set on an instruction that can't do that, issue an
4226  // error.
4227  if (!CanAcceptCarrySet && CarrySetting) {
4228    Parser.EatToEndOfStatement();
4229    return Error(NameLoc, "instruction '" + Mnemonic +
4230                 "' can not set flags, but 's' suffix specified");
4231  }
4232  // If we had a predication code on an instruction that can't do that, issue an
4233  // error.
4234  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
4235    Parser.EatToEndOfStatement();
4236    return Error(NameLoc, "instruction '" + Mnemonic +
4237                 "' is not predicable, but condition code specified");
4238  }
4239
4240  // Add the carry setting operand, if necessary.
4241  if (CanAcceptCarrySet) {
4242    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
4243    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
4244                                               Loc));
4245  }
4246
4247  // Add the predication code operand, if necessary.
4248  if (CanAcceptPredicationCode) {
4249    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
4250                                      CarrySetting);
4251    Operands.push_back(ARMOperand::CreateCondCode(
4252                         ARMCC::CondCodes(PredicationCode), Loc));
4253  }
4254
4255  // Add the processor imod operand, if necessary.
4256  if (ProcessorIMod) {
4257    Operands.push_back(ARMOperand::CreateImm(
4258          MCConstantExpr::Create(ProcessorIMod, getContext()),
4259                                 NameLoc, NameLoc));
4260  }
4261
4262  // Add the remaining tokens in the mnemonic.
4263  while (Next != StringRef::npos) {
4264    Start = Next;
4265    Next = Name.find('.', Start + 1);
4266    StringRef ExtraToken = Name.slice(Start, Next);
4267
4268    // For now, we're only parsing Thumb1 (for the most part), so
4269    // just ignore ".n" qualifiers. We'll use them to restrict
4270    // matching when we do Thumb2.
4271    if (ExtraToken != ".n") {
4272      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
4273      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
4274    }
4275  }
4276
4277  // Read the remaining operands.
4278  if (getLexer().isNot(AsmToken::EndOfStatement)) {
4279    // Read the first operand.
4280    if (parseOperand(Operands, Mnemonic)) {
4281      Parser.EatToEndOfStatement();
4282      return true;
4283    }
4284
4285    while (getLexer().is(AsmToken::Comma)) {
4286      Parser.Lex();  // Eat the comma.
4287
4288      // Parse and remember the operand.
4289      if (parseOperand(Operands, Mnemonic)) {
4290        Parser.EatToEndOfStatement();
4291        return true;
4292      }
4293    }
4294  }
4295
4296  if (getLexer().isNot(AsmToken::EndOfStatement)) {
4297    SMLoc Loc = getLexer().getLoc();
4298    Parser.EatToEndOfStatement();
4299    return Error(Loc, "unexpected token in argument list");
4300  }
4301
4302  Parser.Lex(); // Consume the EndOfStatement
4303
4304  // Some instructions, mostly Thumb, have forms for the same mnemonic that
4305  // do and don't have a cc_out optional-def operand. With some spot-checks
4306  // of the operand list, we can figure out which variant we're trying to
4307  // parse and adjust accordingly before actually matching. We shouldn't ever
4308  // try to remove a cc_out operand that was explicitly set on the the
4309  // mnemonic, of course (CarrySetting == true). Reason number #317 the
4310  // table driven matcher doesn't fit well with the ARM instruction set.
4311  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
4312    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4313    Operands.erase(Operands.begin() + 1);
4314    delete Op;
4315  }
4316
4317  // ARM mode 'blx' need special handling, as the register operand version
4318  // is predicable, but the label operand version is not. So, we can't rely
4319  // on the Mnemonic based checking to correctly figure out when to put
4320  // a k_CondCode operand in the list. If we're trying to match the label
4321  // version, remove the k_CondCode operand here.
4322  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
4323      static_cast<ARMOperand*>(Operands[2])->isImm()) {
4324    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4325    Operands.erase(Operands.begin() + 1);
4326    delete Op;
4327  }
4328
4329  // The vector-compare-to-zero instructions have a literal token "#0" at
4330  // the end that comes to here as an immediate operand. Convert it to a
4331  // token to play nicely with the matcher.
4332  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
4333      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
4334      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4335    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4336    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4337    if (CE && CE->getValue() == 0) {
4338      Operands.erase(Operands.begin() + 5);
4339      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4340      delete Op;
4341    }
4342  }
4343  // VCMP{E} does the same thing, but with a different operand count.
4344  if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
4345      static_cast<ARMOperand*>(Operands[4])->isImm()) {
4346    ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
4347    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4348    if (CE && CE->getValue() == 0) {
4349      Operands.erase(Operands.begin() + 4);
4350      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4351      delete Op;
4352    }
4353  }
4354  // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
4355  // end. Convert it to a token here.
4356  if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
4357      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4358    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4359    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4360    if (CE && CE->getValue() == 0) {
4361      Operands.erase(Operands.begin() + 5);
4362      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4363      delete Op;
4364    }
4365  }
4366
4367  return false;
4368}
4369
4370// Validate context-sensitive operand constraints.
4371
4372// return 'true' if register list contains non-low GPR registers,
4373// 'false' otherwise. If Reg is in the register list or is HiReg, set
4374// 'containsReg' to true.
4375static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
4376                                 unsigned HiReg, bool &containsReg) {
4377  containsReg = false;
4378  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4379    unsigned OpReg = Inst.getOperand(i).getReg();
4380    if (OpReg == Reg)
4381      containsReg = true;
4382    // Anything other than a low register isn't legal here.
4383    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
4384      return true;
4385  }
4386  return false;
4387}
4388
4389// Check if the specified regisgter is in the register list of the inst,
4390// starting at the indicated operand number.
4391static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
4392  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4393    unsigned OpReg = Inst.getOperand(i).getReg();
4394    if (OpReg == Reg)
4395      return true;
4396  }
4397  return false;
4398}
4399
4400// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
4401// the ARMInsts array) instead. Getting that here requires awkward
4402// API changes, though. Better way?
4403namespace llvm {
4404extern const MCInstrDesc ARMInsts[];
4405}
4406static const MCInstrDesc &getInstDesc(unsigned Opcode) {
4407  return ARMInsts[Opcode];
4408}
4409
4410// FIXME: We would really like to be able to tablegen'erate this.
4411bool ARMAsmParser::
4412validateInstruction(MCInst &Inst,
4413                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4414  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
4415  SMLoc Loc = Operands[0]->getStartLoc();
4416  // Check the IT block state first.
4417  // NOTE: In Thumb mode, the BKPT instruction has the interesting property of
4418  // being allowed in IT blocks, but not being predicable.  It just always
4419  // executes.
4420  if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
4421    unsigned bit = 1;
4422    if (ITState.FirstCond)
4423      ITState.FirstCond = false;
4424    else
4425      bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
4426    // The instruction must be predicable.
4427    if (!MCID.isPredicable())
4428      return Error(Loc, "instructions in IT block must be predicable");
4429    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
4430    unsigned ITCond = bit ? ITState.Cond :
4431      ARMCC::getOppositeCondition(ITState.Cond);
4432    if (Cond != ITCond) {
4433      // Find the condition code Operand to get its SMLoc information.
4434      SMLoc CondLoc;
4435      for (unsigned i = 1; i < Operands.size(); ++i)
4436        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
4437          CondLoc = Operands[i]->getStartLoc();
4438      return Error(CondLoc, "incorrect condition in IT block; got '" +
4439                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
4440                   "', but expected '" +
4441                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
4442    }
4443  // Check for non-'al' condition codes outside of the IT block.
4444  } else if (isThumbTwo() && MCID.isPredicable() &&
4445             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
4446             ARMCC::AL && Inst.getOpcode() != ARM::tB &&
4447             Inst.getOpcode() != ARM::t2B)
4448    return Error(Loc, "predicated instructions must be in IT block");
4449
4450  switch (Inst.getOpcode()) {
4451  case ARM::LDRD:
4452  case ARM::LDRD_PRE:
4453  case ARM::LDRD_POST:
4454  case ARM::LDREXD: {
4455    // Rt2 must be Rt + 1.
4456    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4457    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4458    if (Rt2 != Rt + 1)
4459      return Error(Operands[3]->getStartLoc(),
4460                   "destination operands must be sequential");
4461    return false;
4462  }
4463  case ARM::STRD: {
4464    // Rt2 must be Rt + 1.
4465    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4466    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4467    if (Rt2 != Rt + 1)
4468      return Error(Operands[3]->getStartLoc(),
4469                   "source operands must be sequential");
4470    return false;
4471  }
4472  case ARM::STRD_PRE:
4473  case ARM::STRD_POST:
4474  case ARM::STREXD: {
4475    // Rt2 must be Rt + 1.
4476    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4477    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
4478    if (Rt2 != Rt + 1)
4479      return Error(Operands[3]->getStartLoc(),
4480                   "source operands must be sequential");
4481    return false;
4482  }
4483  case ARM::SBFX:
4484  case ARM::UBFX: {
4485    // width must be in range [1, 32-lsb]
4486    unsigned lsb = Inst.getOperand(2).getImm();
4487    unsigned widthm1 = Inst.getOperand(3).getImm();
4488    if (widthm1 >= 32 - lsb)
4489      return Error(Operands[5]->getStartLoc(),
4490                   "bitfield width must be in range [1,32-lsb]");
4491    return false;
4492  }
4493  case ARM::tLDMIA: {
4494    // If we're parsing Thumb2, the .w variant is available and handles
4495    // most cases that are normally illegal for a Thumb1 LDM
4496    // instruction. We'll make the transformation in processInstruction()
4497    // if necessary.
4498    //
4499    // Thumb LDM instructions are writeback iff the base register is not
4500    // in the register list.
4501    unsigned Rn = Inst.getOperand(0).getReg();
4502    bool hasWritebackToken =
4503      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
4504       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
4505    bool listContainsBase;
4506    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
4507      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
4508                   "registers must be in range r0-r7");
4509    // If we should have writeback, then there should be a '!' token.
4510    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
4511      return Error(Operands[2]->getStartLoc(),
4512                   "writeback operator '!' expected");
4513    // If we should not have writeback, there must not be a '!'. This is
4514    // true even for the 32-bit wide encodings.
4515    if (listContainsBase && hasWritebackToken)
4516      return Error(Operands[3]->getStartLoc(),
4517                   "writeback operator '!' not allowed when base register "
4518                   "in register list");
4519
4520    break;
4521  }
4522  case ARM::t2LDMIA_UPD: {
4523    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
4524      return Error(Operands[4]->getStartLoc(),
4525                   "writeback operator '!' not allowed when base register "
4526                   "in register list");
4527    break;
4528  }
4529  case ARM::tPOP: {
4530    bool listContainsBase;
4531    if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
4532      return Error(Operands[2]->getStartLoc(),
4533                   "registers must be in range r0-r7 or pc");
4534    break;
4535  }
4536  case ARM::tPUSH: {
4537    bool listContainsBase;
4538    if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
4539      return Error(Operands[2]->getStartLoc(),
4540                   "registers must be in range r0-r7 or lr");
4541    break;
4542  }
4543  case ARM::tSTMIA_UPD: {
4544    bool listContainsBase;
4545    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
4546      return Error(Operands[4]->getStartLoc(),
4547                   "registers must be in range r0-r7");
4548    break;
4549  }
4550  }
4551
4552  return false;
4553}
4554
4555void ARMAsmParser::
4556processInstruction(MCInst &Inst,
4557                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4558  switch (Inst.getOpcode()) {
4559  // Handle the MOV complex aliases.
4560  case ARM::ASRi:
4561  case ARM::LSRi:
4562  case ARM::LSLi:
4563  case ARM::RORi: {
4564    ARM_AM::ShiftOpc ShiftTy;
4565    unsigned Amt = Inst.getOperand(2).getImm();
4566    switch(Inst.getOpcode()) {
4567    default: llvm_unreachable("unexpected opcode!");
4568    case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
4569    case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
4570    case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
4571    case ARM::RORi: ShiftTy = ARM_AM::ror; break;
4572    }
4573    // A shift by zero is a plain MOVr, not a MOVsi.
4574    unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
4575    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
4576    MCInst TmpInst;
4577    TmpInst.setOpcode(Opc);
4578    TmpInst.addOperand(Inst.getOperand(0)); // Rd
4579    TmpInst.addOperand(Inst.getOperand(1)); // Rn
4580    if (Opc == ARM::MOVsi)
4581      TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
4582    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
4583    TmpInst.addOperand(Inst.getOperand(4));
4584    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
4585    Inst = TmpInst;
4586    break;
4587  }
4588  case ARM::LDMIA_UPD:
4589    // If this is a load of a single register via a 'pop', then we should use
4590    // a post-indexed LDR instruction instead, per the ARM ARM.
4591    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
4592        Inst.getNumOperands() == 5) {
4593      MCInst TmpInst;
4594      TmpInst.setOpcode(ARM::LDR_POST_IMM);
4595      TmpInst.addOperand(Inst.getOperand(4)); // Rt
4596      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4597      TmpInst.addOperand(Inst.getOperand(1)); // Rn
4598      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
4599      TmpInst.addOperand(MCOperand::CreateImm(4));
4600      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4601      TmpInst.addOperand(Inst.getOperand(3));
4602      Inst = TmpInst;
4603    }
4604    break;
4605  case ARM::STMDB_UPD:
4606    // If this is a store of a single register via a 'push', then we should use
4607    // a pre-indexed STR instruction instead, per the ARM ARM.
4608    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
4609        Inst.getNumOperands() == 5) {
4610      MCInst TmpInst;
4611      TmpInst.setOpcode(ARM::STR_PRE_IMM);
4612      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4613      TmpInst.addOperand(Inst.getOperand(4)); // Rt
4614      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
4615      TmpInst.addOperand(MCOperand::CreateImm(-4));
4616      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4617      TmpInst.addOperand(Inst.getOperand(3));
4618      Inst = TmpInst;
4619    }
4620    break;
4621  case ARM::tADDi8:
4622    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
4623    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
4624    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
4625    // to encoding T1 if <Rd> is omitted."
4626    if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
4627      Inst.setOpcode(ARM::tADDi3);
4628    break;
4629  case ARM::tSUBi8:
4630    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
4631    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
4632    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
4633    // to encoding T1 if <Rd> is omitted."
4634    if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
4635      Inst.setOpcode(ARM::tSUBi3);
4636    break;
4637  case ARM::tB:
4638    // A Thumb conditional branch outside of an IT block is a tBcc.
4639    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
4640      Inst.setOpcode(ARM::tBcc);
4641    break;
4642  case ARM::t2B:
4643    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
4644    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
4645      Inst.setOpcode(ARM::t2Bcc);
4646    break;
4647  case ARM::t2Bcc:
4648    // If the conditional is AL or we're in an IT block, we really want t2B.
4649    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock())
4650      Inst.setOpcode(ARM::t2B);
4651    break;
4652  case ARM::tBcc:
4653    // If the conditional is AL, we really want tB.
4654    if (Inst.getOperand(1).getImm() == ARMCC::AL)
4655      Inst.setOpcode(ARM::tB);
4656    break;
4657  case ARM::tLDMIA: {
4658    // If the register list contains any high registers, or if the writeback
4659    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
4660    // instead if we're in Thumb2. Otherwise, this should have generated
4661    // an error in validateInstruction().
4662    unsigned Rn = Inst.getOperand(0).getReg();
4663    bool hasWritebackToken =
4664      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
4665       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
4666    bool listContainsBase;
4667    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
4668        (!listContainsBase && !hasWritebackToken) ||
4669        (listContainsBase && hasWritebackToken)) {
4670      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
4671      assert (isThumbTwo());
4672      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
4673      // If we're switching to the updating version, we need to insert
4674      // the writeback tied operand.
4675      if (hasWritebackToken)
4676        Inst.insert(Inst.begin(),
4677                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
4678    }
4679    break;
4680  }
4681  case ARM::tSTMIA_UPD: {
4682    // If the register list contains any high registers, we need to use
4683    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
4684    // should have generated an error in validateInstruction().
4685    unsigned Rn = Inst.getOperand(0).getReg();
4686    bool listContainsBase;
4687    if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
4688      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
4689      assert (isThumbTwo());
4690      Inst.setOpcode(ARM::t2STMIA_UPD);
4691    }
4692    break;
4693  }
4694  case ARM::t2MOVi: {
4695    // If we can use the 16-bit encoding and the user didn't explicitly
4696    // request the 32-bit variant, transform it here.
4697    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4698        Inst.getOperand(1).getImm() <= 255 &&
4699        ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
4700         Inst.getOperand(4).getReg() == ARM::CPSR) ||
4701        (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
4702        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4703         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4704      // The operands aren't in the same order for tMOVi8...
4705      MCInst TmpInst;
4706      TmpInst.setOpcode(ARM::tMOVi8);
4707      TmpInst.addOperand(Inst.getOperand(0));
4708      TmpInst.addOperand(Inst.getOperand(4));
4709      TmpInst.addOperand(Inst.getOperand(1));
4710      TmpInst.addOperand(Inst.getOperand(2));
4711      TmpInst.addOperand(Inst.getOperand(3));
4712      Inst = TmpInst;
4713    }
4714    break;
4715  }
4716  case ARM::t2MOVr: {
4717    // If we can use the 16-bit encoding and the user didn't explicitly
4718    // request the 32-bit variant, transform it here.
4719    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4720        isARMLowRegister(Inst.getOperand(1).getReg()) &&
4721        Inst.getOperand(2).getImm() == ARMCC::AL &&
4722        Inst.getOperand(4).getReg() == ARM::CPSR &&
4723        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4724         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4725      // The operands aren't the same for tMOV[S]r... (no cc_out)
4726      MCInst TmpInst;
4727      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
4728      TmpInst.addOperand(Inst.getOperand(0));
4729      TmpInst.addOperand(Inst.getOperand(1));
4730      TmpInst.addOperand(Inst.getOperand(2));
4731      TmpInst.addOperand(Inst.getOperand(3));
4732      Inst = TmpInst;
4733    }
4734    break;
4735  }
4736  case ARM::t2SXTH:
4737  case ARM::t2SXTB:
4738  case ARM::t2UXTH:
4739  case ARM::t2UXTB: {
4740    // If we can use the 16-bit encoding and the user didn't explicitly
4741    // request the 32-bit variant, transform it here.
4742    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4743        isARMLowRegister(Inst.getOperand(1).getReg()) &&
4744        Inst.getOperand(2).getImm() == 0 &&
4745        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4746         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4747      unsigned NewOpc;
4748      switch (Inst.getOpcode()) {
4749      default: llvm_unreachable("Illegal opcode!");
4750      case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
4751      case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
4752      case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
4753      case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
4754      }
4755      // The operands aren't the same for thumb1 (no rotate operand).
4756      MCInst TmpInst;
4757      TmpInst.setOpcode(NewOpc);
4758      TmpInst.addOperand(Inst.getOperand(0));
4759      TmpInst.addOperand(Inst.getOperand(1));
4760      TmpInst.addOperand(Inst.getOperand(3));
4761      TmpInst.addOperand(Inst.getOperand(4));
4762      Inst = TmpInst;
4763    }
4764    break;
4765  }
4766  case ARM::t2IT: {
4767    // The mask bits for all but the first condition are represented as
4768    // the low bit of the condition code value implies 't'. We currently
4769    // always have 1 implies 't', so XOR toggle the bits if the low bit
4770    // of the condition code is zero. The encoding also expects the low
4771    // bit of the condition to be encoded as bit 4 of the mask operand,
4772    // so mask that in if needed
4773    MCOperand &MO = Inst.getOperand(1);
4774    unsigned Mask = MO.getImm();
4775    unsigned OrigMask = Mask;
4776    unsigned TZ = CountTrailingZeros_32(Mask);
4777    if ((Inst.getOperand(0).getImm() & 1) == 0) {
4778      assert(Mask && TZ <= 3 && "illegal IT mask value!");
4779      for (unsigned i = 3; i != TZ; --i)
4780        Mask ^= 1 << i;
4781    } else
4782      Mask |= 0x10;
4783    MO.setImm(Mask);
4784
4785    // Set up the IT block state according to the IT instruction we just
4786    // matched.
4787    assert(!inITBlock() && "nested IT blocks?!");
4788    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
4789    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
4790    ITState.CurPosition = 0;
4791    ITState.FirstCond = true;
4792    break;
4793  }
4794  }
4795}
4796
4797unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
4798  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
4799  // suffix depending on whether they're in an IT block or not.
4800  unsigned Opc = Inst.getOpcode();
4801  const MCInstrDesc &MCID = getInstDesc(Opc);
4802  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
4803    assert(MCID.hasOptionalDef() &&
4804           "optionally flag setting instruction missing optional def operand");
4805    assert(MCID.NumOperands == Inst.getNumOperands() &&
4806           "operand count mismatch!");
4807    // Find the optional-def operand (cc_out).
4808    unsigned OpNo;
4809    for (OpNo = 0;
4810         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
4811         ++OpNo)
4812      ;
4813    // If we're parsing Thumb1, reject it completely.
4814    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
4815      return Match_MnemonicFail;
4816    // If we're parsing Thumb2, which form is legal depends on whether we're
4817    // in an IT block.
4818    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
4819        !inITBlock())
4820      return Match_RequiresITBlock;
4821    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
4822        inITBlock())
4823      return Match_RequiresNotITBlock;
4824  }
4825  // Some high-register supporting Thumb1 encodings only allow both registers
4826  // to be from r0-r7 when in Thumb2.
4827  else if (Opc == ARM::tADDhirr && isThumbOne() &&
4828           isARMLowRegister(Inst.getOperand(1).getReg()) &&
4829           isARMLowRegister(Inst.getOperand(2).getReg()))
4830    return Match_RequiresThumb2;
4831  // Others only require ARMv6 or later.
4832  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
4833           isARMLowRegister(Inst.getOperand(0).getReg()) &&
4834           isARMLowRegister(Inst.getOperand(1).getReg()))
4835    return Match_RequiresV6;
4836  return Match_Success;
4837}
4838
4839bool ARMAsmParser::
4840MatchAndEmitInstruction(SMLoc IDLoc,
4841                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4842                        MCStreamer &Out) {
4843  MCInst Inst;
4844  unsigned ErrorInfo;
4845  unsigned MatchResult;
4846  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
4847  switch (MatchResult) {
4848  default: break;
4849  case Match_Success:
4850    // Context sensitive operand constraints aren't handled by the matcher,
4851    // so check them here.
4852    if (validateInstruction(Inst, Operands)) {
4853      // Still progress the IT block, otherwise one wrong condition causes
4854      // nasty cascading errors.
4855      forwardITPosition();
4856      return true;
4857    }
4858
4859    // Some instructions need post-processing to, for example, tweak which
4860    // encoding is selected.
4861    processInstruction(Inst, Operands);
4862
4863    // Only move forward at the very end so that everything in validate
4864    // and process gets a consistent answer about whether we're in an IT
4865    // block.
4866    forwardITPosition();
4867
4868    Out.EmitInstruction(Inst);
4869    return false;
4870  case Match_MissingFeature:
4871    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
4872    return true;
4873  case Match_InvalidOperand: {
4874    SMLoc ErrorLoc = IDLoc;
4875    if (ErrorInfo != ~0U) {
4876      if (ErrorInfo >= Operands.size())
4877        return Error(IDLoc, "too few operands for instruction");
4878
4879      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
4880      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
4881    }
4882
4883    return Error(ErrorLoc, "invalid operand for instruction");
4884  }
4885  case Match_MnemonicFail:
4886    return Error(IDLoc, "invalid instruction");
4887  case Match_ConversionFail:
4888    // The converter function will have already emited a diagnostic.
4889    return true;
4890  case Match_RequiresNotITBlock:
4891    return Error(IDLoc, "flag setting instruction only valid outside IT block");
4892  case Match_RequiresITBlock:
4893    return Error(IDLoc, "instruction only valid inside IT block");
4894  case Match_RequiresV6:
4895    return Error(IDLoc, "instruction variant requires ARMv6 or later");
4896  case Match_RequiresThumb2:
4897    return Error(IDLoc, "instruction variant requires Thumb2");
4898  }
4899
4900  llvm_unreachable("Implement any new match types added!");
4901  return true;
4902}
4903
4904/// parseDirective parses the arm specific directives
4905bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
4906  StringRef IDVal = DirectiveID.getIdentifier();
4907  if (IDVal == ".word")
4908    return parseDirectiveWord(4, DirectiveID.getLoc());
4909  else if (IDVal == ".thumb")
4910    return parseDirectiveThumb(DirectiveID.getLoc());
4911  else if (IDVal == ".thumb_func")
4912    return parseDirectiveThumbFunc(DirectiveID.getLoc());
4913  else if (IDVal == ".code")
4914    return parseDirectiveCode(DirectiveID.getLoc());
4915  else if (IDVal == ".syntax")
4916    return parseDirectiveSyntax(DirectiveID.getLoc());
4917  return true;
4918}
4919
4920/// parseDirectiveWord
4921///  ::= .word [ expression (, expression)* ]
4922bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
4923  if (getLexer().isNot(AsmToken::EndOfStatement)) {
4924    for (;;) {
4925      const MCExpr *Value;
4926      if (getParser().ParseExpression(Value))
4927        return true;
4928
4929      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
4930
4931      if (getLexer().is(AsmToken::EndOfStatement))
4932        break;
4933
4934      // FIXME: Improve diagnostic.
4935      if (getLexer().isNot(AsmToken::Comma))
4936        return Error(L, "unexpected token in directive");
4937      Parser.Lex();
4938    }
4939  }
4940
4941  Parser.Lex();
4942  return false;
4943}
4944
4945/// parseDirectiveThumb
4946///  ::= .thumb
4947bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
4948  if (getLexer().isNot(AsmToken::EndOfStatement))
4949    return Error(L, "unexpected token in directive");
4950  Parser.Lex();
4951
4952  // TODO: set thumb mode
4953  // TODO: tell the MC streamer the mode
4954  // getParser().getStreamer().Emit???();
4955  return false;
4956}
4957
4958/// parseDirectiveThumbFunc
4959///  ::= .thumbfunc symbol_name
4960bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
4961  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
4962  bool isMachO = MAI.hasSubsectionsViaSymbols();
4963  StringRef Name;
4964
4965  // Darwin asm has function name after .thumb_func direction
4966  // ELF doesn't
4967  if (isMachO) {
4968    const AsmToken &Tok = Parser.getTok();
4969    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
4970      return Error(L, "unexpected token in .thumb_func directive");
4971    Name = Tok.getIdentifier();
4972    Parser.Lex(); // Consume the identifier token.
4973  }
4974
4975 if (getLexer().isNot(AsmToken::EndOfStatement))
4976    return Error(L, "unexpected token in directive");
4977  Parser.Lex();
4978
4979  // FIXME: assuming function name will be the line following .thumb_func
4980  if (!isMachO) {
4981    Name = Parser.getTok().getIdentifier();
4982  }
4983
4984  // Mark symbol as a thumb symbol.
4985  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
4986  getParser().getStreamer().EmitThumbFunc(Func);
4987  return false;
4988}
4989
4990/// parseDirectiveSyntax
4991///  ::= .syntax unified | divided
4992bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
4993  const AsmToken &Tok = Parser.getTok();
4994  if (Tok.isNot(AsmToken::Identifier))
4995    return Error(L, "unexpected token in .syntax directive");
4996  StringRef Mode = Tok.getString();
4997  if (Mode == "unified" || Mode == "UNIFIED")
4998    Parser.Lex();
4999  else if (Mode == "divided" || Mode == "DIVIDED")
5000    return Error(L, "'.syntax divided' arm asssembly not supported");
5001  else
5002    return Error(L, "unrecognized syntax mode in .syntax directive");
5003
5004  if (getLexer().isNot(AsmToken::EndOfStatement))
5005    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
5006  Parser.Lex();
5007
5008  // TODO tell the MC streamer the mode
5009  // getParser().getStreamer().Emit???();
5010  return false;
5011}
5012
5013/// parseDirectiveCode
5014///  ::= .code 16 | 32
5015bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
5016  const AsmToken &Tok = Parser.getTok();
5017  if (Tok.isNot(AsmToken::Integer))
5018    return Error(L, "unexpected token in .code directive");
5019  int64_t Val = Parser.getTok().getIntVal();
5020  if (Val == 16)
5021    Parser.Lex();
5022  else if (Val == 32)
5023    Parser.Lex();
5024  else
5025    return Error(L, "invalid operand to .code directive");
5026
5027  if (getLexer().isNot(AsmToken::EndOfStatement))
5028    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
5029  Parser.Lex();
5030
5031  if (Val == 16) {
5032    if (!isThumb())
5033      SwitchMode();
5034    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
5035  } else {
5036    if (isThumb())
5037      SwitchMode();
5038    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
5039  }
5040
5041  return false;
5042}
5043
5044extern "C" void LLVMInitializeARMAsmLexer();
5045
5046/// Force static initialization.
5047extern "C" void LLVMInitializeARMAsmParser() {
5048  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
5049  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
5050  LLVMInitializeARMAsmLexer();
5051}
5052
5053#define GET_REGISTER_MATCHER
5054#define GET_MATCHER_IMPLEMENTATION
5055#include "ARMGenAsmMatcher.inc"
5056