ARMAsmParser.cpp revision 1b7b68f08776dc9553399dc3b4e7ab54e5e596c0 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/MCTargetAsmParser.h"
24#include "llvm/Target/TargetRegistry.h"
25#include "llvm/Support/SourceMgr.h"
26#include "llvm/Support/raw_ostream.h"
27#include "llvm/ADT/OwningPtr.h"
28#include "llvm/ADT/STLExtras.h"
29#include "llvm/ADT/SmallVector.h"
30#include "llvm/ADT/StringExtras.h"
31#include "llvm/ADT/StringSwitch.h"
32#include "llvm/ADT/Twine.h"
33
34using namespace llvm;
35
36namespace {
37
38class ARMOperand;
39
40class ARMAsmParser : public MCTargetAsmParser {
41  MCSubtargetInfo &STI;
42  MCAsmParser &Parser;
43
44  MCAsmParser &getParser() const { return Parser; }
45  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
46
47  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
48  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
49
50  int tryParseRegister();
51  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
52  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
53  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
54  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
55  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
56  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
57  const MCExpr *applyPrefixToExpr(const MCExpr *E,
58                                  MCSymbolRefExpr::VariantKind Variant);
59
60
61  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
62                              unsigned &ShiftAmount);
63  bool parseDirectiveWord(unsigned Size, SMLoc L);
64  bool parseDirectiveThumb(SMLoc L);
65  bool parseDirectiveThumbFunc(SMLoc L);
66  bool parseDirectiveCode(SMLoc L);
67  bool parseDirectiveSyntax(SMLoc L);
68
69  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
70                          bool &CarrySetting, unsigned &ProcessorIMod);
71  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
72                             bool &CanAcceptPredicationCode);
73
74  bool isThumb() const {
75    // FIXME: Can tablegen auto-generate this?
76    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
77  }
78  bool isThumbOne() const {
79    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
80  }
81  bool isThumbTwo() const {
82    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
83  }
84  bool hasV6Ops() const {
85    return STI.getFeatureBits() & ARM::HasV6Ops;
86  }
87  void SwitchMode() {
88    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
89    setAvailableFeatures(FB);
90  }
91
92  /// @name Auto-generated Match Functions
93  /// {
94
95#define GET_ASSEMBLER_HEADER
96#include "ARMGenAsmMatcher.inc"
97
98  /// }
99
100  OperandMatchResultTy parseCoprocNumOperand(
101    SmallVectorImpl<MCParsedAsmOperand*>&);
102  OperandMatchResultTy parseCoprocRegOperand(
103    SmallVectorImpl<MCParsedAsmOperand*>&);
104  OperandMatchResultTy parseMemBarrierOptOperand(
105    SmallVectorImpl<MCParsedAsmOperand*>&);
106  OperandMatchResultTy parseProcIFlagsOperand(
107    SmallVectorImpl<MCParsedAsmOperand*>&);
108  OperandMatchResultTy parseMSRMaskOperand(
109    SmallVectorImpl<MCParsedAsmOperand*>&);
110  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
111                                   StringRef Op, int Low, int High);
112  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
113    return parsePKHImm(O, "lsl", 0, 31);
114  }
115  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
116    return parsePKHImm(O, "asr", 1, 32);
117  }
118  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
119  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
120  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
121  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
122  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
123  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
124
125  // Asm Match Converter Methods
126  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
127                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
128  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
129                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
130  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
131                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
132  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
133                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
134  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
135                             const SmallVectorImpl<MCParsedAsmOperand*> &);
136  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
137                             const SmallVectorImpl<MCParsedAsmOperand*> &);
138  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
139                             const SmallVectorImpl<MCParsedAsmOperand*> &);
140  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
141                             const SmallVectorImpl<MCParsedAsmOperand*> &);
142  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
143                  const SmallVectorImpl<MCParsedAsmOperand*> &);
144  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
145                  const SmallVectorImpl<MCParsedAsmOperand*> &);
146  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
147                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
148
149  bool validateInstruction(MCInst &Inst,
150                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
151  void processInstruction(MCInst &Inst,
152                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
153  bool shouldOmitCCOutOperand(StringRef Mnemonic,
154                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
155
156public:
157  enum ARMMatchResultTy {
158    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
159    Match_RequiresV6,
160    Match_RequiresThumb2
161  };
162
163  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
164    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
165    MCAsmParserExtension::Initialize(_Parser);
166
167    // Initialize the set of available features.
168    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
169  }
170
171  // Implementation of the MCTargetAsmParser interface:
172  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
173  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
174                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
175  bool ParseDirective(AsmToken DirectiveID);
176
177  unsigned checkTargetMatchPredicate(MCInst &Inst);
178
179  bool MatchAndEmitInstruction(SMLoc IDLoc,
180                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
181                               MCStreamer &Out);
182};
183} // end anonymous namespace
184
185namespace {
186
187/// ARMOperand - Instances of this class represent a parsed ARM machine
188/// instruction.
189class ARMOperand : public MCParsedAsmOperand {
190  enum KindTy {
191    CondCode,
192    CCOut,
193    CoprocNum,
194    CoprocReg,
195    Immediate,
196    MemBarrierOpt,
197    Memory,
198    PostIndexRegister,
199    MSRMask,
200    ProcIFlags,
201    Register,
202    RegisterList,
203    DPRRegisterList,
204    SPRRegisterList,
205    ShiftedRegister,
206    ShiftedImmediate,
207    ShifterImmediate,
208    RotateImmediate,
209    BitfieldDescriptor,
210    Token
211  } Kind;
212
213  SMLoc StartLoc, EndLoc;
214  SmallVector<unsigned, 8> Registers;
215
216  union {
217    struct {
218      ARMCC::CondCodes Val;
219    } CC;
220
221    struct {
222      ARM_MB::MemBOpt Val;
223    } MBOpt;
224
225    struct {
226      unsigned Val;
227    } Cop;
228
229    struct {
230      ARM_PROC::IFlags Val;
231    } IFlags;
232
233    struct {
234      unsigned Val;
235    } MMask;
236
237    struct {
238      const char *Data;
239      unsigned Length;
240    } Tok;
241
242    struct {
243      unsigned RegNum;
244    } Reg;
245
246    struct {
247      const MCExpr *Val;
248    } Imm;
249
250    /// Combined record for all forms of ARM address expressions.
251    struct {
252      unsigned BaseRegNum;
253      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
254      // was specified.
255      const MCConstantExpr *OffsetImm;  // Offset immediate value
256      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
257      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
258      unsigned ShiftImm;      // shift for OffsetReg.
259      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
260    } Mem;
261
262    struct {
263      unsigned RegNum;
264      bool isAdd;
265      ARM_AM::ShiftOpc ShiftTy;
266      unsigned ShiftImm;
267    } PostIdxReg;
268
269    struct {
270      bool isASR;
271      unsigned Imm;
272    } ShifterImm;
273    struct {
274      ARM_AM::ShiftOpc ShiftTy;
275      unsigned SrcReg;
276      unsigned ShiftReg;
277      unsigned ShiftImm;
278    } RegShiftedReg;
279    struct {
280      ARM_AM::ShiftOpc ShiftTy;
281      unsigned SrcReg;
282      unsigned ShiftImm;
283    } RegShiftedImm;
284    struct {
285      unsigned Imm;
286    } RotImm;
287    struct {
288      unsigned LSB;
289      unsigned Width;
290    } Bitfield;
291  };
292
293  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
294public:
295  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
296    Kind = o.Kind;
297    StartLoc = o.StartLoc;
298    EndLoc = o.EndLoc;
299    switch (Kind) {
300    case CondCode:
301      CC = o.CC;
302      break;
303    case Token:
304      Tok = o.Tok;
305      break;
306    case CCOut:
307    case Register:
308      Reg = o.Reg;
309      break;
310    case RegisterList:
311    case DPRRegisterList:
312    case SPRRegisterList:
313      Registers = o.Registers;
314      break;
315    case CoprocNum:
316    case CoprocReg:
317      Cop = o.Cop;
318      break;
319    case Immediate:
320      Imm = o.Imm;
321      break;
322    case MemBarrierOpt:
323      MBOpt = o.MBOpt;
324      break;
325    case Memory:
326      Mem = o.Mem;
327      break;
328    case PostIndexRegister:
329      PostIdxReg = o.PostIdxReg;
330      break;
331    case MSRMask:
332      MMask = o.MMask;
333      break;
334    case ProcIFlags:
335      IFlags = o.IFlags;
336      break;
337    case ShifterImmediate:
338      ShifterImm = o.ShifterImm;
339      break;
340    case ShiftedRegister:
341      RegShiftedReg = o.RegShiftedReg;
342      break;
343    case ShiftedImmediate:
344      RegShiftedImm = o.RegShiftedImm;
345      break;
346    case RotateImmediate:
347      RotImm = o.RotImm;
348      break;
349    case BitfieldDescriptor:
350      Bitfield = o.Bitfield;
351      break;
352    }
353  }
354
355  /// getStartLoc - Get the location of the first token of this operand.
356  SMLoc getStartLoc() const { return StartLoc; }
357  /// getEndLoc - Get the location of the last token of this operand.
358  SMLoc getEndLoc() const { return EndLoc; }
359
360  ARMCC::CondCodes getCondCode() const {
361    assert(Kind == CondCode && "Invalid access!");
362    return CC.Val;
363  }
364
365  unsigned getCoproc() const {
366    assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
367    return Cop.Val;
368  }
369
370  StringRef getToken() const {
371    assert(Kind == Token && "Invalid access!");
372    return StringRef(Tok.Data, Tok.Length);
373  }
374
375  unsigned getReg() const {
376    assert((Kind == Register || Kind == CCOut) && "Invalid access!");
377    return Reg.RegNum;
378  }
379
380  const SmallVectorImpl<unsigned> &getRegList() const {
381    assert((Kind == RegisterList || Kind == DPRRegisterList ||
382            Kind == SPRRegisterList) && "Invalid access!");
383    return Registers;
384  }
385
386  const MCExpr *getImm() const {
387    assert(Kind == Immediate && "Invalid access!");
388    return Imm.Val;
389  }
390
391  ARM_MB::MemBOpt getMemBarrierOpt() const {
392    assert(Kind == MemBarrierOpt && "Invalid access!");
393    return MBOpt.Val;
394  }
395
396  ARM_PROC::IFlags getProcIFlags() const {
397    assert(Kind == ProcIFlags && "Invalid access!");
398    return IFlags.Val;
399  }
400
401  unsigned getMSRMask() const {
402    assert(Kind == MSRMask && "Invalid access!");
403    return MMask.Val;
404  }
405
406  bool isCoprocNum() const { return Kind == CoprocNum; }
407  bool isCoprocReg() const { return Kind == CoprocReg; }
408  bool isCondCode() const { return Kind == CondCode; }
409  bool isCCOut() const { return Kind == CCOut; }
410  bool isImm() const { return Kind == Immediate; }
411  bool isImm0_255() const {
412    if (Kind != Immediate)
413      return false;
414    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
415    if (!CE) return false;
416    int64_t Value = CE->getValue();
417    return Value >= 0 && Value < 256;
418  }
419  bool isImm0_7() const {
420    if (Kind != Immediate)
421      return false;
422    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
423    if (!CE) return false;
424    int64_t Value = CE->getValue();
425    return Value >= 0 && Value < 8;
426  }
427  bool isImm0_15() const {
428    if (Kind != Immediate)
429      return false;
430    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
431    if (!CE) return false;
432    int64_t Value = CE->getValue();
433    return Value >= 0 && Value < 16;
434  }
435  bool isImm0_31() const {
436    if (Kind != Immediate)
437      return false;
438    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
439    if (!CE) return false;
440    int64_t Value = CE->getValue();
441    return Value >= 0 && Value < 32;
442  }
443  bool isImm1_16() const {
444    if (Kind != Immediate)
445      return false;
446    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
447    if (!CE) return false;
448    int64_t Value = CE->getValue();
449    return Value > 0 && Value < 17;
450  }
451  bool isImm1_32() const {
452    if (Kind != Immediate)
453      return false;
454    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
455    if (!CE) return false;
456    int64_t Value = CE->getValue();
457    return Value > 0 && Value < 33;
458  }
459  bool isImm0_65535() const {
460    if (Kind != Immediate)
461      return false;
462    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
463    if (!CE) return false;
464    int64_t Value = CE->getValue();
465    return Value >= 0 && Value < 65536;
466  }
467  bool isImm0_65535Expr() const {
468    if (Kind != Immediate)
469      return false;
470    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
471    // If it's not a constant expression, it'll generate a fixup and be
472    // handled later.
473    if (!CE) return true;
474    int64_t Value = CE->getValue();
475    return Value >= 0 && Value < 65536;
476  }
477  bool isImm24bit() const {
478    if (Kind != Immediate)
479      return false;
480    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
481    if (!CE) return false;
482    int64_t Value = CE->getValue();
483    return Value >= 0 && Value <= 0xffffff;
484  }
485  bool isImmThumbSR() const {
486    if (Kind != Immediate)
487      return false;
488    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
489    if (!CE) return false;
490    int64_t Value = CE->getValue();
491    return Value > 0 && Value < 33;
492  }
493  bool isPKHLSLImm() const {
494    if (Kind != Immediate)
495      return false;
496    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
497    if (!CE) return false;
498    int64_t Value = CE->getValue();
499    return Value >= 0 && Value < 32;
500  }
501  bool isPKHASRImm() const {
502    if (Kind != Immediate)
503      return false;
504    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
505    if (!CE) return false;
506    int64_t Value = CE->getValue();
507    return Value > 0 && Value <= 32;
508  }
509  bool isARMSOImm() const {
510    if (Kind != Immediate)
511      return false;
512    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
513    if (!CE) return false;
514    int64_t Value = CE->getValue();
515    return ARM_AM::getSOImmVal(Value) != -1;
516  }
517  bool isT2SOImm() const {
518    if (Kind != Immediate)
519      return false;
520    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
521    if (!CE) return false;
522    int64_t Value = CE->getValue();
523    return ARM_AM::getT2SOImmVal(Value) != -1;
524  }
525  bool isSetEndImm() const {
526    if (Kind != Immediate)
527      return false;
528    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
529    if (!CE) return false;
530    int64_t Value = CE->getValue();
531    return Value == 1 || Value == 0;
532  }
533  bool isReg() const { return Kind == Register; }
534  bool isRegList() const { return Kind == RegisterList; }
535  bool isDPRRegList() const { return Kind == DPRRegisterList; }
536  bool isSPRRegList() const { return Kind == SPRRegisterList; }
537  bool isToken() const { return Kind == Token; }
538  bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
539  bool isMemory() const { return Kind == Memory; }
540  bool isShifterImm() const { return Kind == ShifterImmediate; }
541  bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
542  bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
543  bool isRotImm() const { return Kind == RotateImmediate; }
544  bool isBitfield() const { return Kind == BitfieldDescriptor; }
545  bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
546  bool isPostIdxReg() const {
547    return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
548  }
549  bool isMemNoOffset() const {
550    if (Kind != Memory)
551      return false;
552    // No offset of any kind.
553    return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
554  }
555  bool isAddrMode2() const {
556    if (Kind != Memory)
557      return false;
558    // Check for register offset.
559    if (Mem.OffsetRegNum) return true;
560    // Immediate offset in range [-4095, 4095].
561    if (!Mem.OffsetImm) return true;
562    int64_t Val = Mem.OffsetImm->getValue();
563    return Val > -4096 && Val < 4096;
564  }
565  bool isAM2OffsetImm() const {
566    if (Kind != Immediate)
567      return false;
568    // Immediate offset in range [-4095, 4095].
569    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
570    if (!CE) return false;
571    int64_t Val = CE->getValue();
572    return Val > -4096 && Val < 4096;
573  }
574  bool isAddrMode3() const {
575    if (Kind != Memory)
576      return false;
577    // No shifts are legal for AM3.
578    if (Mem.ShiftType != ARM_AM::no_shift) return false;
579    // Check for register offset.
580    if (Mem.OffsetRegNum) return true;
581    // Immediate offset in range [-255, 255].
582    if (!Mem.OffsetImm) return true;
583    int64_t Val = Mem.OffsetImm->getValue();
584    return Val > -256 && Val < 256;
585  }
586  bool isAM3Offset() const {
587    if (Kind != Immediate && Kind != PostIndexRegister)
588      return false;
589    if (Kind == PostIndexRegister)
590      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
591    // Immediate offset in range [-255, 255].
592    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
593    if (!CE) return false;
594    int64_t Val = CE->getValue();
595    // Special case, #-0 is INT32_MIN.
596    return (Val > -256 && Val < 256) || Val == INT32_MIN;
597  }
598  bool isAddrMode5() const {
599    if (Kind != Memory)
600      return false;
601    // Check for register offset.
602    if (Mem.OffsetRegNum) return false;
603    // Immediate offset in range [-1020, 1020] and a multiple of 4.
604    if (!Mem.OffsetImm) return true;
605    int64_t Val = Mem.OffsetImm->getValue();
606    return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0);
607  }
608  bool isMemRegOffset() const {
609    if (Kind != Memory || !Mem.OffsetRegNum)
610      return false;
611    return true;
612  }
613  bool isMemThumbRR() const {
614    // Thumb reg+reg addressing is simple. Just two registers, a base and
615    // an offset. No shifts, negations or any other complicating factors.
616    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
617        Mem.ShiftType != ARM_AM::no_shift)
618      return false;
619    return isARMLowRegister(Mem.BaseRegNum) &&
620      (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
621  }
622  bool isMemThumbRIs4() const {
623    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
624        !isARMLowRegister(Mem.BaseRegNum))
625      return false;
626    // Immediate offset, multiple of 4 in range [0, 124].
627    if (!Mem.OffsetImm) return true;
628    int64_t Val = Mem.OffsetImm->getValue();
629    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
630  }
631  bool isMemThumbRIs2() const {
632    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
633        !isARMLowRegister(Mem.BaseRegNum))
634      return false;
635    // Immediate offset, multiple of 4 in range [0, 62].
636    if (!Mem.OffsetImm) return true;
637    int64_t Val = Mem.OffsetImm->getValue();
638    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
639  }
640  bool isMemThumbRIs1() const {
641    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
642        !isARMLowRegister(Mem.BaseRegNum))
643      return false;
644    // Immediate offset in range [0, 31].
645    if (!Mem.OffsetImm) return true;
646    int64_t Val = Mem.OffsetImm->getValue();
647    return Val >= 0 && Val <= 31;
648  }
649  bool isMemThumbSPI() const {
650    if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
651      return false;
652    // Immediate offset, multiple of 4 in range [0, 1020].
653    if (!Mem.OffsetImm) return true;
654    int64_t Val = Mem.OffsetImm->getValue();
655    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
656  }
657  bool isMemImm8Offset() const {
658    if (Kind != Memory || Mem.OffsetRegNum != 0)
659      return false;
660    // Immediate offset in range [-255, 255].
661    if (!Mem.OffsetImm) return true;
662    int64_t Val = Mem.OffsetImm->getValue();
663    return Val > -256 && Val < 256;
664  }
665  bool isMemImm12Offset() const {
666    // If we have an immediate that's not a constant, treat it as a label
667    // reference needing a fixup. If it is a constant, it's something else
668    // and we reject it.
669    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
670      return true;
671
672    if (Kind != Memory || Mem.OffsetRegNum != 0)
673      return false;
674    // Immediate offset in range [-4095, 4095].
675    if (!Mem.OffsetImm) return true;
676    int64_t Val = Mem.OffsetImm->getValue();
677    return Val > -4096 && Val < 4096;
678  }
679  bool isPostIdxImm8() const {
680    if (Kind != Immediate)
681      return false;
682    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
683    if (!CE) return false;
684    int64_t Val = CE->getValue();
685    return Val > -256 && Val < 256;
686  }
687
688  bool isMSRMask() const { return Kind == MSRMask; }
689  bool isProcIFlags() const { return Kind == ProcIFlags; }
690
691  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
692    // Add as immediates when possible.  Null MCExpr = 0.
693    if (Expr == 0)
694      Inst.addOperand(MCOperand::CreateImm(0));
695    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
696      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
697    else
698      Inst.addOperand(MCOperand::CreateExpr(Expr));
699  }
700
701  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
702    assert(N == 2 && "Invalid number of operands!");
703    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
704    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
705    Inst.addOperand(MCOperand::CreateReg(RegNum));
706  }
707
708  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
709    assert(N == 1 && "Invalid number of operands!");
710    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
711  }
712
713  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
714    assert(N == 1 && "Invalid number of operands!");
715    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
716  }
717
718  void addCCOutOperands(MCInst &Inst, unsigned N) const {
719    assert(N == 1 && "Invalid number of operands!");
720    Inst.addOperand(MCOperand::CreateReg(getReg()));
721  }
722
723  void addRegOperands(MCInst &Inst, unsigned N) const {
724    assert(N == 1 && "Invalid number of operands!");
725    Inst.addOperand(MCOperand::CreateReg(getReg()));
726  }
727
728  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
729    assert(N == 3 && "Invalid number of operands!");
730    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
731    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
732    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
733    Inst.addOperand(MCOperand::CreateImm(
734      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
735  }
736
737  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
738    assert(N == 2 && "Invalid number of operands!");
739    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
740    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
741    Inst.addOperand(MCOperand::CreateImm(
742      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
743  }
744
745
746  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
747    assert(N == 1 && "Invalid number of operands!");
748    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
749                                         ShifterImm.Imm));
750  }
751
752  void addRegListOperands(MCInst &Inst, unsigned N) const {
753    assert(N == 1 && "Invalid number of operands!");
754    const SmallVectorImpl<unsigned> &RegList = getRegList();
755    for (SmallVectorImpl<unsigned>::const_iterator
756           I = RegList.begin(), E = RegList.end(); I != E; ++I)
757      Inst.addOperand(MCOperand::CreateReg(*I));
758  }
759
760  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
761    addRegListOperands(Inst, N);
762  }
763
764  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
765    addRegListOperands(Inst, N);
766  }
767
768  void addRotImmOperands(MCInst &Inst, unsigned N) const {
769    assert(N == 1 && "Invalid number of operands!");
770    // Encoded as val>>3. The printer handles display as 8, 16, 24.
771    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
772  }
773
774  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
775    assert(N == 1 && "Invalid number of operands!");
776    // Munge the lsb/width into a bitfield mask.
777    unsigned lsb = Bitfield.LSB;
778    unsigned width = Bitfield.Width;
779    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
780    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
781                      (32 - (lsb + width)));
782    Inst.addOperand(MCOperand::CreateImm(Mask));
783  }
784
785  void addImmOperands(MCInst &Inst, unsigned N) const {
786    assert(N == 1 && "Invalid number of operands!");
787    addExpr(Inst, getImm());
788  }
789
790  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
791    assert(N == 1 && "Invalid number of operands!");
792    addExpr(Inst, getImm());
793  }
794
795  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
796    assert(N == 1 && "Invalid number of operands!");
797    addExpr(Inst, getImm());
798  }
799
800  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
801    assert(N == 1 && "Invalid number of operands!");
802    addExpr(Inst, getImm());
803  }
804
805  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
806    assert(N == 1 && "Invalid number of operands!");
807    addExpr(Inst, getImm());
808  }
809
810  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
811    assert(N == 1 && "Invalid number of operands!");
812    // The constant encodes as the immediate-1, and we store in the instruction
813    // the bits as encoded, so subtract off one here.
814    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
815    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
816  }
817
818  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
819    assert(N == 1 && "Invalid number of operands!");
820    // The constant encodes as the immediate-1, and we store in the instruction
821    // the bits as encoded, so subtract off one here.
822    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
823    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
824  }
825
826  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
827    assert(N == 1 && "Invalid number of operands!");
828    addExpr(Inst, getImm());
829  }
830
831  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
832    assert(N == 1 && "Invalid number of operands!");
833    addExpr(Inst, getImm());
834  }
835
836  void addImm24bitOperands(MCInst &Inst, unsigned N) const {
837    assert(N == 1 && "Invalid number of operands!");
838    addExpr(Inst, getImm());
839  }
840
841  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
842    assert(N == 1 && "Invalid number of operands!");
843    // The constant encodes as the immediate, except for 32, which encodes as
844    // zero.
845    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
846    unsigned Imm = CE->getValue();
847    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
848  }
849
850  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
851    assert(N == 1 && "Invalid number of operands!");
852    addExpr(Inst, getImm());
853  }
854
855  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
856    assert(N == 1 && "Invalid number of operands!");
857    // An ASR value of 32 encodes as 0, so that's how we want to add it to
858    // the instruction as well.
859    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
860    int Val = CE->getValue();
861    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
862  }
863
864  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
865    assert(N == 1 && "Invalid number of operands!");
866    addExpr(Inst, getImm());
867  }
868
869  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
870    assert(N == 1 && "Invalid number of operands!");
871    addExpr(Inst, getImm());
872  }
873
874  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
875    assert(N == 1 && "Invalid number of operands!");
876    addExpr(Inst, getImm());
877  }
878
879  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
880    assert(N == 1 && "Invalid number of operands!");
881    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
882  }
883
884  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
885    assert(N == 1 && "Invalid number of operands!");
886    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
887  }
888
889  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
890    assert(N == 3 && "Invalid number of operands!");
891    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
892    if (!Mem.OffsetRegNum) {
893      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
894      // Special case for #-0
895      if (Val == INT32_MIN) Val = 0;
896      if (Val < 0) Val = -Val;
897      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
898    } else {
899      // For register offset, we encode the shift type and negation flag
900      // here.
901      Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
902                              Mem.ShiftImm, Mem.ShiftType);
903    }
904    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
905    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
906    Inst.addOperand(MCOperand::CreateImm(Val));
907  }
908
909  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
910    assert(N == 2 && "Invalid number of operands!");
911    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
912    assert(CE && "non-constant AM2OffsetImm operand!");
913    int32_t Val = CE->getValue();
914    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
915    // Special case for #-0
916    if (Val == INT32_MIN) Val = 0;
917    if (Val < 0) Val = -Val;
918    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
919    Inst.addOperand(MCOperand::CreateReg(0));
920    Inst.addOperand(MCOperand::CreateImm(Val));
921  }
922
923  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
924    assert(N == 3 && "Invalid number of operands!");
925    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
926    if (!Mem.OffsetRegNum) {
927      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
928      // Special case for #-0
929      if (Val == INT32_MIN) Val = 0;
930      if (Val < 0) Val = -Val;
931      Val = ARM_AM::getAM3Opc(AddSub, Val);
932    } else {
933      // For register offset, we encode the shift type and negation flag
934      // here.
935      Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
936    }
937    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
938    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
939    Inst.addOperand(MCOperand::CreateImm(Val));
940  }
941
942  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
943    assert(N == 2 && "Invalid number of operands!");
944    if (Kind == PostIndexRegister) {
945      int32_t Val =
946        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
947      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
948      Inst.addOperand(MCOperand::CreateImm(Val));
949      return;
950    }
951
952    // Constant offset.
953    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
954    int32_t Val = CE->getValue();
955    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
956    // Special case for #-0
957    if (Val == INT32_MIN) Val = 0;
958    if (Val < 0) Val = -Val;
959    Val = ARM_AM::getAM3Opc(AddSub, Val);
960    Inst.addOperand(MCOperand::CreateReg(0));
961    Inst.addOperand(MCOperand::CreateImm(Val));
962  }
963
964  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
965    assert(N == 2 && "Invalid number of operands!");
966    // The lower two bits are always zero and as such are not encoded.
967    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
968    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
969    // Special case for #-0
970    if (Val == INT32_MIN) Val = 0;
971    if (Val < 0) Val = -Val;
972    Val = ARM_AM::getAM5Opc(AddSub, Val);
973    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
974    Inst.addOperand(MCOperand::CreateImm(Val));
975  }
976
977  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
978    assert(N == 2 && "Invalid number of operands!");
979    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
980    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
981    Inst.addOperand(MCOperand::CreateImm(Val));
982  }
983
984  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
985    assert(N == 2 && "Invalid number of operands!");
986    // If this is an immediate, it's a label reference.
987    if (Kind == Immediate) {
988      addExpr(Inst, getImm());
989      Inst.addOperand(MCOperand::CreateImm(0));
990      return;
991    }
992
993    // Otherwise, it's a normal memory reg+offset.
994    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
995    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
996    Inst.addOperand(MCOperand::CreateImm(Val));
997  }
998
999  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1000    assert(N == 3 && "Invalid number of operands!");
1001    unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1002                                     Mem.ShiftImm, Mem.ShiftType);
1003    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1004    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1005    Inst.addOperand(MCOperand::CreateImm(Val));
1006  }
1007
1008  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1009    assert(N == 2 && "Invalid number of operands!");
1010    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1011    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1012  }
1013
1014  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1015    assert(N == 2 && "Invalid number of operands!");
1016    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1017    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1018    Inst.addOperand(MCOperand::CreateImm(Val));
1019  }
1020
1021  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1022    assert(N == 2 && "Invalid number of operands!");
1023    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1024    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1025    Inst.addOperand(MCOperand::CreateImm(Val));
1026  }
1027
1028  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1029    assert(N == 2 && "Invalid number of operands!");
1030    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1031    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1032    Inst.addOperand(MCOperand::CreateImm(Val));
1033  }
1034
1035  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1036    assert(N == 2 && "Invalid number of operands!");
1037    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1038    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1039    Inst.addOperand(MCOperand::CreateImm(Val));
1040  }
1041
1042  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1043    assert(N == 1 && "Invalid number of operands!");
1044    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1045    assert(CE && "non-constant post-idx-imm8 operand!");
1046    int Imm = CE->getValue();
1047    bool isAdd = Imm >= 0;
1048    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1049    Inst.addOperand(MCOperand::CreateImm(Imm));
1050  }
1051
1052  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1053    assert(N == 2 && "Invalid number of operands!");
1054    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1055    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1056  }
1057
1058  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1059    assert(N == 2 && "Invalid number of operands!");
1060    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1061    // The sign, shift type, and shift amount are encoded in a single operand
1062    // using the AM2 encoding helpers.
1063    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1064    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1065                                     PostIdxReg.ShiftTy);
1066    Inst.addOperand(MCOperand::CreateImm(Imm));
1067  }
1068
1069  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1070    assert(N == 1 && "Invalid number of operands!");
1071    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1072  }
1073
1074  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1075    assert(N == 1 && "Invalid number of operands!");
1076    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1077  }
1078
1079  virtual void print(raw_ostream &OS) const;
1080
1081  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1082    ARMOperand *Op = new ARMOperand(CondCode);
1083    Op->CC.Val = CC;
1084    Op->StartLoc = S;
1085    Op->EndLoc = S;
1086    return Op;
1087  }
1088
1089  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1090    ARMOperand *Op = new ARMOperand(CoprocNum);
1091    Op->Cop.Val = CopVal;
1092    Op->StartLoc = S;
1093    Op->EndLoc = S;
1094    return Op;
1095  }
1096
1097  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1098    ARMOperand *Op = new ARMOperand(CoprocReg);
1099    Op->Cop.Val = CopVal;
1100    Op->StartLoc = S;
1101    Op->EndLoc = S;
1102    return Op;
1103  }
1104
1105  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1106    ARMOperand *Op = new ARMOperand(CCOut);
1107    Op->Reg.RegNum = RegNum;
1108    Op->StartLoc = S;
1109    Op->EndLoc = S;
1110    return Op;
1111  }
1112
1113  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1114    ARMOperand *Op = new ARMOperand(Token);
1115    Op->Tok.Data = Str.data();
1116    Op->Tok.Length = Str.size();
1117    Op->StartLoc = S;
1118    Op->EndLoc = S;
1119    return Op;
1120  }
1121
1122  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1123    ARMOperand *Op = new ARMOperand(Register);
1124    Op->Reg.RegNum = RegNum;
1125    Op->StartLoc = S;
1126    Op->EndLoc = E;
1127    return Op;
1128  }
1129
1130  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1131                                           unsigned SrcReg,
1132                                           unsigned ShiftReg,
1133                                           unsigned ShiftImm,
1134                                           SMLoc S, SMLoc E) {
1135    ARMOperand *Op = new ARMOperand(ShiftedRegister);
1136    Op->RegShiftedReg.ShiftTy = ShTy;
1137    Op->RegShiftedReg.SrcReg = SrcReg;
1138    Op->RegShiftedReg.ShiftReg = ShiftReg;
1139    Op->RegShiftedReg.ShiftImm = ShiftImm;
1140    Op->StartLoc = S;
1141    Op->EndLoc = E;
1142    return Op;
1143  }
1144
1145  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1146                                            unsigned SrcReg,
1147                                            unsigned ShiftImm,
1148                                            SMLoc S, SMLoc E) {
1149    ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1150    Op->RegShiftedImm.ShiftTy = ShTy;
1151    Op->RegShiftedImm.SrcReg = SrcReg;
1152    Op->RegShiftedImm.ShiftImm = ShiftImm;
1153    Op->StartLoc = S;
1154    Op->EndLoc = E;
1155    return Op;
1156  }
1157
1158  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1159                                   SMLoc S, SMLoc E) {
1160    ARMOperand *Op = new ARMOperand(ShifterImmediate);
1161    Op->ShifterImm.isASR = isASR;
1162    Op->ShifterImm.Imm = Imm;
1163    Op->StartLoc = S;
1164    Op->EndLoc = E;
1165    return Op;
1166  }
1167
1168  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1169    ARMOperand *Op = new ARMOperand(RotateImmediate);
1170    Op->RotImm.Imm = Imm;
1171    Op->StartLoc = S;
1172    Op->EndLoc = E;
1173    return Op;
1174  }
1175
1176  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1177                                    SMLoc S, SMLoc E) {
1178    ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1179    Op->Bitfield.LSB = LSB;
1180    Op->Bitfield.Width = Width;
1181    Op->StartLoc = S;
1182    Op->EndLoc = E;
1183    return Op;
1184  }
1185
1186  static ARMOperand *
1187  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1188                SMLoc StartLoc, SMLoc EndLoc) {
1189    KindTy Kind = RegisterList;
1190
1191    if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1192        contains(Regs.front().first))
1193      Kind = DPRRegisterList;
1194    else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1195             contains(Regs.front().first))
1196      Kind = SPRRegisterList;
1197
1198    ARMOperand *Op = new ARMOperand(Kind);
1199    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1200           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1201      Op->Registers.push_back(I->first);
1202    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1203    Op->StartLoc = StartLoc;
1204    Op->EndLoc = EndLoc;
1205    return Op;
1206  }
1207
1208  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1209    ARMOperand *Op = new ARMOperand(Immediate);
1210    Op->Imm.Val = Val;
1211    Op->StartLoc = S;
1212    Op->EndLoc = E;
1213    return Op;
1214  }
1215
1216  static ARMOperand *CreateMem(unsigned BaseRegNum,
1217                               const MCConstantExpr *OffsetImm,
1218                               unsigned OffsetRegNum,
1219                               ARM_AM::ShiftOpc ShiftType,
1220                               unsigned ShiftImm,
1221                               bool isNegative,
1222                               SMLoc S, SMLoc E) {
1223    ARMOperand *Op = new ARMOperand(Memory);
1224    Op->Mem.BaseRegNum = BaseRegNum;
1225    Op->Mem.OffsetImm = OffsetImm;
1226    Op->Mem.OffsetRegNum = OffsetRegNum;
1227    Op->Mem.ShiftType = ShiftType;
1228    Op->Mem.ShiftImm = ShiftImm;
1229    Op->Mem.isNegative = isNegative;
1230    Op->StartLoc = S;
1231    Op->EndLoc = E;
1232    return Op;
1233  }
1234
1235  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1236                                      ARM_AM::ShiftOpc ShiftTy,
1237                                      unsigned ShiftImm,
1238                                      SMLoc S, SMLoc E) {
1239    ARMOperand *Op = new ARMOperand(PostIndexRegister);
1240    Op->PostIdxReg.RegNum = RegNum;
1241    Op->PostIdxReg.isAdd = isAdd;
1242    Op->PostIdxReg.ShiftTy = ShiftTy;
1243    Op->PostIdxReg.ShiftImm = ShiftImm;
1244    Op->StartLoc = S;
1245    Op->EndLoc = E;
1246    return Op;
1247  }
1248
1249  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1250    ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1251    Op->MBOpt.Val = Opt;
1252    Op->StartLoc = S;
1253    Op->EndLoc = S;
1254    return Op;
1255  }
1256
1257  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1258    ARMOperand *Op = new ARMOperand(ProcIFlags);
1259    Op->IFlags.Val = IFlags;
1260    Op->StartLoc = S;
1261    Op->EndLoc = S;
1262    return Op;
1263  }
1264
1265  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1266    ARMOperand *Op = new ARMOperand(MSRMask);
1267    Op->MMask.Val = MMask;
1268    Op->StartLoc = S;
1269    Op->EndLoc = S;
1270    return Op;
1271  }
1272};
1273
1274} // end anonymous namespace.
1275
1276void ARMOperand::print(raw_ostream &OS) const {
1277  switch (Kind) {
1278  case CondCode:
1279    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1280    break;
1281  case CCOut:
1282    OS << "<ccout " << getReg() << ">";
1283    break;
1284  case CoprocNum:
1285    OS << "<coprocessor number: " << getCoproc() << ">";
1286    break;
1287  case CoprocReg:
1288    OS << "<coprocessor register: " << getCoproc() << ">";
1289    break;
1290  case MSRMask:
1291    OS << "<mask: " << getMSRMask() << ">";
1292    break;
1293  case Immediate:
1294    getImm()->print(OS);
1295    break;
1296  case MemBarrierOpt:
1297    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1298    break;
1299  case Memory:
1300    OS << "<memory "
1301       << " base:" << Mem.BaseRegNum;
1302    OS << ">";
1303    break;
1304  case PostIndexRegister:
1305    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1306       << PostIdxReg.RegNum;
1307    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1308      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1309         << PostIdxReg.ShiftImm;
1310    OS << ">";
1311    break;
1312  case ProcIFlags: {
1313    OS << "<ARM_PROC::";
1314    unsigned IFlags = getProcIFlags();
1315    for (int i=2; i >= 0; --i)
1316      if (IFlags & (1 << i))
1317        OS << ARM_PROC::IFlagsToString(1 << i);
1318    OS << ">";
1319    break;
1320  }
1321  case Register:
1322    OS << "<register " << getReg() << ">";
1323    break;
1324  case ShifterImmediate:
1325    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1326       << " #" << ShifterImm.Imm << ">";
1327    break;
1328  case ShiftedRegister:
1329    OS << "<so_reg_reg "
1330       << RegShiftedReg.SrcReg
1331       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1332       << ", " << RegShiftedReg.ShiftReg << ", "
1333       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1334       << ">";
1335    break;
1336  case ShiftedImmediate:
1337    OS << "<so_reg_imm "
1338       << RegShiftedImm.SrcReg
1339       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1340       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1341       << ">";
1342    break;
1343  case RotateImmediate:
1344    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1345    break;
1346  case BitfieldDescriptor:
1347    OS << "<bitfield " << "lsb: " << Bitfield.LSB
1348       << ", width: " << Bitfield.Width << ">";
1349    break;
1350  case RegisterList:
1351  case DPRRegisterList:
1352  case SPRRegisterList: {
1353    OS << "<register_list ";
1354
1355    const SmallVectorImpl<unsigned> &RegList = getRegList();
1356    for (SmallVectorImpl<unsigned>::const_iterator
1357           I = RegList.begin(), E = RegList.end(); I != E; ) {
1358      OS << *I;
1359      if (++I < E) OS << ", ";
1360    }
1361
1362    OS << ">";
1363    break;
1364  }
1365  case Token:
1366    OS << "'" << getToken() << "'";
1367    break;
1368  }
1369}
1370
1371/// @name Auto-generated Match Functions
1372/// {
1373
1374static unsigned MatchRegisterName(StringRef Name);
1375
1376/// }
1377
1378bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1379                                 SMLoc &StartLoc, SMLoc &EndLoc) {
1380  RegNo = tryParseRegister();
1381
1382  return (RegNo == (unsigned)-1);
1383}
1384
1385/// Try to parse a register name.  The token must be an Identifier when called,
1386/// and if it is a register name the token is eaten and the register number is
1387/// returned.  Otherwise return -1.
1388///
1389int ARMAsmParser::tryParseRegister() {
1390  const AsmToken &Tok = Parser.getTok();
1391  if (Tok.isNot(AsmToken::Identifier)) return -1;
1392
1393  // FIXME: Validate register for the current architecture; we have to do
1394  // validation later, so maybe there is no need for this here.
1395  std::string upperCase = Tok.getString().str();
1396  std::string lowerCase = LowercaseString(upperCase);
1397  unsigned RegNum = MatchRegisterName(lowerCase);
1398  if (!RegNum) {
1399    RegNum = StringSwitch<unsigned>(lowerCase)
1400      .Case("r13", ARM::SP)
1401      .Case("r14", ARM::LR)
1402      .Case("r15", ARM::PC)
1403      .Case("ip", ARM::R12)
1404      .Default(0);
1405  }
1406  if (!RegNum) return -1;
1407
1408  Parser.Lex(); // Eat identifier token.
1409  return RegNum;
1410}
1411
1412// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
1413// If a recoverable error occurs, return 1. If an irrecoverable error
1414// occurs, return -1. An irrecoverable error is one where tokens have been
1415// consumed in the process of trying to parse the shifter (i.e., when it is
1416// indeed a shifter operand, but malformed).
1417int ARMAsmParser::tryParseShiftRegister(
1418                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1419  SMLoc S = Parser.getTok().getLoc();
1420  const AsmToken &Tok = Parser.getTok();
1421  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1422
1423  std::string upperCase = Tok.getString().str();
1424  std::string lowerCase = LowercaseString(upperCase);
1425  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1426      .Case("lsl", ARM_AM::lsl)
1427      .Case("lsr", ARM_AM::lsr)
1428      .Case("asr", ARM_AM::asr)
1429      .Case("ror", ARM_AM::ror)
1430      .Case("rrx", ARM_AM::rrx)
1431      .Default(ARM_AM::no_shift);
1432
1433  if (ShiftTy == ARM_AM::no_shift)
1434    return 1;
1435
1436  Parser.Lex(); // Eat the operator.
1437
1438  // The source register for the shift has already been added to the
1439  // operand list, so we need to pop it off and combine it into the shifted
1440  // register operand instead.
1441  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1442  if (!PrevOp->isReg())
1443    return Error(PrevOp->getStartLoc(), "shift must be of a register");
1444  int SrcReg = PrevOp->getReg();
1445  int64_t Imm = 0;
1446  int ShiftReg = 0;
1447  if (ShiftTy == ARM_AM::rrx) {
1448    // RRX Doesn't have an explicit shift amount. The encoder expects
1449    // the shift register to be the same as the source register. Seems odd,
1450    // but OK.
1451    ShiftReg = SrcReg;
1452  } else {
1453    // Figure out if this is shifted by a constant or a register (for non-RRX).
1454    if (Parser.getTok().is(AsmToken::Hash)) {
1455      Parser.Lex(); // Eat hash.
1456      SMLoc ImmLoc = Parser.getTok().getLoc();
1457      const MCExpr *ShiftExpr = 0;
1458      if (getParser().ParseExpression(ShiftExpr)) {
1459        Error(ImmLoc, "invalid immediate shift value");
1460        return -1;
1461      }
1462      // The expression must be evaluatable as an immediate.
1463      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1464      if (!CE) {
1465        Error(ImmLoc, "invalid immediate shift value");
1466        return -1;
1467      }
1468      // Range check the immediate.
1469      // lsl, ror: 0 <= imm <= 31
1470      // lsr, asr: 0 <= imm <= 32
1471      Imm = CE->getValue();
1472      if (Imm < 0 ||
1473          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1474          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1475        Error(ImmLoc, "immediate shift value out of range");
1476        return -1;
1477      }
1478    } else if (Parser.getTok().is(AsmToken::Identifier)) {
1479      ShiftReg = tryParseRegister();
1480      SMLoc L = Parser.getTok().getLoc();
1481      if (ShiftReg == -1) {
1482        Error (L, "expected immediate or register in shift operand");
1483        return -1;
1484      }
1485    } else {
1486      Error (Parser.getTok().getLoc(),
1487                    "expected immediate or register in shift operand");
1488      return -1;
1489    }
1490  }
1491
1492  if (ShiftReg && ShiftTy != ARM_AM::rrx)
1493    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1494                                                         ShiftReg, Imm,
1495                                               S, Parser.getTok().getLoc()));
1496  else
1497    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1498                                               S, Parser.getTok().getLoc()));
1499
1500  return 0;
1501}
1502
1503
1504/// Try to parse a register name.  The token must be an Identifier when called.
1505/// If it's a register, an AsmOperand is created. Another AsmOperand is created
1506/// if there is a "writeback". 'true' if it's not a register.
1507///
1508/// TODO this is likely to change to allow different register types and or to
1509/// parse for a specific register type.
1510bool ARMAsmParser::
1511tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1512  SMLoc S = Parser.getTok().getLoc();
1513  int RegNo = tryParseRegister();
1514  if (RegNo == -1)
1515    return true;
1516
1517  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1518
1519  const AsmToken &ExclaimTok = Parser.getTok();
1520  if (ExclaimTok.is(AsmToken::Exclaim)) {
1521    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1522                                               ExclaimTok.getLoc()));
1523    Parser.Lex(); // Eat exclaim token
1524  }
1525
1526  return false;
1527}
1528
1529/// MatchCoprocessorOperandName - Try to parse an coprocessor related
1530/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1531/// "c5", ...
1532static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1533  // Use the same layout as the tablegen'erated register name matcher. Ugly,
1534  // but efficient.
1535  switch (Name.size()) {
1536  default: break;
1537  case 2:
1538    if (Name[0] != CoprocOp)
1539      return -1;
1540    switch (Name[1]) {
1541    default:  return -1;
1542    case '0': return 0;
1543    case '1': return 1;
1544    case '2': return 2;
1545    case '3': return 3;
1546    case '4': return 4;
1547    case '5': return 5;
1548    case '6': return 6;
1549    case '7': return 7;
1550    case '8': return 8;
1551    case '9': return 9;
1552    }
1553    break;
1554  case 3:
1555    if (Name[0] != CoprocOp || Name[1] != '1')
1556      return -1;
1557    switch (Name[2]) {
1558    default:  return -1;
1559    case '0': return 10;
1560    case '1': return 11;
1561    case '2': return 12;
1562    case '3': return 13;
1563    case '4': return 14;
1564    case '5': return 15;
1565    }
1566    break;
1567  }
1568
1569  return -1;
1570}
1571
1572/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1573/// token must be an Identifier when called, and if it is a coprocessor
1574/// number, the token is eaten and the operand is added to the operand list.
1575ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1576parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1577  SMLoc S = Parser.getTok().getLoc();
1578  const AsmToken &Tok = Parser.getTok();
1579  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1580
1581  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1582  if (Num == -1)
1583    return MatchOperand_NoMatch;
1584
1585  Parser.Lex(); // Eat identifier token.
1586  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1587  return MatchOperand_Success;
1588}
1589
1590/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1591/// token must be an Identifier when called, and if it is a coprocessor
1592/// number, the token is eaten and the operand is added to the operand list.
1593ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1594parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1595  SMLoc S = Parser.getTok().getLoc();
1596  const AsmToken &Tok = Parser.getTok();
1597  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1598
1599  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1600  if (Reg == -1)
1601    return MatchOperand_NoMatch;
1602
1603  Parser.Lex(); // Eat identifier token.
1604  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1605  return MatchOperand_Success;
1606}
1607
1608/// Parse a register list, return it if successful else return null.  The first
1609/// token must be a '{' when called.
1610bool ARMAsmParser::
1611parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1612  assert(Parser.getTok().is(AsmToken::LCurly) &&
1613         "Token is not a Left Curly Brace");
1614  SMLoc S = Parser.getTok().getLoc();
1615
1616  // Read the rest of the registers in the list.
1617  unsigned PrevRegNum = 0;
1618  SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1619
1620  do {
1621    bool IsRange = Parser.getTok().is(AsmToken::Minus);
1622    Parser.Lex(); // Eat non-identifier token.
1623
1624    const AsmToken &RegTok = Parser.getTok();
1625    SMLoc RegLoc = RegTok.getLoc();
1626    if (RegTok.isNot(AsmToken::Identifier)) {
1627      Error(RegLoc, "register expected");
1628      return true;
1629    }
1630
1631    int RegNum = tryParseRegister();
1632    if (RegNum == -1) {
1633      Error(RegLoc, "register expected");
1634      return true;
1635    }
1636
1637    if (IsRange) {
1638      int Reg = PrevRegNum;
1639      do {
1640        ++Reg;
1641        Registers.push_back(std::make_pair(Reg, RegLoc));
1642      } while (Reg != RegNum);
1643    } else {
1644      Registers.push_back(std::make_pair(RegNum, RegLoc));
1645    }
1646
1647    PrevRegNum = RegNum;
1648  } while (Parser.getTok().is(AsmToken::Comma) ||
1649           Parser.getTok().is(AsmToken::Minus));
1650
1651  // Process the right curly brace of the list.
1652  const AsmToken &RCurlyTok = Parser.getTok();
1653  if (RCurlyTok.isNot(AsmToken::RCurly)) {
1654    Error(RCurlyTok.getLoc(), "'}' expected");
1655    return true;
1656  }
1657
1658  SMLoc E = RCurlyTok.getLoc();
1659  Parser.Lex(); // Eat right curly brace token.
1660
1661  // Verify the register list.
1662  SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1663    RI = Registers.begin(), RE = Registers.end();
1664
1665  unsigned HighRegNum = getARMRegisterNumbering(RI->first);
1666  bool EmittedWarning = false;
1667
1668  DenseMap<unsigned, bool> RegMap;
1669  RegMap[HighRegNum] = true;
1670
1671  for (++RI; RI != RE; ++RI) {
1672    const std::pair<unsigned, SMLoc> &RegInfo = *RI;
1673    unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1674
1675    if (RegMap[Reg]) {
1676      Error(RegInfo.second, "register duplicated in register list");
1677      return true;
1678    }
1679
1680    if (!EmittedWarning && Reg < HighRegNum)
1681      Warning(RegInfo.second,
1682              "register not in ascending order in register list");
1683
1684    RegMap[Reg] = true;
1685    HighRegNum = std::max(Reg, HighRegNum);
1686  }
1687
1688  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1689  return false;
1690}
1691
1692/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1693ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1694parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1695  SMLoc S = Parser.getTok().getLoc();
1696  const AsmToken &Tok = Parser.getTok();
1697  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1698  StringRef OptStr = Tok.getString();
1699
1700  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1701    .Case("sy",    ARM_MB::SY)
1702    .Case("st",    ARM_MB::ST)
1703    .Case("sh",    ARM_MB::ISH)
1704    .Case("ish",   ARM_MB::ISH)
1705    .Case("shst",  ARM_MB::ISHST)
1706    .Case("ishst", ARM_MB::ISHST)
1707    .Case("nsh",   ARM_MB::NSH)
1708    .Case("un",    ARM_MB::NSH)
1709    .Case("nshst", ARM_MB::NSHST)
1710    .Case("unst",  ARM_MB::NSHST)
1711    .Case("osh",   ARM_MB::OSH)
1712    .Case("oshst", ARM_MB::OSHST)
1713    .Default(~0U);
1714
1715  if (Opt == ~0U)
1716    return MatchOperand_NoMatch;
1717
1718  Parser.Lex(); // Eat identifier token.
1719  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1720  return MatchOperand_Success;
1721}
1722
1723/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1724ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1725parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1726  SMLoc S = Parser.getTok().getLoc();
1727  const AsmToken &Tok = Parser.getTok();
1728  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1729  StringRef IFlagsStr = Tok.getString();
1730
1731  unsigned IFlags = 0;
1732  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1733    unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1734    .Case("a", ARM_PROC::A)
1735    .Case("i", ARM_PROC::I)
1736    .Case("f", ARM_PROC::F)
1737    .Default(~0U);
1738
1739    // If some specific iflag is already set, it means that some letter is
1740    // present more than once, this is not acceptable.
1741    if (Flag == ~0U || (IFlags & Flag))
1742      return MatchOperand_NoMatch;
1743
1744    IFlags |= Flag;
1745  }
1746
1747  Parser.Lex(); // Eat identifier token.
1748  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1749  return MatchOperand_Success;
1750}
1751
1752/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1753ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1754parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1755  SMLoc S = Parser.getTok().getLoc();
1756  const AsmToken &Tok = Parser.getTok();
1757  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1758  StringRef Mask = Tok.getString();
1759
1760  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1761  size_t Start = 0, Next = Mask.find('_');
1762  StringRef Flags = "";
1763  std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1764  if (Next != StringRef::npos)
1765    Flags = Mask.slice(Next+1, Mask.size());
1766
1767  // FlagsVal contains the complete mask:
1768  // 3-0: Mask
1769  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1770  unsigned FlagsVal = 0;
1771
1772  if (SpecReg == "apsr") {
1773    FlagsVal = StringSwitch<unsigned>(Flags)
1774    .Case("nzcvq",  0x8) // same as CPSR_f
1775    .Case("g",      0x4) // same as CPSR_s
1776    .Case("nzcvqg", 0xc) // same as CPSR_fs
1777    .Default(~0U);
1778
1779    if (FlagsVal == ~0U) {
1780      if (!Flags.empty())
1781        return MatchOperand_NoMatch;
1782      else
1783        FlagsVal = 0; // No flag
1784    }
1785  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1786    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1787      Flags = "fc";
1788    for (int i = 0, e = Flags.size(); i != e; ++i) {
1789      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1790      .Case("c", 1)
1791      .Case("x", 2)
1792      .Case("s", 4)
1793      .Case("f", 8)
1794      .Default(~0U);
1795
1796      // If some specific flag is already set, it means that some letter is
1797      // present more than once, this is not acceptable.
1798      if (FlagsVal == ~0U || (FlagsVal & Flag))
1799        return MatchOperand_NoMatch;
1800      FlagsVal |= Flag;
1801    }
1802  } else // No match for special register.
1803    return MatchOperand_NoMatch;
1804
1805  // Special register without flags are equivalent to "fc" flags.
1806  if (!FlagsVal)
1807    FlagsVal = 0x9;
1808
1809  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1810  if (SpecReg == "spsr")
1811    FlagsVal |= 16;
1812
1813  Parser.Lex(); // Eat identifier token.
1814  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1815  return MatchOperand_Success;
1816}
1817
1818ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1819parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1820            int Low, int High) {
1821  const AsmToken &Tok = Parser.getTok();
1822  if (Tok.isNot(AsmToken::Identifier)) {
1823    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1824    return MatchOperand_ParseFail;
1825  }
1826  StringRef ShiftName = Tok.getString();
1827  std::string LowerOp = LowercaseString(Op);
1828  std::string UpperOp = UppercaseString(Op);
1829  if (ShiftName != LowerOp && ShiftName != UpperOp) {
1830    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1831    return MatchOperand_ParseFail;
1832  }
1833  Parser.Lex(); // Eat shift type token.
1834
1835  // There must be a '#' and a shift amount.
1836  if (Parser.getTok().isNot(AsmToken::Hash)) {
1837    Error(Parser.getTok().getLoc(), "'#' expected");
1838    return MatchOperand_ParseFail;
1839  }
1840  Parser.Lex(); // Eat hash token.
1841
1842  const MCExpr *ShiftAmount;
1843  SMLoc Loc = Parser.getTok().getLoc();
1844  if (getParser().ParseExpression(ShiftAmount)) {
1845    Error(Loc, "illegal expression");
1846    return MatchOperand_ParseFail;
1847  }
1848  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1849  if (!CE) {
1850    Error(Loc, "constant expression expected");
1851    return MatchOperand_ParseFail;
1852  }
1853  int Val = CE->getValue();
1854  if (Val < Low || Val > High) {
1855    Error(Loc, "immediate value out of range");
1856    return MatchOperand_ParseFail;
1857  }
1858
1859  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1860
1861  return MatchOperand_Success;
1862}
1863
1864ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1865parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1866  const AsmToken &Tok = Parser.getTok();
1867  SMLoc S = Tok.getLoc();
1868  if (Tok.isNot(AsmToken::Identifier)) {
1869    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1870    return MatchOperand_ParseFail;
1871  }
1872  int Val = StringSwitch<int>(Tok.getString())
1873    .Case("be", 1)
1874    .Case("le", 0)
1875    .Default(-1);
1876  Parser.Lex(); // Eat the token.
1877
1878  if (Val == -1) {
1879    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1880    return MatchOperand_ParseFail;
1881  }
1882  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1883                                                                  getContext()),
1884                                           S, Parser.getTok().getLoc()));
1885  return MatchOperand_Success;
1886}
1887
1888/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
1889/// instructions. Legal values are:
1890///     lsl #n  'n' in [0,31]
1891///     asr #n  'n' in [1,32]
1892///             n == 32 encoded as n == 0.
1893ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1894parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1895  const AsmToken &Tok = Parser.getTok();
1896  SMLoc S = Tok.getLoc();
1897  if (Tok.isNot(AsmToken::Identifier)) {
1898    Error(S, "shift operator 'asr' or 'lsl' expected");
1899    return MatchOperand_ParseFail;
1900  }
1901  StringRef ShiftName = Tok.getString();
1902  bool isASR;
1903  if (ShiftName == "lsl" || ShiftName == "LSL")
1904    isASR = false;
1905  else if (ShiftName == "asr" || ShiftName == "ASR")
1906    isASR = true;
1907  else {
1908    Error(S, "shift operator 'asr' or 'lsl' expected");
1909    return MatchOperand_ParseFail;
1910  }
1911  Parser.Lex(); // Eat the operator.
1912
1913  // A '#' and a shift amount.
1914  if (Parser.getTok().isNot(AsmToken::Hash)) {
1915    Error(Parser.getTok().getLoc(), "'#' expected");
1916    return MatchOperand_ParseFail;
1917  }
1918  Parser.Lex(); // Eat hash token.
1919
1920  const MCExpr *ShiftAmount;
1921  SMLoc E = Parser.getTok().getLoc();
1922  if (getParser().ParseExpression(ShiftAmount)) {
1923    Error(E, "malformed shift expression");
1924    return MatchOperand_ParseFail;
1925  }
1926  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1927  if (!CE) {
1928    Error(E, "shift amount must be an immediate");
1929    return MatchOperand_ParseFail;
1930  }
1931
1932  int64_t Val = CE->getValue();
1933  if (isASR) {
1934    // Shift amount must be in [1,32]
1935    if (Val < 1 || Val > 32) {
1936      Error(E, "'asr' shift amount must be in range [1,32]");
1937      return MatchOperand_ParseFail;
1938    }
1939    // asr #32 encoded as asr #0.
1940    if (Val == 32) Val = 0;
1941  } else {
1942    // Shift amount must be in [1,32]
1943    if (Val < 0 || Val > 31) {
1944      Error(E, "'lsr' shift amount must be in range [0,31]");
1945      return MatchOperand_ParseFail;
1946    }
1947  }
1948
1949  E = Parser.getTok().getLoc();
1950  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
1951
1952  return MatchOperand_Success;
1953}
1954
1955/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
1956/// of instructions. Legal values are:
1957///     ror #n  'n' in {0, 8, 16, 24}
1958ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1959parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1960  const AsmToken &Tok = Parser.getTok();
1961  SMLoc S = Tok.getLoc();
1962  if (Tok.isNot(AsmToken::Identifier)) {
1963    Error(S, "rotate operator 'ror' expected");
1964    return MatchOperand_ParseFail;
1965  }
1966  StringRef ShiftName = Tok.getString();
1967  if (ShiftName != "ror" && ShiftName != "ROR") {
1968    Error(S, "rotate operator 'ror' expected");
1969    return MatchOperand_ParseFail;
1970  }
1971  Parser.Lex(); // Eat the operator.
1972
1973  // A '#' and a rotate amount.
1974  if (Parser.getTok().isNot(AsmToken::Hash)) {
1975    Error(Parser.getTok().getLoc(), "'#' expected");
1976    return MatchOperand_ParseFail;
1977  }
1978  Parser.Lex(); // Eat hash token.
1979
1980  const MCExpr *ShiftAmount;
1981  SMLoc E = Parser.getTok().getLoc();
1982  if (getParser().ParseExpression(ShiftAmount)) {
1983    Error(E, "malformed rotate expression");
1984    return MatchOperand_ParseFail;
1985  }
1986  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1987  if (!CE) {
1988    Error(E, "rotate amount must be an immediate");
1989    return MatchOperand_ParseFail;
1990  }
1991
1992  int64_t Val = CE->getValue();
1993  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
1994  // normally, zero is represented in asm by omitting the rotate operand
1995  // entirely.
1996  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
1997    Error(E, "'ror' rotate amount must be 8, 16, or 24");
1998    return MatchOperand_ParseFail;
1999  }
2000
2001  E = Parser.getTok().getLoc();
2002  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2003
2004  return MatchOperand_Success;
2005}
2006
2007ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2008parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2009  SMLoc S = Parser.getTok().getLoc();
2010  // The bitfield descriptor is really two operands, the LSB and the width.
2011  if (Parser.getTok().isNot(AsmToken::Hash)) {
2012    Error(Parser.getTok().getLoc(), "'#' expected");
2013    return MatchOperand_ParseFail;
2014  }
2015  Parser.Lex(); // Eat hash token.
2016
2017  const MCExpr *LSBExpr;
2018  SMLoc E = Parser.getTok().getLoc();
2019  if (getParser().ParseExpression(LSBExpr)) {
2020    Error(E, "malformed immediate expression");
2021    return MatchOperand_ParseFail;
2022  }
2023  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2024  if (!CE) {
2025    Error(E, "'lsb' operand must be an immediate");
2026    return MatchOperand_ParseFail;
2027  }
2028
2029  int64_t LSB = CE->getValue();
2030  // The LSB must be in the range [0,31]
2031  if (LSB < 0 || LSB > 31) {
2032    Error(E, "'lsb' operand must be in the range [0,31]");
2033    return MatchOperand_ParseFail;
2034  }
2035  E = Parser.getTok().getLoc();
2036
2037  // Expect another immediate operand.
2038  if (Parser.getTok().isNot(AsmToken::Comma)) {
2039    Error(Parser.getTok().getLoc(), "too few operands");
2040    return MatchOperand_ParseFail;
2041  }
2042  Parser.Lex(); // Eat hash token.
2043  if (Parser.getTok().isNot(AsmToken::Hash)) {
2044    Error(Parser.getTok().getLoc(), "'#' expected");
2045    return MatchOperand_ParseFail;
2046  }
2047  Parser.Lex(); // Eat hash token.
2048
2049  const MCExpr *WidthExpr;
2050  if (getParser().ParseExpression(WidthExpr)) {
2051    Error(E, "malformed immediate expression");
2052    return MatchOperand_ParseFail;
2053  }
2054  CE = dyn_cast<MCConstantExpr>(WidthExpr);
2055  if (!CE) {
2056    Error(E, "'width' operand must be an immediate");
2057    return MatchOperand_ParseFail;
2058  }
2059
2060  int64_t Width = CE->getValue();
2061  // The LSB must be in the range [1,32-lsb]
2062  if (Width < 1 || Width > 32 - LSB) {
2063    Error(E, "'width' operand must be in the range [1,32-lsb]");
2064    return MatchOperand_ParseFail;
2065  }
2066  E = Parser.getTok().getLoc();
2067
2068  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2069
2070  return MatchOperand_Success;
2071}
2072
2073ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2074parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2075  // Check for a post-index addressing register operand. Specifically:
2076  // postidx_reg := '+' register {, shift}
2077  //              | '-' register {, shift}
2078  //              | register {, shift}
2079
2080  // This method must return MatchOperand_NoMatch without consuming any tokens
2081  // in the case where there is no match, as other alternatives take other
2082  // parse methods.
2083  AsmToken Tok = Parser.getTok();
2084  SMLoc S = Tok.getLoc();
2085  bool haveEaten = false;
2086  bool isAdd = true;
2087  int Reg = -1;
2088  if (Tok.is(AsmToken::Plus)) {
2089    Parser.Lex(); // Eat the '+' token.
2090    haveEaten = true;
2091  } else if (Tok.is(AsmToken::Minus)) {
2092    Parser.Lex(); // Eat the '-' token.
2093    isAdd = false;
2094    haveEaten = true;
2095  }
2096  if (Parser.getTok().is(AsmToken::Identifier))
2097    Reg = tryParseRegister();
2098  if (Reg == -1) {
2099    if (!haveEaten)
2100      return MatchOperand_NoMatch;
2101    Error(Parser.getTok().getLoc(), "register expected");
2102    return MatchOperand_ParseFail;
2103  }
2104  SMLoc E = Parser.getTok().getLoc();
2105
2106  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2107  unsigned ShiftImm = 0;
2108  if (Parser.getTok().is(AsmToken::Comma)) {
2109    Parser.Lex(); // Eat the ','.
2110    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2111      return MatchOperand_ParseFail;
2112  }
2113
2114  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2115                                                  ShiftImm, S, E));
2116
2117  return MatchOperand_Success;
2118}
2119
2120ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2121parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2122  // Check for a post-index addressing register operand. Specifically:
2123  // am3offset := '+' register
2124  //              | '-' register
2125  //              | register
2126  //              | # imm
2127  //              | # + imm
2128  //              | # - imm
2129
2130  // This method must return MatchOperand_NoMatch without consuming any tokens
2131  // in the case where there is no match, as other alternatives take other
2132  // parse methods.
2133  AsmToken Tok = Parser.getTok();
2134  SMLoc S = Tok.getLoc();
2135
2136  // Do immediates first, as we always parse those if we have a '#'.
2137  if (Parser.getTok().is(AsmToken::Hash)) {
2138    Parser.Lex(); // Eat the '#'.
2139    // Explicitly look for a '-', as we need to encode negative zero
2140    // differently.
2141    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2142    const MCExpr *Offset;
2143    if (getParser().ParseExpression(Offset))
2144      return MatchOperand_ParseFail;
2145    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2146    if (!CE) {
2147      Error(S, "constant expression expected");
2148      return MatchOperand_ParseFail;
2149    }
2150    SMLoc E = Tok.getLoc();
2151    // Negative zero is encoded as the flag value INT32_MIN.
2152    int32_t Val = CE->getValue();
2153    if (isNegative && Val == 0)
2154      Val = INT32_MIN;
2155
2156    Operands.push_back(
2157      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2158
2159    return MatchOperand_Success;
2160  }
2161
2162
2163  bool haveEaten = false;
2164  bool isAdd = true;
2165  int Reg = -1;
2166  if (Tok.is(AsmToken::Plus)) {
2167    Parser.Lex(); // Eat the '+' token.
2168    haveEaten = true;
2169  } else if (Tok.is(AsmToken::Minus)) {
2170    Parser.Lex(); // Eat the '-' token.
2171    isAdd = false;
2172    haveEaten = true;
2173  }
2174  if (Parser.getTok().is(AsmToken::Identifier))
2175    Reg = tryParseRegister();
2176  if (Reg == -1) {
2177    if (!haveEaten)
2178      return MatchOperand_NoMatch;
2179    Error(Parser.getTok().getLoc(), "register expected");
2180    return MatchOperand_ParseFail;
2181  }
2182  SMLoc E = Parser.getTok().getLoc();
2183
2184  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2185                                                  0, S, E));
2186
2187  return MatchOperand_Success;
2188}
2189
2190/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2191/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2192/// when they refer multiple MIOperands inside a single one.
2193bool ARMAsmParser::
2194cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2195                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2196  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2197
2198  // Create a writeback register dummy placeholder.
2199  Inst.addOperand(MCOperand::CreateImm(0));
2200
2201  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2202  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2203  return true;
2204}
2205
2206/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2207/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2208/// when they refer multiple MIOperands inside a single one.
2209bool ARMAsmParser::
2210cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2211                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2212  // Create a writeback register dummy placeholder.
2213  Inst.addOperand(MCOperand::CreateImm(0));
2214  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2215  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2216  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2217  return true;
2218}
2219
2220/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2221/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2222/// when they refer multiple MIOperands inside a single one.
2223bool ARMAsmParser::
2224cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2225                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2226  // Create a writeback register dummy placeholder.
2227  Inst.addOperand(MCOperand::CreateImm(0));
2228  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2229  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2230  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2231  return true;
2232}
2233
2234/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2235/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2236/// when they refer multiple MIOperands inside a single one.
2237bool ARMAsmParser::
2238cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2239                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2240  // Create a writeback register dummy placeholder.
2241  Inst.addOperand(MCOperand::CreateImm(0));
2242  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2243  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2244  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2245  return true;
2246}
2247
2248/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2249/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2250/// when they refer multiple MIOperands inside a single one.
2251bool ARMAsmParser::
2252cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2253                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2254  // Rt
2255  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2256  // Create a writeback register dummy placeholder.
2257  Inst.addOperand(MCOperand::CreateImm(0));
2258  // addr
2259  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2260  // offset
2261  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2262  // pred
2263  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2264  return true;
2265}
2266
2267/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2268/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2269/// when they refer multiple MIOperands inside a single one.
2270bool ARMAsmParser::
2271cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2272                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2273  // Rt
2274  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2275  // Create a writeback register dummy placeholder.
2276  Inst.addOperand(MCOperand::CreateImm(0));
2277  // addr
2278  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2279  // offset
2280  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2281  // pred
2282  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2283  return true;
2284}
2285
2286/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2287/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2288/// when they refer multiple MIOperands inside a single one.
2289bool ARMAsmParser::
2290cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2291                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2292  // Create a writeback register dummy placeholder.
2293  Inst.addOperand(MCOperand::CreateImm(0));
2294  // Rt
2295  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2296  // addr
2297  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2298  // offset
2299  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2300  // pred
2301  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2302  return true;
2303}
2304
2305/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2306/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2307/// when they refer multiple MIOperands inside a single one.
2308bool ARMAsmParser::
2309cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2310                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2311  // Create a writeback register dummy placeholder.
2312  Inst.addOperand(MCOperand::CreateImm(0));
2313  // Rt
2314  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2315  // addr
2316  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2317  // offset
2318  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2319  // pred
2320  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2321  return true;
2322}
2323
2324/// cvtLdrdPre - Convert parsed operands to MCInst.
2325/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2326/// when they refer multiple MIOperands inside a single one.
2327bool ARMAsmParser::
2328cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2329           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2330  // Rt, Rt2
2331  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2332  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2333  // Create a writeback register dummy placeholder.
2334  Inst.addOperand(MCOperand::CreateImm(0));
2335  // addr
2336  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2337  // pred
2338  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2339  return true;
2340}
2341
2342/// cvtStrdPre - Convert parsed operands to MCInst.
2343/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2344/// when they refer multiple MIOperands inside a single one.
2345bool ARMAsmParser::
2346cvtStrdPre(MCInst &Inst, unsigned Opcode,
2347           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2348  // Create a writeback register dummy placeholder.
2349  Inst.addOperand(MCOperand::CreateImm(0));
2350  // Rt, Rt2
2351  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2352  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2353  // addr
2354  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2355  // pred
2356  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2357  return true;
2358}
2359
2360/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2361/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2362/// when they refer multiple MIOperands inside a single one.
2363bool ARMAsmParser::
2364cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2365                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2366  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2367  // Create a writeback register dummy placeholder.
2368  Inst.addOperand(MCOperand::CreateImm(0));
2369  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2370  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2371  return true;
2372}
2373
2374
2375/// Parse an ARM memory expression, return false if successful else return true
2376/// or an error.  The first token must be a '[' when called.
2377bool ARMAsmParser::
2378parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2379  SMLoc S, E;
2380  assert(Parser.getTok().is(AsmToken::LBrac) &&
2381         "Token is not a Left Bracket");
2382  S = Parser.getTok().getLoc();
2383  Parser.Lex(); // Eat left bracket token.
2384
2385  const AsmToken &BaseRegTok = Parser.getTok();
2386  int BaseRegNum = tryParseRegister();
2387  if (BaseRegNum == -1)
2388    return Error(BaseRegTok.getLoc(), "register expected");
2389
2390  // The next token must either be a comma or a closing bracket.
2391  const AsmToken &Tok = Parser.getTok();
2392  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2393    return Error(Tok.getLoc(), "malformed memory operand");
2394
2395  if (Tok.is(AsmToken::RBrac)) {
2396    E = Tok.getLoc();
2397    Parser.Lex(); // Eat right bracket token.
2398
2399    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2400                                             0, false, S, E));
2401
2402    return false;
2403  }
2404
2405  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2406  Parser.Lex(); // Eat the comma.
2407
2408  // If we have a '#' it's an immediate offset, else assume it's a register
2409  // offset.
2410  if (Parser.getTok().is(AsmToken::Hash)) {
2411    Parser.Lex(); // Eat the '#'.
2412    E = Parser.getTok().getLoc();
2413
2414    // FIXME: Special case #-0 so we can correctly set the U bit.
2415
2416    const MCExpr *Offset;
2417    if (getParser().ParseExpression(Offset))
2418     return true;
2419
2420    // The expression has to be a constant. Memory references with relocations
2421    // don't come through here, as they use the <label> forms of the relevant
2422    // instructions.
2423    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2424    if (!CE)
2425      return Error (E, "constant expression expected");
2426
2427    // Now we should have the closing ']'
2428    E = Parser.getTok().getLoc();
2429    if (Parser.getTok().isNot(AsmToken::RBrac))
2430      return Error(E, "']' expected");
2431    Parser.Lex(); // Eat right bracket token.
2432
2433    // Don't worry about range checking the value here. That's handled by
2434    // the is*() predicates.
2435    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2436                                             ARM_AM::no_shift, 0, false, S,E));
2437
2438    // If there's a pre-indexing writeback marker, '!', just add it as a token
2439    // operand.
2440    if (Parser.getTok().is(AsmToken::Exclaim)) {
2441      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2442      Parser.Lex(); // Eat the '!'.
2443    }
2444
2445    return false;
2446  }
2447
2448  // The register offset is optionally preceded by a '+' or '-'
2449  bool isNegative = false;
2450  if (Parser.getTok().is(AsmToken::Minus)) {
2451    isNegative = true;
2452    Parser.Lex(); // Eat the '-'.
2453  } else if (Parser.getTok().is(AsmToken::Plus)) {
2454    // Nothing to do.
2455    Parser.Lex(); // Eat the '+'.
2456  }
2457
2458  E = Parser.getTok().getLoc();
2459  int OffsetRegNum = tryParseRegister();
2460  if (OffsetRegNum == -1)
2461    return Error(E, "register expected");
2462
2463  // If there's a shift operator, handle it.
2464  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2465  unsigned ShiftImm = 0;
2466  if (Parser.getTok().is(AsmToken::Comma)) {
2467    Parser.Lex(); // Eat the ','.
2468    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2469      return true;
2470  }
2471
2472  // Now we should have the closing ']'
2473  E = Parser.getTok().getLoc();
2474  if (Parser.getTok().isNot(AsmToken::RBrac))
2475    return Error(E, "']' expected");
2476  Parser.Lex(); // Eat right bracket token.
2477
2478  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2479                                           ShiftType, ShiftImm, isNegative,
2480                                           S, E));
2481
2482  // If there's a pre-indexing writeback marker, '!', just add it as a token
2483  // operand.
2484  if (Parser.getTok().is(AsmToken::Exclaim)) {
2485    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2486    Parser.Lex(); // Eat the '!'.
2487  }
2488
2489  return false;
2490}
2491
2492/// parseMemRegOffsetShift - one of these two:
2493///   ( lsl | lsr | asr | ror ) , # shift_amount
2494///   rrx
2495/// return true if it parses a shift otherwise it returns false.
2496bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2497                                          unsigned &Amount) {
2498  SMLoc Loc = Parser.getTok().getLoc();
2499  const AsmToken &Tok = Parser.getTok();
2500  if (Tok.isNot(AsmToken::Identifier))
2501    return true;
2502  StringRef ShiftName = Tok.getString();
2503  if (ShiftName == "lsl" || ShiftName == "LSL")
2504    St = ARM_AM::lsl;
2505  else if (ShiftName == "lsr" || ShiftName == "LSR")
2506    St = ARM_AM::lsr;
2507  else if (ShiftName == "asr" || ShiftName == "ASR")
2508    St = ARM_AM::asr;
2509  else if (ShiftName == "ror" || ShiftName == "ROR")
2510    St = ARM_AM::ror;
2511  else if (ShiftName == "rrx" || ShiftName == "RRX")
2512    St = ARM_AM::rrx;
2513  else
2514    return Error(Loc, "illegal shift operator");
2515  Parser.Lex(); // Eat shift type token.
2516
2517  // rrx stands alone.
2518  Amount = 0;
2519  if (St != ARM_AM::rrx) {
2520    Loc = Parser.getTok().getLoc();
2521    // A '#' and a shift amount.
2522    const AsmToken &HashTok = Parser.getTok();
2523    if (HashTok.isNot(AsmToken::Hash))
2524      return Error(HashTok.getLoc(), "'#' expected");
2525    Parser.Lex(); // Eat hash token.
2526
2527    const MCExpr *Expr;
2528    if (getParser().ParseExpression(Expr))
2529      return true;
2530    // Range check the immediate.
2531    // lsl, ror: 0 <= imm <= 31
2532    // lsr, asr: 0 <= imm <= 32
2533    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2534    if (!CE)
2535      return Error(Loc, "shift amount must be an immediate");
2536    int64_t Imm = CE->getValue();
2537    if (Imm < 0 ||
2538        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2539        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2540      return Error(Loc, "immediate shift value out of range");
2541    Amount = Imm;
2542  }
2543
2544  return false;
2545}
2546
2547/// Parse a arm instruction operand.  For now this parses the operand regardless
2548/// of the mnemonic.
2549bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2550                                StringRef Mnemonic) {
2551  SMLoc S, E;
2552
2553  // Check if the current operand has a custom associated parser, if so, try to
2554  // custom parse the operand, or fallback to the general approach.
2555  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2556  if (ResTy == MatchOperand_Success)
2557    return false;
2558  // If there wasn't a custom match, try the generic matcher below. Otherwise,
2559  // there was a match, but an error occurred, in which case, just return that
2560  // the operand parsing failed.
2561  if (ResTy == MatchOperand_ParseFail)
2562    return true;
2563
2564  switch (getLexer().getKind()) {
2565  default:
2566    Error(Parser.getTok().getLoc(), "unexpected token in operand");
2567    return true;
2568  case AsmToken::Identifier: {
2569    if (!tryParseRegisterWithWriteBack(Operands))
2570      return false;
2571    int Res = tryParseShiftRegister(Operands);
2572    if (Res == 0) // success
2573      return false;
2574    else if (Res == -1) // irrecoverable error
2575      return true;
2576
2577    // Fall though for the Identifier case that is not a register or a
2578    // special name.
2579  }
2580  case AsmToken::Integer: // things like 1f and 2b as a branch targets
2581  case AsmToken::Dot: {   // . as a branch target
2582    // This was not a register so parse other operands that start with an
2583    // identifier (like labels) as expressions and create them as immediates.
2584    const MCExpr *IdVal;
2585    S = Parser.getTok().getLoc();
2586    if (getParser().ParseExpression(IdVal))
2587      return true;
2588    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2589    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2590    return false;
2591  }
2592  case AsmToken::LBrac:
2593    return parseMemory(Operands);
2594  case AsmToken::LCurly:
2595    return parseRegisterList(Operands);
2596  case AsmToken::Hash:
2597    // #42 -> immediate.
2598    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2599    S = Parser.getTok().getLoc();
2600    Parser.Lex();
2601    const MCExpr *ImmVal;
2602    if (getParser().ParseExpression(ImmVal))
2603      return true;
2604    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2605    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2606    return false;
2607  case AsmToken::Colon: {
2608    // ":lower16:" and ":upper16:" expression prefixes
2609    // FIXME: Check it's an expression prefix,
2610    // e.g. (FOO - :lower16:BAR) isn't legal.
2611    ARMMCExpr::VariantKind RefKind;
2612    if (parsePrefix(RefKind))
2613      return true;
2614
2615    const MCExpr *SubExprVal;
2616    if (getParser().ParseExpression(SubExprVal))
2617      return true;
2618
2619    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2620                                                   getContext());
2621    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2622    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2623    return false;
2624  }
2625  }
2626}
2627
2628// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2629//  :lower16: and :upper16:.
2630bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2631  RefKind = ARMMCExpr::VK_ARM_None;
2632
2633  // :lower16: and :upper16: modifiers
2634  assert(getLexer().is(AsmToken::Colon) && "expected a :");
2635  Parser.Lex(); // Eat ':'
2636
2637  if (getLexer().isNot(AsmToken::Identifier)) {
2638    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2639    return true;
2640  }
2641
2642  StringRef IDVal = Parser.getTok().getIdentifier();
2643  if (IDVal == "lower16") {
2644    RefKind = ARMMCExpr::VK_ARM_LO16;
2645  } else if (IDVal == "upper16") {
2646    RefKind = ARMMCExpr::VK_ARM_HI16;
2647  } else {
2648    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2649    return true;
2650  }
2651  Parser.Lex();
2652
2653  if (getLexer().isNot(AsmToken::Colon)) {
2654    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2655    return true;
2656  }
2657  Parser.Lex(); // Eat the last ':'
2658  return false;
2659}
2660
2661const MCExpr *
2662ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2663                                MCSymbolRefExpr::VariantKind Variant) {
2664  // Recurse over the given expression, rebuilding it to apply the given variant
2665  // to the leftmost symbol.
2666  if (Variant == MCSymbolRefExpr::VK_None)
2667    return E;
2668
2669  switch (E->getKind()) {
2670  case MCExpr::Target:
2671    llvm_unreachable("Can't handle target expr yet");
2672  case MCExpr::Constant:
2673    llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2674
2675  case MCExpr::SymbolRef: {
2676    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2677
2678    if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2679      return 0;
2680
2681    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2682  }
2683
2684  case MCExpr::Unary:
2685    llvm_unreachable("Can't handle unary expressions yet");
2686
2687  case MCExpr::Binary: {
2688    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2689    const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2690    const MCExpr *RHS = BE->getRHS();
2691    if (!LHS)
2692      return 0;
2693
2694    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2695  }
2696  }
2697
2698  assert(0 && "Invalid expression kind!");
2699  return 0;
2700}
2701
2702/// \brief Given a mnemonic, split out possible predication code and carry
2703/// setting letters to form a canonical mnemonic and flags.
2704//
2705// FIXME: Would be nice to autogen this.
2706StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2707                                      unsigned &PredicationCode,
2708                                      bool &CarrySetting,
2709                                      unsigned &ProcessorIMod) {
2710  PredicationCode = ARMCC::AL;
2711  CarrySetting = false;
2712  ProcessorIMod = 0;
2713
2714  // Ignore some mnemonics we know aren't predicated forms.
2715  //
2716  // FIXME: Would be nice to autogen this.
2717  if ((Mnemonic == "movs" && isThumb()) ||
2718      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
2719      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
2720      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
2721      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
2722      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
2723      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
2724      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2725    return Mnemonic;
2726
2727  // First, split out any predication code. Ignore mnemonics we know aren't
2728  // predicated but do have a carry-set and so weren't caught above.
2729  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2730      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2731      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls") {
2732    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2733      .Case("eq", ARMCC::EQ)
2734      .Case("ne", ARMCC::NE)
2735      .Case("hs", ARMCC::HS)
2736      .Case("cs", ARMCC::HS)
2737      .Case("lo", ARMCC::LO)
2738      .Case("cc", ARMCC::LO)
2739      .Case("mi", ARMCC::MI)
2740      .Case("pl", ARMCC::PL)
2741      .Case("vs", ARMCC::VS)
2742      .Case("vc", ARMCC::VC)
2743      .Case("hi", ARMCC::HI)
2744      .Case("ls", ARMCC::LS)
2745      .Case("ge", ARMCC::GE)
2746      .Case("lt", ARMCC::LT)
2747      .Case("gt", ARMCC::GT)
2748      .Case("le", ARMCC::LE)
2749      .Case("al", ARMCC::AL)
2750      .Default(~0U);
2751    if (CC != ~0U) {
2752      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2753      PredicationCode = CC;
2754    }
2755  }
2756
2757  // Next, determine if we have a carry setting bit. We explicitly ignore all
2758  // the instructions we know end in 's'.
2759  if (Mnemonic.endswith("s") &&
2760      !(Mnemonic == "cps" || Mnemonic == "mls" ||
2761        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2762        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2763        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2764        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
2765        (Mnemonic == "movs" && isThumb()))) {
2766    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2767    CarrySetting = true;
2768  }
2769
2770  // The "cps" instruction can have a interrupt mode operand which is glued into
2771  // the mnemonic. Check if this is the case, split it and parse the imod op
2772  if (Mnemonic.startswith("cps")) {
2773    // Split out any imod code.
2774    unsigned IMod =
2775      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2776      .Case("ie", ARM_PROC::IE)
2777      .Case("id", ARM_PROC::ID)
2778      .Default(~0U);
2779    if (IMod != ~0U) {
2780      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2781      ProcessorIMod = IMod;
2782    }
2783  }
2784
2785  return Mnemonic;
2786}
2787
2788/// \brief Given a canonical mnemonic, determine if the instruction ever allows
2789/// inclusion of carry set or predication code operands.
2790//
2791// FIXME: It would be nice to autogen this.
2792void ARMAsmParser::
2793getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2794                      bool &CanAcceptPredicationCode) {
2795  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2796      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2797      Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2798      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2799      Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2800      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2801      Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2802      Mnemonic == "eor" || Mnemonic == "smlal" ||
2803      // FIXME: We need a better way. This really confused Thumb2
2804      // parsing for 'mov'.
2805      (Mnemonic == "mov" && !isThumbOne())) {
2806    CanAcceptCarrySet = true;
2807  } else {
2808    CanAcceptCarrySet = false;
2809  }
2810
2811  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2812      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2813      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2814      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2815      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2816      Mnemonic == "setend" ||
2817      ((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) ||
2818      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs"))
2819        && !isThumb()) ||
2820      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2821    CanAcceptPredicationCode = false;
2822  } else {
2823    CanAcceptPredicationCode = true;
2824  }
2825
2826  if (isThumb())
2827    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2828        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2829      CanAcceptPredicationCode = false;
2830}
2831
2832bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
2833                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2834
2835  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2836  // another does not. Specifically, the MOVW instruction does not. So we
2837  // special case it here and remove the defaulted (non-setting) cc_out
2838  // operand if that's the instruction we're trying to match.
2839  //
2840  // We do this as post-processing of the explicit operands rather than just
2841  // conditionally adding the cc_out in the first place because we need
2842  // to check the type of the parsed immediate operand.
2843  if (Mnemonic == "mov" && Operands.size() > 4 &&
2844      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
2845      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
2846      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2847    return true;
2848
2849  // Register-register 'add' for thumb does not have a cc_out operand
2850  // when there are only two register operands.
2851  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
2852      static_cast<ARMOperand*>(Operands[3])->isReg() &&
2853      static_cast<ARMOperand*>(Operands[4])->isReg() &&
2854      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2855    return true;
2856
2857  return false;
2858}
2859
2860/// Parse an arm instruction mnemonic followed by its operands.
2861bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2862                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2863  // Create the leading tokens for the mnemonic, split by '.' characters.
2864  size_t Start = 0, Next = Name.find('.');
2865  StringRef Mnemonic = Name.slice(Start, Next);
2866
2867  // Split out the predication code and carry setting flag from the mnemonic.
2868  unsigned PredicationCode;
2869  unsigned ProcessorIMod;
2870  bool CarrySetting;
2871  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
2872                           ProcessorIMod);
2873
2874  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
2875
2876  // FIXME: This is all a pretty gross hack. We should automatically handle
2877  // optional operands like this via tblgen.
2878
2879  // Next, add the CCOut and ConditionCode operands, if needed.
2880  //
2881  // For mnemonics which can ever incorporate a carry setting bit or predication
2882  // code, our matching model involves us always generating CCOut and
2883  // ConditionCode operands to match the mnemonic "as written" and then we let
2884  // the matcher deal with finding the right instruction or generating an
2885  // appropriate error.
2886  bool CanAcceptCarrySet, CanAcceptPredicationCode;
2887  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
2888
2889  // If we had a carry-set on an instruction that can't do that, issue an
2890  // error.
2891  if (!CanAcceptCarrySet && CarrySetting) {
2892    Parser.EatToEndOfStatement();
2893    return Error(NameLoc, "instruction '" + Mnemonic +
2894                 "' can not set flags, but 's' suffix specified");
2895  }
2896  // If we had a predication code on an instruction that can't do that, issue an
2897  // error.
2898  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
2899    Parser.EatToEndOfStatement();
2900    return Error(NameLoc, "instruction '" + Mnemonic +
2901                 "' is not predicable, but condition code specified");
2902  }
2903
2904  // Add the carry setting operand, if necessary.
2905  //
2906  // FIXME: It would be awesome if we could somehow invent a location such that
2907  // match errors on this operand would print a nice diagnostic about how the
2908  // 's' character in the mnemonic resulted in a CCOut operand.
2909  if (CanAcceptCarrySet)
2910    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
2911                                               NameLoc));
2912
2913  // Add the predication code operand, if necessary.
2914  if (CanAcceptPredicationCode) {
2915    Operands.push_back(ARMOperand::CreateCondCode(
2916                         ARMCC::CondCodes(PredicationCode), NameLoc));
2917  }
2918
2919  // Add the processor imod operand, if necessary.
2920  if (ProcessorIMod) {
2921    Operands.push_back(ARMOperand::CreateImm(
2922          MCConstantExpr::Create(ProcessorIMod, getContext()),
2923                                 NameLoc, NameLoc));
2924  } else {
2925    // This mnemonic can't ever accept a imod, but the user wrote
2926    // one (or misspelled another mnemonic).
2927
2928    // FIXME: Issue a nice error.
2929  }
2930
2931  // Add the remaining tokens in the mnemonic.
2932  while (Next != StringRef::npos) {
2933    Start = Next;
2934    Next = Name.find('.', Start + 1);
2935    StringRef ExtraToken = Name.slice(Start, Next);
2936
2937    Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
2938  }
2939
2940  // Read the remaining operands.
2941  if (getLexer().isNot(AsmToken::EndOfStatement)) {
2942    // Read the first operand.
2943    if (parseOperand(Operands, Mnemonic)) {
2944      Parser.EatToEndOfStatement();
2945      return true;
2946    }
2947
2948    while (getLexer().is(AsmToken::Comma)) {
2949      Parser.Lex();  // Eat the comma.
2950
2951      // Parse and remember the operand.
2952      if (parseOperand(Operands, Mnemonic)) {
2953        Parser.EatToEndOfStatement();
2954        return true;
2955      }
2956    }
2957  }
2958
2959  if (getLexer().isNot(AsmToken::EndOfStatement)) {
2960    Parser.EatToEndOfStatement();
2961    return TokError("unexpected token in argument list");
2962  }
2963
2964  Parser.Lex(); // Consume the EndOfStatement
2965
2966  // Some instructions, mostly Thumb, have forms for the same mnemonic that
2967  // do and don't have a cc_out optional-def operand. With some spot-checks
2968  // of the operand list, we can figure out which variant we're trying to
2969  // parse and adjust accordingly before actually matching. Reason number
2970  // #317 the table driven matcher doesn't fit well with the ARM instruction
2971  // set.
2972  if (shouldOmitCCOutOperand(Mnemonic, Operands)) {
2973    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2974    Operands.erase(Operands.begin() + 1);
2975    delete Op;
2976  }
2977
2978  // ARM mode 'blx' need special handling, as the register operand version
2979  // is predicable, but the label operand version is not. So, we can't rely
2980  // on the Mnemonic based checking to correctly figure out when to put
2981  // a CondCode operand in the list. If we're trying to match the label
2982  // version, remove the CondCode operand here.
2983  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
2984      static_cast<ARMOperand*>(Operands[2])->isImm()) {
2985    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2986    Operands.erase(Operands.begin() + 1);
2987    delete Op;
2988  }
2989
2990  // The vector-compare-to-zero instructions have a literal token "#0" at
2991  // the end that comes to here as an immediate operand. Convert it to a
2992  // token to play nicely with the matcher.
2993  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
2994      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
2995      static_cast<ARMOperand*>(Operands[5])->isImm()) {
2996    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
2997    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
2998    if (CE && CE->getValue() == 0) {
2999      Operands.erase(Operands.begin() + 5);
3000      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3001      delete Op;
3002    }
3003  }
3004  return false;
3005}
3006
3007// Validate context-sensitive operand constraints.
3008// FIXME: We would really like to be able to tablegen'erate this.
3009bool ARMAsmParser::
3010validateInstruction(MCInst &Inst,
3011                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3012  switch (Inst.getOpcode()) {
3013  case ARM::LDRD:
3014  case ARM::LDRD_PRE:
3015  case ARM::LDRD_POST:
3016  case ARM::LDREXD: {
3017    // Rt2 must be Rt + 1.
3018    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3019    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3020    if (Rt2 != Rt + 1)
3021      return Error(Operands[3]->getStartLoc(),
3022                   "destination operands must be sequential");
3023    return false;
3024  }
3025  case ARM::STRD: {
3026    // Rt2 must be Rt + 1.
3027    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3028    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3029    if (Rt2 != Rt + 1)
3030      return Error(Operands[3]->getStartLoc(),
3031                   "source operands must be sequential");
3032    return false;
3033  }
3034  case ARM::STRD_PRE:
3035  case ARM::STRD_POST:
3036  case ARM::STREXD: {
3037    // Rt2 must be Rt + 1.
3038    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3039    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3040    if (Rt2 != Rt + 1)
3041      return Error(Operands[3]->getStartLoc(),
3042                   "source operands must be sequential");
3043    return false;
3044  }
3045  case ARM::SBFX:
3046  case ARM::UBFX: {
3047    // width must be in range [1, 32-lsb]
3048    unsigned lsb = Inst.getOperand(2).getImm();
3049    unsigned widthm1 = Inst.getOperand(3).getImm();
3050    if (widthm1 >= 32 - lsb)
3051      return Error(Operands[5]->getStartLoc(),
3052                   "bitfield width must be in range [1,32-lsb]");
3053    return false;
3054  }
3055  case ARM::tLDMIA: {
3056    // Thumb LDM instructions are writeback iff the base register is not
3057    // in the register list.
3058    unsigned Rn = Inst.getOperand(0).getReg();
3059    bool doesWriteback = true;
3060    for (unsigned i = 3; i < Inst.getNumOperands(); ++i) {
3061      unsigned Reg = Inst.getOperand(i).getReg();
3062      if (Reg == Rn)
3063        doesWriteback = false;
3064      // Anything other than a low register isn't legal here.
3065      if (!isARMLowRegister(Reg))
3066        return Error(Operands[4]->getStartLoc(),
3067                     "registers must be in range r0-r7");
3068    }
3069    // If we should have writeback, then there should be a '!' token.
3070    if (doesWriteback &&
3071        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
3072         static_cast<ARMOperand*>(Operands[3])->getToken() != "!"))
3073      return Error(Operands[2]->getStartLoc(),
3074                   "writeback operator '!' expected");
3075
3076    break;
3077  }
3078  }
3079
3080  return false;
3081}
3082
3083void ARMAsmParser::
3084processInstruction(MCInst &Inst,
3085                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3086  switch (Inst.getOpcode()) {
3087  case ARM::LDMIA_UPD:
3088    // If this is a load of a single register via a 'pop', then we should use
3089    // a post-indexed LDR instruction instead, per the ARM ARM.
3090    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3091        Inst.getNumOperands() == 5) {
3092      MCInst TmpInst;
3093      TmpInst.setOpcode(ARM::LDR_POST_IMM);
3094      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3095      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3096      TmpInst.addOperand(Inst.getOperand(1)); // Rn
3097      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
3098      TmpInst.addOperand(MCOperand::CreateImm(4));
3099      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3100      TmpInst.addOperand(Inst.getOperand(3));
3101      Inst = TmpInst;
3102    }
3103    break;
3104  case ARM::STMDB_UPD:
3105    // If this is a store of a single register via a 'push', then we should use
3106    // a pre-indexed STR instruction instead, per the ARM ARM.
3107    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3108        Inst.getNumOperands() == 5) {
3109      MCInst TmpInst;
3110      TmpInst.setOpcode(ARM::STR_PRE_IMM);
3111      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3112      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3113      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3114      TmpInst.addOperand(MCOperand::CreateImm(-4));
3115      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3116      TmpInst.addOperand(Inst.getOperand(3));
3117      Inst = TmpInst;
3118    }
3119    break;
3120  case ARM::tADDi8:
3121    // If the immediate is in the range 0-7, we really wanted tADDi3.
3122    if (Inst.getOperand(3).getImm() < 8)
3123      Inst.setOpcode(ARM::tADDi3);
3124    break;
3125  case ARM::tBcc:
3126    // If the conditional is AL, we really want tB.
3127    if (Inst.getOperand(1).getImm() == ARMCC::AL)
3128      Inst.setOpcode(ARM::tB);
3129    break;
3130  }
3131}
3132
3133// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3134// the ARMInsts array) instead. Getting that here requires awkward
3135// API changes, though. Better way?
3136namespace llvm {
3137extern MCInstrDesc ARMInsts[];
3138}
3139static MCInstrDesc &getInstDesc(unsigned Opcode) {
3140  return ARMInsts[Opcode];
3141}
3142
3143unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3144  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3145  // suffix depending on whether they're in an IT block or not.
3146  unsigned Opc = Inst.getOpcode();
3147  MCInstrDesc &MCID = getInstDesc(Opc);
3148  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3149    assert(MCID.hasOptionalDef() &&
3150           "optionally flag setting instruction missing optional def operand");
3151    assert(MCID.NumOperands == Inst.getNumOperands() &&
3152           "operand count mismatch!");
3153    // Find the optional-def operand (cc_out).
3154    unsigned OpNo;
3155    for (OpNo = 0;
3156         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3157         ++OpNo)
3158      ;
3159    // If we're parsing Thumb1, reject it completely.
3160    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3161      return Match_MnemonicFail;
3162    // If we're parsing Thumb2, which form is legal depends on whether we're
3163    // in an IT block.
3164    // FIXME: We don't yet do IT blocks, so just always consider it to be
3165    // that we aren't in one until we do.
3166    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3167      return Match_RequiresITBlock;
3168  }
3169  // Some high-register supporting Thumb1 encodings only allow both registers
3170  // to be from r0-r7 when in Thumb2.
3171  else if (Opc == ARM::tADDhirr && isThumbOne() &&
3172           isARMLowRegister(Inst.getOperand(1).getReg()) &&
3173           isARMLowRegister(Inst.getOperand(2).getReg()))
3174    return Match_RequiresThumb2;
3175  // Others only require ARMv6 or later.
3176  else if (Opc == ARM::tMOVr && isThumbOne() &&
3177           isARMLowRegister(Inst.getOperand(0).getReg()) &&
3178           isARMLowRegister(Inst.getOperand(1).getReg()))
3179    return Match_RequiresV6;
3180  return Match_Success;
3181}
3182
3183bool ARMAsmParser::
3184MatchAndEmitInstruction(SMLoc IDLoc,
3185                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3186                        MCStreamer &Out) {
3187  MCInst Inst;
3188  unsigned ErrorInfo;
3189  unsigned MatchResult;
3190  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3191  switch (MatchResult) {
3192  default: break;
3193  case Match_Success:
3194    // Context sensitive operand constraints aren't handled by the matcher,
3195    // so check them here.
3196    if (validateInstruction(Inst, Operands))
3197      return true;
3198
3199    // Some instructions need post-processing to, for example, tweak which
3200    // encoding is selected.
3201    processInstruction(Inst, Operands);
3202
3203    Out.EmitInstruction(Inst);
3204    return false;
3205  case Match_MissingFeature:
3206    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3207    return true;
3208  case Match_InvalidOperand: {
3209    SMLoc ErrorLoc = IDLoc;
3210    if (ErrorInfo != ~0U) {
3211      if (ErrorInfo >= Operands.size())
3212        return Error(IDLoc, "too few operands for instruction");
3213
3214      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3215      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3216    }
3217
3218    return Error(ErrorLoc, "invalid operand for instruction");
3219  }
3220  case Match_MnemonicFail:
3221    return Error(IDLoc, "invalid instruction");
3222  case Match_ConversionFail:
3223    return Error(IDLoc, "unable to convert operands to instruction");
3224  case Match_RequiresITBlock:
3225    return Error(IDLoc, "instruction only valid inside IT block");
3226  case Match_RequiresV6:
3227    return Error(IDLoc, "instruction variant requires ARMv6 or later");
3228  case Match_RequiresThumb2:
3229    return Error(IDLoc, "instruction variant requires Thumb2");
3230  }
3231
3232  llvm_unreachable("Implement any new match types added!");
3233  return true;
3234}
3235
3236/// parseDirective parses the arm specific directives
3237bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3238  StringRef IDVal = DirectiveID.getIdentifier();
3239  if (IDVal == ".word")
3240    return parseDirectiveWord(4, DirectiveID.getLoc());
3241  else if (IDVal == ".thumb")
3242    return parseDirectiveThumb(DirectiveID.getLoc());
3243  else if (IDVal == ".thumb_func")
3244    return parseDirectiveThumbFunc(DirectiveID.getLoc());
3245  else if (IDVal == ".code")
3246    return parseDirectiveCode(DirectiveID.getLoc());
3247  else if (IDVal == ".syntax")
3248    return parseDirectiveSyntax(DirectiveID.getLoc());
3249  return true;
3250}
3251
3252/// parseDirectiveWord
3253///  ::= .word [ expression (, expression)* ]
3254bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3255  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3256    for (;;) {
3257      const MCExpr *Value;
3258      if (getParser().ParseExpression(Value))
3259        return true;
3260
3261      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3262
3263      if (getLexer().is(AsmToken::EndOfStatement))
3264        break;
3265
3266      // FIXME: Improve diagnostic.
3267      if (getLexer().isNot(AsmToken::Comma))
3268        return Error(L, "unexpected token in directive");
3269      Parser.Lex();
3270    }
3271  }
3272
3273  Parser.Lex();
3274  return false;
3275}
3276
3277/// parseDirectiveThumb
3278///  ::= .thumb
3279bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3280  if (getLexer().isNot(AsmToken::EndOfStatement))
3281    return Error(L, "unexpected token in directive");
3282  Parser.Lex();
3283
3284  // TODO: set thumb mode
3285  // TODO: tell the MC streamer the mode
3286  // getParser().getStreamer().Emit???();
3287  return false;
3288}
3289
3290/// parseDirectiveThumbFunc
3291///  ::= .thumbfunc symbol_name
3292bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3293  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3294  bool isMachO = MAI.hasSubsectionsViaSymbols();
3295  StringRef Name;
3296
3297  // Darwin asm has function name after .thumb_func direction
3298  // ELF doesn't
3299  if (isMachO) {
3300    const AsmToken &Tok = Parser.getTok();
3301    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3302      return Error(L, "unexpected token in .thumb_func directive");
3303    Name = Tok.getString();
3304    Parser.Lex(); // Consume the identifier token.
3305  }
3306
3307  if (getLexer().isNot(AsmToken::EndOfStatement))
3308    return Error(L, "unexpected token in directive");
3309  Parser.Lex();
3310
3311  // FIXME: assuming function name will be the line following .thumb_func
3312  if (!isMachO) {
3313    Name = Parser.getTok().getString();
3314  }
3315
3316  // Mark symbol as a thumb symbol.
3317  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3318  getParser().getStreamer().EmitThumbFunc(Func);
3319  return false;
3320}
3321
3322/// parseDirectiveSyntax
3323///  ::= .syntax unified | divided
3324bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3325  const AsmToken &Tok = Parser.getTok();
3326  if (Tok.isNot(AsmToken::Identifier))
3327    return Error(L, "unexpected token in .syntax directive");
3328  StringRef Mode = Tok.getString();
3329  if (Mode == "unified" || Mode == "UNIFIED")
3330    Parser.Lex();
3331  else if (Mode == "divided" || Mode == "DIVIDED")
3332    return Error(L, "'.syntax divided' arm asssembly not supported");
3333  else
3334    return Error(L, "unrecognized syntax mode in .syntax directive");
3335
3336  if (getLexer().isNot(AsmToken::EndOfStatement))
3337    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3338  Parser.Lex();
3339
3340  // TODO tell the MC streamer the mode
3341  // getParser().getStreamer().Emit???();
3342  return false;
3343}
3344
3345/// parseDirectiveCode
3346///  ::= .code 16 | 32
3347bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3348  const AsmToken &Tok = Parser.getTok();
3349  if (Tok.isNot(AsmToken::Integer))
3350    return Error(L, "unexpected token in .code directive");
3351  int64_t Val = Parser.getTok().getIntVal();
3352  if (Val == 16)
3353    Parser.Lex();
3354  else if (Val == 32)
3355    Parser.Lex();
3356  else
3357    return Error(L, "invalid operand to .code directive");
3358
3359  if (getLexer().isNot(AsmToken::EndOfStatement))
3360    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3361  Parser.Lex();
3362
3363  if (Val == 16) {
3364    if (!isThumb()) {
3365      SwitchMode();
3366      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3367    }
3368  } else {
3369    if (isThumb()) {
3370      SwitchMode();
3371      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3372    }
3373  }
3374
3375  return false;
3376}
3377
3378extern "C" void LLVMInitializeARMAsmLexer();
3379
3380/// Force static initialization.
3381extern "C" void LLVMInitializeARMAsmParser() {
3382  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3383  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3384  LLVMInitializeARMAsmLexer();
3385}
3386
3387#define GET_REGISTER_MATCHER
3388#define GET_MATCHER_IMPLEMENTATION
3389#include "ARMGenAsmMatcher.inc"
3390