ARMAsmParser.cpp revision 1fd374e9c1c074c1681336bef31e65f0170b0f7e 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "ARM.h"
11#include "ARMAddressingModes.h"
12#include "ARMSubtarget.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCStreamer.h"
18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/Target/TargetRegistry.h"
21#include "llvm/Target/TargetAsmParser.h"
22#include "llvm/Support/SourceMgr.h"
23#include "llvm/Support/raw_ostream.h"
24#include "llvm/ADT/SmallVector.h"
25#include "llvm/ADT/StringSwitch.h"
26#include "llvm/ADT/Twine.h"
27using namespace llvm;
28
29// The shift types for register controlled shifts in arm memory addressing
30enum ShiftType {
31  Lsl,
32  Lsr,
33  Asr,
34  Ror,
35  Rrx
36};
37
38namespace {
39
40class ARMOperand;
41
42class ARMAsmParser : public TargetAsmParser {
43  MCAsmParser &Parser;
44  TargetMachine &TM;
45
46  MCAsmParser &getParser() const { return Parser; }
47  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
48
49  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
50  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
51
52  int TryParseRegister();
53  bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
54  bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
55  bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
56  bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &);
57
58  bool ParseMemoryOffsetReg(bool &Negative,
59                            bool &OffsetRegShifted,
60                            enum ShiftType &ShiftType,
61                            const MCExpr *&ShiftAmount,
62                            const MCExpr *&Offset,
63                            bool &OffsetIsReg,
64                            int &OffsetRegNum,
65                            SMLoc &E);
66  bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
67  bool ParseDirectiveWord(unsigned Size, SMLoc L);
68  bool ParseDirectiveThumb(SMLoc L);
69  bool ParseDirectiveThumbFunc(SMLoc L);
70  bool ParseDirectiveCode(SMLoc L);
71  bool ParseDirectiveSyntax(SMLoc L);
72
73  bool MatchAndEmitInstruction(SMLoc IDLoc,
74                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
75                               MCStreamer &Out);
76
77  /// @name Auto-generated Match Functions
78  /// {
79
80#define GET_ASSEMBLER_HEADER
81#include "ARMGenAsmMatcher.inc"
82
83  /// }
84
85public:
86  ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
87    : TargetAsmParser(T), Parser(_Parser), TM(_TM) {
88      // Initialize the set of available features.
89      setAvailableFeatures(ComputeAvailableFeatures(
90          &TM.getSubtarget<ARMSubtarget>()));
91    }
92
93  virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
94                                SmallVectorImpl<MCParsedAsmOperand*> &Operands);
95  virtual bool ParseDirective(AsmToken DirectiveID);
96};
97} // end anonymous namespace
98
99namespace {
100
101/// ARMOperand - Instances of this class represent a parsed ARM machine
102/// instruction.
103class ARMOperand : public MCParsedAsmOperand {
104  enum KindTy {
105    CondCode,
106    Immediate,
107    Memory,
108    Register,
109    RegisterList,
110    DPRRegisterList,
111    SPRRegisterList,
112    Token
113  } Kind;
114
115  SMLoc StartLoc, EndLoc;
116  SmallVector<unsigned, 8> Registers;
117
118  union {
119    struct {
120      ARMCC::CondCodes Val;
121    } CC;
122
123    struct {
124      const char *Data;
125      unsigned Length;
126    } Tok;
127
128    struct {
129      unsigned RegNum;
130    } Reg;
131
132    struct {
133      const MCExpr *Val;
134    } Imm;
135
136    // This is for all forms of ARM address expressions
137    struct {
138      unsigned BaseRegNum;
139      unsigned OffsetRegNum;         // used when OffsetIsReg is true
140      const MCExpr *Offset;          // used when OffsetIsReg is false
141      const MCExpr *ShiftAmount;     // used when OffsetRegShifted is true
142      enum ShiftType ShiftType;      // used when OffsetRegShifted is true
143      unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true
144      unsigned Preindexed       : 1;
145      unsigned Postindexed      : 1;
146      unsigned OffsetIsReg      : 1;
147      unsigned Negative         : 1; // only used when OffsetIsReg is true
148      unsigned Writeback        : 1;
149    } Mem;
150  };
151
152  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
153public:
154  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
155    Kind = o.Kind;
156    StartLoc = o.StartLoc;
157    EndLoc = o.EndLoc;
158    switch (Kind) {
159    case CondCode:
160      CC = o.CC;
161      break;
162    case Token:
163      Tok = o.Tok;
164      break;
165    case Register:
166      Reg = o.Reg;
167      break;
168    case RegisterList:
169    case DPRRegisterList:
170    case SPRRegisterList:
171      Registers = o.Registers;
172      break;
173    case Immediate:
174      Imm = o.Imm;
175      break;
176    case Memory:
177      Mem = o.Mem;
178      break;
179    }
180  }
181
182  /// getStartLoc - Get the location of the first token of this operand.
183  SMLoc getStartLoc() const { return StartLoc; }
184  /// getEndLoc - Get the location of the last token of this operand.
185  SMLoc getEndLoc() const { return EndLoc; }
186
187  ARMCC::CondCodes getCondCode() const {
188    assert(Kind == CondCode && "Invalid access!");
189    return CC.Val;
190  }
191
192  StringRef getToken() const {
193    assert(Kind == Token && "Invalid access!");
194    return StringRef(Tok.Data, Tok.Length);
195  }
196
197  unsigned getReg() const {
198    assert(Kind == Register && "Invalid access!");
199    return Reg.RegNum;
200  }
201
202  const SmallVectorImpl<unsigned> &getRegList() const {
203    assert((Kind == RegisterList || Kind == DPRRegisterList ||
204            Kind == SPRRegisterList) && "Invalid access!");
205    return Registers;
206  }
207
208  const MCExpr *getImm() const {
209    assert(Kind == Immediate && "Invalid access!");
210    return Imm.Val;
211  }
212
213  bool isCondCode() const { return Kind == CondCode; }
214  bool isImm() const { return Kind == Immediate; }
215  bool isReg() const { return Kind == Register; }
216  bool isRegList() const { return Kind == RegisterList; }
217  bool isDPRRegList() const { return Kind == DPRRegisterList; }
218  bool isSPRRegList() const { return Kind == SPRRegisterList; }
219  bool isToken() const { return Kind == Token; }
220  bool isMemory() const { return Kind == Memory; }
221  bool isMemMode5() const {
222    if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted ||
223        Mem.Writeback || Mem.Negative)
224      return false;
225
226    // If there is an offset expression, make sure it's valid.
227    if (!Mem.Offset) return true;
228
229    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
230    if (!CE) return false;
231
232    // The offset must be a multiple of 4 in the range 0-1020.
233    int64_t Value = CE->getValue();
234    return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
235  }
236  bool isMemModeThumb() const {
237    if (!isMemory() || (!Mem.OffsetIsReg && !Mem.Offset) || Mem.Writeback)
238      return false;
239
240    if (!Mem.Offset) return true;
241
242    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
243    if (!CE) return false;
244
245    // The offset must be a multiple of 4 in the range 0-124.
246    uint64_t Value = CE->getValue();
247    return ((Value & 0x3) == 0 && Value <= 124);
248  }
249
250  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
251    // Add as immediates when possible.  Null MCExpr = 0.
252    if (Expr == 0)
253      Inst.addOperand(MCOperand::CreateImm(0));
254    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
255      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
256    else
257      Inst.addOperand(MCOperand::CreateExpr(Expr));
258  }
259
260  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
261    assert(N == 2 && "Invalid number of operands!");
262    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
263    // FIXME: What belongs here?
264    Inst.addOperand(MCOperand::CreateReg(0));
265  }
266
267  void addRegOperands(MCInst &Inst, unsigned N) const {
268    assert(N == 1 && "Invalid number of operands!");
269    Inst.addOperand(MCOperand::CreateReg(getReg()));
270  }
271
272  void addRegListOperands(MCInst &Inst, unsigned N) const {
273    assert(N == 1 && "Invalid number of operands!");
274    const SmallVectorImpl<unsigned> &RegList = getRegList();
275    for (SmallVectorImpl<unsigned>::const_iterator
276           I = RegList.begin(), E = RegList.end(); I != E; ++I)
277      Inst.addOperand(MCOperand::CreateReg(*I));
278  }
279
280  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
281    addRegListOperands(Inst, N);
282  }
283
284  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
285    addRegListOperands(Inst, N);
286  }
287
288  void addImmOperands(MCInst &Inst, unsigned N) const {
289    assert(N == 1 && "Invalid number of operands!");
290    addExpr(Inst, getImm());
291  }
292
293  void addMemMode5Operands(MCInst &Inst, unsigned N) const {
294    assert(N == 2 && isMemMode5() && "Invalid number of operands!");
295
296    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
297    assert(!Mem.OffsetIsReg && "Invalid mode 5 operand");
298
299    // FIXME: #-0 is encoded differently than #0. Does the parser preserve
300    // the difference?
301    if (Mem.Offset) {
302      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
303      assert(CE && "Non-constant mode 5 offset operand!");
304
305      // The MCInst offset operand doesn't include the low two bits (like
306      // the instruction encoding).
307      int64_t Offset = CE->getValue() / 4;
308      if (Offset >= 0)
309        Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
310                                                               Offset)));
311      else
312        Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
313                                                               -Offset)));
314    } else {
315      Inst.addOperand(MCOperand::CreateImm(0));
316    }
317  }
318
319  void addMemModeThumbOperands(MCInst &Inst, unsigned N) const {
320    assert(N == 3 && isMemModeThumb() && "Invalid number of operands!");
321    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
322
323    if (Mem.Offset) {
324      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
325      assert(CE && "Non-constant mode offset operand!");
326      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
327      Inst.addOperand(MCOperand::CreateReg(0));
328    } else {
329      Inst.addOperand(MCOperand::CreateImm(0));
330      Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
331    }
332  }
333
334  virtual void dump(raw_ostream &OS) const;
335
336  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
337    ARMOperand *Op = new ARMOperand(CondCode);
338    Op->CC.Val = CC;
339    Op->StartLoc = S;
340    Op->EndLoc = S;
341    return Op;
342  }
343
344  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
345    ARMOperand *Op = new ARMOperand(Token);
346    Op->Tok.Data = Str.data();
347    Op->Tok.Length = Str.size();
348    Op->StartLoc = S;
349    Op->EndLoc = S;
350    return Op;
351  }
352
353  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
354    ARMOperand *Op = new ARMOperand(Register);
355    Op->Reg.RegNum = RegNum;
356    Op->StartLoc = S;
357    Op->EndLoc = E;
358    return Op;
359  }
360
361  static ARMOperand *
362  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
363                SMLoc StartLoc, SMLoc EndLoc) {
364    KindTy Kind = RegisterList;
365
366    if (ARM::DPRRegClass.contains(Regs.front().first))
367      Kind = DPRRegisterList;
368    else if (ARM::SPRRegClass.contains(Regs.front().first))
369      Kind = SPRRegisterList;
370
371    ARMOperand *Op = new ARMOperand(Kind);
372    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
373           I = Regs.begin(), E = Regs.end(); I != E; ++I)
374      Op->Registers.push_back(I->first);
375    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
376    Op->StartLoc = StartLoc;
377    Op->EndLoc = EndLoc;
378    return Op;
379  }
380
381  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
382    ARMOperand *Op = new ARMOperand(Immediate);
383    Op->Imm.Val = Val;
384    Op->StartLoc = S;
385    Op->EndLoc = E;
386    return Op;
387  }
388
389  static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
390                               const MCExpr *Offset, unsigned OffsetRegNum,
391                               bool OffsetRegShifted, enum ShiftType ShiftType,
392                               const MCExpr *ShiftAmount, bool Preindexed,
393                               bool Postindexed, bool Negative, bool Writeback,
394                               SMLoc S, SMLoc E) {
395    ARMOperand *Op = new ARMOperand(Memory);
396    Op->Mem.BaseRegNum = BaseRegNum;
397    Op->Mem.OffsetIsReg = OffsetIsReg;
398    Op->Mem.Offset = Offset;
399    Op->Mem.OffsetRegNum = OffsetRegNum;
400    Op->Mem.OffsetRegShifted = OffsetRegShifted;
401    Op->Mem.ShiftType = ShiftType;
402    Op->Mem.ShiftAmount = ShiftAmount;
403    Op->Mem.Preindexed = Preindexed;
404    Op->Mem.Postindexed = Postindexed;
405    Op->Mem.Negative = Negative;
406    Op->Mem.Writeback = Writeback;
407
408    Op->StartLoc = S;
409    Op->EndLoc = E;
410    return Op;
411  }
412};
413
414} // end anonymous namespace.
415
416void ARMOperand::dump(raw_ostream &OS) const {
417  switch (Kind) {
418  case CondCode:
419    OS << ARMCondCodeToString(getCondCode());
420    break;
421  case Immediate:
422    getImm()->print(OS);
423    break;
424  case Memory:
425    OS << "<memory>";
426    break;
427  case Register:
428    OS << "<register " << getReg() << ">";
429    break;
430  case RegisterList:
431  case DPRRegisterList:
432  case SPRRegisterList: {
433    OS << "<register_list ";
434
435    const SmallVectorImpl<unsigned> &RegList = getRegList();
436    for (SmallVectorImpl<unsigned>::const_iterator
437           I = RegList.begin(), E = RegList.end(); I != E; ) {
438      OS << *I;
439      if (++I < E) OS << ", ";
440    }
441
442    OS << ">";
443    break;
444  }
445  case Token:
446    OS << "'" << getToken() << "'";
447    break;
448  }
449}
450
451/// @name Auto-generated Match Functions
452/// {
453
454static unsigned MatchRegisterName(StringRef Name);
455
456/// }
457
458/// Try to parse a register name.  The token must be an Identifier when called,
459/// and if it is a register name the token is eaten and the register number is
460/// returned.  Otherwise return -1.
461///
462int ARMAsmParser::TryParseRegister() {
463  const AsmToken &Tok = Parser.getTok();
464  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
465
466  // FIXME: Validate register for the current architecture; we have to do
467  // validation later, so maybe there is no need for this here.
468  unsigned RegNum = MatchRegisterName(Tok.getString());
469  if (RegNum == 0)
470    return -1;
471  Parser.Lex(); // Eat identifier token.
472  return RegNum;
473}
474
475
476/// Try to parse a register name.  The token must be an Identifier when called.
477/// If it's a register, an AsmOperand is created. Another AsmOperand is created
478/// if there is a "writeback". 'true' if it's not a register.
479///
480/// TODO this is likely to change to allow different register types and or to
481/// parse for a specific register type.
482bool ARMAsmParser::
483TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
484  SMLoc S = Parser.getTok().getLoc();
485  int RegNo = TryParseRegister();
486  if (RegNo == -1)
487    return true;
488
489  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
490
491  const AsmToken &ExclaimTok = Parser.getTok();
492  if (ExclaimTok.is(AsmToken::Exclaim)) {
493    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
494                                               ExclaimTok.getLoc()));
495    Parser.Lex(); // Eat exclaim token
496  }
497
498  return false;
499}
500
501/// Parse a register list, return it if successful else return null.  The first
502/// token must be a '{' when called.
503bool ARMAsmParser::
504ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
505  assert(Parser.getTok().is(AsmToken::LCurly) &&
506         "Token is not a Left Curly Brace");
507  SMLoc S = Parser.getTok().getLoc();
508
509  // Read the rest of the registers in the list.
510  unsigned PrevRegNum = 0;
511  SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
512
513  do {
514    bool IsRange = Parser.getTok().is(AsmToken::Minus);
515    Parser.Lex(); // Eat non-identifier token.
516
517    const AsmToken &RegTok = Parser.getTok();
518    SMLoc RegLoc = RegTok.getLoc();
519    if (RegTok.isNot(AsmToken::Identifier)) {
520      Error(RegLoc, "register expected");
521      return true;
522    }
523
524    int RegNum = TryParseRegister();
525    if (RegNum == -1) {
526      Error(RegLoc, "register expected");
527      return true;
528    }
529
530    if (IsRange) {
531      int Reg = PrevRegNum;
532      do {
533        ++Reg;
534        Registers.push_back(std::make_pair(Reg, RegLoc));
535      } while (Reg != RegNum);
536    } else {
537      Registers.push_back(std::make_pair(RegNum, RegLoc));
538    }
539
540    PrevRegNum = RegNum;
541  } while (Parser.getTok().is(AsmToken::Comma) ||
542           Parser.getTok().is(AsmToken::Minus));
543
544  // Process the right curly brace of the list.
545  const AsmToken &RCurlyTok = Parser.getTok();
546  if (RCurlyTok.isNot(AsmToken::RCurly)) {
547    Error(RCurlyTok.getLoc(), "'}' expected");
548    return true;
549  }
550
551  SMLoc E = RCurlyTok.getLoc();
552  Parser.Lex(); // Eat right curly brace token.
553
554  // Verify the register list.
555  SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
556    RI = Registers.begin(), RE = Registers.end();
557
558  DenseMap<unsigned, bool> RegMap;
559  RegMap[RI->first] = true;
560
561  unsigned HighRegNum = RI->first;
562  bool EmittedWarning = false;
563
564  for (++RI; RI != RE; ++RI) {
565    const std::pair<unsigned, SMLoc> &RegInfo = *RI;
566    unsigned Reg = RegInfo.first;
567
568    if (RegMap[Reg]) {
569      Error(RegInfo.second, "register duplicated in register list");
570      return true;
571    }
572
573    if (!EmittedWarning && Reg < HighRegNum)
574      Warning(RegInfo.second,
575              "register not in ascending order in register list");
576
577    RegMap[Reg] = true;
578    HighRegNum = std::max(Reg, HighRegNum);
579  }
580
581  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
582  return false;
583}
584
585/// Parse an ARM memory expression, return false if successful else return true
586/// or an error.  The first token must be a '[' when called.
587///
588/// TODO Only preindexing and postindexing addressing are started, unindexed
589/// with option, etc are still to do.
590bool ARMAsmParser::
591ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
592  SMLoc S, E;
593  assert(Parser.getTok().is(AsmToken::LBrac) &&
594         "Token is not a Left Bracket");
595  S = Parser.getTok().getLoc();
596  Parser.Lex(); // Eat left bracket token.
597
598  const AsmToken &BaseRegTok = Parser.getTok();
599  if (BaseRegTok.isNot(AsmToken::Identifier)) {
600    Error(BaseRegTok.getLoc(), "register expected");
601    return true;
602  }
603  int BaseRegNum = TryParseRegister();
604  if (BaseRegNum == -1) {
605    Error(BaseRegTok.getLoc(), "register expected");
606    return true;
607  }
608
609  bool Preindexed = false;
610  bool Postindexed = false;
611  bool OffsetIsReg = false;
612  bool Negative = false;
613  bool Writeback = false;
614
615  // First look for preindexed address forms, that is after the "[Rn" we now
616  // have to see if the next token is a comma.
617  const AsmToken &Tok = Parser.getTok();
618  if (Tok.is(AsmToken::Comma)) {
619    Preindexed = true;
620    Parser.Lex(); // Eat comma token.
621    int OffsetRegNum;
622    bool OffsetRegShifted;
623    enum ShiftType ShiftType;
624    const MCExpr *ShiftAmount = 0;
625    const MCExpr *Offset = 0;
626    if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
627                             Offset, OffsetIsReg, OffsetRegNum, E))
628      return true;
629    const AsmToken &RBracTok = Parser.getTok();
630    if (RBracTok.isNot(AsmToken::RBrac)) {
631      Error(RBracTok.getLoc(), "']' expected");
632      return true;
633    }
634    E = RBracTok.getLoc();
635    Parser.Lex(); // Eat right bracket token.
636
637
638    const AsmToken &ExclaimTok = Parser.getTok();
639    ARMOperand *WBOp = 0;
640    if (ExclaimTok.is(AsmToken::Exclaim)) {
641      WBOp = ARMOperand::CreateToken(ExclaimTok.getString(),
642                                     ExclaimTok.getLoc());
643      Writeback = true;
644      Parser.Lex(); // Eat exclaim token
645    }
646
647    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,
648                                             OffsetRegNum, OffsetRegShifted,
649                                             ShiftType, ShiftAmount, Preindexed,
650                                             Postindexed, Negative, Writeback,
651                                             S, E));
652    if (WBOp)
653      Operands.push_back(WBOp);
654
655    return false;
656  }
657  // The "[Rn" we have so far was not followed by a comma.
658  else if (Tok.is(AsmToken::RBrac)) {
659    // If there's anything other than the right brace, this is a post indexing
660    // addressing form.
661    E = Tok.getLoc();
662    Parser.Lex(); // Eat right bracket token.
663
664    int OffsetRegNum = 0;
665    bool OffsetRegShifted = false;
666    enum ShiftType ShiftType = Lsl;
667    const MCExpr *ShiftAmount = 0;
668    const MCExpr *Offset = 0;
669
670    const AsmToken &NextTok = Parser.getTok();
671
672    if (NextTok.isNot(AsmToken::EndOfStatement)) {
673      Postindexed = true;
674      Writeback = true;
675
676      if (NextTok.isNot(AsmToken::Comma)) {
677        Error(NextTok.getLoc(), "',' expected");
678        return true;
679      }
680
681      Parser.Lex(); // Eat comma token.
682
683      if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
684                               ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
685                               E))
686        return true;
687    }
688
689    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,
690                                             OffsetRegNum, OffsetRegShifted,
691                                             ShiftType, ShiftAmount, Preindexed,
692                                             Postindexed, Negative, Writeback,
693                                             S, E));
694    return false;
695  }
696
697  return true;
698}
699
700/// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
701/// we will parse the following (were +/- means that a plus or minus is
702/// optional):
703///   +/-Rm
704///   +/-Rm, shift
705///   #offset
706/// we return false on success or an error otherwise.
707bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
708                                        bool &OffsetRegShifted,
709                                        enum ShiftType &ShiftType,
710                                        const MCExpr *&ShiftAmount,
711                                        const MCExpr *&Offset,
712                                        bool &OffsetIsReg,
713                                        int &OffsetRegNum,
714                                        SMLoc &E) {
715  Negative = false;
716  OffsetRegShifted = false;
717  OffsetIsReg = false;
718  OffsetRegNum = -1;
719  const AsmToken &NextTok = Parser.getTok();
720  E = NextTok.getLoc();
721  if (NextTok.is(AsmToken::Plus))
722    Parser.Lex(); // Eat plus token.
723  else if (NextTok.is(AsmToken::Minus)) {
724    Negative = true;
725    Parser.Lex(); // Eat minus token
726  }
727  // See if there is a register following the "[Rn," or "[Rn]," we have so far.
728  const AsmToken &OffsetRegTok = Parser.getTok();
729  if (OffsetRegTok.is(AsmToken::Identifier)) {
730    SMLoc CurLoc = OffsetRegTok.getLoc();
731    OffsetRegNum = TryParseRegister();
732    if (OffsetRegNum != -1) {
733      OffsetIsReg = true;
734      E = CurLoc;
735    }
736  }
737
738  // If we parsed a register as the offset then there can be a shift after that.
739  if (OffsetRegNum != -1) {
740    // Look for a comma then a shift
741    const AsmToken &Tok = Parser.getTok();
742    if (Tok.is(AsmToken::Comma)) {
743      Parser.Lex(); // Eat comma token.
744
745      const AsmToken &Tok = Parser.getTok();
746      if (ParseShift(ShiftType, ShiftAmount, E))
747        return Error(Tok.getLoc(), "shift expected");
748      OffsetRegShifted = true;
749    }
750  }
751  else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
752    // Look for #offset following the "[Rn," or "[Rn],"
753    const AsmToken &HashTok = Parser.getTok();
754    if (HashTok.isNot(AsmToken::Hash))
755      return Error(HashTok.getLoc(), "'#' expected");
756
757    Parser.Lex(); // Eat hash token.
758
759    if (getParser().ParseExpression(Offset))
760     return true;
761    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
762  }
763  return false;
764}
765
766/// ParseShift as one of these two:
767///   ( lsl | lsr | asr | ror ) , # shift_amount
768///   rrx
769/// and returns true if it parses a shift otherwise it returns false.
770bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
771                              SMLoc &E) {
772  const AsmToken &Tok = Parser.getTok();
773  if (Tok.isNot(AsmToken::Identifier))
774    return true;
775  StringRef ShiftName = Tok.getString();
776  if (ShiftName == "lsl" || ShiftName == "LSL")
777    St = Lsl;
778  else if (ShiftName == "lsr" || ShiftName == "LSR")
779    St = Lsr;
780  else if (ShiftName == "asr" || ShiftName == "ASR")
781    St = Asr;
782  else if (ShiftName == "ror" || ShiftName == "ROR")
783    St = Ror;
784  else if (ShiftName == "rrx" || ShiftName == "RRX")
785    St = Rrx;
786  else
787    return true;
788  Parser.Lex(); // Eat shift type token.
789
790  // Rrx stands alone.
791  if (St == Rrx)
792    return false;
793
794  // Otherwise, there must be a '#' and a shift amount.
795  const AsmToken &HashTok = Parser.getTok();
796  if (HashTok.isNot(AsmToken::Hash))
797    return Error(HashTok.getLoc(), "'#' expected");
798  Parser.Lex(); // Eat hash token.
799
800  if (getParser().ParseExpression(ShiftAmount))
801    return true;
802
803  return false;
804}
805
806/// Parse a arm instruction operand.  For now this parses the operand regardless
807/// of the mnemonic.
808bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands){
809  SMLoc S, E;
810  switch (getLexer().getKind()) {
811  default:
812    Error(Parser.getTok().getLoc(), "unexpected token in operand");
813    return true;
814  case AsmToken::Identifier: {
815    if (!TryParseRegisterWithWriteBack(Operands))
816      return false;
817
818    // This was not a register so parse other operands that start with an
819    // identifier (like labels) as expressions and create them as immediates.
820    const MCExpr *IdVal;
821    S = Parser.getTok().getLoc();
822    if (getParser().ParseExpression(IdVal))
823      return true;
824    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
825    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
826    return false;
827  }
828  case AsmToken::LBrac:
829    return ParseMemory(Operands);
830  case AsmToken::LCurly:
831    return ParseRegisterList(Operands);
832  case AsmToken::Hash:
833    // #42 -> immediate.
834    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
835    S = Parser.getTok().getLoc();
836    Parser.Lex();
837    const MCExpr *ImmVal;
838    if (getParser().ParseExpression(ImmVal))
839      return true;
840    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
841    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
842    return false;
843  }
844}
845
846/// Parse an arm instruction mnemonic followed by its operands.
847bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
848                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
849  // Create the leading tokens for the mnemonic, split by '.' characters.
850  size_t Start = 0, Next = Name.find('.');
851  StringRef Head = Name.slice(Start, Next);
852
853  // Determine the predicate, if any.
854  //
855  // FIXME: We need a way to check whether a prefix supports predication,
856  // otherwise we will end up with an ambiguity for instructions that happen to
857  // end with a predicate name.
858  // FIXME: Likewise, some arithmetic instructions have an 's' prefix which
859  // indicates to update the condition codes. Those instructions have an
860  // additional immediate operand which encodes the prefix as reg0 or CPSR.
861  // Just checking for a suffix of 's' definitely creates ambiguities; e.g,
862  // the SMMLS instruction.
863  unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
864    .Case("eq", ARMCC::EQ)
865    .Case("ne", ARMCC::NE)
866    .Case("hs", ARMCC::HS)
867    .Case("lo", ARMCC::LO)
868    .Case("mi", ARMCC::MI)
869    .Case("pl", ARMCC::PL)
870    .Case("vs", ARMCC::VS)
871    .Case("vc", ARMCC::VC)
872    .Case("hi", ARMCC::HI)
873    .Case("ls", ARMCC::LS)
874    .Case("ge", ARMCC::GE)
875    .Case("lt", ARMCC::LT)
876    .Case("gt", ARMCC::GT)
877    .Case("le", ARMCC::LE)
878    .Case("al", ARMCC::AL)
879    .Default(~0U);
880
881  if (CC == ~0U ||
882      (CC == ARMCC::LS && (Head == "vmls" || Head == "vnmls"))) {
883    CC = ARMCC::AL;
884  } else {
885    Head = Head.slice(0, Head.size() - 2);
886  }
887
888  Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
889
890  if (Head != "trap")
891    // FIXME: Should only add this operand for predicated instructions
892    Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC),
893                                                  NameLoc));
894
895  // Add the remaining tokens in the mnemonic.
896  while (Next != StringRef::npos) {
897    Start = Next;
898    Next = Name.find('.', Start + 1);
899    Head = Name.slice(Start, Next);
900
901    Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
902  }
903
904  // Read the remaining operands.
905  if (getLexer().isNot(AsmToken::EndOfStatement)) {
906    // Read the first operand.
907    if (ParseOperand(Operands)) {
908      Parser.EatToEndOfStatement();
909      return true;
910    }
911
912    while (getLexer().is(AsmToken::Comma)) {
913      Parser.Lex();  // Eat the comma.
914
915      // Parse and remember the operand.
916      if (ParseOperand(Operands)) {
917        Parser.EatToEndOfStatement();
918        return true;
919      }
920    }
921  }
922
923  if (getLexer().isNot(AsmToken::EndOfStatement)) {
924    Parser.EatToEndOfStatement();
925    return TokError("unexpected token in argument list");
926  }
927
928  Parser.Lex(); // Consume the EndOfStatement
929  return false;
930}
931
932bool ARMAsmParser::
933MatchAndEmitInstruction(SMLoc IDLoc,
934                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
935                        MCStreamer &Out) {
936  MCInst Inst;
937  unsigned ErrorInfo;
938  switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) {
939  case Match_Success:
940    Out.EmitInstruction(Inst);
941    return false;
942  case Match_MissingFeature:
943    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
944    return true;
945  case Match_InvalidOperand: {
946    SMLoc ErrorLoc = IDLoc;
947    if (ErrorInfo != ~0U) {
948      if (ErrorInfo >= Operands.size())
949        return Error(IDLoc, "too few operands for instruction");
950
951      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
952      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
953    }
954
955    return Error(ErrorLoc, "invalid operand for instruction");
956  }
957  case Match_MnemonicFail:
958    return Error(IDLoc, "unrecognized instruction mnemonic");
959  }
960
961  llvm_unreachable("Implement any new match types added!");
962  return true;
963}
964
965/// ParseDirective parses the arm specific directives
966bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
967  StringRef IDVal = DirectiveID.getIdentifier();
968  if (IDVal == ".word")
969    return ParseDirectiveWord(4, DirectiveID.getLoc());
970  else if (IDVal == ".thumb")
971    return ParseDirectiveThumb(DirectiveID.getLoc());
972  else if (IDVal == ".thumb_func")
973    return ParseDirectiveThumbFunc(DirectiveID.getLoc());
974  else if (IDVal == ".code")
975    return ParseDirectiveCode(DirectiveID.getLoc());
976  else if (IDVal == ".syntax")
977    return ParseDirectiveSyntax(DirectiveID.getLoc());
978  return true;
979}
980
981/// ParseDirectiveWord
982///  ::= .word [ expression (, expression)* ]
983bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
984  if (getLexer().isNot(AsmToken::EndOfStatement)) {
985    for (;;) {
986      const MCExpr *Value;
987      if (getParser().ParseExpression(Value))
988        return true;
989
990      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
991
992      if (getLexer().is(AsmToken::EndOfStatement))
993        break;
994
995      // FIXME: Improve diagnostic.
996      if (getLexer().isNot(AsmToken::Comma))
997        return Error(L, "unexpected token in directive");
998      Parser.Lex();
999    }
1000  }
1001
1002  Parser.Lex();
1003  return false;
1004}
1005
1006/// ParseDirectiveThumb
1007///  ::= .thumb
1008bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
1009  if (getLexer().isNot(AsmToken::EndOfStatement))
1010    return Error(L, "unexpected token in directive");
1011  Parser.Lex();
1012
1013  // TODO: set thumb mode
1014  // TODO: tell the MC streamer the mode
1015  // getParser().getStreamer().Emit???();
1016  return false;
1017}
1018
1019/// ParseDirectiveThumbFunc
1020///  ::= .thumbfunc symbol_name
1021bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
1022  const AsmToken &Tok = Parser.getTok();
1023  if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
1024    return Error(L, "unexpected token in .thumb_func directive");
1025  StringRef Name = Tok.getString();
1026  Parser.Lex(); // Consume the identifier token.
1027  if (getLexer().isNot(AsmToken::EndOfStatement))
1028    return Error(L, "unexpected token in directive");
1029  Parser.Lex();
1030
1031  // Mark symbol as a thumb symbol.
1032  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
1033  getParser().getStreamer().EmitThumbFunc(Func);
1034  return false;
1035}
1036
1037/// ParseDirectiveSyntax
1038///  ::= .syntax unified | divided
1039bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
1040  const AsmToken &Tok = Parser.getTok();
1041  if (Tok.isNot(AsmToken::Identifier))
1042    return Error(L, "unexpected token in .syntax directive");
1043  StringRef Mode = Tok.getString();
1044  if (Mode == "unified" || Mode == "UNIFIED")
1045    Parser.Lex();
1046  else if (Mode == "divided" || Mode == "DIVIDED")
1047    Parser.Lex();
1048  else
1049    return Error(L, "unrecognized syntax mode in .syntax directive");
1050
1051  if (getLexer().isNot(AsmToken::EndOfStatement))
1052    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
1053  Parser.Lex();
1054
1055  // TODO tell the MC streamer the mode
1056  // getParser().getStreamer().Emit???();
1057  return false;
1058}
1059
1060/// ParseDirectiveCode
1061///  ::= .code 16 | 32
1062bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
1063  const AsmToken &Tok = Parser.getTok();
1064  if (Tok.isNot(AsmToken::Integer))
1065    return Error(L, "unexpected token in .code directive");
1066  int64_t Val = Parser.getTok().getIntVal();
1067  if (Val == 16)
1068    Parser.Lex();
1069  else if (Val == 32)
1070    Parser.Lex();
1071  else
1072    return Error(L, "invalid operand to .code directive");
1073
1074  if (getLexer().isNot(AsmToken::EndOfStatement))
1075    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
1076  Parser.Lex();
1077
1078  if (Val == 16)
1079    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
1080  else
1081    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
1082
1083  return false;
1084}
1085
1086extern "C" void LLVMInitializeARMAsmLexer();
1087
1088/// Force static initialization.
1089extern "C" void LLVMInitializeARMAsmParser() {
1090  RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
1091  RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
1092  LLVMInitializeARMAsmLexer();
1093}
1094
1095#define GET_REGISTER_MATCHER
1096#define GET_MATCHER_IMPLEMENTATION
1097#include "ARMGenAsmMatcher.inc"
1098