ARMAsmParser.cpp revision 22685876ed7231f32f7d1698c00acab22825b74c 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/MCTargetAsmParser.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/SourceMgr.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/ADT/BitVector.h"
30#include "llvm/ADT/OwningPtr.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/StringSwitch.h"
34#include "llvm/ADT/Twine.h"
35
36using namespace llvm;
37
38namespace {
39
40class ARMOperand;
41
42enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
43
44class ARMAsmParser : public MCTargetAsmParser {
45  MCSubtargetInfo &STI;
46  MCAsmParser &Parser;
47  const MCRegisterInfo *MRI;
48
49  // Map of register aliases registers via the .req directive.
50  StringMap<unsigned> RegisterReqs;
51
52  struct {
53    ARMCC::CondCodes Cond;    // Condition for IT block.
54    unsigned Mask:4;          // Condition mask for instructions.
55                              // Starting at first 1 (from lsb).
56                              //   '1'  condition as indicated in IT.
57                              //   '0'  inverse of condition (else).
58                              // Count of instructions in IT block is
59                              // 4 - trailingzeroes(mask)
60
61    bool FirstCond;           // Explicit flag for when we're parsing the
62                              // First instruction in the IT block. It's
63                              // implied in the mask, so needs special
64                              // handling.
65
66    unsigned CurPosition;     // Current position in parsing of IT
67                              // block. In range [0,3]. Initialized
68                              // according to count of instructions in block.
69                              // ~0U if no active IT block.
70  } ITState;
71  bool inITBlock() { return ITState.CurPosition != ~0U;}
72  void forwardITPosition() {
73    if (!inITBlock()) return;
74    // Move to the next instruction in the IT block, if there is one. If not,
75    // mark the block as done.
76    unsigned TZ = CountTrailingZeros_32(ITState.Mask);
77    if (++ITState.CurPosition == 5 - TZ)
78      ITState.CurPosition = ~0U; // Done with the IT block after this.
79  }
80
81
82  MCAsmParser &getParser() const { return Parser; }
83  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
84
85  bool Warning(SMLoc L, const Twine &Msg,
86               ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
87    return Parser.Warning(L, Msg, Ranges);
88  }
89  bool Error(SMLoc L, const Twine &Msg,
90             ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
91    return Parser.Error(L, Msg, Ranges);
92  }
93
94  int tryParseRegister();
95  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
96  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
97  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
98  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
99  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
100  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
101  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
102                              unsigned &ShiftAmount);
103  bool parseDirectiveWord(unsigned Size, SMLoc L);
104  bool parseDirectiveThumb(SMLoc L);
105  bool parseDirectiveARM(SMLoc L);
106  bool parseDirectiveThumbFunc(SMLoc L);
107  bool parseDirectiveCode(SMLoc L);
108  bool parseDirectiveSyntax(SMLoc L);
109  bool parseDirectiveReq(StringRef Name, SMLoc L);
110  bool parseDirectiveUnreq(SMLoc L);
111  bool parseDirectiveArch(SMLoc L);
112  bool parseDirectiveEabiAttr(SMLoc L);
113
114  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
115                          bool &CarrySetting, unsigned &ProcessorIMod,
116                          StringRef &ITMask);
117  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
118                             bool &CanAcceptPredicationCode);
119
120  bool isThumb() const {
121    // FIXME: Can tablegen auto-generate this?
122    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
123  }
124  bool isThumbOne() const {
125    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
126  }
127  bool isThumbTwo() const {
128    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
129  }
130  bool hasV6Ops() const {
131    return STI.getFeatureBits() & ARM::HasV6Ops;
132  }
133  bool hasV7Ops() const {
134    return STI.getFeatureBits() & ARM::HasV7Ops;
135  }
136  void SwitchMode() {
137    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
138    setAvailableFeatures(FB);
139  }
140  bool isMClass() const {
141    return STI.getFeatureBits() & ARM::FeatureMClass;
142  }
143
144  /// @name Auto-generated Match Functions
145  /// {
146
147#define GET_ASSEMBLER_HEADER
148#include "ARMGenAsmMatcher.inc"
149
150  /// }
151
152  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
153  OperandMatchResultTy parseCoprocNumOperand(
154    SmallVectorImpl<MCParsedAsmOperand*>&);
155  OperandMatchResultTy parseCoprocRegOperand(
156    SmallVectorImpl<MCParsedAsmOperand*>&);
157  OperandMatchResultTy parseCoprocOptionOperand(
158    SmallVectorImpl<MCParsedAsmOperand*>&);
159  OperandMatchResultTy parseMemBarrierOptOperand(
160    SmallVectorImpl<MCParsedAsmOperand*>&);
161  OperandMatchResultTy parseProcIFlagsOperand(
162    SmallVectorImpl<MCParsedAsmOperand*>&);
163  OperandMatchResultTy parseMSRMaskOperand(
164    SmallVectorImpl<MCParsedAsmOperand*>&);
165  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
166                                   StringRef Op, int Low, int High);
167  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
168    return parsePKHImm(O, "lsl", 0, 31);
169  }
170  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
171    return parsePKHImm(O, "asr", 1, 32);
172  }
173  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
174  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
175  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
176  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
177  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
178  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
179  OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
180  OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
181  OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index);
182
183  // Asm Match Converter Methods
184  void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
185  void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
186  void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
187                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
188  void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
189                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
190  void cvtLdWriteBackRegAddrMode2(MCInst &Inst,
191                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
192  void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
193                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
194  void cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
195                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
196  void cvtStWriteBackRegAddrMode2(MCInst &Inst,
197                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
198  void cvtStWriteBackRegAddrMode3(MCInst &Inst,
199                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
200  void cvtLdExtTWriteBackImm(MCInst &Inst,
201                             const SmallVectorImpl<MCParsedAsmOperand*> &);
202  void cvtLdExtTWriteBackReg(MCInst &Inst,
203                             const SmallVectorImpl<MCParsedAsmOperand*> &);
204  void cvtStExtTWriteBackImm(MCInst &Inst,
205                             const SmallVectorImpl<MCParsedAsmOperand*> &);
206  void cvtStExtTWriteBackReg(MCInst &Inst,
207                             const SmallVectorImpl<MCParsedAsmOperand*> &);
208  void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
209  void cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
210  void cvtLdWriteBackRegAddrMode3(MCInst &Inst,
211                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
212  void cvtThumbMultiply(MCInst &Inst,
213                        const SmallVectorImpl<MCParsedAsmOperand*> &);
214  void cvtVLDwbFixed(MCInst &Inst,
215                     const SmallVectorImpl<MCParsedAsmOperand*> &);
216  void cvtVLDwbRegister(MCInst &Inst,
217                        const SmallVectorImpl<MCParsedAsmOperand*> &);
218  void cvtVSTwbFixed(MCInst &Inst,
219                     const SmallVectorImpl<MCParsedAsmOperand*> &);
220  void cvtVSTwbRegister(MCInst &Inst,
221                        const SmallVectorImpl<MCParsedAsmOperand*> &);
222  bool validateInstruction(MCInst &Inst,
223                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
224  bool processInstruction(MCInst &Inst,
225                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
226  bool shouldOmitCCOutOperand(StringRef Mnemonic,
227                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
228
229public:
230  enum ARMMatchResultTy {
231    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
232    Match_RequiresNotITBlock,
233    Match_RequiresV6,
234    Match_RequiresThumb2,
235#define GET_OPERAND_DIAGNOSTIC_TYPES
236#include "ARMGenAsmMatcher.inc"
237
238  };
239
240  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
241    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
242    MCAsmParserExtension::Initialize(_Parser);
243
244    // Cache the MCRegisterInfo.
245    MRI = &getContext().getRegisterInfo();
246
247    // Initialize the set of available features.
248    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
249
250    // Not in an ITBlock to start with.
251    ITState.CurPosition = ~0U;
252  }
253
254  // Implementation of the MCTargetAsmParser interface:
255  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
256  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
257                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
258  bool ParseDirective(AsmToken DirectiveID);
259
260  unsigned checkTargetMatchPredicate(MCInst &Inst);
261
262  bool MatchAndEmitInstruction(SMLoc IDLoc,
263                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
264                               MCStreamer &Out);
265};
266} // end anonymous namespace
267
268namespace {
269
270/// ARMOperand - Instances of this class represent a parsed ARM machine
271/// instruction.
272class ARMOperand : public MCParsedAsmOperand {
273  enum KindTy {
274    k_CondCode,
275    k_CCOut,
276    k_ITCondMask,
277    k_CoprocNum,
278    k_CoprocReg,
279    k_CoprocOption,
280    k_Immediate,
281    k_MemBarrierOpt,
282    k_Memory,
283    k_PostIndexRegister,
284    k_MSRMask,
285    k_ProcIFlags,
286    k_VectorIndex,
287    k_Register,
288    k_RegisterList,
289    k_DPRRegisterList,
290    k_SPRRegisterList,
291    k_VectorList,
292    k_VectorListAllLanes,
293    k_VectorListIndexed,
294    k_ShiftedRegister,
295    k_ShiftedImmediate,
296    k_ShifterImmediate,
297    k_RotateImmediate,
298    k_BitfieldDescriptor,
299    k_Token
300  } Kind;
301
302  SMLoc StartLoc, EndLoc;
303  SmallVector<unsigned, 8> Registers;
304
305  union {
306    struct {
307      ARMCC::CondCodes Val;
308    } CC;
309
310    struct {
311      unsigned Val;
312    } Cop;
313
314    struct {
315      unsigned Val;
316    } CoprocOption;
317
318    struct {
319      unsigned Mask:4;
320    } ITMask;
321
322    struct {
323      ARM_MB::MemBOpt Val;
324    } MBOpt;
325
326    struct {
327      ARM_PROC::IFlags Val;
328    } IFlags;
329
330    struct {
331      unsigned Val;
332    } MMask;
333
334    struct {
335      const char *Data;
336      unsigned Length;
337    } Tok;
338
339    struct {
340      unsigned RegNum;
341    } Reg;
342
343    // A vector register list is a sequential list of 1 to 4 registers.
344    struct {
345      unsigned RegNum;
346      unsigned Count;
347      unsigned LaneIndex;
348      bool isDoubleSpaced;
349    } VectorList;
350
351    struct {
352      unsigned Val;
353    } VectorIndex;
354
355    struct {
356      const MCExpr *Val;
357    } Imm;
358
359    /// Combined record for all forms of ARM address expressions.
360    struct {
361      unsigned BaseRegNum;
362      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
363      // was specified.
364      const MCConstantExpr *OffsetImm;  // Offset immediate value
365      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
366      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
367      unsigned ShiftImm;        // shift for OffsetReg.
368      unsigned Alignment;       // 0 = no alignment specified
369                                // n = alignment in bytes (2, 4, 8, 16, or 32)
370      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
371    } Memory;
372
373    struct {
374      unsigned RegNum;
375      bool isAdd;
376      ARM_AM::ShiftOpc ShiftTy;
377      unsigned ShiftImm;
378    } PostIdxReg;
379
380    struct {
381      bool isASR;
382      unsigned Imm;
383    } ShifterImm;
384    struct {
385      ARM_AM::ShiftOpc ShiftTy;
386      unsigned SrcReg;
387      unsigned ShiftReg;
388      unsigned ShiftImm;
389    } RegShiftedReg;
390    struct {
391      ARM_AM::ShiftOpc ShiftTy;
392      unsigned SrcReg;
393      unsigned ShiftImm;
394    } RegShiftedImm;
395    struct {
396      unsigned Imm;
397    } RotImm;
398    struct {
399      unsigned LSB;
400      unsigned Width;
401    } Bitfield;
402  };
403
404  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
405public:
406  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
407    Kind = o.Kind;
408    StartLoc = o.StartLoc;
409    EndLoc = o.EndLoc;
410    switch (Kind) {
411    case k_CondCode:
412      CC = o.CC;
413      break;
414    case k_ITCondMask:
415      ITMask = o.ITMask;
416      break;
417    case k_Token:
418      Tok = o.Tok;
419      break;
420    case k_CCOut:
421    case k_Register:
422      Reg = o.Reg;
423      break;
424    case k_RegisterList:
425    case k_DPRRegisterList:
426    case k_SPRRegisterList:
427      Registers = o.Registers;
428      break;
429    case k_VectorList:
430    case k_VectorListAllLanes:
431    case k_VectorListIndexed:
432      VectorList = o.VectorList;
433      break;
434    case k_CoprocNum:
435    case k_CoprocReg:
436      Cop = o.Cop;
437      break;
438    case k_CoprocOption:
439      CoprocOption = o.CoprocOption;
440      break;
441    case k_Immediate:
442      Imm = o.Imm;
443      break;
444    case k_MemBarrierOpt:
445      MBOpt = o.MBOpt;
446      break;
447    case k_Memory:
448      Memory = o.Memory;
449      break;
450    case k_PostIndexRegister:
451      PostIdxReg = o.PostIdxReg;
452      break;
453    case k_MSRMask:
454      MMask = o.MMask;
455      break;
456    case k_ProcIFlags:
457      IFlags = o.IFlags;
458      break;
459    case k_ShifterImmediate:
460      ShifterImm = o.ShifterImm;
461      break;
462    case k_ShiftedRegister:
463      RegShiftedReg = o.RegShiftedReg;
464      break;
465    case k_ShiftedImmediate:
466      RegShiftedImm = o.RegShiftedImm;
467      break;
468    case k_RotateImmediate:
469      RotImm = o.RotImm;
470      break;
471    case k_BitfieldDescriptor:
472      Bitfield = o.Bitfield;
473      break;
474    case k_VectorIndex:
475      VectorIndex = o.VectorIndex;
476      break;
477    }
478  }
479
480  /// getStartLoc - Get the location of the first token of this operand.
481  SMLoc getStartLoc() const { return StartLoc; }
482  /// getEndLoc - Get the location of the last token of this operand.
483  SMLoc getEndLoc() const { return EndLoc; }
484  /// getLocRange - Get the range between the first and last token of this
485  /// operand.
486  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
487
488  ARMCC::CondCodes getCondCode() const {
489    assert(Kind == k_CondCode && "Invalid access!");
490    return CC.Val;
491  }
492
493  unsigned getCoproc() const {
494    assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
495    return Cop.Val;
496  }
497
498  StringRef getToken() const {
499    assert(Kind == k_Token && "Invalid access!");
500    return StringRef(Tok.Data, Tok.Length);
501  }
502
503  unsigned getReg() const {
504    assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
505    return Reg.RegNum;
506  }
507
508  const SmallVectorImpl<unsigned> &getRegList() const {
509    assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
510            Kind == k_SPRRegisterList) && "Invalid access!");
511    return Registers;
512  }
513
514  const MCExpr *getImm() const {
515    assert(isImm() && "Invalid access!");
516    return Imm.Val;
517  }
518
519  unsigned getVectorIndex() const {
520    assert(Kind == k_VectorIndex && "Invalid access!");
521    return VectorIndex.Val;
522  }
523
524  ARM_MB::MemBOpt getMemBarrierOpt() const {
525    assert(Kind == k_MemBarrierOpt && "Invalid access!");
526    return MBOpt.Val;
527  }
528
529  ARM_PROC::IFlags getProcIFlags() const {
530    assert(Kind == k_ProcIFlags && "Invalid access!");
531    return IFlags.Val;
532  }
533
534  unsigned getMSRMask() const {
535    assert(Kind == k_MSRMask && "Invalid access!");
536    return MMask.Val;
537  }
538
539  bool isCoprocNum() const { return Kind == k_CoprocNum; }
540  bool isCoprocReg() const { return Kind == k_CoprocReg; }
541  bool isCoprocOption() const { return Kind == k_CoprocOption; }
542  bool isCondCode() const { return Kind == k_CondCode; }
543  bool isCCOut() const { return Kind == k_CCOut; }
544  bool isITMask() const { return Kind == k_ITCondMask; }
545  bool isITCondCode() const { return Kind == k_CondCode; }
546  bool isImm() const { return Kind == k_Immediate; }
547  bool isFPImm() const {
548    if (!isImm()) return false;
549    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
550    if (!CE) return false;
551    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
552    return Val != -1;
553  }
554  bool isFBits16() const {
555    if (!isImm()) return false;
556    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
557    if (!CE) return false;
558    int64_t Value = CE->getValue();
559    return Value >= 0 && Value <= 16;
560  }
561  bool isFBits32() const {
562    if (!isImm()) return false;
563    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
564    if (!CE) return false;
565    int64_t Value = CE->getValue();
566    return Value >= 1 && Value <= 32;
567  }
568  bool isImm8s4() const {
569    if (!isImm()) return false;
570    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
571    if (!CE) return false;
572    int64_t Value = CE->getValue();
573    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
574  }
575  bool isImm0_1020s4() const {
576    if (!isImm()) return false;
577    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
578    if (!CE) return false;
579    int64_t Value = CE->getValue();
580    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
581  }
582  bool isImm0_508s4() const {
583    if (!isImm()) return false;
584    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
585    if (!CE) return false;
586    int64_t Value = CE->getValue();
587    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
588  }
589  bool isImm0_508s4Neg() const {
590    if (!isImm()) return false;
591    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
592    if (!CE) return false;
593    int64_t Value = -CE->getValue();
594    // explicitly exclude zero. we want that to use the normal 0_508 version.
595    return ((Value & 3) == 0) && Value > 0 && Value <= 508;
596  }
597  bool isImm0_255() const {
598    if (!isImm()) return false;
599    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
600    if (!CE) return false;
601    int64_t Value = CE->getValue();
602    return Value >= 0 && Value < 256;
603  }
604  bool isImm0_4095() const {
605    if (!isImm()) return false;
606    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
607    if (!CE) return false;
608    int64_t Value = CE->getValue();
609    return Value >= 0 && Value < 4096;
610  }
611  bool isImm0_4095Neg() const {
612    if (!isImm()) return false;
613    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
614    if (!CE) return false;
615    int64_t Value = -CE->getValue();
616    return Value > 0 && Value < 4096;
617  }
618  bool isImm0_1() const {
619    if (!isImm()) return false;
620    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
621    if (!CE) return false;
622    int64_t Value = CE->getValue();
623    return Value >= 0 && Value < 2;
624  }
625  bool isImm0_3() const {
626    if (!isImm()) return false;
627    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
628    if (!CE) return false;
629    int64_t Value = CE->getValue();
630    return Value >= 0 && Value < 4;
631  }
632  bool isImm0_7() const {
633    if (!isImm()) return false;
634    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
635    if (!CE) return false;
636    int64_t Value = CE->getValue();
637    return Value >= 0 && Value < 8;
638  }
639  bool isImm0_15() const {
640    if (!isImm()) return false;
641    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
642    if (!CE) return false;
643    int64_t Value = CE->getValue();
644    return Value >= 0 && Value < 16;
645  }
646  bool isImm0_31() const {
647    if (!isImm()) return false;
648    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
649    if (!CE) return false;
650    int64_t Value = CE->getValue();
651    return Value >= 0 && Value < 32;
652  }
653  bool isImm0_63() const {
654    if (!isImm()) return false;
655    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
656    if (!CE) return false;
657    int64_t Value = CE->getValue();
658    return Value >= 0 && Value < 64;
659  }
660  bool isImm8() const {
661    if (!isImm()) return false;
662    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
663    if (!CE) return false;
664    int64_t Value = CE->getValue();
665    return Value == 8;
666  }
667  bool isImm16() const {
668    if (!isImm()) return false;
669    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
670    if (!CE) return false;
671    int64_t Value = CE->getValue();
672    return Value == 16;
673  }
674  bool isImm32() const {
675    if (!isImm()) return false;
676    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
677    if (!CE) return false;
678    int64_t Value = CE->getValue();
679    return Value == 32;
680  }
681  bool isShrImm8() const {
682    if (!isImm()) return false;
683    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
684    if (!CE) return false;
685    int64_t Value = CE->getValue();
686    return Value > 0 && Value <= 8;
687  }
688  bool isShrImm16() const {
689    if (!isImm()) return false;
690    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
691    if (!CE) return false;
692    int64_t Value = CE->getValue();
693    return Value > 0 && Value <= 16;
694  }
695  bool isShrImm32() const {
696    if (!isImm()) return false;
697    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
698    if (!CE) return false;
699    int64_t Value = CE->getValue();
700    return Value > 0 && Value <= 32;
701  }
702  bool isShrImm64() const {
703    if (!isImm()) return false;
704    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
705    if (!CE) return false;
706    int64_t Value = CE->getValue();
707    return Value > 0 && Value <= 64;
708  }
709  bool isImm1_7() const {
710    if (!isImm()) return false;
711    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
712    if (!CE) return false;
713    int64_t Value = CE->getValue();
714    return Value > 0 && Value < 8;
715  }
716  bool isImm1_15() const {
717    if (!isImm()) return false;
718    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
719    if (!CE) return false;
720    int64_t Value = CE->getValue();
721    return Value > 0 && Value < 16;
722  }
723  bool isImm1_31() const {
724    if (!isImm()) return false;
725    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
726    if (!CE) return false;
727    int64_t Value = CE->getValue();
728    return Value > 0 && Value < 32;
729  }
730  bool isImm1_16() const {
731    if (!isImm()) return false;
732    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
733    if (!CE) return false;
734    int64_t Value = CE->getValue();
735    return Value > 0 && Value < 17;
736  }
737  bool isImm1_32() const {
738    if (!isImm()) return false;
739    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
740    if (!CE) return false;
741    int64_t Value = CE->getValue();
742    return Value > 0 && Value < 33;
743  }
744  bool isImm0_32() const {
745    if (!isImm()) return false;
746    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
747    if (!CE) return false;
748    int64_t Value = CE->getValue();
749    return Value >= 0 && Value < 33;
750  }
751  bool isImm0_65535() const {
752    if (!isImm()) return false;
753    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
754    if (!CE) return false;
755    int64_t Value = CE->getValue();
756    return Value >= 0 && Value < 65536;
757  }
758  bool isImm0_65535Expr() const {
759    if (!isImm()) return false;
760    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
761    // If it's not a constant expression, it'll generate a fixup and be
762    // handled later.
763    if (!CE) return true;
764    int64_t Value = CE->getValue();
765    return Value >= 0 && Value < 65536;
766  }
767  bool isImm24bit() const {
768    if (!isImm()) return false;
769    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
770    if (!CE) return false;
771    int64_t Value = CE->getValue();
772    return Value >= 0 && Value <= 0xffffff;
773  }
774  bool isImmThumbSR() const {
775    if (!isImm()) return false;
776    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
777    if (!CE) return false;
778    int64_t Value = CE->getValue();
779    return Value > 0 && Value < 33;
780  }
781  bool isPKHLSLImm() const {
782    if (!isImm()) return false;
783    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
784    if (!CE) return false;
785    int64_t Value = CE->getValue();
786    return Value >= 0 && Value < 32;
787  }
788  bool isPKHASRImm() const {
789    if (!isImm()) return false;
790    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
791    if (!CE) return false;
792    int64_t Value = CE->getValue();
793    return Value > 0 && Value <= 32;
794  }
795  bool isAdrLabel() const {
796    // If we have an immediate that's not a constant, treat it as a label
797    // reference needing a fixup. If it is a constant, but it can't fit
798    // into shift immediate encoding, we reject it.
799    if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
800    else return (isARMSOImm() || isARMSOImmNeg());
801  }
802  bool isARMSOImm() const {
803    if (!isImm()) return false;
804    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
805    if (!CE) return false;
806    int64_t Value = CE->getValue();
807    return ARM_AM::getSOImmVal(Value) != -1;
808  }
809  bool isARMSOImmNot() const {
810    if (!isImm()) return false;
811    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
812    if (!CE) return false;
813    int64_t Value = CE->getValue();
814    return ARM_AM::getSOImmVal(~Value) != -1;
815  }
816  bool isARMSOImmNeg() const {
817    if (!isImm()) return false;
818    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
819    if (!CE) return false;
820    int64_t Value = CE->getValue();
821    // Only use this when not representable as a plain so_imm.
822    return ARM_AM::getSOImmVal(Value) == -1 &&
823      ARM_AM::getSOImmVal(-Value) != -1;
824  }
825  bool isT2SOImm() const {
826    if (!isImm()) return false;
827    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
828    if (!CE) return false;
829    int64_t Value = CE->getValue();
830    return ARM_AM::getT2SOImmVal(Value) != -1;
831  }
832  bool isT2SOImmNot() const {
833    if (!isImm()) return false;
834    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
835    if (!CE) return false;
836    int64_t Value = CE->getValue();
837    return ARM_AM::getT2SOImmVal(~Value) != -1;
838  }
839  bool isT2SOImmNeg() const {
840    if (!isImm()) return false;
841    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
842    if (!CE) return false;
843    int64_t Value = CE->getValue();
844    // Only use this when not representable as a plain so_imm.
845    return ARM_AM::getT2SOImmVal(Value) == -1 &&
846      ARM_AM::getT2SOImmVal(-Value) != -1;
847  }
848  bool isSetEndImm() const {
849    if (!isImm()) return false;
850    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
851    if (!CE) return false;
852    int64_t Value = CE->getValue();
853    return Value == 1 || Value == 0;
854  }
855  bool isReg() const { return Kind == k_Register; }
856  bool isRegList() const { return Kind == k_RegisterList; }
857  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
858  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
859  bool isToken() const { return Kind == k_Token; }
860  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
861  bool isMem() const { return Kind == k_Memory; }
862  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
863  bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
864  bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
865  bool isRotImm() const { return Kind == k_RotateImmediate; }
866  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
867  bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
868  bool isPostIdxReg() const {
869    return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
870  }
871  bool isMemNoOffset(bool alignOK = false) const {
872    if (!isMem())
873      return false;
874    // No offset of any kind.
875    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
876     (alignOK || Memory.Alignment == 0);
877  }
878  bool isMemPCRelImm12() const {
879    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
880      return false;
881    // Base register must be PC.
882    if (Memory.BaseRegNum != ARM::PC)
883      return false;
884    // Immediate offset in range [-4095, 4095].
885    if (!Memory.OffsetImm) return true;
886    int64_t Val = Memory.OffsetImm->getValue();
887    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
888  }
889  bool isAlignedMemory() const {
890    return isMemNoOffset(true);
891  }
892  bool isAddrMode2() const {
893    if (!isMem() || Memory.Alignment != 0) return false;
894    // Check for register offset.
895    if (Memory.OffsetRegNum) return true;
896    // Immediate offset in range [-4095, 4095].
897    if (!Memory.OffsetImm) return true;
898    int64_t Val = Memory.OffsetImm->getValue();
899    return Val > -4096 && Val < 4096;
900  }
901  bool isAM2OffsetImm() const {
902    if (!isImm()) return false;
903    // Immediate offset in range [-4095, 4095].
904    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
905    if (!CE) return false;
906    int64_t Val = CE->getValue();
907    return Val > -4096 && Val < 4096;
908  }
909  bool isAddrMode3() const {
910    // If we have an immediate that's not a constant, treat it as a label
911    // reference needing a fixup. If it is a constant, it's something else
912    // and we reject it.
913    if (isImm() && !isa<MCConstantExpr>(getImm()))
914      return true;
915    if (!isMem() || Memory.Alignment != 0) return false;
916    // No shifts are legal for AM3.
917    if (Memory.ShiftType != ARM_AM::no_shift) return false;
918    // Check for register offset.
919    if (Memory.OffsetRegNum) return true;
920    // Immediate offset in range [-255, 255].
921    if (!Memory.OffsetImm) return true;
922    int64_t Val = Memory.OffsetImm->getValue();
923    // The #-0 offset is encoded as INT32_MIN, and we have to check
924    // for this too.
925    return (Val > -256 && Val < 256) || Val == INT32_MIN;
926  }
927  bool isAM3Offset() const {
928    if (Kind != k_Immediate && Kind != k_PostIndexRegister)
929      return false;
930    if (Kind == k_PostIndexRegister)
931      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
932    // Immediate offset in range [-255, 255].
933    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
934    if (!CE) return false;
935    int64_t Val = CE->getValue();
936    // Special case, #-0 is INT32_MIN.
937    return (Val > -256 && Val < 256) || Val == INT32_MIN;
938  }
939  bool isAddrMode5() const {
940    // If we have an immediate that's not a constant, treat it as a label
941    // reference needing a fixup. If it is a constant, it's something else
942    // and we reject it.
943    if (isImm() && !isa<MCConstantExpr>(getImm()))
944      return true;
945    if (!isMem() || Memory.Alignment != 0) return false;
946    // Check for register offset.
947    if (Memory.OffsetRegNum) return false;
948    // Immediate offset in range [-1020, 1020] and a multiple of 4.
949    if (!Memory.OffsetImm) return true;
950    int64_t Val = Memory.OffsetImm->getValue();
951    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
952      Val == INT32_MIN;
953  }
954  bool isMemTBB() const {
955    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
956        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
957      return false;
958    return true;
959  }
960  bool isMemTBH() const {
961    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
962        Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
963        Memory.Alignment != 0 )
964      return false;
965    return true;
966  }
967  bool isMemRegOffset() const {
968    if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
969      return false;
970    return true;
971  }
972  bool isT2MemRegOffset() const {
973    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
974        Memory.Alignment != 0)
975      return false;
976    // Only lsl #{0, 1, 2, 3} allowed.
977    if (Memory.ShiftType == ARM_AM::no_shift)
978      return true;
979    if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
980      return false;
981    return true;
982  }
983  bool isMemThumbRR() const {
984    // Thumb reg+reg addressing is simple. Just two registers, a base and
985    // an offset. No shifts, negations or any other complicating factors.
986    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
987        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
988      return false;
989    return isARMLowRegister(Memory.BaseRegNum) &&
990      (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
991  }
992  bool isMemThumbRIs4() const {
993    if (!isMem() || Memory.OffsetRegNum != 0 ||
994        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
995      return false;
996    // Immediate offset, multiple of 4 in range [0, 124].
997    if (!Memory.OffsetImm) return true;
998    int64_t Val = Memory.OffsetImm->getValue();
999    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1000  }
1001  bool isMemThumbRIs2() const {
1002    if (!isMem() || Memory.OffsetRegNum != 0 ||
1003        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1004      return false;
1005    // Immediate offset, multiple of 4 in range [0, 62].
1006    if (!Memory.OffsetImm) return true;
1007    int64_t Val = Memory.OffsetImm->getValue();
1008    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1009  }
1010  bool isMemThumbRIs1() const {
1011    if (!isMem() || Memory.OffsetRegNum != 0 ||
1012        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1013      return false;
1014    // Immediate offset in range [0, 31].
1015    if (!Memory.OffsetImm) return true;
1016    int64_t Val = Memory.OffsetImm->getValue();
1017    return Val >= 0 && Val <= 31;
1018  }
1019  bool isMemThumbSPI() const {
1020    if (!isMem() || Memory.OffsetRegNum != 0 ||
1021        Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1022      return false;
1023    // Immediate offset, multiple of 4 in range [0, 1020].
1024    if (!Memory.OffsetImm) return true;
1025    int64_t Val = Memory.OffsetImm->getValue();
1026    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1027  }
1028  bool isMemImm8s4Offset() const {
1029    // If we have an immediate that's not a constant, treat it as a label
1030    // reference needing a fixup. If it is a constant, it's something else
1031    // and we reject it.
1032    if (isImm() && !isa<MCConstantExpr>(getImm()))
1033      return true;
1034    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1035      return false;
1036    // Immediate offset a multiple of 4 in range [-1020, 1020].
1037    if (!Memory.OffsetImm) return true;
1038    int64_t Val = Memory.OffsetImm->getValue();
1039    // Special case, #-0 is INT32_MIN.
1040    return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1041  }
1042  bool isMemImm0_1020s4Offset() const {
1043    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1044      return false;
1045    // Immediate offset a multiple of 4 in range [0, 1020].
1046    if (!Memory.OffsetImm) return true;
1047    int64_t Val = Memory.OffsetImm->getValue();
1048    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1049  }
1050  bool isMemImm8Offset() const {
1051    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1052      return false;
1053    // Base reg of PC isn't allowed for these encodings.
1054    if (Memory.BaseRegNum == ARM::PC) return false;
1055    // Immediate offset in range [-255, 255].
1056    if (!Memory.OffsetImm) return true;
1057    int64_t Val = Memory.OffsetImm->getValue();
1058    return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1059  }
1060  bool isMemPosImm8Offset() const {
1061    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1062      return false;
1063    // Immediate offset in range [0, 255].
1064    if (!Memory.OffsetImm) return true;
1065    int64_t Val = Memory.OffsetImm->getValue();
1066    return Val >= 0 && Val < 256;
1067  }
1068  bool isMemNegImm8Offset() const {
1069    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1070      return false;
1071    // Base reg of PC isn't allowed for these encodings.
1072    if (Memory.BaseRegNum == ARM::PC) return false;
1073    // Immediate offset in range [-255, -1].
1074    if (!Memory.OffsetImm) return false;
1075    int64_t Val = Memory.OffsetImm->getValue();
1076    return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1077  }
1078  bool isMemUImm12Offset() const {
1079    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1080      return false;
1081    // Immediate offset in range [0, 4095].
1082    if (!Memory.OffsetImm) return true;
1083    int64_t Val = Memory.OffsetImm->getValue();
1084    return (Val >= 0 && Val < 4096);
1085  }
1086  bool isMemImm12Offset() const {
1087    // If we have an immediate that's not a constant, treat it as a label
1088    // reference needing a fixup. If it is a constant, it's something else
1089    // and we reject it.
1090    if (isImm() && !isa<MCConstantExpr>(getImm()))
1091      return true;
1092
1093    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1094      return false;
1095    // Immediate offset in range [-4095, 4095].
1096    if (!Memory.OffsetImm) return true;
1097    int64_t Val = Memory.OffsetImm->getValue();
1098    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1099  }
1100  bool isPostIdxImm8() const {
1101    if (!isImm()) return false;
1102    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1103    if (!CE) return false;
1104    int64_t Val = CE->getValue();
1105    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1106  }
1107  bool isPostIdxImm8s4() const {
1108    if (!isImm()) return false;
1109    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1110    if (!CE) return false;
1111    int64_t Val = CE->getValue();
1112    return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1113      (Val == INT32_MIN);
1114  }
1115
1116  bool isMSRMask() const { return Kind == k_MSRMask; }
1117  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1118
1119  // NEON operands.
1120  bool isSingleSpacedVectorList() const {
1121    return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1122  }
1123  bool isDoubleSpacedVectorList() const {
1124    return Kind == k_VectorList && VectorList.isDoubleSpaced;
1125  }
1126  bool isVecListOneD() const {
1127    if (!isSingleSpacedVectorList()) return false;
1128    return VectorList.Count == 1;
1129  }
1130
1131  bool isVecListDPair() const {
1132    if (!isSingleSpacedVectorList()) return false;
1133    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1134              .contains(VectorList.RegNum));
1135  }
1136
1137  bool isVecListThreeD() const {
1138    if (!isSingleSpacedVectorList()) return false;
1139    return VectorList.Count == 3;
1140  }
1141
1142  bool isVecListFourD() const {
1143    if (!isSingleSpacedVectorList()) return false;
1144    return VectorList.Count == 4;
1145  }
1146
1147  bool isVecListDPairSpaced() const {
1148    if (isSingleSpacedVectorList()) return false;
1149    return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1150              .contains(VectorList.RegNum));
1151  }
1152
1153  bool isVecListThreeQ() const {
1154    if (!isDoubleSpacedVectorList()) return false;
1155    return VectorList.Count == 3;
1156  }
1157
1158  bool isVecListFourQ() const {
1159    if (!isDoubleSpacedVectorList()) return false;
1160    return VectorList.Count == 4;
1161  }
1162
1163  bool isSingleSpacedVectorAllLanes() const {
1164    return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1165  }
1166  bool isDoubleSpacedVectorAllLanes() const {
1167    return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1168  }
1169  bool isVecListOneDAllLanes() const {
1170    if (!isSingleSpacedVectorAllLanes()) return false;
1171    return VectorList.Count == 1;
1172  }
1173
1174  bool isVecListDPairAllLanes() const {
1175    if (!isSingleSpacedVectorAllLanes()) return false;
1176    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1177              .contains(VectorList.RegNum));
1178  }
1179
1180  bool isVecListDPairSpacedAllLanes() const {
1181    if (!isDoubleSpacedVectorAllLanes()) return false;
1182    return VectorList.Count == 2;
1183  }
1184
1185  bool isVecListThreeDAllLanes() const {
1186    if (!isSingleSpacedVectorAllLanes()) return false;
1187    return VectorList.Count == 3;
1188  }
1189
1190  bool isVecListThreeQAllLanes() const {
1191    if (!isDoubleSpacedVectorAllLanes()) return false;
1192    return VectorList.Count == 3;
1193  }
1194
1195  bool isVecListFourDAllLanes() const {
1196    if (!isSingleSpacedVectorAllLanes()) return false;
1197    return VectorList.Count == 4;
1198  }
1199
1200  bool isVecListFourQAllLanes() const {
1201    if (!isDoubleSpacedVectorAllLanes()) return false;
1202    return VectorList.Count == 4;
1203  }
1204
1205  bool isSingleSpacedVectorIndexed() const {
1206    return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1207  }
1208  bool isDoubleSpacedVectorIndexed() const {
1209    return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1210  }
1211  bool isVecListOneDByteIndexed() const {
1212    if (!isSingleSpacedVectorIndexed()) return false;
1213    return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1214  }
1215
1216  bool isVecListOneDHWordIndexed() const {
1217    if (!isSingleSpacedVectorIndexed()) return false;
1218    return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1219  }
1220
1221  bool isVecListOneDWordIndexed() const {
1222    if (!isSingleSpacedVectorIndexed()) return false;
1223    return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1224  }
1225
1226  bool isVecListTwoDByteIndexed() const {
1227    if (!isSingleSpacedVectorIndexed()) return false;
1228    return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1229  }
1230
1231  bool isVecListTwoDHWordIndexed() const {
1232    if (!isSingleSpacedVectorIndexed()) return false;
1233    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1234  }
1235
1236  bool isVecListTwoQWordIndexed() const {
1237    if (!isDoubleSpacedVectorIndexed()) return false;
1238    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1239  }
1240
1241  bool isVecListTwoQHWordIndexed() const {
1242    if (!isDoubleSpacedVectorIndexed()) return false;
1243    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1244  }
1245
1246  bool isVecListTwoDWordIndexed() const {
1247    if (!isSingleSpacedVectorIndexed()) return false;
1248    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1249  }
1250
1251  bool isVecListThreeDByteIndexed() const {
1252    if (!isSingleSpacedVectorIndexed()) return false;
1253    return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1254  }
1255
1256  bool isVecListThreeDHWordIndexed() const {
1257    if (!isSingleSpacedVectorIndexed()) return false;
1258    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1259  }
1260
1261  bool isVecListThreeQWordIndexed() const {
1262    if (!isDoubleSpacedVectorIndexed()) return false;
1263    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1264  }
1265
1266  bool isVecListThreeQHWordIndexed() const {
1267    if (!isDoubleSpacedVectorIndexed()) return false;
1268    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1269  }
1270
1271  bool isVecListThreeDWordIndexed() const {
1272    if (!isSingleSpacedVectorIndexed()) return false;
1273    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1274  }
1275
1276  bool isVecListFourDByteIndexed() const {
1277    if (!isSingleSpacedVectorIndexed()) return false;
1278    return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1279  }
1280
1281  bool isVecListFourDHWordIndexed() const {
1282    if (!isSingleSpacedVectorIndexed()) return false;
1283    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1284  }
1285
1286  bool isVecListFourQWordIndexed() const {
1287    if (!isDoubleSpacedVectorIndexed()) return false;
1288    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1289  }
1290
1291  bool isVecListFourQHWordIndexed() const {
1292    if (!isDoubleSpacedVectorIndexed()) return false;
1293    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1294  }
1295
1296  bool isVecListFourDWordIndexed() const {
1297    if (!isSingleSpacedVectorIndexed()) return false;
1298    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1299  }
1300
1301  bool isVectorIndex8() const {
1302    if (Kind != k_VectorIndex) return false;
1303    return VectorIndex.Val < 8;
1304  }
1305  bool isVectorIndex16() const {
1306    if (Kind != k_VectorIndex) return false;
1307    return VectorIndex.Val < 4;
1308  }
1309  bool isVectorIndex32() const {
1310    if (Kind != k_VectorIndex) return false;
1311    return VectorIndex.Val < 2;
1312  }
1313
1314  bool isNEONi8splat() const {
1315    if (!isImm()) return false;
1316    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1317    // Must be a constant.
1318    if (!CE) return false;
1319    int64_t Value = CE->getValue();
1320    // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1321    // value.
1322    return Value >= 0 && Value < 256;
1323  }
1324
1325  bool isNEONi16splat() const {
1326    if (!isImm()) return false;
1327    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1328    // Must be a constant.
1329    if (!CE) return false;
1330    int64_t Value = CE->getValue();
1331    // i16 value in the range [0,255] or [0x0100, 0xff00]
1332    return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1333  }
1334
1335  bool isNEONi32splat() const {
1336    if (!isImm()) return false;
1337    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1338    // Must be a constant.
1339    if (!CE) return false;
1340    int64_t Value = CE->getValue();
1341    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1342    return (Value >= 0 && Value < 256) ||
1343      (Value >= 0x0100 && Value <= 0xff00) ||
1344      (Value >= 0x010000 && Value <= 0xff0000) ||
1345      (Value >= 0x01000000 && Value <= 0xff000000);
1346  }
1347
1348  bool isNEONi32vmov() const {
1349    if (!isImm()) return false;
1350    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1351    // Must be a constant.
1352    if (!CE) return false;
1353    int64_t Value = CE->getValue();
1354    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1355    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1356    return (Value >= 0 && Value < 256) ||
1357      (Value >= 0x0100 && Value <= 0xff00) ||
1358      (Value >= 0x010000 && Value <= 0xff0000) ||
1359      (Value >= 0x01000000 && Value <= 0xff000000) ||
1360      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1361      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1362  }
1363  bool isNEONi32vmovNeg() const {
1364    if (!isImm()) return false;
1365    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1366    // Must be a constant.
1367    if (!CE) return false;
1368    int64_t Value = ~CE->getValue();
1369    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1370    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1371    return (Value >= 0 && Value < 256) ||
1372      (Value >= 0x0100 && Value <= 0xff00) ||
1373      (Value >= 0x010000 && Value <= 0xff0000) ||
1374      (Value >= 0x01000000 && Value <= 0xff000000) ||
1375      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1376      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1377  }
1378
1379  bool isNEONi64splat() const {
1380    if (!isImm()) return false;
1381    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1382    // Must be a constant.
1383    if (!CE) return false;
1384    uint64_t Value = CE->getValue();
1385    // i64 value with each byte being either 0 or 0xff.
1386    for (unsigned i = 0; i < 8; ++i)
1387      if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1388    return true;
1389  }
1390
1391  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1392    // Add as immediates when possible.  Null MCExpr = 0.
1393    if (Expr == 0)
1394      Inst.addOperand(MCOperand::CreateImm(0));
1395    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1396      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1397    else
1398      Inst.addOperand(MCOperand::CreateExpr(Expr));
1399  }
1400
1401  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1402    assert(N == 2 && "Invalid number of operands!");
1403    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1404    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1405    Inst.addOperand(MCOperand::CreateReg(RegNum));
1406  }
1407
1408  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1409    assert(N == 1 && "Invalid number of operands!");
1410    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1411  }
1412
1413  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1414    assert(N == 1 && "Invalid number of operands!");
1415    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1416  }
1417
1418  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1419    assert(N == 1 && "Invalid number of operands!");
1420    Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1421  }
1422
1423  void addITMaskOperands(MCInst &Inst, unsigned N) const {
1424    assert(N == 1 && "Invalid number of operands!");
1425    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1426  }
1427
1428  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1429    assert(N == 1 && "Invalid number of operands!");
1430    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1431  }
1432
1433  void addCCOutOperands(MCInst &Inst, unsigned N) const {
1434    assert(N == 1 && "Invalid number of operands!");
1435    Inst.addOperand(MCOperand::CreateReg(getReg()));
1436  }
1437
1438  void addRegOperands(MCInst &Inst, unsigned N) const {
1439    assert(N == 1 && "Invalid number of operands!");
1440    Inst.addOperand(MCOperand::CreateReg(getReg()));
1441  }
1442
1443  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1444    assert(N == 3 && "Invalid number of operands!");
1445    assert(isRegShiftedReg() &&
1446           "addRegShiftedRegOperands() on non RegShiftedReg!");
1447    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1448    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1449    Inst.addOperand(MCOperand::CreateImm(
1450      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1451  }
1452
1453  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1454    assert(N == 2 && "Invalid number of operands!");
1455    assert(isRegShiftedImm() &&
1456           "addRegShiftedImmOperands() on non RegShiftedImm!");
1457    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1458    // Shift of #32 is encoded as 0 where permitted
1459    unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1460    Inst.addOperand(MCOperand::CreateImm(
1461      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1462  }
1463
1464  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1465    assert(N == 1 && "Invalid number of operands!");
1466    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1467                                         ShifterImm.Imm));
1468  }
1469
1470  void addRegListOperands(MCInst &Inst, unsigned N) const {
1471    assert(N == 1 && "Invalid number of operands!");
1472    const SmallVectorImpl<unsigned> &RegList = getRegList();
1473    for (SmallVectorImpl<unsigned>::const_iterator
1474           I = RegList.begin(), E = RegList.end(); I != E; ++I)
1475      Inst.addOperand(MCOperand::CreateReg(*I));
1476  }
1477
1478  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1479    addRegListOperands(Inst, N);
1480  }
1481
1482  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1483    addRegListOperands(Inst, N);
1484  }
1485
1486  void addRotImmOperands(MCInst &Inst, unsigned N) const {
1487    assert(N == 1 && "Invalid number of operands!");
1488    // Encoded as val>>3. The printer handles display as 8, 16, 24.
1489    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1490  }
1491
1492  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1493    assert(N == 1 && "Invalid number of operands!");
1494    // Munge the lsb/width into a bitfield mask.
1495    unsigned lsb = Bitfield.LSB;
1496    unsigned width = Bitfield.Width;
1497    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1498    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1499                      (32 - (lsb + width)));
1500    Inst.addOperand(MCOperand::CreateImm(Mask));
1501  }
1502
1503  void addImmOperands(MCInst &Inst, unsigned N) const {
1504    assert(N == 1 && "Invalid number of operands!");
1505    addExpr(Inst, getImm());
1506  }
1507
1508  void addFBits16Operands(MCInst &Inst, unsigned N) const {
1509    assert(N == 1 && "Invalid number of operands!");
1510    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1511    Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1512  }
1513
1514  void addFBits32Operands(MCInst &Inst, unsigned N) const {
1515    assert(N == 1 && "Invalid number of operands!");
1516    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1517    Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1518  }
1519
1520  void addFPImmOperands(MCInst &Inst, unsigned N) const {
1521    assert(N == 1 && "Invalid number of operands!");
1522    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1523    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1524    Inst.addOperand(MCOperand::CreateImm(Val));
1525  }
1526
1527  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1528    assert(N == 1 && "Invalid number of operands!");
1529    // FIXME: We really want to scale the value here, but the LDRD/STRD
1530    // instruction don't encode operands that way yet.
1531    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1532    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1533  }
1534
1535  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1536    assert(N == 1 && "Invalid number of operands!");
1537    // The immediate is scaled by four in the encoding and is stored
1538    // in the MCInst as such. Lop off the low two bits here.
1539    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1540    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1541  }
1542
1543  void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1544    assert(N == 1 && "Invalid number of operands!");
1545    // The immediate is scaled by four in the encoding and is stored
1546    // in the MCInst as such. Lop off the low two bits here.
1547    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1548    Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1549  }
1550
1551  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1552    assert(N == 1 && "Invalid number of operands!");
1553    // The immediate is scaled by four in the encoding and is stored
1554    // in the MCInst as such. Lop off the low two bits here.
1555    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1556    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1557  }
1558
1559  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1560    assert(N == 1 && "Invalid number of operands!");
1561    // The constant encodes as the immediate-1, and we store in the instruction
1562    // the bits as encoded, so subtract off one here.
1563    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1564    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1565  }
1566
1567  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1568    assert(N == 1 && "Invalid number of operands!");
1569    // The constant encodes as the immediate-1, and we store in the instruction
1570    // the bits as encoded, so subtract off one here.
1571    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1572    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1573  }
1574
1575  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1576    assert(N == 1 && "Invalid number of operands!");
1577    // The constant encodes as the immediate, except for 32, which encodes as
1578    // zero.
1579    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1580    unsigned Imm = CE->getValue();
1581    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1582  }
1583
1584  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1585    assert(N == 1 && "Invalid number of operands!");
1586    // An ASR value of 32 encodes as 0, so that's how we want to add it to
1587    // the instruction as well.
1588    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1589    int Val = CE->getValue();
1590    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1591  }
1592
1593  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1594    assert(N == 1 && "Invalid number of operands!");
1595    // The operand is actually a t2_so_imm, but we have its bitwise
1596    // negation in the assembly source, so twiddle it here.
1597    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1598    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1599  }
1600
1601  void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1602    assert(N == 1 && "Invalid number of operands!");
1603    // The operand is actually a t2_so_imm, but we have its
1604    // negation in the assembly source, so twiddle it here.
1605    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1606    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1607  }
1608
1609  void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1610    assert(N == 1 && "Invalid number of operands!");
1611    // The operand is actually an imm0_4095, but we have its
1612    // negation in the assembly source, so twiddle it here.
1613    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1614    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1615  }
1616
1617  void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1618    assert(N == 1 && "Invalid number of operands!");
1619    // The operand is actually a so_imm, but we have its bitwise
1620    // negation in the assembly source, so twiddle it here.
1621    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1622    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1623  }
1624
1625  void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1626    assert(N == 1 && "Invalid number of operands!");
1627    // The operand is actually a so_imm, but we have its
1628    // negation in the assembly source, so twiddle it here.
1629    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1630    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1631  }
1632
1633  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1634    assert(N == 1 && "Invalid number of operands!");
1635    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1636  }
1637
1638  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1639    assert(N == 1 && "Invalid number of operands!");
1640    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1641  }
1642
1643  void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1644    assert(N == 1 && "Invalid number of operands!");
1645    int32_t Imm = Memory.OffsetImm->getValue();
1646    // FIXME: Handle #-0
1647    if (Imm == INT32_MIN) Imm = 0;
1648    Inst.addOperand(MCOperand::CreateImm(Imm));
1649  }
1650
1651  void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1652    assert(N == 1 && "Invalid number of operands!");
1653    assert(isImm() && "Not an immediate!");
1654
1655    // If we have an immediate that's not a constant, treat it as a label
1656    // reference needing a fixup.
1657    if (!isa<MCConstantExpr>(getImm())) {
1658      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1659      return;
1660    }
1661
1662    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1663    int Val = CE->getValue();
1664    Inst.addOperand(MCOperand::CreateImm(Val));
1665  }
1666
1667  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1668    assert(N == 2 && "Invalid number of operands!");
1669    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1670    Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1671  }
1672
1673  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1674    assert(N == 3 && "Invalid number of operands!");
1675    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1676    if (!Memory.OffsetRegNum) {
1677      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1678      // Special case for #-0
1679      if (Val == INT32_MIN) Val = 0;
1680      if (Val < 0) Val = -Val;
1681      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1682    } else {
1683      // For register offset, we encode the shift type and negation flag
1684      // here.
1685      Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1686                              Memory.ShiftImm, Memory.ShiftType);
1687    }
1688    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1689    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1690    Inst.addOperand(MCOperand::CreateImm(Val));
1691  }
1692
1693  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1694    assert(N == 2 && "Invalid number of operands!");
1695    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1696    assert(CE && "non-constant AM2OffsetImm operand!");
1697    int32_t Val = CE->getValue();
1698    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1699    // Special case for #-0
1700    if (Val == INT32_MIN) Val = 0;
1701    if (Val < 0) Val = -Val;
1702    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1703    Inst.addOperand(MCOperand::CreateReg(0));
1704    Inst.addOperand(MCOperand::CreateImm(Val));
1705  }
1706
1707  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1708    assert(N == 3 && "Invalid number of operands!");
1709    // If we have an immediate that's not a constant, treat it as a label
1710    // reference needing a fixup. If it is a constant, it's something else
1711    // and we reject it.
1712    if (isImm()) {
1713      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1714      Inst.addOperand(MCOperand::CreateReg(0));
1715      Inst.addOperand(MCOperand::CreateImm(0));
1716      return;
1717    }
1718
1719    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1720    if (!Memory.OffsetRegNum) {
1721      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1722      // Special case for #-0
1723      if (Val == INT32_MIN) Val = 0;
1724      if (Val < 0) Val = -Val;
1725      Val = ARM_AM::getAM3Opc(AddSub, Val);
1726    } else {
1727      // For register offset, we encode the shift type and negation flag
1728      // here.
1729      Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1730    }
1731    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1732    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1733    Inst.addOperand(MCOperand::CreateImm(Val));
1734  }
1735
1736  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1737    assert(N == 2 && "Invalid number of operands!");
1738    if (Kind == k_PostIndexRegister) {
1739      int32_t Val =
1740        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1741      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1742      Inst.addOperand(MCOperand::CreateImm(Val));
1743      return;
1744    }
1745
1746    // Constant offset.
1747    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1748    int32_t Val = CE->getValue();
1749    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1750    // Special case for #-0
1751    if (Val == INT32_MIN) Val = 0;
1752    if (Val < 0) Val = -Val;
1753    Val = ARM_AM::getAM3Opc(AddSub, Val);
1754    Inst.addOperand(MCOperand::CreateReg(0));
1755    Inst.addOperand(MCOperand::CreateImm(Val));
1756  }
1757
1758  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1759    assert(N == 2 && "Invalid number of operands!");
1760    // If we have an immediate that's not a constant, treat it as a label
1761    // reference needing a fixup. If it is a constant, it's something else
1762    // and we reject it.
1763    if (isImm()) {
1764      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1765      Inst.addOperand(MCOperand::CreateImm(0));
1766      return;
1767    }
1768
1769    // The lower two bits are always zero and as such are not encoded.
1770    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1771    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1772    // Special case for #-0
1773    if (Val == INT32_MIN) Val = 0;
1774    if (Val < 0) Val = -Val;
1775    Val = ARM_AM::getAM5Opc(AddSub, Val);
1776    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1777    Inst.addOperand(MCOperand::CreateImm(Val));
1778  }
1779
1780  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1781    assert(N == 2 && "Invalid number of operands!");
1782    // If we have an immediate that's not a constant, treat it as a label
1783    // reference needing a fixup. If it is a constant, it's something else
1784    // and we reject it.
1785    if (isImm()) {
1786      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1787      Inst.addOperand(MCOperand::CreateImm(0));
1788      return;
1789    }
1790
1791    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1792    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1793    Inst.addOperand(MCOperand::CreateImm(Val));
1794  }
1795
1796  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1797    assert(N == 2 && "Invalid number of operands!");
1798    // The lower two bits are always zero and as such are not encoded.
1799    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1800    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1801    Inst.addOperand(MCOperand::CreateImm(Val));
1802  }
1803
1804  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1805    assert(N == 2 && "Invalid number of operands!");
1806    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1807    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1808    Inst.addOperand(MCOperand::CreateImm(Val));
1809  }
1810
1811  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1812    addMemImm8OffsetOperands(Inst, N);
1813  }
1814
1815  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1816    addMemImm8OffsetOperands(Inst, N);
1817  }
1818
1819  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1820    assert(N == 2 && "Invalid number of operands!");
1821    // If this is an immediate, it's a label reference.
1822    if (isImm()) {
1823      addExpr(Inst, getImm());
1824      Inst.addOperand(MCOperand::CreateImm(0));
1825      return;
1826    }
1827
1828    // Otherwise, it's a normal memory reg+offset.
1829    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1830    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1831    Inst.addOperand(MCOperand::CreateImm(Val));
1832  }
1833
1834  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1835    assert(N == 2 && "Invalid number of operands!");
1836    // If this is an immediate, it's a label reference.
1837    if (isImm()) {
1838      addExpr(Inst, getImm());
1839      Inst.addOperand(MCOperand::CreateImm(0));
1840      return;
1841    }
1842
1843    // Otherwise, it's a normal memory reg+offset.
1844    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1845    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1846    Inst.addOperand(MCOperand::CreateImm(Val));
1847  }
1848
1849  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1850    assert(N == 2 && "Invalid number of operands!");
1851    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1852    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1853  }
1854
1855  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1856    assert(N == 2 && "Invalid number of operands!");
1857    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1858    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1859  }
1860
1861  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1862    assert(N == 3 && "Invalid number of operands!");
1863    unsigned Val =
1864      ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1865                        Memory.ShiftImm, Memory.ShiftType);
1866    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1867    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1868    Inst.addOperand(MCOperand::CreateImm(Val));
1869  }
1870
1871  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1872    assert(N == 3 && "Invalid number of operands!");
1873    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1874    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1875    Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1876  }
1877
1878  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1879    assert(N == 2 && "Invalid number of operands!");
1880    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1881    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1882  }
1883
1884  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1885    assert(N == 2 && "Invalid number of operands!");
1886    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1887    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1888    Inst.addOperand(MCOperand::CreateImm(Val));
1889  }
1890
1891  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1892    assert(N == 2 && "Invalid number of operands!");
1893    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1894    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1895    Inst.addOperand(MCOperand::CreateImm(Val));
1896  }
1897
1898  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1899    assert(N == 2 && "Invalid number of operands!");
1900    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1901    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1902    Inst.addOperand(MCOperand::CreateImm(Val));
1903  }
1904
1905  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1906    assert(N == 2 && "Invalid number of operands!");
1907    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1908    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1909    Inst.addOperand(MCOperand::CreateImm(Val));
1910  }
1911
1912  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1913    assert(N == 1 && "Invalid number of operands!");
1914    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1915    assert(CE && "non-constant post-idx-imm8 operand!");
1916    int Imm = CE->getValue();
1917    bool isAdd = Imm >= 0;
1918    if (Imm == INT32_MIN) Imm = 0;
1919    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1920    Inst.addOperand(MCOperand::CreateImm(Imm));
1921  }
1922
1923  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1924    assert(N == 1 && "Invalid number of operands!");
1925    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1926    assert(CE && "non-constant post-idx-imm8s4 operand!");
1927    int Imm = CE->getValue();
1928    bool isAdd = Imm >= 0;
1929    if (Imm == INT32_MIN) Imm = 0;
1930    // Immediate is scaled by 4.
1931    Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1932    Inst.addOperand(MCOperand::CreateImm(Imm));
1933  }
1934
1935  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1936    assert(N == 2 && "Invalid number of operands!");
1937    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1938    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1939  }
1940
1941  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1942    assert(N == 2 && "Invalid number of operands!");
1943    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1944    // The sign, shift type, and shift amount are encoded in a single operand
1945    // using the AM2 encoding helpers.
1946    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1947    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1948                                     PostIdxReg.ShiftTy);
1949    Inst.addOperand(MCOperand::CreateImm(Imm));
1950  }
1951
1952  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1953    assert(N == 1 && "Invalid number of operands!");
1954    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1955  }
1956
1957  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1958    assert(N == 1 && "Invalid number of operands!");
1959    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1960  }
1961
1962  void addVecListOperands(MCInst &Inst, unsigned N) const {
1963    assert(N == 1 && "Invalid number of operands!");
1964    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1965  }
1966
1967  void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
1968    assert(N == 2 && "Invalid number of operands!");
1969    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1970    Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
1971  }
1972
1973  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1974    assert(N == 1 && "Invalid number of operands!");
1975    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1976  }
1977
1978  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1979    assert(N == 1 && "Invalid number of operands!");
1980    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1981  }
1982
1983  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1984    assert(N == 1 && "Invalid number of operands!");
1985    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1986  }
1987
1988  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1989    assert(N == 1 && "Invalid number of operands!");
1990    // The immediate encodes the type of constant as well as the value.
1991    // Mask in that this is an i8 splat.
1992    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1993    Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1994  }
1995
1996  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1997    assert(N == 1 && "Invalid number of operands!");
1998    // The immediate encodes the type of constant as well as the value.
1999    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2000    unsigned Value = CE->getValue();
2001    if (Value >= 256)
2002      Value = (Value >> 8) | 0xa00;
2003    else
2004      Value |= 0x800;
2005    Inst.addOperand(MCOperand::CreateImm(Value));
2006  }
2007
2008  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2009    assert(N == 1 && "Invalid number of operands!");
2010    // The immediate encodes the type of constant as well as the value.
2011    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2012    unsigned Value = CE->getValue();
2013    if (Value >= 256 && Value <= 0xff00)
2014      Value = (Value >> 8) | 0x200;
2015    else if (Value > 0xffff && Value <= 0xff0000)
2016      Value = (Value >> 16) | 0x400;
2017    else if (Value > 0xffffff)
2018      Value = (Value >> 24) | 0x600;
2019    Inst.addOperand(MCOperand::CreateImm(Value));
2020  }
2021
2022  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2023    assert(N == 1 && "Invalid number of operands!");
2024    // The immediate encodes the type of constant as well as the value.
2025    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2026    unsigned Value = CE->getValue();
2027    if (Value >= 256 && Value <= 0xffff)
2028      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2029    else if (Value > 0xffff && Value <= 0xffffff)
2030      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2031    else if (Value > 0xffffff)
2032      Value = (Value >> 24) | 0x600;
2033    Inst.addOperand(MCOperand::CreateImm(Value));
2034  }
2035
2036  void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2037    assert(N == 1 && "Invalid number of operands!");
2038    // The immediate encodes the type of constant as well as the value.
2039    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2040    unsigned Value = ~CE->getValue();
2041    if (Value >= 256 && Value <= 0xffff)
2042      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2043    else if (Value > 0xffff && Value <= 0xffffff)
2044      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2045    else if (Value > 0xffffff)
2046      Value = (Value >> 24) | 0x600;
2047    Inst.addOperand(MCOperand::CreateImm(Value));
2048  }
2049
2050  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2051    assert(N == 1 && "Invalid number of operands!");
2052    // The immediate encodes the type of constant as well as the value.
2053    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2054    uint64_t Value = CE->getValue();
2055    unsigned Imm = 0;
2056    for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2057      Imm |= (Value & 1) << i;
2058    }
2059    Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2060  }
2061
2062  virtual void print(raw_ostream &OS) const;
2063
2064  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2065    ARMOperand *Op = new ARMOperand(k_ITCondMask);
2066    Op->ITMask.Mask = Mask;
2067    Op->StartLoc = S;
2068    Op->EndLoc = S;
2069    return Op;
2070  }
2071
2072  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2073    ARMOperand *Op = new ARMOperand(k_CondCode);
2074    Op->CC.Val = CC;
2075    Op->StartLoc = S;
2076    Op->EndLoc = S;
2077    return Op;
2078  }
2079
2080  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2081    ARMOperand *Op = new ARMOperand(k_CoprocNum);
2082    Op->Cop.Val = CopVal;
2083    Op->StartLoc = S;
2084    Op->EndLoc = S;
2085    return Op;
2086  }
2087
2088  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2089    ARMOperand *Op = new ARMOperand(k_CoprocReg);
2090    Op->Cop.Val = CopVal;
2091    Op->StartLoc = S;
2092    Op->EndLoc = S;
2093    return Op;
2094  }
2095
2096  static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2097    ARMOperand *Op = new ARMOperand(k_CoprocOption);
2098    Op->Cop.Val = Val;
2099    Op->StartLoc = S;
2100    Op->EndLoc = E;
2101    return Op;
2102  }
2103
2104  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2105    ARMOperand *Op = new ARMOperand(k_CCOut);
2106    Op->Reg.RegNum = RegNum;
2107    Op->StartLoc = S;
2108    Op->EndLoc = S;
2109    return Op;
2110  }
2111
2112  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2113    ARMOperand *Op = new ARMOperand(k_Token);
2114    Op->Tok.Data = Str.data();
2115    Op->Tok.Length = Str.size();
2116    Op->StartLoc = S;
2117    Op->EndLoc = S;
2118    return Op;
2119  }
2120
2121  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2122    ARMOperand *Op = new ARMOperand(k_Register);
2123    Op->Reg.RegNum = RegNum;
2124    Op->StartLoc = S;
2125    Op->EndLoc = E;
2126    return Op;
2127  }
2128
2129  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2130                                           unsigned SrcReg,
2131                                           unsigned ShiftReg,
2132                                           unsigned ShiftImm,
2133                                           SMLoc S, SMLoc E) {
2134    ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2135    Op->RegShiftedReg.ShiftTy = ShTy;
2136    Op->RegShiftedReg.SrcReg = SrcReg;
2137    Op->RegShiftedReg.ShiftReg = ShiftReg;
2138    Op->RegShiftedReg.ShiftImm = ShiftImm;
2139    Op->StartLoc = S;
2140    Op->EndLoc = E;
2141    return Op;
2142  }
2143
2144  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2145                                            unsigned SrcReg,
2146                                            unsigned ShiftImm,
2147                                            SMLoc S, SMLoc E) {
2148    ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2149    Op->RegShiftedImm.ShiftTy = ShTy;
2150    Op->RegShiftedImm.SrcReg = SrcReg;
2151    Op->RegShiftedImm.ShiftImm = ShiftImm;
2152    Op->StartLoc = S;
2153    Op->EndLoc = E;
2154    return Op;
2155  }
2156
2157  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2158                                   SMLoc S, SMLoc E) {
2159    ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2160    Op->ShifterImm.isASR = isASR;
2161    Op->ShifterImm.Imm = Imm;
2162    Op->StartLoc = S;
2163    Op->EndLoc = E;
2164    return Op;
2165  }
2166
2167  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2168    ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2169    Op->RotImm.Imm = Imm;
2170    Op->StartLoc = S;
2171    Op->EndLoc = E;
2172    return Op;
2173  }
2174
2175  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2176                                    SMLoc S, SMLoc E) {
2177    ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2178    Op->Bitfield.LSB = LSB;
2179    Op->Bitfield.Width = Width;
2180    Op->StartLoc = S;
2181    Op->EndLoc = E;
2182    return Op;
2183  }
2184
2185  static ARMOperand *
2186  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
2187                SMLoc StartLoc, SMLoc EndLoc) {
2188    KindTy Kind = k_RegisterList;
2189
2190    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
2191      Kind = k_DPRRegisterList;
2192    else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2193             contains(Regs.front().first))
2194      Kind = k_SPRRegisterList;
2195
2196    ARMOperand *Op = new ARMOperand(Kind);
2197    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
2198           I = Regs.begin(), E = Regs.end(); I != E; ++I)
2199      Op->Registers.push_back(I->first);
2200    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
2201    Op->StartLoc = StartLoc;
2202    Op->EndLoc = EndLoc;
2203    return Op;
2204  }
2205
2206  static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2207                                      bool isDoubleSpaced, SMLoc S, SMLoc E) {
2208    ARMOperand *Op = new ARMOperand(k_VectorList);
2209    Op->VectorList.RegNum = RegNum;
2210    Op->VectorList.Count = Count;
2211    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2212    Op->StartLoc = S;
2213    Op->EndLoc = E;
2214    return Op;
2215  }
2216
2217  static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2218                                              bool isDoubleSpaced,
2219                                              SMLoc S, SMLoc E) {
2220    ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2221    Op->VectorList.RegNum = RegNum;
2222    Op->VectorList.Count = Count;
2223    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2224    Op->StartLoc = S;
2225    Op->EndLoc = E;
2226    return Op;
2227  }
2228
2229  static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2230                                             unsigned Index,
2231                                             bool isDoubleSpaced,
2232                                             SMLoc S, SMLoc E) {
2233    ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2234    Op->VectorList.RegNum = RegNum;
2235    Op->VectorList.Count = Count;
2236    Op->VectorList.LaneIndex = Index;
2237    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2238    Op->StartLoc = S;
2239    Op->EndLoc = E;
2240    return Op;
2241  }
2242
2243  static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2244                                       MCContext &Ctx) {
2245    ARMOperand *Op = new ARMOperand(k_VectorIndex);
2246    Op->VectorIndex.Val = Idx;
2247    Op->StartLoc = S;
2248    Op->EndLoc = E;
2249    return Op;
2250  }
2251
2252  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2253    ARMOperand *Op = new ARMOperand(k_Immediate);
2254    Op->Imm.Val = Val;
2255    Op->StartLoc = S;
2256    Op->EndLoc = E;
2257    return Op;
2258  }
2259
2260  static ARMOperand *CreateMem(unsigned BaseRegNum,
2261                               const MCConstantExpr *OffsetImm,
2262                               unsigned OffsetRegNum,
2263                               ARM_AM::ShiftOpc ShiftType,
2264                               unsigned ShiftImm,
2265                               unsigned Alignment,
2266                               bool isNegative,
2267                               SMLoc S, SMLoc E) {
2268    ARMOperand *Op = new ARMOperand(k_Memory);
2269    Op->Memory.BaseRegNum = BaseRegNum;
2270    Op->Memory.OffsetImm = OffsetImm;
2271    Op->Memory.OffsetRegNum = OffsetRegNum;
2272    Op->Memory.ShiftType = ShiftType;
2273    Op->Memory.ShiftImm = ShiftImm;
2274    Op->Memory.Alignment = Alignment;
2275    Op->Memory.isNegative = isNegative;
2276    Op->StartLoc = S;
2277    Op->EndLoc = E;
2278    return Op;
2279  }
2280
2281  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2282                                      ARM_AM::ShiftOpc ShiftTy,
2283                                      unsigned ShiftImm,
2284                                      SMLoc S, SMLoc E) {
2285    ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2286    Op->PostIdxReg.RegNum = RegNum;
2287    Op->PostIdxReg.isAdd = isAdd;
2288    Op->PostIdxReg.ShiftTy = ShiftTy;
2289    Op->PostIdxReg.ShiftImm = ShiftImm;
2290    Op->StartLoc = S;
2291    Op->EndLoc = E;
2292    return Op;
2293  }
2294
2295  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2296    ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2297    Op->MBOpt.Val = Opt;
2298    Op->StartLoc = S;
2299    Op->EndLoc = S;
2300    return Op;
2301  }
2302
2303  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2304    ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2305    Op->IFlags.Val = IFlags;
2306    Op->StartLoc = S;
2307    Op->EndLoc = S;
2308    return Op;
2309  }
2310
2311  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2312    ARMOperand *Op = new ARMOperand(k_MSRMask);
2313    Op->MMask.Val = MMask;
2314    Op->StartLoc = S;
2315    Op->EndLoc = S;
2316    return Op;
2317  }
2318};
2319
2320} // end anonymous namespace.
2321
2322void ARMOperand::print(raw_ostream &OS) const {
2323  switch (Kind) {
2324  case k_CondCode:
2325    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2326    break;
2327  case k_CCOut:
2328    OS << "<ccout " << getReg() << ">";
2329    break;
2330  case k_ITCondMask: {
2331    static const char *const MaskStr[] = {
2332      "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2333      "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2334    };
2335    assert((ITMask.Mask & 0xf) == ITMask.Mask);
2336    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2337    break;
2338  }
2339  case k_CoprocNum:
2340    OS << "<coprocessor number: " << getCoproc() << ">";
2341    break;
2342  case k_CoprocReg:
2343    OS << "<coprocessor register: " << getCoproc() << ">";
2344    break;
2345  case k_CoprocOption:
2346    OS << "<coprocessor option: " << CoprocOption.Val << ">";
2347    break;
2348  case k_MSRMask:
2349    OS << "<mask: " << getMSRMask() << ">";
2350    break;
2351  case k_Immediate:
2352    getImm()->print(OS);
2353    break;
2354  case k_MemBarrierOpt:
2355    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2356    break;
2357  case k_Memory:
2358    OS << "<memory "
2359       << " base:" << Memory.BaseRegNum;
2360    OS << ">";
2361    break;
2362  case k_PostIndexRegister:
2363    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2364       << PostIdxReg.RegNum;
2365    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2366      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2367         << PostIdxReg.ShiftImm;
2368    OS << ">";
2369    break;
2370  case k_ProcIFlags: {
2371    OS << "<ARM_PROC::";
2372    unsigned IFlags = getProcIFlags();
2373    for (int i=2; i >= 0; --i)
2374      if (IFlags & (1 << i))
2375        OS << ARM_PROC::IFlagsToString(1 << i);
2376    OS << ">";
2377    break;
2378  }
2379  case k_Register:
2380    OS << "<register " << getReg() << ">";
2381    break;
2382  case k_ShifterImmediate:
2383    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2384       << " #" << ShifterImm.Imm << ">";
2385    break;
2386  case k_ShiftedRegister:
2387    OS << "<so_reg_reg "
2388       << RegShiftedReg.SrcReg << " "
2389       << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2390       << " " << RegShiftedReg.ShiftReg << ">";
2391    break;
2392  case k_ShiftedImmediate:
2393    OS << "<so_reg_imm "
2394       << RegShiftedImm.SrcReg << " "
2395       << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2396       << " #" << RegShiftedImm.ShiftImm << ">";
2397    break;
2398  case k_RotateImmediate:
2399    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2400    break;
2401  case k_BitfieldDescriptor:
2402    OS << "<bitfield " << "lsb: " << Bitfield.LSB
2403       << ", width: " << Bitfield.Width << ">";
2404    break;
2405  case k_RegisterList:
2406  case k_DPRRegisterList:
2407  case k_SPRRegisterList: {
2408    OS << "<register_list ";
2409
2410    const SmallVectorImpl<unsigned> &RegList = getRegList();
2411    for (SmallVectorImpl<unsigned>::const_iterator
2412           I = RegList.begin(), E = RegList.end(); I != E; ) {
2413      OS << *I;
2414      if (++I < E) OS << ", ";
2415    }
2416
2417    OS << ">";
2418    break;
2419  }
2420  case k_VectorList:
2421    OS << "<vector_list " << VectorList.Count << " * "
2422       << VectorList.RegNum << ">";
2423    break;
2424  case k_VectorListAllLanes:
2425    OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2426       << VectorList.RegNum << ">";
2427    break;
2428  case k_VectorListIndexed:
2429    OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2430       << VectorList.Count << " * " << VectorList.RegNum << ">";
2431    break;
2432  case k_Token:
2433    OS << "'" << getToken() << "'";
2434    break;
2435  case k_VectorIndex:
2436    OS << "<vectorindex " << getVectorIndex() << ">";
2437    break;
2438  }
2439}
2440
2441/// @name Auto-generated Match Functions
2442/// {
2443
2444static unsigned MatchRegisterName(StringRef Name);
2445
2446/// }
2447
2448bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2449                                 SMLoc &StartLoc, SMLoc &EndLoc) {
2450  StartLoc = Parser.getTok().getLoc();
2451  RegNo = tryParseRegister();
2452  EndLoc = Parser.getTok().getLoc();
2453
2454  return (RegNo == (unsigned)-1);
2455}
2456
2457/// Try to parse a register name.  The token must be an Identifier when called,
2458/// and if it is a register name the token is eaten and the register number is
2459/// returned.  Otherwise return -1.
2460///
2461int ARMAsmParser::tryParseRegister() {
2462  const AsmToken &Tok = Parser.getTok();
2463  if (Tok.isNot(AsmToken::Identifier)) return -1;
2464
2465  std::string lowerCase = Tok.getString().lower();
2466  unsigned RegNum = MatchRegisterName(lowerCase);
2467  if (!RegNum) {
2468    RegNum = StringSwitch<unsigned>(lowerCase)
2469      .Case("r13", ARM::SP)
2470      .Case("r14", ARM::LR)
2471      .Case("r15", ARM::PC)
2472      .Case("ip", ARM::R12)
2473      // Additional register name aliases for 'gas' compatibility.
2474      .Case("a1", ARM::R0)
2475      .Case("a2", ARM::R1)
2476      .Case("a3", ARM::R2)
2477      .Case("a4", ARM::R3)
2478      .Case("v1", ARM::R4)
2479      .Case("v2", ARM::R5)
2480      .Case("v3", ARM::R6)
2481      .Case("v4", ARM::R7)
2482      .Case("v5", ARM::R8)
2483      .Case("v6", ARM::R9)
2484      .Case("v7", ARM::R10)
2485      .Case("v8", ARM::R11)
2486      .Case("sb", ARM::R9)
2487      .Case("sl", ARM::R10)
2488      .Case("fp", ARM::R11)
2489      .Default(0);
2490  }
2491  if (!RegNum) {
2492    // Check for aliases registered via .req. Canonicalize to lower case.
2493    // That's more consistent since register names are case insensitive, and
2494    // it's how the original entry was passed in from MC/MCParser/AsmParser.
2495    StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2496    // If no match, return failure.
2497    if (Entry == RegisterReqs.end())
2498      return -1;
2499    Parser.Lex(); // Eat identifier token.
2500    return Entry->getValue();
2501  }
2502
2503  Parser.Lex(); // Eat identifier token.
2504
2505  return RegNum;
2506}
2507
2508// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2509// If a recoverable error occurs, return 1. If an irrecoverable error
2510// occurs, return -1. An irrecoverable error is one where tokens have been
2511// consumed in the process of trying to parse the shifter (i.e., when it is
2512// indeed a shifter operand, but malformed).
2513int ARMAsmParser::tryParseShiftRegister(
2514                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2515  SMLoc S = Parser.getTok().getLoc();
2516  const AsmToken &Tok = Parser.getTok();
2517  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2518
2519  std::string lowerCase = Tok.getString().lower();
2520  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2521      .Case("asl", ARM_AM::lsl)
2522      .Case("lsl", ARM_AM::lsl)
2523      .Case("lsr", ARM_AM::lsr)
2524      .Case("asr", ARM_AM::asr)
2525      .Case("ror", ARM_AM::ror)
2526      .Case("rrx", ARM_AM::rrx)
2527      .Default(ARM_AM::no_shift);
2528
2529  if (ShiftTy == ARM_AM::no_shift)
2530    return 1;
2531
2532  Parser.Lex(); // Eat the operator.
2533
2534  // The source register for the shift has already been added to the
2535  // operand list, so we need to pop it off and combine it into the shifted
2536  // register operand instead.
2537  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2538  if (!PrevOp->isReg())
2539    return Error(PrevOp->getStartLoc(), "shift must be of a register");
2540  int SrcReg = PrevOp->getReg();
2541  int64_t Imm = 0;
2542  int ShiftReg = 0;
2543  if (ShiftTy == ARM_AM::rrx) {
2544    // RRX Doesn't have an explicit shift amount. The encoder expects
2545    // the shift register to be the same as the source register. Seems odd,
2546    // but OK.
2547    ShiftReg = SrcReg;
2548  } else {
2549    // Figure out if this is shifted by a constant or a register (for non-RRX).
2550    if (Parser.getTok().is(AsmToken::Hash) ||
2551        Parser.getTok().is(AsmToken::Dollar)) {
2552      Parser.Lex(); // Eat hash.
2553      SMLoc ImmLoc = Parser.getTok().getLoc();
2554      const MCExpr *ShiftExpr = 0;
2555      if (getParser().ParseExpression(ShiftExpr)) {
2556        Error(ImmLoc, "invalid immediate shift value");
2557        return -1;
2558      }
2559      // The expression must be evaluatable as an immediate.
2560      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2561      if (!CE) {
2562        Error(ImmLoc, "invalid immediate shift value");
2563        return -1;
2564      }
2565      // Range check the immediate.
2566      // lsl, ror: 0 <= imm <= 31
2567      // lsr, asr: 0 <= imm <= 32
2568      Imm = CE->getValue();
2569      if (Imm < 0 ||
2570          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2571          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2572        Error(ImmLoc, "immediate shift value out of range");
2573        return -1;
2574      }
2575      // shift by zero is a nop. Always send it through as lsl.
2576      // ('as' compatibility)
2577      if (Imm == 0)
2578        ShiftTy = ARM_AM::lsl;
2579    } else if (Parser.getTok().is(AsmToken::Identifier)) {
2580      ShiftReg = tryParseRegister();
2581      SMLoc L = Parser.getTok().getLoc();
2582      if (ShiftReg == -1) {
2583        Error (L, "expected immediate or register in shift operand");
2584        return -1;
2585      }
2586    } else {
2587      Error (Parser.getTok().getLoc(),
2588                    "expected immediate or register in shift operand");
2589      return -1;
2590    }
2591  }
2592
2593  if (ShiftReg && ShiftTy != ARM_AM::rrx)
2594    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2595                                                         ShiftReg, Imm,
2596                                               S, Parser.getTok().getLoc()));
2597  else
2598    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2599                                               S, Parser.getTok().getLoc()));
2600
2601  return 0;
2602}
2603
2604
2605/// Try to parse a register name.  The token must be an Identifier when called.
2606/// If it's a register, an AsmOperand is created. Another AsmOperand is created
2607/// if there is a "writeback". 'true' if it's not a register.
2608///
2609/// TODO this is likely to change to allow different register types and or to
2610/// parse for a specific register type.
2611bool ARMAsmParser::
2612tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2613  SMLoc S = Parser.getTok().getLoc();
2614  int RegNo = tryParseRegister();
2615  if (RegNo == -1)
2616    return true;
2617
2618  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2619
2620  const AsmToken &ExclaimTok = Parser.getTok();
2621  if (ExclaimTok.is(AsmToken::Exclaim)) {
2622    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2623                                               ExclaimTok.getLoc()));
2624    Parser.Lex(); // Eat exclaim token
2625    return false;
2626  }
2627
2628  // Also check for an index operand. This is only legal for vector registers,
2629  // but that'll get caught OK in operand matching, so we don't need to
2630  // explicitly filter everything else out here.
2631  if (Parser.getTok().is(AsmToken::LBrac)) {
2632    SMLoc SIdx = Parser.getTok().getLoc();
2633    Parser.Lex(); // Eat left bracket token.
2634
2635    const MCExpr *ImmVal;
2636    if (getParser().ParseExpression(ImmVal))
2637      return true;
2638    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2639    if (!MCE)
2640      return TokError("immediate value expected for vector index");
2641
2642    SMLoc E = Parser.getTok().getLoc();
2643    if (Parser.getTok().isNot(AsmToken::RBrac))
2644      return Error(E, "']' expected");
2645
2646    Parser.Lex(); // Eat right bracket token.
2647
2648    Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2649                                                     SIdx, E,
2650                                                     getContext()));
2651  }
2652
2653  return false;
2654}
2655
2656/// MatchCoprocessorOperandName - Try to parse an coprocessor related
2657/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2658/// "c5", ...
2659static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2660  // Use the same layout as the tablegen'erated register name matcher. Ugly,
2661  // but efficient.
2662  switch (Name.size()) {
2663  default: return -1;
2664  case 2:
2665    if (Name[0] != CoprocOp)
2666      return -1;
2667    switch (Name[1]) {
2668    default:  return -1;
2669    case '0': return 0;
2670    case '1': return 1;
2671    case '2': return 2;
2672    case '3': return 3;
2673    case '4': return 4;
2674    case '5': return 5;
2675    case '6': return 6;
2676    case '7': return 7;
2677    case '8': return 8;
2678    case '9': return 9;
2679    }
2680  case 3:
2681    if (Name[0] != CoprocOp || Name[1] != '1')
2682      return -1;
2683    switch (Name[2]) {
2684    default:  return -1;
2685    case '0': return 10;
2686    case '1': return 11;
2687    case '2': return 12;
2688    case '3': return 13;
2689    case '4': return 14;
2690    case '5': return 15;
2691    }
2692  }
2693}
2694
2695/// parseITCondCode - Try to parse a condition code for an IT instruction.
2696ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2697parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2698  SMLoc S = Parser.getTok().getLoc();
2699  const AsmToken &Tok = Parser.getTok();
2700  if (!Tok.is(AsmToken::Identifier))
2701    return MatchOperand_NoMatch;
2702  unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2703    .Case("eq", ARMCC::EQ)
2704    .Case("ne", ARMCC::NE)
2705    .Case("hs", ARMCC::HS)
2706    .Case("cs", ARMCC::HS)
2707    .Case("lo", ARMCC::LO)
2708    .Case("cc", ARMCC::LO)
2709    .Case("mi", ARMCC::MI)
2710    .Case("pl", ARMCC::PL)
2711    .Case("vs", ARMCC::VS)
2712    .Case("vc", ARMCC::VC)
2713    .Case("hi", ARMCC::HI)
2714    .Case("ls", ARMCC::LS)
2715    .Case("ge", ARMCC::GE)
2716    .Case("lt", ARMCC::LT)
2717    .Case("gt", ARMCC::GT)
2718    .Case("le", ARMCC::LE)
2719    .Case("al", ARMCC::AL)
2720    .Default(~0U);
2721  if (CC == ~0U)
2722    return MatchOperand_NoMatch;
2723  Parser.Lex(); // Eat the token.
2724
2725  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2726
2727  return MatchOperand_Success;
2728}
2729
2730/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2731/// token must be an Identifier when called, and if it is a coprocessor
2732/// number, the token is eaten and the operand is added to the operand list.
2733ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2734parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2735  SMLoc S = Parser.getTok().getLoc();
2736  const AsmToken &Tok = Parser.getTok();
2737  if (Tok.isNot(AsmToken::Identifier))
2738    return MatchOperand_NoMatch;
2739
2740  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2741  if (Num == -1)
2742    return MatchOperand_NoMatch;
2743
2744  Parser.Lex(); // Eat identifier token.
2745  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2746  return MatchOperand_Success;
2747}
2748
2749/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2750/// token must be an Identifier when called, and if it is a coprocessor
2751/// number, the token is eaten and the operand is added to the operand list.
2752ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2753parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2754  SMLoc S = Parser.getTok().getLoc();
2755  const AsmToken &Tok = Parser.getTok();
2756  if (Tok.isNot(AsmToken::Identifier))
2757    return MatchOperand_NoMatch;
2758
2759  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2760  if (Reg == -1)
2761    return MatchOperand_NoMatch;
2762
2763  Parser.Lex(); // Eat identifier token.
2764  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2765  return MatchOperand_Success;
2766}
2767
2768/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2769/// coproc_option : '{' imm0_255 '}'
2770ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2771parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2772  SMLoc S = Parser.getTok().getLoc();
2773
2774  // If this isn't a '{', this isn't a coprocessor immediate operand.
2775  if (Parser.getTok().isNot(AsmToken::LCurly))
2776    return MatchOperand_NoMatch;
2777  Parser.Lex(); // Eat the '{'
2778
2779  const MCExpr *Expr;
2780  SMLoc Loc = Parser.getTok().getLoc();
2781  if (getParser().ParseExpression(Expr)) {
2782    Error(Loc, "illegal expression");
2783    return MatchOperand_ParseFail;
2784  }
2785  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2786  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2787    Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2788    return MatchOperand_ParseFail;
2789  }
2790  int Val = CE->getValue();
2791
2792  // Check for and consume the closing '}'
2793  if (Parser.getTok().isNot(AsmToken::RCurly))
2794    return MatchOperand_ParseFail;
2795  SMLoc E = Parser.getTok().getLoc();
2796  Parser.Lex(); // Eat the '}'
2797
2798  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2799  return MatchOperand_Success;
2800}
2801
2802// For register list parsing, we need to map from raw GPR register numbering
2803// to the enumeration values. The enumeration values aren't sorted by
2804// register number due to our using "sp", "lr" and "pc" as canonical names.
2805static unsigned getNextRegister(unsigned Reg) {
2806  // If this is a GPR, we need to do it manually, otherwise we can rely
2807  // on the sort ordering of the enumeration since the other reg-classes
2808  // are sane.
2809  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2810    return Reg + 1;
2811  switch(Reg) {
2812  default: llvm_unreachable("Invalid GPR number!");
2813  case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
2814  case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
2815  case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
2816  case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
2817  case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
2818  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2819  case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
2820  case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
2821  }
2822}
2823
2824// Return the low-subreg of a given Q register.
2825static unsigned getDRegFromQReg(unsigned QReg) {
2826  switch (QReg) {
2827  default: llvm_unreachable("expected a Q register!");
2828  case ARM::Q0:  return ARM::D0;
2829  case ARM::Q1:  return ARM::D2;
2830  case ARM::Q2:  return ARM::D4;
2831  case ARM::Q3:  return ARM::D6;
2832  case ARM::Q4:  return ARM::D8;
2833  case ARM::Q5:  return ARM::D10;
2834  case ARM::Q6:  return ARM::D12;
2835  case ARM::Q7:  return ARM::D14;
2836  case ARM::Q8:  return ARM::D16;
2837  case ARM::Q9:  return ARM::D18;
2838  case ARM::Q10: return ARM::D20;
2839  case ARM::Q11: return ARM::D22;
2840  case ARM::Q12: return ARM::D24;
2841  case ARM::Q13: return ARM::D26;
2842  case ARM::Q14: return ARM::D28;
2843  case ARM::Q15: return ARM::D30;
2844  }
2845}
2846
2847/// Parse a register list.
2848bool ARMAsmParser::
2849parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2850  assert(Parser.getTok().is(AsmToken::LCurly) &&
2851         "Token is not a Left Curly Brace");
2852  SMLoc S = Parser.getTok().getLoc();
2853  Parser.Lex(); // Eat '{' token.
2854  SMLoc RegLoc = Parser.getTok().getLoc();
2855
2856  // Check the first register in the list to see what register class
2857  // this is a list of.
2858  int Reg = tryParseRegister();
2859  if (Reg == -1)
2860    return Error(RegLoc, "register expected");
2861
2862  // The reglist instructions have at most 16 registers, so reserve
2863  // space for that many.
2864  SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2865
2866  // Allow Q regs and just interpret them as the two D sub-registers.
2867  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2868    Reg = getDRegFromQReg(Reg);
2869    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2870    ++Reg;
2871  }
2872  const MCRegisterClass *RC;
2873  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2874    RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2875  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2876    RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2877  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2878    RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2879  else
2880    return Error(RegLoc, "invalid register in register list");
2881
2882  // Store the register.
2883  Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2884
2885  // This starts immediately after the first register token in the list,
2886  // so we can see either a comma or a minus (range separator) as a legal
2887  // next token.
2888  while (Parser.getTok().is(AsmToken::Comma) ||
2889         Parser.getTok().is(AsmToken::Minus)) {
2890    if (Parser.getTok().is(AsmToken::Minus)) {
2891      Parser.Lex(); // Eat the minus.
2892      SMLoc EndLoc = Parser.getTok().getLoc();
2893      int EndReg = tryParseRegister();
2894      if (EndReg == -1)
2895        return Error(EndLoc, "register expected");
2896      // Allow Q regs and just interpret them as the two D sub-registers.
2897      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2898        EndReg = getDRegFromQReg(EndReg) + 1;
2899      // If the register is the same as the start reg, there's nothing
2900      // more to do.
2901      if (Reg == EndReg)
2902        continue;
2903      // The register must be in the same register class as the first.
2904      if (!RC->contains(EndReg))
2905        return Error(EndLoc, "invalid register in register list");
2906      // Ranges must go from low to high.
2907      if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
2908        return Error(EndLoc, "bad range in register list");
2909
2910      // Add all the registers in the range to the register list.
2911      while (Reg != EndReg) {
2912        Reg = getNextRegister(Reg);
2913        Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2914      }
2915      continue;
2916    }
2917    Parser.Lex(); // Eat the comma.
2918    RegLoc = Parser.getTok().getLoc();
2919    int OldReg = Reg;
2920    const AsmToken RegTok = Parser.getTok();
2921    Reg = tryParseRegister();
2922    if (Reg == -1)
2923      return Error(RegLoc, "register expected");
2924    // Allow Q regs and just interpret them as the two D sub-registers.
2925    bool isQReg = false;
2926    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2927      Reg = getDRegFromQReg(Reg);
2928      isQReg = true;
2929    }
2930    // The register must be in the same register class as the first.
2931    if (!RC->contains(Reg))
2932      return Error(RegLoc, "invalid register in register list");
2933    // List must be monotonically increasing.
2934    if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
2935      if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2936        Warning(RegLoc, "register list not in ascending order");
2937      else
2938        return Error(RegLoc, "register list not in ascending order");
2939    }
2940    if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
2941      Warning(RegLoc, "duplicated register (" + RegTok.getString() +
2942              ") in register list");
2943      continue;
2944    }
2945    // VFP register lists must also be contiguous.
2946    // It's OK to use the enumeration values directly here rather, as the
2947    // VFP register classes have the enum sorted properly.
2948    if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2949        Reg != OldReg + 1)
2950      return Error(RegLoc, "non-contiguous register range");
2951    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2952    if (isQReg)
2953      Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2954  }
2955
2956  SMLoc E = Parser.getTok().getLoc();
2957  if (Parser.getTok().isNot(AsmToken::RCurly))
2958    return Error(E, "'}' expected");
2959  Parser.Lex(); // Eat '}' token.
2960
2961  // Push the register list operand.
2962  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2963
2964  // The ARM system instruction variants for LDM/STM have a '^' token here.
2965  if (Parser.getTok().is(AsmToken::Caret)) {
2966    Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
2967    Parser.Lex(); // Eat '^' token.
2968  }
2969
2970  return false;
2971}
2972
2973// Helper function to parse the lane index for vector lists.
2974ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2975parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) {
2976  Index = 0; // Always return a defined index value.
2977  if (Parser.getTok().is(AsmToken::LBrac)) {
2978    Parser.Lex(); // Eat the '['.
2979    if (Parser.getTok().is(AsmToken::RBrac)) {
2980      // "Dn[]" is the 'all lanes' syntax.
2981      LaneKind = AllLanes;
2982      Parser.Lex(); // Eat the ']'.
2983      return MatchOperand_Success;
2984    }
2985
2986    // There's an optional '#' token here. Normally there wouldn't be, but
2987    // inline assemble puts one in, and it's friendly to accept that.
2988    if (Parser.getTok().is(AsmToken::Hash))
2989      Parser.Lex(); // Eat the '#'
2990
2991    const MCExpr *LaneIndex;
2992    SMLoc Loc = Parser.getTok().getLoc();
2993    if (getParser().ParseExpression(LaneIndex)) {
2994      Error(Loc, "illegal expression");
2995      return MatchOperand_ParseFail;
2996    }
2997    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
2998    if (!CE) {
2999      Error(Loc, "lane index must be empty or an integer");
3000      return MatchOperand_ParseFail;
3001    }
3002    if (Parser.getTok().isNot(AsmToken::RBrac)) {
3003      Error(Parser.getTok().getLoc(), "']' expected");
3004      return MatchOperand_ParseFail;
3005    }
3006    Parser.Lex(); // Eat the ']'.
3007    int64_t Val = CE->getValue();
3008
3009    // FIXME: Make this range check context sensitive for .8, .16, .32.
3010    if (Val < 0 || Val > 7) {
3011      Error(Parser.getTok().getLoc(), "lane index out of range");
3012      return MatchOperand_ParseFail;
3013    }
3014    Index = Val;
3015    LaneKind = IndexedLane;
3016    return MatchOperand_Success;
3017  }
3018  LaneKind = NoLanes;
3019  return MatchOperand_Success;
3020}
3021
3022// parse a vector register list
3023ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3024parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3025  VectorLaneTy LaneKind;
3026  unsigned LaneIndex;
3027  SMLoc S = Parser.getTok().getLoc();
3028  // As an extension (to match gas), support a plain D register or Q register
3029  // (without encosing curly braces) as a single or double entry list,
3030  // respectively.
3031  if (Parser.getTok().is(AsmToken::Identifier)) {
3032    int Reg = tryParseRegister();
3033    if (Reg == -1)
3034      return MatchOperand_NoMatch;
3035    SMLoc E = Parser.getTok().getLoc();
3036    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3037      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
3038      if (Res != MatchOperand_Success)
3039        return Res;
3040      switch (LaneKind) {
3041      case NoLanes:
3042        E = Parser.getTok().getLoc();
3043        Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3044        break;
3045      case AllLanes:
3046        E = Parser.getTok().getLoc();
3047        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3048                                                                S, E));
3049        break;
3050      case IndexedLane:
3051        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3052                                                               LaneIndex,
3053                                                               false, S, E));
3054        break;
3055      }
3056      return MatchOperand_Success;
3057    }
3058    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3059      Reg = getDRegFromQReg(Reg);
3060      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
3061      if (Res != MatchOperand_Success)
3062        return Res;
3063      switch (LaneKind) {
3064      case NoLanes:
3065        E = Parser.getTok().getLoc();
3066        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3067                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3068        Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3069        break;
3070      case AllLanes:
3071        E = Parser.getTok().getLoc();
3072        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3073                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3074        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3075                                                                S, E));
3076        break;
3077      case IndexedLane:
3078        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3079                                                               LaneIndex,
3080                                                               false, S, E));
3081        break;
3082      }
3083      return MatchOperand_Success;
3084    }
3085    Error(S, "vector register expected");
3086    return MatchOperand_ParseFail;
3087  }
3088
3089  if (Parser.getTok().isNot(AsmToken::LCurly))
3090    return MatchOperand_NoMatch;
3091
3092  Parser.Lex(); // Eat '{' token.
3093  SMLoc RegLoc = Parser.getTok().getLoc();
3094
3095  int Reg = tryParseRegister();
3096  if (Reg == -1) {
3097    Error(RegLoc, "register expected");
3098    return MatchOperand_ParseFail;
3099  }
3100  unsigned Count = 1;
3101  int Spacing = 0;
3102  unsigned FirstReg = Reg;
3103  // The list is of D registers, but we also allow Q regs and just interpret
3104  // them as the two D sub-registers.
3105  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3106    FirstReg = Reg = getDRegFromQReg(Reg);
3107    Spacing = 1; // double-spacing requires explicit D registers, otherwise
3108                 // it's ambiguous with four-register single spaced.
3109    ++Reg;
3110    ++Count;
3111  }
3112  if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success)
3113    return MatchOperand_ParseFail;
3114
3115  while (Parser.getTok().is(AsmToken::Comma) ||
3116         Parser.getTok().is(AsmToken::Minus)) {
3117    if (Parser.getTok().is(AsmToken::Minus)) {
3118      if (!Spacing)
3119        Spacing = 1; // Register range implies a single spaced list.
3120      else if (Spacing == 2) {
3121        Error(Parser.getTok().getLoc(),
3122              "sequential registers in double spaced list");
3123        return MatchOperand_ParseFail;
3124      }
3125      Parser.Lex(); // Eat the minus.
3126      SMLoc EndLoc = Parser.getTok().getLoc();
3127      int EndReg = tryParseRegister();
3128      if (EndReg == -1) {
3129        Error(EndLoc, "register expected");
3130        return MatchOperand_ParseFail;
3131      }
3132      // Allow Q regs and just interpret them as the two D sub-registers.
3133      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3134        EndReg = getDRegFromQReg(EndReg) + 1;
3135      // If the register is the same as the start reg, there's nothing
3136      // more to do.
3137      if (Reg == EndReg)
3138        continue;
3139      // The register must be in the same register class as the first.
3140      if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3141        Error(EndLoc, "invalid register in register list");
3142        return MatchOperand_ParseFail;
3143      }
3144      // Ranges must go from low to high.
3145      if (Reg > EndReg) {
3146        Error(EndLoc, "bad range in register list");
3147        return MatchOperand_ParseFail;
3148      }
3149      // Parse the lane specifier if present.
3150      VectorLaneTy NextLaneKind;
3151      unsigned NextLaneIndex;
3152      if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3153        return MatchOperand_ParseFail;
3154      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3155        Error(EndLoc, "mismatched lane index in register list");
3156        return MatchOperand_ParseFail;
3157      }
3158      EndLoc = Parser.getTok().getLoc();
3159
3160      // Add all the registers in the range to the register list.
3161      Count += EndReg - Reg;
3162      Reg = EndReg;
3163      continue;
3164    }
3165    Parser.Lex(); // Eat the comma.
3166    RegLoc = Parser.getTok().getLoc();
3167    int OldReg = Reg;
3168    Reg = tryParseRegister();
3169    if (Reg == -1) {
3170      Error(RegLoc, "register expected");
3171      return MatchOperand_ParseFail;
3172    }
3173    // vector register lists must be contiguous.
3174    // It's OK to use the enumeration values directly here rather, as the
3175    // VFP register classes have the enum sorted properly.
3176    //
3177    // The list is of D registers, but we also allow Q regs and just interpret
3178    // them as the two D sub-registers.
3179    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3180      if (!Spacing)
3181        Spacing = 1; // Register range implies a single spaced list.
3182      else if (Spacing == 2) {
3183        Error(RegLoc,
3184              "invalid register in double-spaced list (must be 'D' register')");
3185        return MatchOperand_ParseFail;
3186      }
3187      Reg = getDRegFromQReg(Reg);
3188      if (Reg != OldReg + 1) {
3189        Error(RegLoc, "non-contiguous register range");
3190        return MatchOperand_ParseFail;
3191      }
3192      ++Reg;
3193      Count += 2;
3194      // Parse the lane specifier if present.
3195      VectorLaneTy NextLaneKind;
3196      unsigned NextLaneIndex;
3197      SMLoc EndLoc = Parser.getTok().getLoc();
3198      if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3199        return MatchOperand_ParseFail;
3200      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3201        Error(EndLoc, "mismatched lane index in register list");
3202        return MatchOperand_ParseFail;
3203      }
3204      continue;
3205    }
3206    // Normal D register.
3207    // Figure out the register spacing (single or double) of the list if
3208    // we don't know it already.
3209    if (!Spacing)
3210      Spacing = 1 + (Reg == OldReg + 2);
3211
3212    // Just check that it's contiguous and keep going.
3213    if (Reg != OldReg + Spacing) {
3214      Error(RegLoc, "non-contiguous register range");
3215      return MatchOperand_ParseFail;
3216    }
3217    ++Count;
3218    // Parse the lane specifier if present.
3219    VectorLaneTy NextLaneKind;
3220    unsigned NextLaneIndex;
3221    SMLoc EndLoc = Parser.getTok().getLoc();
3222    if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3223      return MatchOperand_ParseFail;
3224    if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3225      Error(EndLoc, "mismatched lane index in register list");
3226      return MatchOperand_ParseFail;
3227    }
3228  }
3229
3230  SMLoc E = Parser.getTok().getLoc();
3231  if (Parser.getTok().isNot(AsmToken::RCurly)) {
3232    Error(E, "'}' expected");
3233    return MatchOperand_ParseFail;
3234  }
3235  Parser.Lex(); // Eat '}' token.
3236
3237  switch (LaneKind) {
3238  case NoLanes:
3239    // Two-register operands have been converted to the
3240    // composite register classes.
3241    if (Count == 2) {
3242      const MCRegisterClass *RC = (Spacing == 1) ?
3243        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3244        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3245      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3246    }
3247
3248    Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3249                                                    (Spacing == 2), S, E));
3250    break;
3251  case AllLanes:
3252    // Two-register operands have been converted to the
3253    // composite register classes.
3254    if (Count == 2) {
3255      const MCRegisterClass *RC = (Spacing == 1) ?
3256        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3257        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3258      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3259    }
3260    Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3261                                                            (Spacing == 2),
3262                                                            S, E));
3263    break;
3264  case IndexedLane:
3265    Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3266                                                           LaneIndex,
3267                                                           (Spacing == 2),
3268                                                           S, E));
3269    break;
3270  }
3271  return MatchOperand_Success;
3272}
3273
3274/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3275ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3276parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3277  SMLoc S = Parser.getTok().getLoc();
3278  const AsmToken &Tok = Parser.getTok();
3279  unsigned Opt;
3280
3281  if (Tok.is(AsmToken::Identifier)) {
3282    StringRef OptStr = Tok.getString();
3283
3284    Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3285      .Case("sy",    ARM_MB::SY)
3286      .Case("st",    ARM_MB::ST)
3287      .Case("sh",    ARM_MB::ISH)
3288      .Case("ish",   ARM_MB::ISH)
3289      .Case("shst",  ARM_MB::ISHST)
3290      .Case("ishst", ARM_MB::ISHST)
3291      .Case("nsh",   ARM_MB::NSH)
3292      .Case("un",    ARM_MB::NSH)
3293      .Case("nshst", ARM_MB::NSHST)
3294      .Case("unst",  ARM_MB::NSHST)
3295      .Case("osh",   ARM_MB::OSH)
3296      .Case("oshst", ARM_MB::OSHST)
3297      .Default(~0U);
3298
3299    if (Opt == ~0U)
3300      return MatchOperand_NoMatch;
3301
3302    Parser.Lex(); // Eat identifier token.
3303  } else if (Tok.is(AsmToken::Hash) ||
3304             Tok.is(AsmToken::Dollar) ||
3305             Tok.is(AsmToken::Integer)) {
3306    if (Parser.getTok().isNot(AsmToken::Integer))
3307      Parser.Lex(); // Eat the '#'.
3308    SMLoc Loc = Parser.getTok().getLoc();
3309
3310    const MCExpr *MemBarrierID;
3311    if (getParser().ParseExpression(MemBarrierID)) {
3312      Error(Loc, "illegal expression");
3313      return MatchOperand_ParseFail;
3314    }
3315
3316    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3317    if (!CE) {
3318      Error(Loc, "constant expression expected");
3319      return MatchOperand_ParseFail;
3320    }
3321
3322    int Val = CE->getValue();
3323    if (Val & ~0xf) {
3324      Error(Loc, "immediate value out of range");
3325      return MatchOperand_ParseFail;
3326    }
3327
3328    Opt = ARM_MB::RESERVED_0 + Val;
3329  } else
3330    return MatchOperand_ParseFail;
3331
3332  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3333  return MatchOperand_Success;
3334}
3335
3336/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3337ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3338parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3339  SMLoc S = Parser.getTok().getLoc();
3340  const AsmToken &Tok = Parser.getTok();
3341  if (!Tok.is(AsmToken::Identifier))
3342    return MatchOperand_NoMatch;
3343  StringRef IFlagsStr = Tok.getString();
3344
3345  // An iflags string of "none" is interpreted to mean that none of the AIF
3346  // bits are set.  Not a terribly useful instruction, but a valid encoding.
3347  unsigned IFlags = 0;
3348  if (IFlagsStr != "none") {
3349        for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3350      unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3351        .Case("a", ARM_PROC::A)
3352        .Case("i", ARM_PROC::I)
3353        .Case("f", ARM_PROC::F)
3354        .Default(~0U);
3355
3356      // If some specific iflag is already set, it means that some letter is
3357      // present more than once, this is not acceptable.
3358      if (Flag == ~0U || (IFlags & Flag))
3359        return MatchOperand_NoMatch;
3360
3361      IFlags |= Flag;
3362    }
3363  }
3364
3365  Parser.Lex(); // Eat identifier token.
3366  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3367  return MatchOperand_Success;
3368}
3369
3370/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3371ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3372parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3373  SMLoc S = Parser.getTok().getLoc();
3374  const AsmToken &Tok = Parser.getTok();
3375  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3376  StringRef Mask = Tok.getString();
3377
3378  if (isMClass()) {
3379    // See ARMv6-M 10.1.1
3380    std::string Name = Mask.lower();
3381    unsigned FlagsVal = StringSwitch<unsigned>(Name)
3382      // Note: in the documentation:
3383      //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3384      //  for MSR APSR_nzcvq.
3385      // but we do make it an alias here.  This is so to get the "mask encoding"
3386      // bits correct on MSR APSR writes.
3387      //
3388      // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3389      // should really only be allowed when writing a special register.  Note
3390      // they get dropped in the MRS instruction reading a special register as
3391      // the SYSm field is only 8 bits.
3392      //
3393      // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3394      // includes the DSP extension but that is not checked.
3395      .Case("apsr", 0x800)
3396      .Case("apsr_nzcvq", 0x800)
3397      .Case("apsr_g", 0x400)
3398      .Case("apsr_nzcvqg", 0xc00)
3399      .Case("iapsr", 0x801)
3400      .Case("iapsr_nzcvq", 0x801)
3401      .Case("iapsr_g", 0x401)
3402      .Case("iapsr_nzcvqg", 0xc01)
3403      .Case("eapsr", 0x802)
3404      .Case("eapsr_nzcvq", 0x802)
3405      .Case("eapsr_g", 0x402)
3406      .Case("eapsr_nzcvqg", 0xc02)
3407      .Case("xpsr", 0x803)
3408      .Case("xpsr_nzcvq", 0x803)
3409      .Case("xpsr_g", 0x403)
3410      .Case("xpsr_nzcvqg", 0xc03)
3411      .Case("ipsr", 0x805)
3412      .Case("epsr", 0x806)
3413      .Case("iepsr", 0x807)
3414      .Case("msp", 0x808)
3415      .Case("psp", 0x809)
3416      .Case("primask", 0x810)
3417      .Case("basepri", 0x811)
3418      .Case("basepri_max", 0x812)
3419      .Case("faultmask", 0x813)
3420      .Case("control", 0x814)
3421      .Default(~0U);
3422
3423    if (FlagsVal == ~0U)
3424      return MatchOperand_NoMatch;
3425
3426    if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3427      // basepri, basepri_max and faultmask only valid for V7m.
3428      return MatchOperand_NoMatch;
3429
3430    Parser.Lex(); // Eat identifier token.
3431    Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3432    return MatchOperand_Success;
3433  }
3434
3435  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3436  size_t Start = 0, Next = Mask.find('_');
3437  StringRef Flags = "";
3438  std::string SpecReg = Mask.slice(Start, Next).lower();
3439  if (Next != StringRef::npos)
3440    Flags = Mask.slice(Next+1, Mask.size());
3441
3442  // FlagsVal contains the complete mask:
3443  // 3-0: Mask
3444  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3445  unsigned FlagsVal = 0;
3446
3447  if (SpecReg == "apsr") {
3448    FlagsVal = StringSwitch<unsigned>(Flags)
3449    .Case("nzcvq",  0x8) // same as CPSR_f
3450    .Case("g",      0x4) // same as CPSR_s
3451    .Case("nzcvqg", 0xc) // same as CPSR_fs
3452    .Default(~0U);
3453
3454    if (FlagsVal == ~0U) {
3455      if (!Flags.empty())
3456        return MatchOperand_NoMatch;
3457      else
3458        FlagsVal = 8; // No flag
3459    }
3460  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3461    // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3462    if (Flags == "all" || Flags == "")
3463      Flags = "fc";
3464    for (int i = 0, e = Flags.size(); i != e; ++i) {
3465      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3466      .Case("c", 1)
3467      .Case("x", 2)
3468      .Case("s", 4)
3469      .Case("f", 8)
3470      .Default(~0U);
3471
3472      // If some specific flag is already set, it means that some letter is
3473      // present more than once, this is not acceptable.
3474      if (FlagsVal == ~0U || (FlagsVal & Flag))
3475        return MatchOperand_NoMatch;
3476      FlagsVal |= Flag;
3477    }
3478  } else // No match for special register.
3479    return MatchOperand_NoMatch;
3480
3481  // Special register without flags is NOT equivalent to "fc" flags.
3482  // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
3483  // two lines would enable gas compatibility at the expense of breaking
3484  // round-tripping.
3485  //
3486  // if (!FlagsVal)
3487  //  FlagsVal = 0x9;
3488
3489  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3490  if (SpecReg == "spsr")
3491    FlagsVal |= 16;
3492
3493  Parser.Lex(); // Eat identifier token.
3494  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3495  return MatchOperand_Success;
3496}
3497
3498ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3499parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3500            int Low, int High) {
3501  const AsmToken &Tok = Parser.getTok();
3502  if (Tok.isNot(AsmToken::Identifier)) {
3503    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3504    return MatchOperand_ParseFail;
3505  }
3506  StringRef ShiftName = Tok.getString();
3507  std::string LowerOp = Op.lower();
3508  std::string UpperOp = Op.upper();
3509  if (ShiftName != LowerOp && ShiftName != UpperOp) {
3510    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3511    return MatchOperand_ParseFail;
3512  }
3513  Parser.Lex(); // Eat shift type token.
3514
3515  // There must be a '#' and a shift amount.
3516  if (Parser.getTok().isNot(AsmToken::Hash) &&
3517      Parser.getTok().isNot(AsmToken::Dollar)) {
3518    Error(Parser.getTok().getLoc(), "'#' expected");
3519    return MatchOperand_ParseFail;
3520  }
3521  Parser.Lex(); // Eat hash token.
3522
3523  const MCExpr *ShiftAmount;
3524  SMLoc Loc = Parser.getTok().getLoc();
3525  if (getParser().ParseExpression(ShiftAmount)) {
3526    Error(Loc, "illegal expression");
3527    return MatchOperand_ParseFail;
3528  }
3529  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3530  if (!CE) {
3531    Error(Loc, "constant expression expected");
3532    return MatchOperand_ParseFail;
3533  }
3534  int Val = CE->getValue();
3535  if (Val < Low || Val > High) {
3536    Error(Loc, "immediate value out of range");
3537    return MatchOperand_ParseFail;
3538  }
3539
3540  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
3541
3542  return MatchOperand_Success;
3543}
3544
3545ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3546parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3547  const AsmToken &Tok = Parser.getTok();
3548  SMLoc S = Tok.getLoc();
3549  if (Tok.isNot(AsmToken::Identifier)) {
3550    Error(Tok.getLoc(), "'be' or 'le' operand expected");
3551    return MatchOperand_ParseFail;
3552  }
3553  int Val = StringSwitch<int>(Tok.getString())
3554    .Case("be", 1)
3555    .Case("le", 0)
3556    .Default(-1);
3557  Parser.Lex(); // Eat the token.
3558
3559  if (Val == -1) {
3560    Error(Tok.getLoc(), "'be' or 'le' operand expected");
3561    return MatchOperand_ParseFail;
3562  }
3563  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3564                                                                  getContext()),
3565                                           S, Parser.getTok().getLoc()));
3566  return MatchOperand_Success;
3567}
3568
3569/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3570/// instructions. Legal values are:
3571///     lsl #n  'n' in [0,31]
3572///     asr #n  'n' in [1,32]
3573///             n == 32 encoded as n == 0.
3574ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3575parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3576  const AsmToken &Tok = Parser.getTok();
3577  SMLoc S = Tok.getLoc();
3578  if (Tok.isNot(AsmToken::Identifier)) {
3579    Error(S, "shift operator 'asr' or 'lsl' expected");
3580    return MatchOperand_ParseFail;
3581  }
3582  StringRef ShiftName = Tok.getString();
3583  bool isASR;
3584  if (ShiftName == "lsl" || ShiftName == "LSL")
3585    isASR = false;
3586  else if (ShiftName == "asr" || ShiftName == "ASR")
3587    isASR = true;
3588  else {
3589    Error(S, "shift operator 'asr' or 'lsl' expected");
3590    return MatchOperand_ParseFail;
3591  }
3592  Parser.Lex(); // Eat the operator.
3593
3594  // A '#' and a shift amount.
3595  if (Parser.getTok().isNot(AsmToken::Hash) &&
3596      Parser.getTok().isNot(AsmToken::Dollar)) {
3597    Error(Parser.getTok().getLoc(), "'#' expected");
3598    return MatchOperand_ParseFail;
3599  }
3600  Parser.Lex(); // Eat hash token.
3601
3602  const MCExpr *ShiftAmount;
3603  SMLoc E = Parser.getTok().getLoc();
3604  if (getParser().ParseExpression(ShiftAmount)) {
3605    Error(E, "malformed shift expression");
3606    return MatchOperand_ParseFail;
3607  }
3608  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3609  if (!CE) {
3610    Error(E, "shift amount must be an immediate");
3611    return MatchOperand_ParseFail;
3612  }
3613
3614  int64_t Val = CE->getValue();
3615  if (isASR) {
3616    // Shift amount must be in [1,32]
3617    if (Val < 1 || Val > 32) {
3618      Error(E, "'asr' shift amount must be in range [1,32]");
3619      return MatchOperand_ParseFail;
3620    }
3621    // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3622    if (isThumb() && Val == 32) {
3623      Error(E, "'asr #32' shift amount not allowed in Thumb mode");
3624      return MatchOperand_ParseFail;
3625    }
3626    if (Val == 32) Val = 0;
3627  } else {
3628    // Shift amount must be in [1,32]
3629    if (Val < 0 || Val > 31) {
3630      Error(E, "'lsr' shift amount must be in range [0,31]");
3631      return MatchOperand_ParseFail;
3632    }
3633  }
3634
3635  E = Parser.getTok().getLoc();
3636  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
3637
3638  return MatchOperand_Success;
3639}
3640
3641/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3642/// of instructions. Legal values are:
3643///     ror #n  'n' in {0, 8, 16, 24}
3644ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3645parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3646  const AsmToken &Tok = Parser.getTok();
3647  SMLoc S = Tok.getLoc();
3648  if (Tok.isNot(AsmToken::Identifier))
3649    return MatchOperand_NoMatch;
3650  StringRef ShiftName = Tok.getString();
3651  if (ShiftName != "ror" && ShiftName != "ROR")
3652    return MatchOperand_NoMatch;
3653  Parser.Lex(); // Eat the operator.
3654
3655  // A '#' and a rotate amount.
3656  if (Parser.getTok().isNot(AsmToken::Hash) &&
3657      Parser.getTok().isNot(AsmToken::Dollar)) {
3658    Error(Parser.getTok().getLoc(), "'#' expected");
3659    return MatchOperand_ParseFail;
3660  }
3661  Parser.Lex(); // Eat hash token.
3662
3663  const MCExpr *ShiftAmount;
3664  SMLoc E = Parser.getTok().getLoc();
3665  if (getParser().ParseExpression(ShiftAmount)) {
3666    Error(E, "malformed rotate expression");
3667    return MatchOperand_ParseFail;
3668  }
3669  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3670  if (!CE) {
3671    Error(E, "rotate amount must be an immediate");
3672    return MatchOperand_ParseFail;
3673  }
3674
3675  int64_t Val = CE->getValue();
3676  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3677  // normally, zero is represented in asm by omitting the rotate operand
3678  // entirely.
3679  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3680    Error(E, "'ror' rotate amount must be 8, 16, or 24");
3681    return MatchOperand_ParseFail;
3682  }
3683
3684  E = Parser.getTok().getLoc();
3685  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
3686
3687  return MatchOperand_Success;
3688}
3689
3690ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3691parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3692  SMLoc S = Parser.getTok().getLoc();
3693  // The bitfield descriptor is really two operands, the LSB and the width.
3694  if (Parser.getTok().isNot(AsmToken::Hash) &&
3695      Parser.getTok().isNot(AsmToken::Dollar)) {
3696    Error(Parser.getTok().getLoc(), "'#' expected");
3697    return MatchOperand_ParseFail;
3698  }
3699  Parser.Lex(); // Eat hash token.
3700
3701  const MCExpr *LSBExpr;
3702  SMLoc E = Parser.getTok().getLoc();
3703  if (getParser().ParseExpression(LSBExpr)) {
3704    Error(E, "malformed immediate expression");
3705    return MatchOperand_ParseFail;
3706  }
3707  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3708  if (!CE) {
3709    Error(E, "'lsb' operand must be an immediate");
3710    return MatchOperand_ParseFail;
3711  }
3712
3713  int64_t LSB = CE->getValue();
3714  // The LSB must be in the range [0,31]
3715  if (LSB < 0 || LSB > 31) {
3716    Error(E, "'lsb' operand must be in the range [0,31]");
3717    return MatchOperand_ParseFail;
3718  }
3719  E = Parser.getTok().getLoc();
3720
3721  // Expect another immediate operand.
3722  if (Parser.getTok().isNot(AsmToken::Comma)) {
3723    Error(Parser.getTok().getLoc(), "too few operands");
3724    return MatchOperand_ParseFail;
3725  }
3726  Parser.Lex(); // Eat hash token.
3727  if (Parser.getTok().isNot(AsmToken::Hash) &&
3728      Parser.getTok().isNot(AsmToken::Dollar)) {
3729    Error(Parser.getTok().getLoc(), "'#' expected");
3730    return MatchOperand_ParseFail;
3731  }
3732  Parser.Lex(); // Eat hash token.
3733
3734  const MCExpr *WidthExpr;
3735  if (getParser().ParseExpression(WidthExpr)) {
3736    Error(E, "malformed immediate expression");
3737    return MatchOperand_ParseFail;
3738  }
3739  CE = dyn_cast<MCConstantExpr>(WidthExpr);
3740  if (!CE) {
3741    Error(E, "'width' operand must be an immediate");
3742    return MatchOperand_ParseFail;
3743  }
3744
3745  int64_t Width = CE->getValue();
3746  // The LSB must be in the range [1,32-lsb]
3747  if (Width < 1 || Width > 32 - LSB) {
3748    Error(E, "'width' operand must be in the range [1,32-lsb]");
3749    return MatchOperand_ParseFail;
3750  }
3751  E = Parser.getTok().getLoc();
3752
3753  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
3754
3755  return MatchOperand_Success;
3756}
3757
3758ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3759parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3760  // Check for a post-index addressing register operand. Specifically:
3761  // postidx_reg := '+' register {, shift}
3762  //              | '-' register {, shift}
3763  //              | register {, shift}
3764
3765  // This method must return MatchOperand_NoMatch without consuming any tokens
3766  // in the case where there is no match, as other alternatives take other
3767  // parse methods.
3768  AsmToken Tok = Parser.getTok();
3769  SMLoc S = Tok.getLoc();
3770  bool haveEaten = false;
3771  bool isAdd = true;
3772  int Reg = -1;
3773  if (Tok.is(AsmToken::Plus)) {
3774    Parser.Lex(); // Eat the '+' token.
3775    haveEaten = true;
3776  } else if (Tok.is(AsmToken::Minus)) {
3777    Parser.Lex(); // Eat the '-' token.
3778    isAdd = false;
3779    haveEaten = true;
3780  }
3781  if (Parser.getTok().is(AsmToken::Identifier))
3782    Reg = tryParseRegister();
3783  if (Reg == -1) {
3784    if (!haveEaten)
3785      return MatchOperand_NoMatch;
3786    Error(Parser.getTok().getLoc(), "register expected");
3787    return MatchOperand_ParseFail;
3788  }
3789  SMLoc E = Parser.getTok().getLoc();
3790
3791  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3792  unsigned ShiftImm = 0;
3793  if (Parser.getTok().is(AsmToken::Comma)) {
3794    Parser.Lex(); // Eat the ','.
3795    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3796      return MatchOperand_ParseFail;
3797  }
3798
3799  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3800                                                  ShiftImm, S, E));
3801
3802  return MatchOperand_Success;
3803}
3804
3805ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3806parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3807  // Check for a post-index addressing register operand. Specifically:
3808  // am3offset := '+' register
3809  //              | '-' register
3810  //              | register
3811  //              | # imm
3812  //              | # + imm
3813  //              | # - imm
3814
3815  // This method must return MatchOperand_NoMatch without consuming any tokens
3816  // in the case where there is no match, as other alternatives take other
3817  // parse methods.
3818  AsmToken Tok = Parser.getTok();
3819  SMLoc S = Tok.getLoc();
3820
3821  // Do immediates first, as we always parse those if we have a '#'.
3822  if (Parser.getTok().is(AsmToken::Hash) ||
3823      Parser.getTok().is(AsmToken::Dollar)) {
3824    Parser.Lex(); // Eat the '#'.
3825    // Explicitly look for a '-', as we need to encode negative zero
3826    // differently.
3827    bool isNegative = Parser.getTok().is(AsmToken::Minus);
3828    const MCExpr *Offset;
3829    if (getParser().ParseExpression(Offset))
3830      return MatchOperand_ParseFail;
3831    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3832    if (!CE) {
3833      Error(S, "constant expression expected");
3834      return MatchOperand_ParseFail;
3835    }
3836    SMLoc E = Tok.getLoc();
3837    // Negative zero is encoded as the flag value INT32_MIN.
3838    int32_t Val = CE->getValue();
3839    if (isNegative && Val == 0)
3840      Val = INT32_MIN;
3841
3842    Operands.push_back(
3843      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3844
3845    return MatchOperand_Success;
3846  }
3847
3848
3849  bool haveEaten = false;
3850  bool isAdd = true;
3851  int Reg = -1;
3852  if (Tok.is(AsmToken::Plus)) {
3853    Parser.Lex(); // Eat the '+' token.
3854    haveEaten = true;
3855  } else if (Tok.is(AsmToken::Minus)) {
3856    Parser.Lex(); // Eat the '-' token.
3857    isAdd = false;
3858    haveEaten = true;
3859  }
3860  if (Parser.getTok().is(AsmToken::Identifier))
3861    Reg = tryParseRegister();
3862  if (Reg == -1) {
3863    if (!haveEaten)
3864      return MatchOperand_NoMatch;
3865    Error(Parser.getTok().getLoc(), "register expected");
3866    return MatchOperand_ParseFail;
3867  }
3868  SMLoc E = Parser.getTok().getLoc();
3869
3870  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3871                                                  0, S, E));
3872
3873  return MatchOperand_Success;
3874}
3875
3876/// cvtT2LdrdPre - Convert parsed operands to MCInst.
3877/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3878/// when they refer multiple MIOperands inside a single one.
3879void ARMAsmParser::
3880cvtT2LdrdPre(MCInst &Inst,
3881             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3882  // Rt, Rt2
3883  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3884  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3885  // Create a writeback register dummy placeholder.
3886  Inst.addOperand(MCOperand::CreateReg(0));
3887  // addr
3888  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3889  // pred
3890  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3891}
3892
3893/// cvtT2StrdPre - Convert parsed operands to MCInst.
3894/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3895/// when they refer multiple MIOperands inside a single one.
3896void ARMAsmParser::
3897cvtT2StrdPre(MCInst &Inst,
3898             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3899  // Create a writeback register dummy placeholder.
3900  Inst.addOperand(MCOperand::CreateReg(0));
3901  // Rt, Rt2
3902  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3903  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3904  // addr
3905  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3906  // pred
3907  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3908}
3909
3910/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3911/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3912/// when they refer multiple MIOperands inside a single one.
3913void ARMAsmParser::
3914cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
3915                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3916  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3917
3918  // Create a writeback register dummy placeholder.
3919  Inst.addOperand(MCOperand::CreateImm(0));
3920
3921  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3922  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3923}
3924
3925/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3926/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3927/// when they refer multiple MIOperands inside a single one.
3928void ARMAsmParser::
3929cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
3930                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3931  // Create a writeback register dummy placeholder.
3932  Inst.addOperand(MCOperand::CreateImm(0));
3933  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3934  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3935  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3936}
3937
3938/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3939/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3940/// when they refer multiple MIOperands inside a single one.
3941void ARMAsmParser::
3942cvtLdWriteBackRegAddrMode2(MCInst &Inst,
3943                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3944  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3945
3946  // Create a writeback register dummy placeholder.
3947  Inst.addOperand(MCOperand::CreateImm(0));
3948
3949  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3950  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3951}
3952
3953/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3954/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3955/// when they refer multiple MIOperands inside a single one.
3956void ARMAsmParser::
3957cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
3958                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3959  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3960
3961  // Create a writeback register dummy placeholder.
3962  Inst.addOperand(MCOperand::CreateImm(0));
3963
3964  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3965  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3966}
3967
3968
3969/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3970/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3971/// when they refer multiple MIOperands inside a single one.
3972void ARMAsmParser::
3973cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
3974                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3975  // Create a writeback register dummy placeholder.
3976  Inst.addOperand(MCOperand::CreateImm(0));
3977  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3978  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3979  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3980}
3981
3982/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3983/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3984/// when they refer multiple MIOperands inside a single one.
3985void ARMAsmParser::
3986cvtStWriteBackRegAddrMode2(MCInst &Inst,
3987                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3988  // Create a writeback register dummy placeholder.
3989  Inst.addOperand(MCOperand::CreateImm(0));
3990  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3991  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3992  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3993}
3994
3995/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3996/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3997/// when they refer multiple MIOperands inside a single one.
3998void ARMAsmParser::
3999cvtStWriteBackRegAddrMode3(MCInst &Inst,
4000                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4001  // Create a writeback register dummy placeholder.
4002  Inst.addOperand(MCOperand::CreateImm(0));
4003  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4004  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4005  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4006}
4007
4008/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
4009/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4010/// when they refer multiple MIOperands inside a single one.
4011void ARMAsmParser::
4012cvtLdExtTWriteBackImm(MCInst &Inst,
4013                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4014  // Rt
4015  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4016  // Create a writeback register dummy placeholder.
4017  Inst.addOperand(MCOperand::CreateImm(0));
4018  // addr
4019  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4020  // offset
4021  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4022  // pred
4023  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4024}
4025
4026/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
4027/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4028/// when they refer multiple MIOperands inside a single one.
4029void ARMAsmParser::
4030cvtLdExtTWriteBackReg(MCInst &Inst,
4031                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4032  // Rt
4033  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4034  // Create a writeback register dummy placeholder.
4035  Inst.addOperand(MCOperand::CreateImm(0));
4036  // addr
4037  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4038  // offset
4039  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4040  // pred
4041  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4042}
4043
4044/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
4045/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4046/// when they refer multiple MIOperands inside a single one.
4047void ARMAsmParser::
4048cvtStExtTWriteBackImm(MCInst &Inst,
4049                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4050  // Create a writeback register dummy placeholder.
4051  Inst.addOperand(MCOperand::CreateImm(0));
4052  // Rt
4053  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4054  // addr
4055  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4056  // offset
4057  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4058  // pred
4059  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4060}
4061
4062/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
4063/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4064/// when they refer multiple MIOperands inside a single one.
4065void ARMAsmParser::
4066cvtStExtTWriteBackReg(MCInst &Inst,
4067                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4068  // Create a writeback register dummy placeholder.
4069  Inst.addOperand(MCOperand::CreateImm(0));
4070  // Rt
4071  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4072  // addr
4073  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4074  // offset
4075  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4076  // pred
4077  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4078}
4079
4080/// cvtLdrdPre - Convert parsed operands to MCInst.
4081/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4082/// when they refer multiple MIOperands inside a single one.
4083void ARMAsmParser::
4084cvtLdrdPre(MCInst &Inst,
4085           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4086  // Rt, Rt2
4087  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4088  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4089  // Create a writeback register dummy placeholder.
4090  Inst.addOperand(MCOperand::CreateImm(0));
4091  // addr
4092  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4093  // pred
4094  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4095}
4096
4097/// cvtStrdPre - Convert parsed operands to MCInst.
4098/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4099/// when they refer multiple MIOperands inside a single one.
4100void ARMAsmParser::
4101cvtStrdPre(MCInst &Inst,
4102           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4103  // Create a writeback register dummy placeholder.
4104  Inst.addOperand(MCOperand::CreateImm(0));
4105  // Rt, Rt2
4106  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4107  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4108  // addr
4109  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4110  // pred
4111  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4112}
4113
4114/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4115/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4116/// when they refer multiple MIOperands inside a single one.
4117void ARMAsmParser::
4118cvtLdWriteBackRegAddrMode3(MCInst &Inst,
4119                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4120  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4121  // Create a writeback register dummy placeholder.
4122  Inst.addOperand(MCOperand::CreateImm(0));
4123  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4124  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4125}
4126
4127/// cvtThumbMultiply - Convert parsed operands to MCInst.
4128/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4129/// when they refer multiple MIOperands inside a single one.
4130void ARMAsmParser::
4131cvtThumbMultiply(MCInst &Inst,
4132           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4133  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4134  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4135  // If we have a three-operand form, make sure to set Rn to be the operand
4136  // that isn't the same as Rd.
4137  unsigned RegOp = 4;
4138  if (Operands.size() == 6 &&
4139      ((ARMOperand*)Operands[4])->getReg() ==
4140        ((ARMOperand*)Operands[3])->getReg())
4141    RegOp = 5;
4142  ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4143  Inst.addOperand(Inst.getOperand(0));
4144  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4145}
4146
4147void ARMAsmParser::
4148cvtVLDwbFixed(MCInst &Inst,
4149              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4150  // Vd
4151  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4152  // Create a writeback register dummy placeholder.
4153  Inst.addOperand(MCOperand::CreateImm(0));
4154  // Vn
4155  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4156  // pred
4157  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4158}
4159
4160void ARMAsmParser::
4161cvtVLDwbRegister(MCInst &Inst,
4162                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4163  // Vd
4164  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4165  // Create a writeback register dummy placeholder.
4166  Inst.addOperand(MCOperand::CreateImm(0));
4167  // Vn
4168  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4169  // Vm
4170  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4171  // pred
4172  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4173}
4174
4175void ARMAsmParser::
4176cvtVSTwbFixed(MCInst &Inst,
4177              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4178  // Create a writeback register dummy placeholder.
4179  Inst.addOperand(MCOperand::CreateImm(0));
4180  // Vn
4181  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4182  // Vt
4183  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4184  // pred
4185  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4186}
4187
4188void ARMAsmParser::
4189cvtVSTwbRegister(MCInst &Inst,
4190                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4191  // Create a writeback register dummy placeholder.
4192  Inst.addOperand(MCOperand::CreateImm(0));
4193  // Vn
4194  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4195  // Vm
4196  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4197  // Vt
4198  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4199  // pred
4200  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4201}
4202
4203/// Parse an ARM memory expression, return false if successful else return true
4204/// or an error.  The first token must be a '[' when called.
4205bool ARMAsmParser::
4206parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4207  SMLoc S, E;
4208  assert(Parser.getTok().is(AsmToken::LBrac) &&
4209         "Token is not a Left Bracket");
4210  S = Parser.getTok().getLoc();
4211  Parser.Lex(); // Eat left bracket token.
4212
4213  const AsmToken &BaseRegTok = Parser.getTok();
4214  int BaseRegNum = tryParseRegister();
4215  if (BaseRegNum == -1)
4216    return Error(BaseRegTok.getLoc(), "register expected");
4217
4218  // The next token must either be a comma or a closing bracket.
4219  const AsmToken &Tok = Parser.getTok();
4220  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
4221    return Error(Tok.getLoc(), "malformed memory operand");
4222
4223  if (Tok.is(AsmToken::RBrac)) {
4224    E = Tok.getLoc();
4225    Parser.Lex(); // Eat right bracket token.
4226
4227    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4228                                             0, 0, false, S, E));
4229
4230    // If there's a pre-indexing writeback marker, '!', just add it as a token
4231    // operand. It's rather odd, but syntactically valid.
4232    if (Parser.getTok().is(AsmToken::Exclaim)) {
4233      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4234      Parser.Lex(); // Eat the '!'.
4235    }
4236
4237    return false;
4238  }
4239
4240  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
4241  Parser.Lex(); // Eat the comma.
4242
4243  // If we have a ':', it's an alignment specifier.
4244  if (Parser.getTok().is(AsmToken::Colon)) {
4245    Parser.Lex(); // Eat the ':'.
4246    E = Parser.getTok().getLoc();
4247
4248    const MCExpr *Expr;
4249    if (getParser().ParseExpression(Expr))
4250     return true;
4251
4252    // The expression has to be a constant. Memory references with relocations
4253    // don't come through here, as they use the <label> forms of the relevant
4254    // instructions.
4255    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4256    if (!CE)
4257      return Error (E, "constant expression expected");
4258
4259    unsigned Align = 0;
4260    switch (CE->getValue()) {
4261    default:
4262      return Error(E,
4263                   "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4264    case 16:  Align = 2; break;
4265    case 32:  Align = 4; break;
4266    case 64:  Align = 8; break;
4267    case 128: Align = 16; break;
4268    case 256: Align = 32; break;
4269    }
4270
4271    // Now we should have the closing ']'
4272    E = Parser.getTok().getLoc();
4273    if (Parser.getTok().isNot(AsmToken::RBrac))
4274      return Error(E, "']' expected");
4275    Parser.Lex(); // Eat right bracket token.
4276
4277    // Don't worry about range checking the value here. That's handled by
4278    // the is*() predicates.
4279    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4280                                             ARM_AM::no_shift, 0, Align,
4281                                             false, S, E));
4282
4283    // If there's a pre-indexing writeback marker, '!', just add it as a token
4284    // operand.
4285    if (Parser.getTok().is(AsmToken::Exclaim)) {
4286      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4287      Parser.Lex(); // Eat the '!'.
4288    }
4289
4290    return false;
4291  }
4292
4293  // If we have a '#', it's an immediate offset, else assume it's a register
4294  // offset. Be friendly and also accept a plain integer (without a leading
4295  // hash) for gas compatibility.
4296  if (Parser.getTok().is(AsmToken::Hash) ||
4297      Parser.getTok().is(AsmToken::Dollar) ||
4298      Parser.getTok().is(AsmToken::Integer)) {
4299    if (Parser.getTok().isNot(AsmToken::Integer))
4300      Parser.Lex(); // Eat the '#'.
4301    E = Parser.getTok().getLoc();
4302
4303    bool isNegative = getParser().getTok().is(AsmToken::Minus);
4304    const MCExpr *Offset;
4305    if (getParser().ParseExpression(Offset))
4306     return true;
4307
4308    // The expression has to be a constant. Memory references with relocations
4309    // don't come through here, as they use the <label> forms of the relevant
4310    // instructions.
4311    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4312    if (!CE)
4313      return Error (E, "constant expression expected");
4314
4315    // If the constant was #-0, represent it as INT32_MIN.
4316    int32_t Val = CE->getValue();
4317    if (isNegative && Val == 0)
4318      CE = MCConstantExpr::Create(INT32_MIN, getContext());
4319
4320    // Now we should have the closing ']'
4321    E = Parser.getTok().getLoc();
4322    if (Parser.getTok().isNot(AsmToken::RBrac))
4323      return Error(E, "']' expected");
4324    Parser.Lex(); // Eat right bracket token.
4325
4326    // Don't worry about range checking the value here. That's handled by
4327    // the is*() predicates.
4328    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4329                                             ARM_AM::no_shift, 0, 0,
4330                                             false, S, E));
4331
4332    // If there's a pre-indexing writeback marker, '!', just add it as a token
4333    // operand.
4334    if (Parser.getTok().is(AsmToken::Exclaim)) {
4335      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4336      Parser.Lex(); // Eat the '!'.
4337    }
4338
4339    return false;
4340  }
4341
4342  // The register offset is optionally preceded by a '+' or '-'
4343  bool isNegative = false;
4344  if (Parser.getTok().is(AsmToken::Minus)) {
4345    isNegative = true;
4346    Parser.Lex(); // Eat the '-'.
4347  } else if (Parser.getTok().is(AsmToken::Plus)) {
4348    // Nothing to do.
4349    Parser.Lex(); // Eat the '+'.
4350  }
4351
4352  E = Parser.getTok().getLoc();
4353  int OffsetRegNum = tryParseRegister();
4354  if (OffsetRegNum == -1)
4355    return Error(E, "register expected");
4356
4357  // If there's a shift operator, handle it.
4358  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4359  unsigned ShiftImm = 0;
4360  if (Parser.getTok().is(AsmToken::Comma)) {
4361    Parser.Lex(); // Eat the ','.
4362    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4363      return true;
4364  }
4365
4366  // Now we should have the closing ']'
4367  E = Parser.getTok().getLoc();
4368  if (Parser.getTok().isNot(AsmToken::RBrac))
4369    return Error(E, "']' expected");
4370  Parser.Lex(); // Eat right bracket token.
4371
4372  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4373                                           ShiftType, ShiftImm, 0, isNegative,
4374                                           S, E));
4375
4376  // If there's a pre-indexing writeback marker, '!', just add it as a token
4377  // operand.
4378  if (Parser.getTok().is(AsmToken::Exclaim)) {
4379    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4380    Parser.Lex(); // Eat the '!'.
4381  }
4382
4383  return false;
4384}
4385
4386/// parseMemRegOffsetShift - one of these two:
4387///   ( lsl | lsr | asr | ror ) , # shift_amount
4388///   rrx
4389/// return true if it parses a shift otherwise it returns false.
4390bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4391                                          unsigned &Amount) {
4392  SMLoc Loc = Parser.getTok().getLoc();
4393  const AsmToken &Tok = Parser.getTok();
4394  if (Tok.isNot(AsmToken::Identifier))
4395    return true;
4396  StringRef ShiftName = Tok.getString();
4397  if (ShiftName == "lsl" || ShiftName == "LSL" ||
4398      ShiftName == "asl" || ShiftName == "ASL")
4399    St = ARM_AM::lsl;
4400  else if (ShiftName == "lsr" || ShiftName == "LSR")
4401    St = ARM_AM::lsr;
4402  else if (ShiftName == "asr" || ShiftName == "ASR")
4403    St = ARM_AM::asr;
4404  else if (ShiftName == "ror" || ShiftName == "ROR")
4405    St = ARM_AM::ror;
4406  else if (ShiftName == "rrx" || ShiftName == "RRX")
4407    St = ARM_AM::rrx;
4408  else
4409    return Error(Loc, "illegal shift operator");
4410  Parser.Lex(); // Eat shift type token.
4411
4412  // rrx stands alone.
4413  Amount = 0;
4414  if (St != ARM_AM::rrx) {
4415    Loc = Parser.getTok().getLoc();
4416    // A '#' and a shift amount.
4417    const AsmToken &HashTok = Parser.getTok();
4418    if (HashTok.isNot(AsmToken::Hash) &&
4419        HashTok.isNot(AsmToken::Dollar))
4420      return Error(HashTok.getLoc(), "'#' expected");
4421    Parser.Lex(); // Eat hash token.
4422
4423    const MCExpr *Expr;
4424    if (getParser().ParseExpression(Expr))
4425      return true;
4426    // Range check the immediate.
4427    // lsl, ror: 0 <= imm <= 31
4428    // lsr, asr: 0 <= imm <= 32
4429    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4430    if (!CE)
4431      return Error(Loc, "shift amount must be an immediate");
4432    int64_t Imm = CE->getValue();
4433    if (Imm < 0 ||
4434        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4435        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4436      return Error(Loc, "immediate shift value out of range");
4437    // If <ShiftTy> #0, turn it into a no_shift.
4438    if (Imm == 0)
4439      St = ARM_AM::lsl;
4440    // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4441    if (Imm == 32)
4442      Imm = 0;
4443    Amount = Imm;
4444  }
4445
4446  return false;
4447}
4448
4449/// parseFPImm - A floating point immediate expression operand.
4450ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4451parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4452  // Anything that can accept a floating point constant as an operand
4453  // needs to go through here, as the regular ParseExpression is
4454  // integer only.
4455  //
4456  // This routine still creates a generic Immediate operand, containing
4457  // a bitcast of the 64-bit floating point value. The various operands
4458  // that accept floats can check whether the value is valid for them
4459  // via the standard is*() predicates.
4460
4461  SMLoc S = Parser.getTok().getLoc();
4462
4463  if (Parser.getTok().isNot(AsmToken::Hash) &&
4464      Parser.getTok().isNot(AsmToken::Dollar))
4465    return MatchOperand_NoMatch;
4466
4467  // Disambiguate the VMOV forms that can accept an FP immediate.
4468  // vmov.f32 <sreg>, #imm
4469  // vmov.f64 <dreg>, #imm
4470  // vmov.f32 <dreg>, #imm  @ vector f32x2
4471  // vmov.f32 <qreg>, #imm  @ vector f32x4
4472  //
4473  // There are also the NEON VMOV instructions which expect an
4474  // integer constant. Make sure we don't try to parse an FPImm
4475  // for these:
4476  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4477  ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4478  if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4479                           TyOp->getToken() != ".f64"))
4480    return MatchOperand_NoMatch;
4481
4482  Parser.Lex(); // Eat the '#'.
4483
4484  // Handle negation, as that still comes through as a separate token.
4485  bool isNegative = false;
4486  if (Parser.getTok().is(AsmToken::Minus)) {
4487    isNegative = true;
4488    Parser.Lex();
4489  }
4490  const AsmToken &Tok = Parser.getTok();
4491  SMLoc Loc = Tok.getLoc();
4492  if (Tok.is(AsmToken::Real)) {
4493    APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4494    uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4495    // If we had a '-' in front, toggle the sign bit.
4496    IntVal ^= (uint64_t)isNegative << 31;
4497    Parser.Lex(); // Eat the token.
4498    Operands.push_back(ARMOperand::CreateImm(
4499          MCConstantExpr::Create(IntVal, getContext()),
4500          S, Parser.getTok().getLoc()));
4501    return MatchOperand_Success;
4502  }
4503  // Also handle plain integers. Instructions which allow floating point
4504  // immediates also allow a raw encoded 8-bit value.
4505  if (Tok.is(AsmToken::Integer)) {
4506    int64_t Val = Tok.getIntVal();
4507    Parser.Lex(); // Eat the token.
4508    if (Val > 255 || Val < 0) {
4509      Error(Loc, "encoded floating point value out of range");
4510      return MatchOperand_ParseFail;
4511    }
4512    double RealVal = ARM_AM::getFPImmFloat(Val);
4513    Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4514    Operands.push_back(ARMOperand::CreateImm(
4515        MCConstantExpr::Create(Val, getContext()), S,
4516        Parser.getTok().getLoc()));
4517    return MatchOperand_Success;
4518  }
4519
4520  Error(Loc, "invalid floating point immediate");
4521  return MatchOperand_ParseFail;
4522}
4523
4524/// Parse a arm instruction operand.  For now this parses the operand regardless
4525/// of the mnemonic.
4526bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4527                                StringRef Mnemonic) {
4528  SMLoc S, E;
4529
4530  // Check if the current operand has a custom associated parser, if so, try to
4531  // custom parse the operand, or fallback to the general approach.
4532  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4533  if (ResTy == MatchOperand_Success)
4534    return false;
4535  // If there wasn't a custom match, try the generic matcher below. Otherwise,
4536  // there was a match, but an error occurred, in which case, just return that
4537  // the operand parsing failed.
4538  if (ResTy == MatchOperand_ParseFail)
4539    return true;
4540
4541  switch (getLexer().getKind()) {
4542  default:
4543    Error(Parser.getTok().getLoc(), "unexpected token in operand");
4544    return true;
4545  case AsmToken::Identifier: {
4546    if (!tryParseRegisterWithWriteBack(Operands))
4547      return false;
4548    int Res = tryParseShiftRegister(Operands);
4549    if (Res == 0) // success
4550      return false;
4551    else if (Res == -1) // irrecoverable error
4552      return true;
4553    // If this is VMRS, check for the apsr_nzcv operand.
4554    if (Mnemonic == "vmrs" &&
4555        Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4556      S = Parser.getTok().getLoc();
4557      Parser.Lex();
4558      Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4559      return false;
4560    }
4561
4562    // Fall though for the Identifier case that is not a register or a
4563    // special name.
4564  }
4565  case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4566  case AsmToken::Integer: // things like 1f and 2b as a branch targets
4567  case AsmToken::String:  // quoted label names.
4568  case AsmToken::Dot: {   // . as a branch target
4569    // This was not a register so parse other operands that start with an
4570    // identifier (like labels) as expressions and create them as immediates.
4571    const MCExpr *IdVal;
4572    S = Parser.getTok().getLoc();
4573    if (getParser().ParseExpression(IdVal))
4574      return true;
4575    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4576    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4577    return false;
4578  }
4579  case AsmToken::LBrac:
4580    return parseMemory(Operands);
4581  case AsmToken::LCurly:
4582    return parseRegisterList(Operands);
4583  case AsmToken::Dollar:
4584  case AsmToken::Hash: {
4585    // #42 -> immediate.
4586    S = Parser.getTok().getLoc();
4587    Parser.Lex();
4588
4589    if (Parser.getTok().isNot(AsmToken::Colon)) {
4590      bool isNegative = Parser.getTok().is(AsmToken::Minus);
4591      const MCExpr *ImmVal;
4592      if (getParser().ParseExpression(ImmVal))
4593        return true;
4594      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4595      if (CE) {
4596        int32_t Val = CE->getValue();
4597        if (isNegative && Val == 0)
4598          ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4599      }
4600      E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4601      Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4602      return false;
4603    }
4604    // w/ a ':' after the '#', it's just like a plain ':'.
4605    // FALLTHROUGH
4606  }
4607  case AsmToken::Colon: {
4608    // ":lower16:" and ":upper16:" expression prefixes
4609    // FIXME: Check it's an expression prefix,
4610    // e.g. (FOO - :lower16:BAR) isn't legal.
4611    ARMMCExpr::VariantKind RefKind;
4612    if (parsePrefix(RefKind))
4613      return true;
4614
4615    const MCExpr *SubExprVal;
4616    if (getParser().ParseExpression(SubExprVal))
4617      return true;
4618
4619    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4620                                              getContext());
4621    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4622    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4623    return false;
4624  }
4625  }
4626}
4627
4628// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4629//  :lower16: and :upper16:.
4630bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4631  RefKind = ARMMCExpr::VK_ARM_None;
4632
4633  // :lower16: and :upper16: modifiers
4634  assert(getLexer().is(AsmToken::Colon) && "expected a :");
4635  Parser.Lex(); // Eat ':'
4636
4637  if (getLexer().isNot(AsmToken::Identifier)) {
4638    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4639    return true;
4640  }
4641
4642  StringRef IDVal = Parser.getTok().getIdentifier();
4643  if (IDVal == "lower16") {
4644    RefKind = ARMMCExpr::VK_ARM_LO16;
4645  } else if (IDVal == "upper16") {
4646    RefKind = ARMMCExpr::VK_ARM_HI16;
4647  } else {
4648    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4649    return true;
4650  }
4651  Parser.Lex();
4652
4653  if (getLexer().isNot(AsmToken::Colon)) {
4654    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4655    return true;
4656  }
4657  Parser.Lex(); // Eat the last ':'
4658  return false;
4659}
4660
4661/// \brief Given a mnemonic, split out possible predication code and carry
4662/// setting letters to form a canonical mnemonic and flags.
4663//
4664// FIXME: Would be nice to autogen this.
4665// FIXME: This is a bit of a maze of special cases.
4666StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4667                                      unsigned &PredicationCode,
4668                                      bool &CarrySetting,
4669                                      unsigned &ProcessorIMod,
4670                                      StringRef &ITMask) {
4671  PredicationCode = ARMCC::AL;
4672  CarrySetting = false;
4673  ProcessorIMod = 0;
4674
4675  // Ignore some mnemonics we know aren't predicated forms.
4676  //
4677  // FIXME: Would be nice to autogen this.
4678  if ((Mnemonic == "movs" && isThumb()) ||
4679      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
4680      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
4681      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
4682      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
4683      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
4684      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
4685      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4686      Mnemonic == "fmuls")
4687    return Mnemonic;
4688
4689  // First, split out any predication code. Ignore mnemonics we know aren't
4690  // predicated but do have a carry-set and so weren't caught above.
4691  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4692      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4693      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4694      Mnemonic != "sbcs" && Mnemonic != "rscs") {
4695    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4696      .Case("eq", ARMCC::EQ)
4697      .Case("ne", ARMCC::NE)
4698      .Case("hs", ARMCC::HS)
4699      .Case("cs", ARMCC::HS)
4700      .Case("lo", ARMCC::LO)
4701      .Case("cc", ARMCC::LO)
4702      .Case("mi", ARMCC::MI)
4703      .Case("pl", ARMCC::PL)
4704      .Case("vs", ARMCC::VS)
4705      .Case("vc", ARMCC::VC)
4706      .Case("hi", ARMCC::HI)
4707      .Case("ls", ARMCC::LS)
4708      .Case("ge", ARMCC::GE)
4709      .Case("lt", ARMCC::LT)
4710      .Case("gt", ARMCC::GT)
4711      .Case("le", ARMCC::LE)
4712      .Case("al", ARMCC::AL)
4713      .Default(~0U);
4714    if (CC != ~0U) {
4715      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4716      PredicationCode = CC;
4717    }
4718  }
4719
4720  // Next, determine if we have a carry setting bit. We explicitly ignore all
4721  // the instructions we know end in 's'.
4722  if (Mnemonic.endswith("s") &&
4723      !(Mnemonic == "cps" || Mnemonic == "mls" ||
4724        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4725        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4726        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4727        Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4728        Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4729        Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4730        Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4731        Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4732        (Mnemonic == "movs" && isThumb()))) {
4733    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4734    CarrySetting = true;
4735  }
4736
4737  // The "cps" instruction can have a interrupt mode operand which is glued into
4738  // the mnemonic. Check if this is the case, split it and parse the imod op
4739  if (Mnemonic.startswith("cps")) {
4740    // Split out any imod code.
4741    unsigned IMod =
4742      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4743      .Case("ie", ARM_PROC::IE)
4744      .Case("id", ARM_PROC::ID)
4745      .Default(~0U);
4746    if (IMod != ~0U) {
4747      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4748      ProcessorIMod = IMod;
4749    }
4750  }
4751
4752  // The "it" instruction has the condition mask on the end of the mnemonic.
4753  if (Mnemonic.startswith("it")) {
4754    ITMask = Mnemonic.slice(2, Mnemonic.size());
4755    Mnemonic = Mnemonic.slice(0, 2);
4756  }
4757
4758  return Mnemonic;
4759}
4760
4761/// \brief Given a canonical mnemonic, determine if the instruction ever allows
4762/// inclusion of carry set or predication code operands.
4763//
4764// FIXME: It would be nice to autogen this.
4765void ARMAsmParser::
4766getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4767                      bool &CanAcceptPredicationCode) {
4768  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4769      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4770      Mnemonic == "add" || Mnemonic == "adc" ||
4771      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4772      Mnemonic == "orr" || Mnemonic == "mvn" ||
4773      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4774      Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4775      Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4776      (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4777                      Mnemonic == "mla" || Mnemonic == "smlal" ||
4778                      Mnemonic == "umlal" || Mnemonic == "umull"))) {
4779    CanAcceptCarrySet = true;
4780  } else
4781    CanAcceptCarrySet = false;
4782
4783  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4784      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4785      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4786      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4787      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4788      (Mnemonic == "clrex" && !isThumb()) ||
4789      (Mnemonic == "nop" && isThumbOne()) ||
4790      ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4791        Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4792        Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4793      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4794       !isThumb()) ||
4795      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4796    CanAcceptPredicationCode = false;
4797  } else
4798    CanAcceptPredicationCode = true;
4799
4800  if (isThumb()) {
4801    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4802        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4803      CanAcceptPredicationCode = false;
4804  }
4805}
4806
4807bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4808                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4809  // FIXME: This is all horribly hacky. We really need a better way to deal
4810  // with optional operands like this in the matcher table.
4811
4812  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4813  // another does not. Specifically, the MOVW instruction does not. So we
4814  // special case it here and remove the defaulted (non-setting) cc_out
4815  // operand if that's the instruction we're trying to match.
4816  //
4817  // We do this as post-processing of the explicit operands rather than just
4818  // conditionally adding the cc_out in the first place because we need
4819  // to check the type of the parsed immediate operand.
4820  if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4821      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4822      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4823      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4824    return true;
4825
4826  // Register-register 'add' for thumb does not have a cc_out operand
4827  // when there are only two register operands.
4828  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4829      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4830      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4831      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4832    return true;
4833  // Register-register 'add' for thumb does not have a cc_out operand
4834  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4835  // have to check the immediate range here since Thumb2 has a variant
4836  // that can handle a different range and has a cc_out operand.
4837  if (((isThumb() && Mnemonic == "add") ||
4838       (isThumbTwo() && Mnemonic == "sub")) &&
4839      Operands.size() == 6 &&
4840      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4841      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4842      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4843      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4844      ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4845       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4846    return true;
4847  // For Thumb2, add/sub immediate does not have a cc_out operand for the
4848  // imm0_4095 variant. That's the least-preferred variant when
4849  // selecting via the generic "add" mnemonic, so to know that we
4850  // should remove the cc_out operand, we have to explicitly check that
4851  // it's not one of the other variants. Ugh.
4852  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4853      Operands.size() == 6 &&
4854      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4855      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4856      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4857    // Nest conditions rather than one big 'if' statement for readability.
4858    //
4859    // If either register is a high reg, it's either one of the SP
4860    // variants (handled above) or a 32-bit encoding, so we just
4861    // check against T3. If the second register is the PC, this is an
4862    // alternate form of ADR, which uses encoding T4, so check for that too.
4863    if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4864         !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4865        static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4866        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4867      return false;
4868    // If both registers are low, we're in an IT block, and the immediate is
4869    // in range, we should use encoding T1 instead, which has a cc_out.
4870    if (inITBlock() &&
4871        isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4872        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4873        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4874      return false;
4875
4876    // Otherwise, we use encoding T4, which does not have a cc_out
4877    // operand.
4878    return true;
4879  }
4880
4881  // The thumb2 multiply instruction doesn't have a CCOut register, so
4882  // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4883  // use the 16-bit encoding or not.
4884  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4885      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4886      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4887      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4888      static_cast<ARMOperand*>(Operands[5])->isReg() &&
4889      // If the registers aren't low regs, the destination reg isn't the
4890      // same as one of the source regs, or the cc_out operand is zero
4891      // outside of an IT block, we have to use the 32-bit encoding, so
4892      // remove the cc_out operand.
4893      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4894       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4895       !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4896       !inITBlock() ||
4897       (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4898        static_cast<ARMOperand*>(Operands[5])->getReg() &&
4899        static_cast<ARMOperand*>(Operands[3])->getReg() !=
4900        static_cast<ARMOperand*>(Operands[4])->getReg())))
4901    return true;
4902
4903  // Also check the 'mul' syntax variant that doesn't specify an explicit
4904  // destination register.
4905  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4906      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4907      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4908      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4909      // If the registers aren't low regs  or the cc_out operand is zero
4910      // outside of an IT block, we have to use the 32-bit encoding, so
4911      // remove the cc_out operand.
4912      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4913       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4914       !inITBlock()))
4915    return true;
4916
4917
4918
4919  // Register-register 'add/sub' for thumb does not have a cc_out operand
4920  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4921  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4922  // right, this will result in better diagnostics (which operand is off)
4923  // anyway.
4924  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4925      (Operands.size() == 5 || Operands.size() == 6) &&
4926      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4927      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4928      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4929      (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4930       (Operands.size() == 6 &&
4931        static_cast<ARMOperand*>(Operands[5])->isImm())))
4932    return true;
4933
4934  return false;
4935}
4936
4937static bool isDataTypeToken(StringRef Tok) {
4938  return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4939    Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4940    Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4941    Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4942    Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4943    Tok == ".f" || Tok == ".d";
4944}
4945
4946// FIXME: This bit should probably be handled via an explicit match class
4947// in the .td files that matches the suffix instead of having it be
4948// a literal string token the way it is now.
4949static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4950  return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4951}
4952
4953static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features);
4954/// Parse an arm instruction mnemonic followed by its operands.
4955bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4956                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4957  // Apply mnemonic aliases before doing anything else, as the destination
4958  // mnemnonic may include suffices and we want to handle them normally.
4959  // The generic tblgen'erated code does this later, at the start of
4960  // MatchInstructionImpl(), but that's too late for aliases that include
4961  // any sort of suffix.
4962  unsigned AvailableFeatures = getAvailableFeatures();
4963  applyMnemonicAliases(Name, AvailableFeatures);
4964
4965  // First check for the ARM-specific .req directive.
4966  if (Parser.getTok().is(AsmToken::Identifier) &&
4967      Parser.getTok().getIdentifier() == ".req") {
4968    parseDirectiveReq(Name, NameLoc);
4969    // We always return 'error' for this, as we're done with this
4970    // statement and don't need to match the 'instruction."
4971    return true;
4972  }
4973
4974  // Create the leading tokens for the mnemonic, split by '.' characters.
4975  size_t Start = 0, Next = Name.find('.');
4976  StringRef Mnemonic = Name.slice(Start, Next);
4977
4978  // Split out the predication code and carry setting flag from the mnemonic.
4979  unsigned PredicationCode;
4980  unsigned ProcessorIMod;
4981  bool CarrySetting;
4982  StringRef ITMask;
4983  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
4984                           ProcessorIMod, ITMask);
4985
4986  // In Thumb1, only the branch (B) instruction can be predicated.
4987  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
4988    Parser.EatToEndOfStatement();
4989    return Error(NameLoc, "conditional execution not supported in Thumb1");
4990  }
4991
4992  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
4993
4994  // Handle the IT instruction ITMask. Convert it to a bitmask. This
4995  // is the mask as it will be for the IT encoding if the conditional
4996  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
4997  // where the conditional bit0 is zero, the instruction post-processing
4998  // will adjust the mask accordingly.
4999  if (Mnemonic == "it") {
5000    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5001    if (ITMask.size() > 3) {
5002      Parser.EatToEndOfStatement();
5003      return Error(Loc, "too many conditions on IT instruction");
5004    }
5005    unsigned Mask = 8;
5006    for (unsigned i = ITMask.size(); i != 0; --i) {
5007      char pos = ITMask[i - 1];
5008      if (pos != 't' && pos != 'e') {
5009        Parser.EatToEndOfStatement();
5010        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5011      }
5012      Mask >>= 1;
5013      if (ITMask[i - 1] == 't')
5014        Mask |= 8;
5015    }
5016    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5017  }
5018
5019  // FIXME: This is all a pretty gross hack. We should automatically handle
5020  // optional operands like this via tblgen.
5021
5022  // Next, add the CCOut and ConditionCode operands, if needed.
5023  //
5024  // For mnemonics which can ever incorporate a carry setting bit or predication
5025  // code, our matching model involves us always generating CCOut and
5026  // ConditionCode operands to match the mnemonic "as written" and then we let
5027  // the matcher deal with finding the right instruction or generating an
5028  // appropriate error.
5029  bool CanAcceptCarrySet, CanAcceptPredicationCode;
5030  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5031
5032  // If we had a carry-set on an instruction that can't do that, issue an
5033  // error.
5034  if (!CanAcceptCarrySet && CarrySetting) {
5035    Parser.EatToEndOfStatement();
5036    return Error(NameLoc, "instruction '" + Mnemonic +
5037                 "' can not set flags, but 's' suffix specified");
5038  }
5039  // If we had a predication code on an instruction that can't do that, issue an
5040  // error.
5041  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5042    Parser.EatToEndOfStatement();
5043    return Error(NameLoc, "instruction '" + Mnemonic +
5044                 "' is not predicable, but condition code specified");
5045  }
5046
5047  // Add the carry setting operand, if necessary.
5048  if (CanAcceptCarrySet) {
5049    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5050    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5051                                               Loc));
5052  }
5053
5054  // Add the predication code operand, if necessary.
5055  if (CanAcceptPredicationCode) {
5056    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5057                                      CarrySetting);
5058    Operands.push_back(ARMOperand::CreateCondCode(
5059                         ARMCC::CondCodes(PredicationCode), Loc));
5060  }
5061
5062  // Add the processor imod operand, if necessary.
5063  if (ProcessorIMod) {
5064    Operands.push_back(ARMOperand::CreateImm(
5065          MCConstantExpr::Create(ProcessorIMod, getContext()),
5066                                 NameLoc, NameLoc));
5067  }
5068
5069  // Add the remaining tokens in the mnemonic.
5070  while (Next != StringRef::npos) {
5071    Start = Next;
5072    Next = Name.find('.', Start + 1);
5073    StringRef ExtraToken = Name.slice(Start, Next);
5074
5075    // Some NEON instructions have an optional datatype suffix that is
5076    // completely ignored. Check for that.
5077    if (isDataTypeToken(ExtraToken) &&
5078        doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5079      continue;
5080
5081    if (ExtraToken != ".n") {
5082      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5083      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5084    }
5085  }
5086
5087  // Read the remaining operands.
5088  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5089    // Read the first operand.
5090    if (parseOperand(Operands, Mnemonic)) {
5091      Parser.EatToEndOfStatement();
5092      return true;
5093    }
5094
5095    while (getLexer().is(AsmToken::Comma)) {
5096      Parser.Lex();  // Eat the comma.
5097
5098      // Parse and remember the operand.
5099      if (parseOperand(Operands, Mnemonic)) {
5100        Parser.EatToEndOfStatement();
5101        return true;
5102      }
5103    }
5104  }
5105
5106  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5107    SMLoc Loc = getLexer().getLoc();
5108    Parser.EatToEndOfStatement();
5109    return Error(Loc, "unexpected token in argument list");
5110  }
5111
5112  Parser.Lex(); // Consume the EndOfStatement
5113
5114  // Some instructions, mostly Thumb, have forms for the same mnemonic that
5115  // do and don't have a cc_out optional-def operand. With some spot-checks
5116  // of the operand list, we can figure out which variant we're trying to
5117  // parse and adjust accordingly before actually matching. We shouldn't ever
5118  // try to remove a cc_out operand that was explicitly set on the the
5119  // mnemonic, of course (CarrySetting == true). Reason number #317 the
5120  // table driven matcher doesn't fit well with the ARM instruction set.
5121  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5122    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5123    Operands.erase(Operands.begin() + 1);
5124    delete Op;
5125  }
5126
5127  // ARM mode 'blx' need special handling, as the register operand version
5128  // is predicable, but the label operand version is not. So, we can't rely
5129  // on the Mnemonic based checking to correctly figure out when to put
5130  // a k_CondCode operand in the list. If we're trying to match the label
5131  // version, remove the k_CondCode operand here.
5132  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5133      static_cast<ARMOperand*>(Operands[2])->isImm()) {
5134    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5135    Operands.erase(Operands.begin() + 1);
5136    delete Op;
5137  }
5138
5139  // The vector-compare-to-zero instructions have a literal token "#0" at
5140  // the end that comes to here as an immediate operand. Convert it to a
5141  // token to play nicely with the matcher.
5142  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
5143      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
5144      static_cast<ARMOperand*>(Operands[5])->isImm()) {
5145    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5146    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5147    if (CE && CE->getValue() == 0) {
5148      Operands.erase(Operands.begin() + 5);
5149      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5150      delete Op;
5151    }
5152  }
5153  // VCMP{E} does the same thing, but with a different operand count.
5154  if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
5155      static_cast<ARMOperand*>(Operands[4])->isImm()) {
5156    ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
5157    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5158    if (CE && CE->getValue() == 0) {
5159      Operands.erase(Operands.begin() + 4);
5160      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5161      delete Op;
5162    }
5163  }
5164  // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
5165  // end. Convert it to a token here. Take care not to convert those
5166  // that should hit the Thumb2 encoding.
5167  if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
5168      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5169      static_cast<ARMOperand*>(Operands[4])->isReg() &&
5170      static_cast<ARMOperand*>(Operands[5])->isImm()) {
5171    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5172    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5173    if (CE && CE->getValue() == 0 &&
5174        (isThumbOne() ||
5175         // The cc_out operand matches the IT block.
5176         ((inITBlock() != CarrySetting) &&
5177         // Neither register operand is a high register.
5178         (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5179          isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){
5180      Operands.erase(Operands.begin() + 5);
5181      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5182      delete Op;
5183    }
5184  }
5185
5186  return false;
5187}
5188
5189// Validate context-sensitive operand constraints.
5190
5191// return 'true' if register list contains non-low GPR registers,
5192// 'false' otherwise. If Reg is in the register list or is HiReg, set
5193// 'containsReg' to true.
5194static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5195                                 unsigned HiReg, bool &containsReg) {
5196  containsReg = false;
5197  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5198    unsigned OpReg = Inst.getOperand(i).getReg();
5199    if (OpReg == Reg)
5200      containsReg = true;
5201    // Anything other than a low register isn't legal here.
5202    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5203      return true;
5204  }
5205  return false;
5206}
5207
5208// Check if the specified regisgter is in the register list of the inst,
5209// starting at the indicated operand number.
5210static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5211  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5212    unsigned OpReg = Inst.getOperand(i).getReg();
5213    if (OpReg == Reg)
5214      return true;
5215  }
5216  return false;
5217}
5218
5219// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5220// the ARMInsts array) instead. Getting that here requires awkward
5221// API changes, though. Better way?
5222namespace llvm {
5223extern const MCInstrDesc ARMInsts[];
5224}
5225static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5226  return ARMInsts[Opcode];
5227}
5228
5229// FIXME: We would really like to be able to tablegen'erate this.
5230bool ARMAsmParser::
5231validateInstruction(MCInst &Inst,
5232                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5233  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5234  SMLoc Loc = Operands[0]->getStartLoc();
5235  // Check the IT block state first.
5236  // NOTE: BKPT instruction has the interesting property of being
5237  // allowed in IT blocks, but not being predicable.  It just always
5238  // executes.
5239  if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5240      Inst.getOpcode() != ARM::BKPT) {
5241    unsigned bit = 1;
5242    if (ITState.FirstCond)
5243      ITState.FirstCond = false;
5244    else
5245      bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5246    // The instruction must be predicable.
5247    if (!MCID.isPredicable())
5248      return Error(Loc, "instructions in IT block must be predicable");
5249    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5250    unsigned ITCond = bit ? ITState.Cond :
5251      ARMCC::getOppositeCondition(ITState.Cond);
5252    if (Cond != ITCond) {
5253      // Find the condition code Operand to get its SMLoc information.
5254      SMLoc CondLoc;
5255      for (unsigned i = 1; i < Operands.size(); ++i)
5256        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5257          CondLoc = Operands[i]->getStartLoc();
5258      return Error(CondLoc, "incorrect condition in IT block; got '" +
5259                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5260                   "', but expected '" +
5261                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5262    }
5263  // Check for non-'al' condition codes outside of the IT block.
5264  } else if (isThumbTwo() && MCID.isPredicable() &&
5265             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5266             ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5267             Inst.getOpcode() != ARM::t2B)
5268    return Error(Loc, "predicated instructions must be in IT block");
5269
5270  switch (Inst.getOpcode()) {
5271  case ARM::LDRD:
5272  case ARM::LDRD_PRE:
5273  case ARM::LDRD_POST:
5274  case ARM::LDREXD: {
5275    // Rt2 must be Rt + 1.
5276    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5277    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5278    if (Rt2 != Rt + 1)
5279      return Error(Operands[3]->getStartLoc(),
5280                   "destination operands must be sequential");
5281    return false;
5282  }
5283  case ARM::STRD: {
5284    // Rt2 must be Rt + 1.
5285    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5286    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5287    if (Rt2 != Rt + 1)
5288      return Error(Operands[3]->getStartLoc(),
5289                   "source operands must be sequential");
5290    return false;
5291  }
5292  case ARM::STRD_PRE:
5293  case ARM::STRD_POST:
5294  case ARM::STREXD: {
5295    // Rt2 must be Rt + 1.
5296    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5297    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5298    if (Rt2 != Rt + 1)
5299      return Error(Operands[3]->getStartLoc(),
5300                   "source operands must be sequential");
5301    return false;
5302  }
5303  case ARM::SBFX:
5304  case ARM::UBFX: {
5305    // width must be in range [1, 32-lsb]
5306    unsigned lsb = Inst.getOperand(2).getImm();
5307    unsigned widthm1 = Inst.getOperand(3).getImm();
5308    if (widthm1 >= 32 - lsb)
5309      return Error(Operands[5]->getStartLoc(),
5310                   "bitfield width must be in range [1,32-lsb]");
5311    return false;
5312  }
5313  case ARM::tLDMIA: {
5314    // If we're parsing Thumb2, the .w variant is available and handles
5315    // most cases that are normally illegal for a Thumb1 LDM
5316    // instruction. We'll make the transformation in processInstruction()
5317    // if necessary.
5318    //
5319    // Thumb LDM instructions are writeback iff the base register is not
5320    // in the register list.
5321    unsigned Rn = Inst.getOperand(0).getReg();
5322    bool hasWritebackToken =
5323      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5324       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5325    bool listContainsBase;
5326    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5327      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5328                   "registers must be in range r0-r7");
5329    // If we should have writeback, then there should be a '!' token.
5330    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5331      return Error(Operands[2]->getStartLoc(),
5332                   "writeback operator '!' expected");
5333    // If we should not have writeback, there must not be a '!'. This is
5334    // true even for the 32-bit wide encodings.
5335    if (listContainsBase && hasWritebackToken)
5336      return Error(Operands[3]->getStartLoc(),
5337                   "writeback operator '!' not allowed when base register "
5338                   "in register list");
5339
5340    break;
5341  }
5342  case ARM::t2LDMIA_UPD: {
5343    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5344      return Error(Operands[4]->getStartLoc(),
5345                   "writeback operator '!' not allowed when base register "
5346                   "in register list");
5347    break;
5348  }
5349  case ARM::tMUL: {
5350    // The second source operand must be the same register as the destination
5351    // operand.
5352    //
5353    // In this case, we must directly check the parsed operands because the
5354    // cvtThumbMultiply() function is written in such a way that it guarantees
5355    // this first statement is always true for the new Inst.  Essentially, the
5356    // destination is unconditionally copied into the second source operand
5357    // without checking to see if it matches what we actually parsed.
5358    if (Operands.size() == 6 &&
5359        (((ARMOperand*)Operands[3])->getReg() !=
5360         ((ARMOperand*)Operands[5])->getReg()) &&
5361        (((ARMOperand*)Operands[3])->getReg() !=
5362         ((ARMOperand*)Operands[4])->getReg())) {
5363      return Error(Operands[3]->getStartLoc(),
5364                   "destination register must match source register");
5365    }
5366    break;
5367  }
5368  // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5369  // so only issue a diagnostic for thumb1. The instructions will be
5370  // switched to the t2 encodings in processInstruction() if necessary.
5371  case ARM::tPOP: {
5372    bool listContainsBase;
5373    if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5374        !isThumbTwo())
5375      return Error(Operands[2]->getStartLoc(),
5376                   "registers must be in range r0-r7 or pc");
5377    break;
5378  }
5379  case ARM::tPUSH: {
5380    bool listContainsBase;
5381    if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5382        !isThumbTwo())
5383      return Error(Operands[2]->getStartLoc(),
5384                   "registers must be in range r0-r7 or lr");
5385    break;
5386  }
5387  case ARM::tSTMIA_UPD: {
5388    bool listContainsBase;
5389    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5390      return Error(Operands[4]->getStartLoc(),
5391                   "registers must be in range r0-r7");
5392    break;
5393  }
5394  case ARM::tADDrSP: {
5395    // If the non-SP source operand and the destination operand are not the
5396    // same, we need thumb2 (for the wide encoding), or we have an error.
5397    if (!isThumbTwo() &&
5398        Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5399      return Error(Operands[4]->getStartLoc(),
5400                   "source register must be the same as destination");
5401    }
5402    break;
5403  }
5404  }
5405
5406  return false;
5407}
5408
5409static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5410  switch(Opc) {
5411  default: llvm_unreachable("unexpected opcode!");
5412  // VST1LN
5413  case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5414  case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5415  case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5416  case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5417  case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5418  case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5419  case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
5420  case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5421  case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5422
5423  // VST2LN
5424  case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5425  case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5426  case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5427  case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5428  case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5429
5430  case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5431  case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5432  case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5433  case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5434  case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5435
5436  case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
5437  case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5438  case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5439  case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5440  case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5441
5442  // VST3LN
5443  case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5444  case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5445  case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5446  case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5447  case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5448  case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5449  case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5450  case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5451  case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5452  case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5453  case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
5454  case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5455  case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5456  case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5457  case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5458
5459  // VST3
5460  case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5461  case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5462  case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5463  case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5464  case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5465  case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5466  case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5467  case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5468  case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5469  case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5470  case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5471  case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5472  case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
5473  case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5474  case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5475  case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
5476  case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5477  case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5478
5479  // VST4LN
5480  case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5481  case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5482  case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5483  case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5484  case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5485  case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5486  case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5487  case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5488  case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5489  case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5490  case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
5491  case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5492  case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5493  case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5494  case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5495
5496  // VST4
5497  case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5498  case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5499  case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5500  case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5501  case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5502  case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5503  case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5504  case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5505  case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5506  case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5507  case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5508  case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5509  case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
5510  case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5511  case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5512  case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
5513  case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5514  case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5515  }
5516}
5517
5518static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5519  switch(Opc) {
5520  default: llvm_unreachable("unexpected opcode!");
5521  // VLD1LN
5522  case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5523  case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5524  case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5525  case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5526  case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5527  case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5528  case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
5529  case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5530  case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5531
5532  // VLD2LN
5533  case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5534  case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5535  case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5536  case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5537  case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5538  case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5539  case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5540  case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5541  case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5542  case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5543  case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
5544  case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5545  case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5546  case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5547  case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5548
5549  // VLD3DUP
5550  case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5551  case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5552  case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5553  case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5554  case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5555  case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5556  case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5557  case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5558  case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5559  case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5560  case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5561  case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5562  case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
5563  case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5564  case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5565  case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5566  case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5567  case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5568
5569  // VLD3LN
5570  case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5571  case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5572  case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5573  case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5574  case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5575  case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5576  case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5577  case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5578  case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5579  case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5580  case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
5581  case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5582  case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5583  case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5584  case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5585
5586  // VLD3
5587  case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5588  case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5589  case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5590  case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5591  case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5592  case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5593  case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5594  case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5595  case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5596  case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5597  case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5598  case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5599  case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
5600  case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5601  case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5602  case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
5603  case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5604  case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5605
5606  // VLD4LN
5607  case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5608  case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5609  case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5610  case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5611  case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5612  case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5613  case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5614  case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5615  case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5616  case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5617  case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
5618  case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5619  case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5620  case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5621  case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5622
5623  // VLD4DUP
5624  case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5625  case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5626  case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5627  case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5628  case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5629  case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5630  case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5631  case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5632  case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5633  case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5634  case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5635  case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5636  case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
5637  case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5638  case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5639  case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5640  case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5641  case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5642
5643  // VLD4
5644  case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5645  case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5646  case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5647  case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5648  case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5649  case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5650  case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5651  case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5652  case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5653  case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5654  case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5655  case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5656  case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
5657  case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5658  case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5659  case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
5660  case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5661  case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5662  }
5663}
5664
5665bool ARMAsmParser::
5666processInstruction(MCInst &Inst,
5667                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5668  switch (Inst.getOpcode()) {
5669  // Alias for alternate form of 'ADR Rd, #imm' instruction.
5670  case ARM::ADDri: {
5671    if (Inst.getOperand(1).getReg() != ARM::PC ||
5672        Inst.getOperand(5).getReg() != 0)
5673      return false;
5674    MCInst TmpInst;
5675    TmpInst.setOpcode(ARM::ADR);
5676    TmpInst.addOperand(Inst.getOperand(0));
5677    TmpInst.addOperand(Inst.getOperand(2));
5678    TmpInst.addOperand(Inst.getOperand(3));
5679    TmpInst.addOperand(Inst.getOperand(4));
5680    Inst = TmpInst;
5681    return true;
5682  }
5683  // Aliases for alternate PC+imm syntax of LDR instructions.
5684  case ARM::t2LDRpcrel:
5685    Inst.setOpcode(ARM::t2LDRpci);
5686    return true;
5687  case ARM::t2LDRBpcrel:
5688    Inst.setOpcode(ARM::t2LDRBpci);
5689    return true;
5690  case ARM::t2LDRHpcrel:
5691    Inst.setOpcode(ARM::t2LDRHpci);
5692    return true;
5693  case ARM::t2LDRSBpcrel:
5694    Inst.setOpcode(ARM::t2LDRSBpci);
5695    return true;
5696  case ARM::t2LDRSHpcrel:
5697    Inst.setOpcode(ARM::t2LDRSHpci);
5698    return true;
5699  // Handle NEON VST complex aliases.
5700  case ARM::VST1LNdWB_register_Asm_8:
5701  case ARM::VST1LNdWB_register_Asm_16:
5702  case ARM::VST1LNdWB_register_Asm_32: {
5703    MCInst TmpInst;
5704    // Shuffle the operands around so the lane index operand is in the
5705    // right place.
5706    unsigned Spacing;
5707    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5708    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5709    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5710    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5711    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5712    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5713    TmpInst.addOperand(Inst.getOperand(1)); // lane
5714    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5715    TmpInst.addOperand(Inst.getOperand(6));
5716    Inst = TmpInst;
5717    return true;
5718  }
5719
5720  case ARM::VST2LNdWB_register_Asm_8:
5721  case ARM::VST2LNdWB_register_Asm_16:
5722  case ARM::VST2LNdWB_register_Asm_32:
5723  case ARM::VST2LNqWB_register_Asm_16:
5724  case ARM::VST2LNqWB_register_Asm_32: {
5725    MCInst TmpInst;
5726    // Shuffle the operands around so the lane index operand is in the
5727    // right place.
5728    unsigned Spacing;
5729    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5730    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5731    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5732    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5733    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5734    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5735    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5736                                            Spacing));
5737    TmpInst.addOperand(Inst.getOperand(1)); // lane
5738    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5739    TmpInst.addOperand(Inst.getOperand(6));
5740    Inst = TmpInst;
5741    return true;
5742  }
5743
5744  case ARM::VST3LNdWB_register_Asm_8:
5745  case ARM::VST3LNdWB_register_Asm_16:
5746  case ARM::VST3LNdWB_register_Asm_32:
5747  case ARM::VST3LNqWB_register_Asm_16:
5748  case ARM::VST3LNqWB_register_Asm_32: {
5749    MCInst TmpInst;
5750    // Shuffle the operands around so the lane index operand is in the
5751    // right place.
5752    unsigned Spacing;
5753    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5754    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5755    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5756    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5757    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5758    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5759    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5760                                            Spacing));
5761    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5762                                            Spacing * 2));
5763    TmpInst.addOperand(Inst.getOperand(1)); // lane
5764    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5765    TmpInst.addOperand(Inst.getOperand(6));
5766    Inst = TmpInst;
5767    return true;
5768  }
5769
5770  case ARM::VST4LNdWB_register_Asm_8:
5771  case ARM::VST4LNdWB_register_Asm_16:
5772  case ARM::VST4LNdWB_register_Asm_32:
5773  case ARM::VST4LNqWB_register_Asm_16:
5774  case ARM::VST4LNqWB_register_Asm_32: {
5775    MCInst TmpInst;
5776    // Shuffle the operands around so the lane index operand is in the
5777    // right place.
5778    unsigned Spacing;
5779    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5780    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5781    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5782    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5783    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5784    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5785    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5786                                            Spacing));
5787    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5788                                            Spacing * 2));
5789    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5790                                            Spacing * 3));
5791    TmpInst.addOperand(Inst.getOperand(1)); // lane
5792    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5793    TmpInst.addOperand(Inst.getOperand(6));
5794    Inst = TmpInst;
5795    return true;
5796  }
5797
5798  case ARM::VST1LNdWB_fixed_Asm_8:
5799  case ARM::VST1LNdWB_fixed_Asm_16:
5800  case ARM::VST1LNdWB_fixed_Asm_32: {
5801    MCInst TmpInst;
5802    // Shuffle the operands around so the lane index operand is in the
5803    // right place.
5804    unsigned Spacing;
5805    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5806    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5807    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5808    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5809    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5810    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5811    TmpInst.addOperand(Inst.getOperand(1)); // lane
5812    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5813    TmpInst.addOperand(Inst.getOperand(5));
5814    Inst = TmpInst;
5815    return true;
5816  }
5817
5818  case ARM::VST2LNdWB_fixed_Asm_8:
5819  case ARM::VST2LNdWB_fixed_Asm_16:
5820  case ARM::VST2LNdWB_fixed_Asm_32:
5821  case ARM::VST2LNqWB_fixed_Asm_16:
5822  case ARM::VST2LNqWB_fixed_Asm_32: {
5823    MCInst TmpInst;
5824    // Shuffle the operands around so the lane index operand is in the
5825    // right place.
5826    unsigned Spacing;
5827    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5828    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5829    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5830    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5831    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5832    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5833    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5834                                            Spacing));
5835    TmpInst.addOperand(Inst.getOperand(1)); // lane
5836    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5837    TmpInst.addOperand(Inst.getOperand(5));
5838    Inst = TmpInst;
5839    return true;
5840  }
5841
5842  case ARM::VST3LNdWB_fixed_Asm_8:
5843  case ARM::VST3LNdWB_fixed_Asm_16:
5844  case ARM::VST3LNdWB_fixed_Asm_32:
5845  case ARM::VST3LNqWB_fixed_Asm_16:
5846  case ARM::VST3LNqWB_fixed_Asm_32: {
5847    MCInst TmpInst;
5848    // Shuffle the operands around so the lane index operand is in the
5849    // right place.
5850    unsigned Spacing;
5851    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5852    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5853    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5854    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5855    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5856    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5857    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5858                                            Spacing));
5859    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5860                                            Spacing * 2));
5861    TmpInst.addOperand(Inst.getOperand(1)); // lane
5862    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5863    TmpInst.addOperand(Inst.getOperand(5));
5864    Inst = TmpInst;
5865    return true;
5866  }
5867
5868  case ARM::VST4LNdWB_fixed_Asm_8:
5869  case ARM::VST4LNdWB_fixed_Asm_16:
5870  case ARM::VST4LNdWB_fixed_Asm_32:
5871  case ARM::VST4LNqWB_fixed_Asm_16:
5872  case ARM::VST4LNqWB_fixed_Asm_32: {
5873    MCInst TmpInst;
5874    // Shuffle the operands around so the lane index operand is in the
5875    // right place.
5876    unsigned Spacing;
5877    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5878    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5879    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5880    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5881    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5882    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5883    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5884                                            Spacing));
5885    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5886                                            Spacing * 2));
5887    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5888                                            Spacing * 3));
5889    TmpInst.addOperand(Inst.getOperand(1)); // lane
5890    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5891    TmpInst.addOperand(Inst.getOperand(5));
5892    Inst = TmpInst;
5893    return true;
5894  }
5895
5896  case ARM::VST1LNdAsm_8:
5897  case ARM::VST1LNdAsm_16:
5898  case ARM::VST1LNdAsm_32: {
5899    MCInst TmpInst;
5900    // Shuffle the operands around so the lane index operand is in the
5901    // right place.
5902    unsigned Spacing;
5903    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5904    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5905    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5906    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5907    TmpInst.addOperand(Inst.getOperand(1)); // lane
5908    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5909    TmpInst.addOperand(Inst.getOperand(5));
5910    Inst = TmpInst;
5911    return true;
5912  }
5913
5914  case ARM::VST2LNdAsm_8:
5915  case ARM::VST2LNdAsm_16:
5916  case ARM::VST2LNdAsm_32:
5917  case ARM::VST2LNqAsm_16:
5918  case ARM::VST2LNqAsm_32: {
5919    MCInst TmpInst;
5920    // Shuffle the operands around so the lane index operand is in the
5921    // right place.
5922    unsigned Spacing;
5923    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5924    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5925    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5926    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5927    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5928                                            Spacing));
5929    TmpInst.addOperand(Inst.getOperand(1)); // lane
5930    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5931    TmpInst.addOperand(Inst.getOperand(5));
5932    Inst = TmpInst;
5933    return true;
5934  }
5935
5936  case ARM::VST3LNdAsm_8:
5937  case ARM::VST3LNdAsm_16:
5938  case ARM::VST3LNdAsm_32:
5939  case ARM::VST3LNqAsm_16:
5940  case ARM::VST3LNqAsm_32: {
5941    MCInst TmpInst;
5942    // Shuffle the operands around so the lane index operand is in the
5943    // right place.
5944    unsigned Spacing;
5945    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5946    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5947    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5948    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5949    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5950                                            Spacing));
5951    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5952                                            Spacing * 2));
5953    TmpInst.addOperand(Inst.getOperand(1)); // lane
5954    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5955    TmpInst.addOperand(Inst.getOperand(5));
5956    Inst = TmpInst;
5957    return true;
5958  }
5959
5960  case ARM::VST4LNdAsm_8:
5961  case ARM::VST4LNdAsm_16:
5962  case ARM::VST4LNdAsm_32:
5963  case ARM::VST4LNqAsm_16:
5964  case ARM::VST4LNqAsm_32: {
5965    MCInst TmpInst;
5966    // Shuffle the operands around so the lane index operand is in the
5967    // right place.
5968    unsigned Spacing;
5969    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5970    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5971    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5972    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5973    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5974                                            Spacing));
5975    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5976                                            Spacing * 2));
5977    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5978                                            Spacing * 3));
5979    TmpInst.addOperand(Inst.getOperand(1)); // lane
5980    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5981    TmpInst.addOperand(Inst.getOperand(5));
5982    Inst = TmpInst;
5983    return true;
5984  }
5985
5986  // Handle NEON VLD complex aliases.
5987  case ARM::VLD1LNdWB_register_Asm_8:
5988  case ARM::VLD1LNdWB_register_Asm_16:
5989  case ARM::VLD1LNdWB_register_Asm_32: {
5990    MCInst TmpInst;
5991    // Shuffle the operands around so the lane index operand is in the
5992    // right place.
5993    unsigned Spacing;
5994    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5995    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5996    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5997    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5998    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5999    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6000    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6001    TmpInst.addOperand(Inst.getOperand(1)); // lane
6002    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6003    TmpInst.addOperand(Inst.getOperand(6));
6004    Inst = TmpInst;
6005    return true;
6006  }
6007
6008  case ARM::VLD2LNdWB_register_Asm_8:
6009  case ARM::VLD2LNdWB_register_Asm_16:
6010  case ARM::VLD2LNdWB_register_Asm_32:
6011  case ARM::VLD2LNqWB_register_Asm_16:
6012  case ARM::VLD2LNqWB_register_Asm_32: {
6013    MCInst TmpInst;
6014    // Shuffle the operands around so the lane index operand is in the
6015    // right place.
6016    unsigned Spacing;
6017    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6018    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6019    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6020                                            Spacing));
6021    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6022    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6023    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6024    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6025    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6026    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6027                                            Spacing));
6028    TmpInst.addOperand(Inst.getOperand(1)); // lane
6029    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6030    TmpInst.addOperand(Inst.getOperand(6));
6031    Inst = TmpInst;
6032    return true;
6033  }
6034
6035  case ARM::VLD3LNdWB_register_Asm_8:
6036  case ARM::VLD3LNdWB_register_Asm_16:
6037  case ARM::VLD3LNdWB_register_Asm_32:
6038  case ARM::VLD3LNqWB_register_Asm_16:
6039  case ARM::VLD3LNqWB_register_Asm_32: {
6040    MCInst TmpInst;
6041    // Shuffle the operands around so the lane index operand is in the
6042    // right place.
6043    unsigned Spacing;
6044    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6045    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6046    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6047                                            Spacing));
6048    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6049                                            Spacing * 2));
6050    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6051    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6052    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6053    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6054    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6055    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6056                                            Spacing));
6057    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6058                                            Spacing * 2));
6059    TmpInst.addOperand(Inst.getOperand(1)); // lane
6060    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6061    TmpInst.addOperand(Inst.getOperand(6));
6062    Inst = TmpInst;
6063    return true;
6064  }
6065
6066  case ARM::VLD4LNdWB_register_Asm_8:
6067  case ARM::VLD4LNdWB_register_Asm_16:
6068  case ARM::VLD4LNdWB_register_Asm_32:
6069  case ARM::VLD4LNqWB_register_Asm_16:
6070  case ARM::VLD4LNqWB_register_Asm_32: {
6071    MCInst TmpInst;
6072    // Shuffle the operands around so the lane index operand is in the
6073    // right place.
6074    unsigned Spacing;
6075    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6076    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6077    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6078                                            Spacing));
6079    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6080                                            Spacing * 2));
6081    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6082                                            Spacing * 3));
6083    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6084    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6085    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6086    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6087    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6088    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6089                                            Spacing));
6090    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6091                                            Spacing * 2));
6092    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6093                                            Spacing * 3));
6094    TmpInst.addOperand(Inst.getOperand(1)); // lane
6095    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6096    TmpInst.addOperand(Inst.getOperand(6));
6097    Inst = TmpInst;
6098    return true;
6099  }
6100
6101  case ARM::VLD1LNdWB_fixed_Asm_8:
6102  case ARM::VLD1LNdWB_fixed_Asm_16:
6103  case ARM::VLD1LNdWB_fixed_Asm_32: {
6104    MCInst TmpInst;
6105    // Shuffle the operands around so the lane index operand is in the
6106    // right place.
6107    unsigned Spacing;
6108    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6109    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6110    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6111    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6112    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6113    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6114    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6115    TmpInst.addOperand(Inst.getOperand(1)); // lane
6116    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6117    TmpInst.addOperand(Inst.getOperand(5));
6118    Inst = TmpInst;
6119    return true;
6120  }
6121
6122  case ARM::VLD2LNdWB_fixed_Asm_8:
6123  case ARM::VLD2LNdWB_fixed_Asm_16:
6124  case ARM::VLD2LNdWB_fixed_Asm_32:
6125  case ARM::VLD2LNqWB_fixed_Asm_16:
6126  case ARM::VLD2LNqWB_fixed_Asm_32: {
6127    MCInst TmpInst;
6128    // Shuffle the operands around so the lane index operand is in the
6129    // right place.
6130    unsigned Spacing;
6131    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6132    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6133    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6134                                            Spacing));
6135    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6136    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6137    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6138    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6139    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6140    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6141                                            Spacing));
6142    TmpInst.addOperand(Inst.getOperand(1)); // lane
6143    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6144    TmpInst.addOperand(Inst.getOperand(5));
6145    Inst = TmpInst;
6146    return true;
6147  }
6148
6149  case ARM::VLD3LNdWB_fixed_Asm_8:
6150  case ARM::VLD3LNdWB_fixed_Asm_16:
6151  case ARM::VLD3LNdWB_fixed_Asm_32:
6152  case ARM::VLD3LNqWB_fixed_Asm_16:
6153  case ARM::VLD3LNqWB_fixed_Asm_32: {
6154    MCInst TmpInst;
6155    // Shuffle the operands around so the lane index operand is in the
6156    // right place.
6157    unsigned Spacing;
6158    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6159    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6160    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6161                                            Spacing));
6162    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6163                                            Spacing * 2));
6164    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6165    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6166    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6167    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6168    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6169    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6170                                            Spacing));
6171    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6172                                            Spacing * 2));
6173    TmpInst.addOperand(Inst.getOperand(1)); // lane
6174    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6175    TmpInst.addOperand(Inst.getOperand(5));
6176    Inst = TmpInst;
6177    return true;
6178  }
6179
6180  case ARM::VLD4LNdWB_fixed_Asm_8:
6181  case ARM::VLD4LNdWB_fixed_Asm_16:
6182  case ARM::VLD4LNdWB_fixed_Asm_32:
6183  case ARM::VLD4LNqWB_fixed_Asm_16:
6184  case ARM::VLD4LNqWB_fixed_Asm_32: {
6185    MCInst TmpInst;
6186    // Shuffle the operands around so the lane index operand is in the
6187    // right place.
6188    unsigned Spacing;
6189    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6190    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6191    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6192                                            Spacing));
6193    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6194                                            Spacing * 2));
6195    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6196                                            Spacing * 3));
6197    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6198    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6199    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6200    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6201    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6202    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6203                                            Spacing));
6204    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6205                                            Spacing * 2));
6206    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6207                                            Spacing * 3));
6208    TmpInst.addOperand(Inst.getOperand(1)); // lane
6209    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6210    TmpInst.addOperand(Inst.getOperand(5));
6211    Inst = TmpInst;
6212    return true;
6213  }
6214
6215  case ARM::VLD1LNdAsm_8:
6216  case ARM::VLD1LNdAsm_16:
6217  case ARM::VLD1LNdAsm_32: {
6218    MCInst TmpInst;
6219    // Shuffle the operands around so the lane index operand is in the
6220    // right place.
6221    unsigned Spacing;
6222    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6223    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6224    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6225    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6226    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6227    TmpInst.addOperand(Inst.getOperand(1)); // lane
6228    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6229    TmpInst.addOperand(Inst.getOperand(5));
6230    Inst = TmpInst;
6231    return true;
6232  }
6233
6234  case ARM::VLD2LNdAsm_8:
6235  case ARM::VLD2LNdAsm_16:
6236  case ARM::VLD2LNdAsm_32:
6237  case ARM::VLD2LNqAsm_16:
6238  case ARM::VLD2LNqAsm_32: {
6239    MCInst TmpInst;
6240    // Shuffle the operands around so the lane index operand is in the
6241    // right place.
6242    unsigned Spacing;
6243    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6244    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6245    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6246                                            Spacing));
6247    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6248    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6249    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6250    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6251                                            Spacing));
6252    TmpInst.addOperand(Inst.getOperand(1)); // lane
6253    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6254    TmpInst.addOperand(Inst.getOperand(5));
6255    Inst = TmpInst;
6256    return true;
6257  }
6258
6259  case ARM::VLD3LNdAsm_8:
6260  case ARM::VLD3LNdAsm_16:
6261  case ARM::VLD3LNdAsm_32:
6262  case ARM::VLD3LNqAsm_16:
6263  case ARM::VLD3LNqAsm_32: {
6264    MCInst TmpInst;
6265    // Shuffle the operands around so the lane index operand is in the
6266    // right place.
6267    unsigned Spacing;
6268    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6269    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6270    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6271                                            Spacing));
6272    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6273                                            Spacing * 2));
6274    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6275    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6276    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6277    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6278                                            Spacing));
6279    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6280                                            Spacing * 2));
6281    TmpInst.addOperand(Inst.getOperand(1)); // lane
6282    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6283    TmpInst.addOperand(Inst.getOperand(5));
6284    Inst = TmpInst;
6285    return true;
6286  }
6287
6288  case ARM::VLD4LNdAsm_8:
6289  case ARM::VLD4LNdAsm_16:
6290  case ARM::VLD4LNdAsm_32:
6291  case ARM::VLD4LNqAsm_16:
6292  case ARM::VLD4LNqAsm_32: {
6293    MCInst TmpInst;
6294    // Shuffle the operands around so the lane index operand is in the
6295    // right place.
6296    unsigned Spacing;
6297    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6298    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6299    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6300                                            Spacing));
6301    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6302                                            Spacing * 2));
6303    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6304                                            Spacing * 3));
6305    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6306    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6307    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6308    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6309                                            Spacing));
6310    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6311                                            Spacing * 2));
6312    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6313                                            Spacing * 3));
6314    TmpInst.addOperand(Inst.getOperand(1)); // lane
6315    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6316    TmpInst.addOperand(Inst.getOperand(5));
6317    Inst = TmpInst;
6318    return true;
6319  }
6320
6321  // VLD3DUP single 3-element structure to all lanes instructions.
6322  case ARM::VLD3DUPdAsm_8:
6323  case ARM::VLD3DUPdAsm_16:
6324  case ARM::VLD3DUPdAsm_32:
6325  case ARM::VLD3DUPqAsm_8:
6326  case ARM::VLD3DUPqAsm_16:
6327  case ARM::VLD3DUPqAsm_32: {
6328    MCInst TmpInst;
6329    unsigned Spacing;
6330    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6331    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6332    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6333                                            Spacing));
6334    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6335                                            Spacing * 2));
6336    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6337    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6338    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6339    TmpInst.addOperand(Inst.getOperand(4));
6340    Inst = TmpInst;
6341    return true;
6342  }
6343
6344  case ARM::VLD3DUPdWB_fixed_Asm_8:
6345  case ARM::VLD3DUPdWB_fixed_Asm_16:
6346  case ARM::VLD3DUPdWB_fixed_Asm_32:
6347  case ARM::VLD3DUPqWB_fixed_Asm_8:
6348  case ARM::VLD3DUPqWB_fixed_Asm_16:
6349  case ARM::VLD3DUPqWB_fixed_Asm_32: {
6350    MCInst TmpInst;
6351    unsigned Spacing;
6352    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6353    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6354    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6355                                            Spacing));
6356    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6357                                            Spacing * 2));
6358    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6359    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6360    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6361    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6362    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6363    TmpInst.addOperand(Inst.getOperand(4));
6364    Inst = TmpInst;
6365    return true;
6366  }
6367
6368  case ARM::VLD3DUPdWB_register_Asm_8:
6369  case ARM::VLD3DUPdWB_register_Asm_16:
6370  case ARM::VLD3DUPdWB_register_Asm_32:
6371  case ARM::VLD3DUPqWB_register_Asm_8:
6372  case ARM::VLD3DUPqWB_register_Asm_16:
6373  case ARM::VLD3DUPqWB_register_Asm_32: {
6374    MCInst TmpInst;
6375    unsigned Spacing;
6376    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6377    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6378    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6379                                            Spacing));
6380    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6381                                            Spacing * 2));
6382    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6383    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6384    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6385    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6386    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6387    TmpInst.addOperand(Inst.getOperand(5));
6388    Inst = TmpInst;
6389    return true;
6390  }
6391
6392  // VLD3 multiple 3-element structure instructions.
6393  case ARM::VLD3dAsm_8:
6394  case ARM::VLD3dAsm_16:
6395  case ARM::VLD3dAsm_32:
6396  case ARM::VLD3qAsm_8:
6397  case ARM::VLD3qAsm_16:
6398  case ARM::VLD3qAsm_32: {
6399    MCInst TmpInst;
6400    unsigned Spacing;
6401    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6402    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6403    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6404                                            Spacing));
6405    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6406                                            Spacing * 2));
6407    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6408    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6409    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6410    TmpInst.addOperand(Inst.getOperand(4));
6411    Inst = TmpInst;
6412    return true;
6413  }
6414
6415  case ARM::VLD3dWB_fixed_Asm_8:
6416  case ARM::VLD3dWB_fixed_Asm_16:
6417  case ARM::VLD3dWB_fixed_Asm_32:
6418  case ARM::VLD3qWB_fixed_Asm_8:
6419  case ARM::VLD3qWB_fixed_Asm_16:
6420  case ARM::VLD3qWB_fixed_Asm_32: {
6421    MCInst TmpInst;
6422    unsigned Spacing;
6423    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6424    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6425    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6426                                            Spacing));
6427    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6428                                            Spacing * 2));
6429    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6430    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6431    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6432    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6433    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6434    TmpInst.addOperand(Inst.getOperand(4));
6435    Inst = TmpInst;
6436    return true;
6437  }
6438
6439  case ARM::VLD3dWB_register_Asm_8:
6440  case ARM::VLD3dWB_register_Asm_16:
6441  case ARM::VLD3dWB_register_Asm_32:
6442  case ARM::VLD3qWB_register_Asm_8:
6443  case ARM::VLD3qWB_register_Asm_16:
6444  case ARM::VLD3qWB_register_Asm_32: {
6445    MCInst TmpInst;
6446    unsigned Spacing;
6447    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6448    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6449    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6450                                            Spacing));
6451    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6452                                            Spacing * 2));
6453    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6454    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6455    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6456    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6457    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6458    TmpInst.addOperand(Inst.getOperand(5));
6459    Inst = TmpInst;
6460    return true;
6461  }
6462
6463  // VLD4DUP single 3-element structure to all lanes instructions.
6464  case ARM::VLD4DUPdAsm_8:
6465  case ARM::VLD4DUPdAsm_16:
6466  case ARM::VLD4DUPdAsm_32:
6467  case ARM::VLD4DUPqAsm_8:
6468  case ARM::VLD4DUPqAsm_16:
6469  case ARM::VLD4DUPqAsm_32: {
6470    MCInst TmpInst;
6471    unsigned Spacing;
6472    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6473    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6474    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6475                                            Spacing));
6476    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6477                                            Spacing * 2));
6478    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6479                                            Spacing * 3));
6480    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6481    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6482    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6483    TmpInst.addOperand(Inst.getOperand(4));
6484    Inst = TmpInst;
6485    return true;
6486  }
6487
6488  case ARM::VLD4DUPdWB_fixed_Asm_8:
6489  case ARM::VLD4DUPdWB_fixed_Asm_16:
6490  case ARM::VLD4DUPdWB_fixed_Asm_32:
6491  case ARM::VLD4DUPqWB_fixed_Asm_8:
6492  case ARM::VLD4DUPqWB_fixed_Asm_16:
6493  case ARM::VLD4DUPqWB_fixed_Asm_32: {
6494    MCInst TmpInst;
6495    unsigned Spacing;
6496    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6497    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6498    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6499                                            Spacing));
6500    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6501                                            Spacing * 2));
6502    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6503                                            Spacing * 3));
6504    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6505    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6506    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6507    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6508    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6509    TmpInst.addOperand(Inst.getOperand(4));
6510    Inst = TmpInst;
6511    return true;
6512  }
6513
6514  case ARM::VLD4DUPdWB_register_Asm_8:
6515  case ARM::VLD4DUPdWB_register_Asm_16:
6516  case ARM::VLD4DUPdWB_register_Asm_32:
6517  case ARM::VLD4DUPqWB_register_Asm_8:
6518  case ARM::VLD4DUPqWB_register_Asm_16:
6519  case ARM::VLD4DUPqWB_register_Asm_32: {
6520    MCInst TmpInst;
6521    unsigned Spacing;
6522    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6523    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6524    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6525                                            Spacing));
6526    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6527                                            Spacing * 2));
6528    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6529                                            Spacing * 3));
6530    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6531    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6532    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6533    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6534    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6535    TmpInst.addOperand(Inst.getOperand(5));
6536    Inst = TmpInst;
6537    return true;
6538  }
6539
6540  // VLD4 multiple 4-element structure instructions.
6541  case ARM::VLD4dAsm_8:
6542  case ARM::VLD4dAsm_16:
6543  case ARM::VLD4dAsm_32:
6544  case ARM::VLD4qAsm_8:
6545  case ARM::VLD4qAsm_16:
6546  case ARM::VLD4qAsm_32: {
6547    MCInst TmpInst;
6548    unsigned Spacing;
6549    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6550    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6551    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6552                                            Spacing));
6553    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6554                                            Spacing * 2));
6555    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6556                                            Spacing * 3));
6557    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6558    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6559    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6560    TmpInst.addOperand(Inst.getOperand(4));
6561    Inst = TmpInst;
6562    return true;
6563  }
6564
6565  case ARM::VLD4dWB_fixed_Asm_8:
6566  case ARM::VLD4dWB_fixed_Asm_16:
6567  case ARM::VLD4dWB_fixed_Asm_32:
6568  case ARM::VLD4qWB_fixed_Asm_8:
6569  case ARM::VLD4qWB_fixed_Asm_16:
6570  case ARM::VLD4qWB_fixed_Asm_32: {
6571    MCInst TmpInst;
6572    unsigned Spacing;
6573    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6574    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6575    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6576                                            Spacing));
6577    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6578                                            Spacing * 2));
6579    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6580                                            Spacing * 3));
6581    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6582    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6583    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6584    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6585    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6586    TmpInst.addOperand(Inst.getOperand(4));
6587    Inst = TmpInst;
6588    return true;
6589  }
6590
6591  case ARM::VLD4dWB_register_Asm_8:
6592  case ARM::VLD4dWB_register_Asm_16:
6593  case ARM::VLD4dWB_register_Asm_32:
6594  case ARM::VLD4qWB_register_Asm_8:
6595  case ARM::VLD4qWB_register_Asm_16:
6596  case ARM::VLD4qWB_register_Asm_32: {
6597    MCInst TmpInst;
6598    unsigned Spacing;
6599    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6600    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6601    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6602                                            Spacing));
6603    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6604                                            Spacing * 2));
6605    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6606                                            Spacing * 3));
6607    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6608    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6609    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6610    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6611    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6612    TmpInst.addOperand(Inst.getOperand(5));
6613    Inst = TmpInst;
6614    return true;
6615  }
6616
6617  // VST3 multiple 3-element structure instructions.
6618  case ARM::VST3dAsm_8:
6619  case ARM::VST3dAsm_16:
6620  case ARM::VST3dAsm_32:
6621  case ARM::VST3qAsm_8:
6622  case ARM::VST3qAsm_16:
6623  case ARM::VST3qAsm_32: {
6624    MCInst TmpInst;
6625    unsigned Spacing;
6626    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6627    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6628    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6629    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6630    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6631                                            Spacing));
6632    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6633                                            Spacing * 2));
6634    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6635    TmpInst.addOperand(Inst.getOperand(4));
6636    Inst = TmpInst;
6637    return true;
6638  }
6639
6640  case ARM::VST3dWB_fixed_Asm_8:
6641  case ARM::VST3dWB_fixed_Asm_16:
6642  case ARM::VST3dWB_fixed_Asm_32:
6643  case ARM::VST3qWB_fixed_Asm_8:
6644  case ARM::VST3qWB_fixed_Asm_16:
6645  case ARM::VST3qWB_fixed_Asm_32: {
6646    MCInst TmpInst;
6647    unsigned Spacing;
6648    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6649    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6650    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6651    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6652    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6653    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6654    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6655                                            Spacing));
6656    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6657                                            Spacing * 2));
6658    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6659    TmpInst.addOperand(Inst.getOperand(4));
6660    Inst = TmpInst;
6661    return true;
6662  }
6663
6664  case ARM::VST3dWB_register_Asm_8:
6665  case ARM::VST3dWB_register_Asm_16:
6666  case ARM::VST3dWB_register_Asm_32:
6667  case ARM::VST3qWB_register_Asm_8:
6668  case ARM::VST3qWB_register_Asm_16:
6669  case ARM::VST3qWB_register_Asm_32: {
6670    MCInst TmpInst;
6671    unsigned Spacing;
6672    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6673    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6674    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6675    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6676    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6677    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6678    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6679                                            Spacing));
6680    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6681                                            Spacing * 2));
6682    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6683    TmpInst.addOperand(Inst.getOperand(5));
6684    Inst = TmpInst;
6685    return true;
6686  }
6687
6688  // VST4 multiple 3-element structure instructions.
6689  case ARM::VST4dAsm_8:
6690  case ARM::VST4dAsm_16:
6691  case ARM::VST4dAsm_32:
6692  case ARM::VST4qAsm_8:
6693  case ARM::VST4qAsm_16:
6694  case ARM::VST4qAsm_32: {
6695    MCInst TmpInst;
6696    unsigned Spacing;
6697    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6698    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6699    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6700    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6701    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6702                                            Spacing));
6703    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6704                                            Spacing * 2));
6705    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6706                                            Spacing * 3));
6707    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6708    TmpInst.addOperand(Inst.getOperand(4));
6709    Inst = TmpInst;
6710    return true;
6711  }
6712
6713  case ARM::VST4dWB_fixed_Asm_8:
6714  case ARM::VST4dWB_fixed_Asm_16:
6715  case ARM::VST4dWB_fixed_Asm_32:
6716  case ARM::VST4qWB_fixed_Asm_8:
6717  case ARM::VST4qWB_fixed_Asm_16:
6718  case ARM::VST4qWB_fixed_Asm_32: {
6719    MCInst TmpInst;
6720    unsigned Spacing;
6721    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6722    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6723    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6724    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6725    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6726    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6727    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6728                                            Spacing));
6729    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6730                                            Spacing * 2));
6731    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6732                                            Spacing * 3));
6733    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6734    TmpInst.addOperand(Inst.getOperand(4));
6735    Inst = TmpInst;
6736    return true;
6737  }
6738
6739  case ARM::VST4dWB_register_Asm_8:
6740  case ARM::VST4dWB_register_Asm_16:
6741  case ARM::VST4dWB_register_Asm_32:
6742  case ARM::VST4qWB_register_Asm_8:
6743  case ARM::VST4qWB_register_Asm_16:
6744  case ARM::VST4qWB_register_Asm_32: {
6745    MCInst TmpInst;
6746    unsigned Spacing;
6747    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6748    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6749    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6750    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6751    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6752    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6753    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6754                                            Spacing));
6755    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6756                                            Spacing * 2));
6757    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6758                                            Spacing * 3));
6759    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6760    TmpInst.addOperand(Inst.getOperand(5));
6761    Inst = TmpInst;
6762    return true;
6763  }
6764
6765  // Handle encoding choice for the shift-immediate instructions.
6766  case ARM::t2LSLri:
6767  case ARM::t2LSRri:
6768  case ARM::t2ASRri: {
6769    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6770        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6771        Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6772        !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6773         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6774      unsigned NewOpc;
6775      switch (Inst.getOpcode()) {
6776      default: llvm_unreachable("unexpected opcode");
6777      case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6778      case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6779      case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6780      }
6781      // The Thumb1 operands aren't in the same order. Awesome, eh?
6782      MCInst TmpInst;
6783      TmpInst.setOpcode(NewOpc);
6784      TmpInst.addOperand(Inst.getOperand(0));
6785      TmpInst.addOperand(Inst.getOperand(5));
6786      TmpInst.addOperand(Inst.getOperand(1));
6787      TmpInst.addOperand(Inst.getOperand(2));
6788      TmpInst.addOperand(Inst.getOperand(3));
6789      TmpInst.addOperand(Inst.getOperand(4));
6790      Inst = TmpInst;
6791      return true;
6792    }
6793    return false;
6794  }
6795
6796  // Handle the Thumb2 mode MOV complex aliases.
6797  case ARM::t2MOVsr:
6798  case ARM::t2MOVSsr: {
6799    // Which instruction to expand to depends on the CCOut operand and
6800    // whether we're in an IT block if the register operands are low
6801    // registers.
6802    bool isNarrow = false;
6803    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6804        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6805        isARMLowRegister(Inst.getOperand(2).getReg()) &&
6806        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6807        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6808      isNarrow = true;
6809    MCInst TmpInst;
6810    unsigned newOpc;
6811    switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6812    default: llvm_unreachable("unexpected opcode!");
6813    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6814    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6815    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6816    case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
6817    }
6818    TmpInst.setOpcode(newOpc);
6819    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6820    if (isNarrow)
6821      TmpInst.addOperand(MCOperand::CreateReg(
6822          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6823    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6824    TmpInst.addOperand(Inst.getOperand(2)); // Rm
6825    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6826    TmpInst.addOperand(Inst.getOperand(5));
6827    if (!isNarrow)
6828      TmpInst.addOperand(MCOperand::CreateReg(
6829          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6830    Inst = TmpInst;
6831    return true;
6832  }
6833  case ARM::t2MOVsi:
6834  case ARM::t2MOVSsi: {
6835    // Which instruction to expand to depends on the CCOut operand and
6836    // whether we're in an IT block if the register operands are low
6837    // registers.
6838    bool isNarrow = false;
6839    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6840        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6841        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6842      isNarrow = true;
6843    MCInst TmpInst;
6844    unsigned newOpc;
6845    switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6846    default: llvm_unreachable("unexpected opcode!");
6847    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6848    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6849    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6850    case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6851    case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6852    }
6853    unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6854    if (Amount == 32) Amount = 0;
6855    TmpInst.setOpcode(newOpc);
6856    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6857    if (isNarrow)
6858      TmpInst.addOperand(MCOperand::CreateReg(
6859          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6860    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6861    if (newOpc != ARM::t2RRX)
6862      TmpInst.addOperand(MCOperand::CreateImm(Amount));
6863    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6864    TmpInst.addOperand(Inst.getOperand(4));
6865    if (!isNarrow)
6866      TmpInst.addOperand(MCOperand::CreateReg(
6867          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6868    Inst = TmpInst;
6869    return true;
6870  }
6871  // Handle the ARM mode MOV complex aliases.
6872  case ARM::ASRr:
6873  case ARM::LSRr:
6874  case ARM::LSLr:
6875  case ARM::RORr: {
6876    ARM_AM::ShiftOpc ShiftTy;
6877    switch(Inst.getOpcode()) {
6878    default: llvm_unreachable("unexpected opcode!");
6879    case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6880    case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6881    case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6882    case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6883    }
6884    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6885    MCInst TmpInst;
6886    TmpInst.setOpcode(ARM::MOVsr);
6887    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6888    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6889    TmpInst.addOperand(Inst.getOperand(2)); // Rm
6890    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6891    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6892    TmpInst.addOperand(Inst.getOperand(4));
6893    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6894    Inst = TmpInst;
6895    return true;
6896  }
6897  case ARM::ASRi:
6898  case ARM::LSRi:
6899  case ARM::LSLi:
6900  case ARM::RORi: {
6901    ARM_AM::ShiftOpc ShiftTy;
6902    switch(Inst.getOpcode()) {
6903    default: llvm_unreachable("unexpected opcode!");
6904    case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6905    case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6906    case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
6907    case ARM::RORi: ShiftTy = ARM_AM::ror; break;
6908    }
6909    // A shift by zero is a plain MOVr, not a MOVsi.
6910    unsigned Amt = Inst.getOperand(2).getImm();
6911    unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6912    // A shift by 32 should be encoded as 0 when permitted
6913    if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
6914      Amt = 0;
6915    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
6916    MCInst TmpInst;
6917    TmpInst.setOpcode(Opc);
6918    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6919    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6920    if (Opc == ARM::MOVsi)
6921      TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6922    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6923    TmpInst.addOperand(Inst.getOperand(4));
6924    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6925    Inst = TmpInst;
6926    return true;
6927  }
6928  case ARM::RRXi: {
6929    unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
6930    MCInst TmpInst;
6931    TmpInst.setOpcode(ARM::MOVsi);
6932    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6933    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6934    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6935    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6936    TmpInst.addOperand(Inst.getOperand(3));
6937    TmpInst.addOperand(Inst.getOperand(4)); // cc_out
6938    Inst = TmpInst;
6939    return true;
6940  }
6941  case ARM::t2LDMIA_UPD: {
6942    // If this is a load of a single register, then we should use
6943    // a post-indexed LDR instruction instead, per the ARM ARM.
6944    if (Inst.getNumOperands() != 5)
6945      return false;
6946    MCInst TmpInst;
6947    TmpInst.setOpcode(ARM::t2LDR_POST);
6948    TmpInst.addOperand(Inst.getOperand(4)); // Rt
6949    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6950    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6951    TmpInst.addOperand(MCOperand::CreateImm(4));
6952    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6953    TmpInst.addOperand(Inst.getOperand(3));
6954    Inst = TmpInst;
6955    return true;
6956  }
6957  case ARM::t2STMDB_UPD: {
6958    // If this is a store of a single register, then we should use
6959    // a pre-indexed STR instruction instead, per the ARM ARM.
6960    if (Inst.getNumOperands() != 5)
6961      return false;
6962    MCInst TmpInst;
6963    TmpInst.setOpcode(ARM::t2STR_PRE);
6964    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6965    TmpInst.addOperand(Inst.getOperand(4)); // Rt
6966    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6967    TmpInst.addOperand(MCOperand::CreateImm(-4));
6968    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6969    TmpInst.addOperand(Inst.getOperand(3));
6970    Inst = TmpInst;
6971    return true;
6972  }
6973  case ARM::LDMIA_UPD:
6974    // If this is a load of a single register via a 'pop', then we should use
6975    // a post-indexed LDR instruction instead, per the ARM ARM.
6976    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
6977        Inst.getNumOperands() == 5) {
6978      MCInst TmpInst;
6979      TmpInst.setOpcode(ARM::LDR_POST_IMM);
6980      TmpInst.addOperand(Inst.getOperand(4)); // Rt
6981      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6982      TmpInst.addOperand(Inst.getOperand(1)); // Rn
6983      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
6984      TmpInst.addOperand(MCOperand::CreateImm(4));
6985      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6986      TmpInst.addOperand(Inst.getOperand(3));
6987      Inst = TmpInst;
6988      return true;
6989    }
6990    break;
6991  case ARM::STMDB_UPD:
6992    // If this is a store of a single register via a 'push', then we should use
6993    // a pre-indexed STR instruction instead, per the ARM ARM.
6994    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
6995        Inst.getNumOperands() == 5) {
6996      MCInst TmpInst;
6997      TmpInst.setOpcode(ARM::STR_PRE_IMM);
6998      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6999      TmpInst.addOperand(Inst.getOperand(4)); // Rt
7000      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7001      TmpInst.addOperand(MCOperand::CreateImm(-4));
7002      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7003      TmpInst.addOperand(Inst.getOperand(3));
7004      Inst = TmpInst;
7005    }
7006    break;
7007  case ARM::t2ADDri12:
7008    // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7009    // mnemonic was used (not "addw"), encoding T3 is preferred.
7010    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7011        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7012      break;
7013    Inst.setOpcode(ARM::t2ADDri);
7014    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7015    break;
7016  case ARM::t2SUBri12:
7017    // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7018    // mnemonic was used (not "subw"), encoding T3 is preferred.
7019    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7020        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7021      break;
7022    Inst.setOpcode(ARM::t2SUBri);
7023    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7024    break;
7025  case ARM::tADDi8:
7026    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7027    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7028    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7029    // to encoding T1 if <Rd> is omitted."
7030    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7031      Inst.setOpcode(ARM::tADDi3);
7032      return true;
7033    }
7034    break;
7035  case ARM::tSUBi8:
7036    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7037    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7038    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7039    // to encoding T1 if <Rd> is omitted."
7040    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7041      Inst.setOpcode(ARM::tSUBi3);
7042      return true;
7043    }
7044    break;
7045  case ARM::t2ADDri:
7046  case ARM::t2SUBri: {
7047    // If the destination and first source operand are the same, and
7048    // the flags are compatible with the current IT status, use encoding T2
7049    // instead of T3. For compatibility with the system 'as'. Make sure the
7050    // wide encoding wasn't explicit.
7051    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7052        !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7053        (unsigned)Inst.getOperand(2).getImm() > 255 ||
7054        ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7055        (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7056        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7057         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7058      break;
7059    MCInst TmpInst;
7060    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7061                      ARM::tADDi8 : ARM::tSUBi8);
7062    TmpInst.addOperand(Inst.getOperand(0));
7063    TmpInst.addOperand(Inst.getOperand(5));
7064    TmpInst.addOperand(Inst.getOperand(0));
7065    TmpInst.addOperand(Inst.getOperand(2));
7066    TmpInst.addOperand(Inst.getOperand(3));
7067    TmpInst.addOperand(Inst.getOperand(4));
7068    Inst = TmpInst;
7069    return true;
7070  }
7071  case ARM::t2ADDrr: {
7072    // If the destination and first source operand are the same, and
7073    // there's no setting of the flags, use encoding T2 instead of T3.
7074    // Note that this is only for ADD, not SUB. This mirrors the system
7075    // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7076    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7077        Inst.getOperand(5).getReg() != 0 ||
7078        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7079         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7080      break;
7081    MCInst TmpInst;
7082    TmpInst.setOpcode(ARM::tADDhirr);
7083    TmpInst.addOperand(Inst.getOperand(0));
7084    TmpInst.addOperand(Inst.getOperand(0));
7085    TmpInst.addOperand(Inst.getOperand(2));
7086    TmpInst.addOperand(Inst.getOperand(3));
7087    TmpInst.addOperand(Inst.getOperand(4));
7088    Inst = TmpInst;
7089    return true;
7090  }
7091  case ARM::tADDrSP: {
7092    // If the non-SP source operand and the destination operand are not the
7093    // same, we need to use the 32-bit encoding if it's available.
7094    if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7095      Inst.setOpcode(ARM::t2ADDrr);
7096      Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7097      return true;
7098    }
7099    break;
7100  }
7101  case ARM::tB:
7102    // A Thumb conditional branch outside of an IT block is a tBcc.
7103    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7104      Inst.setOpcode(ARM::tBcc);
7105      return true;
7106    }
7107    break;
7108  case ARM::t2B:
7109    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7110    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7111      Inst.setOpcode(ARM::t2Bcc);
7112      return true;
7113    }
7114    break;
7115  case ARM::t2Bcc:
7116    // If the conditional is AL or we're in an IT block, we really want t2B.
7117    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7118      Inst.setOpcode(ARM::t2B);
7119      return true;
7120    }
7121    break;
7122  case ARM::tBcc:
7123    // If the conditional is AL, we really want tB.
7124    if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7125      Inst.setOpcode(ARM::tB);
7126      return true;
7127    }
7128    break;
7129  case ARM::tLDMIA: {
7130    // If the register list contains any high registers, or if the writeback
7131    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7132    // instead if we're in Thumb2. Otherwise, this should have generated
7133    // an error in validateInstruction().
7134    unsigned Rn = Inst.getOperand(0).getReg();
7135    bool hasWritebackToken =
7136      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7137       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7138    bool listContainsBase;
7139    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7140        (!listContainsBase && !hasWritebackToken) ||
7141        (listContainsBase && hasWritebackToken)) {
7142      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7143      assert (isThumbTwo());
7144      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7145      // If we're switching to the updating version, we need to insert
7146      // the writeback tied operand.
7147      if (hasWritebackToken)
7148        Inst.insert(Inst.begin(),
7149                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7150      return true;
7151    }
7152    break;
7153  }
7154  case ARM::tSTMIA_UPD: {
7155    // If the register list contains any high registers, we need to use
7156    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7157    // should have generated an error in validateInstruction().
7158    unsigned Rn = Inst.getOperand(0).getReg();
7159    bool listContainsBase;
7160    if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7161      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7162      assert (isThumbTwo());
7163      Inst.setOpcode(ARM::t2STMIA_UPD);
7164      return true;
7165    }
7166    break;
7167  }
7168  case ARM::tPOP: {
7169    bool listContainsBase;
7170    // If the register list contains any high registers, we need to use
7171    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7172    // should have generated an error in validateInstruction().
7173    if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7174      return false;
7175    assert (isThumbTwo());
7176    Inst.setOpcode(ARM::t2LDMIA_UPD);
7177    // Add the base register and writeback operands.
7178    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7179    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7180    return true;
7181  }
7182  case ARM::tPUSH: {
7183    bool listContainsBase;
7184    if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7185      return false;
7186    assert (isThumbTwo());
7187    Inst.setOpcode(ARM::t2STMDB_UPD);
7188    // Add the base register and writeback operands.
7189    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7190    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7191    return true;
7192  }
7193  case ARM::t2MOVi: {
7194    // If we can use the 16-bit encoding and the user didn't explicitly
7195    // request the 32-bit variant, transform it here.
7196    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7197        (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7198        ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7199         Inst.getOperand(4).getReg() == ARM::CPSR) ||
7200        (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7201        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7202         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7203      // The operands aren't in the same order for tMOVi8...
7204      MCInst TmpInst;
7205      TmpInst.setOpcode(ARM::tMOVi8);
7206      TmpInst.addOperand(Inst.getOperand(0));
7207      TmpInst.addOperand(Inst.getOperand(4));
7208      TmpInst.addOperand(Inst.getOperand(1));
7209      TmpInst.addOperand(Inst.getOperand(2));
7210      TmpInst.addOperand(Inst.getOperand(3));
7211      Inst = TmpInst;
7212      return true;
7213    }
7214    break;
7215  }
7216  case ARM::t2MOVr: {
7217    // If we can use the 16-bit encoding and the user didn't explicitly
7218    // request the 32-bit variant, transform it here.
7219    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7220        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7221        Inst.getOperand(2).getImm() == ARMCC::AL &&
7222        Inst.getOperand(4).getReg() == ARM::CPSR &&
7223        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7224         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7225      // The operands aren't the same for tMOV[S]r... (no cc_out)
7226      MCInst TmpInst;
7227      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7228      TmpInst.addOperand(Inst.getOperand(0));
7229      TmpInst.addOperand(Inst.getOperand(1));
7230      TmpInst.addOperand(Inst.getOperand(2));
7231      TmpInst.addOperand(Inst.getOperand(3));
7232      Inst = TmpInst;
7233      return true;
7234    }
7235    break;
7236  }
7237  case ARM::t2SXTH:
7238  case ARM::t2SXTB:
7239  case ARM::t2UXTH:
7240  case ARM::t2UXTB: {
7241    // If we can use the 16-bit encoding and the user didn't explicitly
7242    // request the 32-bit variant, transform it here.
7243    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7244        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7245        Inst.getOperand(2).getImm() == 0 &&
7246        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7247         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7248      unsigned NewOpc;
7249      switch (Inst.getOpcode()) {
7250      default: llvm_unreachable("Illegal opcode!");
7251      case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7252      case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7253      case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7254      case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7255      }
7256      // The operands aren't the same for thumb1 (no rotate operand).
7257      MCInst TmpInst;
7258      TmpInst.setOpcode(NewOpc);
7259      TmpInst.addOperand(Inst.getOperand(0));
7260      TmpInst.addOperand(Inst.getOperand(1));
7261      TmpInst.addOperand(Inst.getOperand(3));
7262      TmpInst.addOperand(Inst.getOperand(4));
7263      Inst = TmpInst;
7264      return true;
7265    }
7266    break;
7267  }
7268  case ARM::MOVsi: {
7269    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7270    // rrx shifts and asr/lsr of #32 is encoded as 0
7271    if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7272      return false;
7273    if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7274      // Shifting by zero is accepted as a vanilla 'MOVr'
7275      MCInst TmpInst;
7276      TmpInst.setOpcode(ARM::MOVr);
7277      TmpInst.addOperand(Inst.getOperand(0));
7278      TmpInst.addOperand(Inst.getOperand(1));
7279      TmpInst.addOperand(Inst.getOperand(3));
7280      TmpInst.addOperand(Inst.getOperand(4));
7281      TmpInst.addOperand(Inst.getOperand(5));
7282      Inst = TmpInst;
7283      return true;
7284    }
7285    return false;
7286  }
7287  case ARM::ANDrsi:
7288  case ARM::ORRrsi:
7289  case ARM::EORrsi:
7290  case ARM::BICrsi:
7291  case ARM::SUBrsi:
7292  case ARM::ADDrsi: {
7293    unsigned newOpc;
7294    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7295    if (SOpc == ARM_AM::rrx) return false;
7296    switch (Inst.getOpcode()) {
7297    default: llvm_unreachable("unexpected opcode!");
7298    case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7299    case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7300    case ARM::EORrsi: newOpc = ARM::EORrr; break;
7301    case ARM::BICrsi: newOpc = ARM::BICrr; break;
7302    case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7303    case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7304    }
7305    // If the shift is by zero, use the non-shifted instruction definition.
7306    // The exception is for right shifts, where 0 == 32
7307    if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7308        !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7309      MCInst TmpInst;
7310      TmpInst.setOpcode(newOpc);
7311      TmpInst.addOperand(Inst.getOperand(0));
7312      TmpInst.addOperand(Inst.getOperand(1));
7313      TmpInst.addOperand(Inst.getOperand(2));
7314      TmpInst.addOperand(Inst.getOperand(4));
7315      TmpInst.addOperand(Inst.getOperand(5));
7316      TmpInst.addOperand(Inst.getOperand(6));
7317      Inst = TmpInst;
7318      return true;
7319    }
7320    return false;
7321  }
7322  case ARM::ITasm:
7323  case ARM::t2IT: {
7324    // The mask bits for all but the first condition are represented as
7325    // the low bit of the condition code value implies 't'. We currently
7326    // always have 1 implies 't', so XOR toggle the bits if the low bit
7327    // of the condition code is zero.
7328    MCOperand &MO = Inst.getOperand(1);
7329    unsigned Mask = MO.getImm();
7330    unsigned OrigMask = Mask;
7331    unsigned TZ = CountTrailingZeros_32(Mask);
7332    if ((Inst.getOperand(0).getImm() & 1) == 0) {
7333      assert(Mask && TZ <= 3 && "illegal IT mask value!");
7334      for (unsigned i = 3; i != TZ; --i)
7335        Mask ^= 1 << i;
7336    }
7337    MO.setImm(Mask);
7338
7339    // Set up the IT block state according to the IT instruction we just
7340    // matched.
7341    assert(!inITBlock() && "nested IT blocks?!");
7342    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7343    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7344    ITState.CurPosition = 0;
7345    ITState.FirstCond = true;
7346    break;
7347  }
7348  case ARM::t2LSLrr:
7349  case ARM::t2LSRrr:
7350  case ARM::t2ASRrr:
7351  case ARM::t2SBCrr:
7352  case ARM::t2RORrr:
7353  case ARM::t2BICrr:
7354  {
7355    // Assemblers should use the narrow encodings of these instructions when permissible.
7356    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7357         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7358        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7359        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7360         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7361        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7362         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7363      unsigned NewOpc;
7364      switch (Inst.getOpcode()) {
7365        default: llvm_unreachable("unexpected opcode");
7366        case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7367        case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7368        case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7369        case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7370        case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7371        case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7372      }
7373      MCInst TmpInst;
7374      TmpInst.setOpcode(NewOpc);
7375      TmpInst.addOperand(Inst.getOperand(0));
7376      TmpInst.addOperand(Inst.getOperand(5));
7377      TmpInst.addOperand(Inst.getOperand(1));
7378      TmpInst.addOperand(Inst.getOperand(2));
7379      TmpInst.addOperand(Inst.getOperand(3));
7380      TmpInst.addOperand(Inst.getOperand(4));
7381      Inst = TmpInst;
7382      return true;
7383    }
7384    return false;
7385  }
7386  case ARM::t2ANDrr:
7387  case ARM::t2EORrr:
7388  case ARM::t2ADCrr:
7389  case ARM::t2ORRrr:
7390  {
7391    // Assemblers should use the narrow encodings of these instructions when permissible.
7392    // These instructions are special in that they are commutable, so shorter encodings
7393    // are available more often.
7394    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7395         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7396        (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7397         Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7398        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7399         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7400        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7401         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7402      unsigned NewOpc;
7403      switch (Inst.getOpcode()) {
7404        default: llvm_unreachable("unexpected opcode");
7405        case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7406        case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7407        case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7408        case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7409      }
7410      MCInst TmpInst;
7411      TmpInst.setOpcode(NewOpc);
7412      TmpInst.addOperand(Inst.getOperand(0));
7413      TmpInst.addOperand(Inst.getOperand(5));
7414      if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7415        TmpInst.addOperand(Inst.getOperand(1));
7416        TmpInst.addOperand(Inst.getOperand(2));
7417      } else {
7418        TmpInst.addOperand(Inst.getOperand(2));
7419        TmpInst.addOperand(Inst.getOperand(1));
7420      }
7421      TmpInst.addOperand(Inst.getOperand(3));
7422      TmpInst.addOperand(Inst.getOperand(4));
7423      Inst = TmpInst;
7424      return true;
7425    }
7426    return false;
7427  }
7428  }
7429  return false;
7430}
7431
7432unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7433  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7434  // suffix depending on whether they're in an IT block or not.
7435  unsigned Opc = Inst.getOpcode();
7436  const MCInstrDesc &MCID = getInstDesc(Opc);
7437  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7438    assert(MCID.hasOptionalDef() &&
7439           "optionally flag setting instruction missing optional def operand");
7440    assert(MCID.NumOperands == Inst.getNumOperands() &&
7441           "operand count mismatch!");
7442    // Find the optional-def operand (cc_out).
7443    unsigned OpNo;
7444    for (OpNo = 0;
7445         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7446         ++OpNo)
7447      ;
7448    // If we're parsing Thumb1, reject it completely.
7449    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7450      return Match_MnemonicFail;
7451    // If we're parsing Thumb2, which form is legal depends on whether we're
7452    // in an IT block.
7453    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7454        !inITBlock())
7455      return Match_RequiresITBlock;
7456    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7457        inITBlock())
7458      return Match_RequiresNotITBlock;
7459  }
7460  // Some high-register supporting Thumb1 encodings only allow both registers
7461  // to be from r0-r7 when in Thumb2.
7462  else if (Opc == ARM::tADDhirr && isThumbOne() &&
7463           isARMLowRegister(Inst.getOperand(1).getReg()) &&
7464           isARMLowRegister(Inst.getOperand(2).getReg()))
7465    return Match_RequiresThumb2;
7466  // Others only require ARMv6 or later.
7467  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7468           isARMLowRegister(Inst.getOperand(0).getReg()) &&
7469           isARMLowRegister(Inst.getOperand(1).getReg()))
7470    return Match_RequiresV6;
7471  return Match_Success;
7472}
7473
7474static const char *getSubtargetFeatureName(unsigned Val);
7475bool ARMAsmParser::
7476MatchAndEmitInstruction(SMLoc IDLoc,
7477                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7478                        MCStreamer &Out) {
7479  MCInst Inst;
7480  unsigned Kind;
7481  unsigned ErrorInfo;
7482  unsigned MatchResult;
7483  SmallVector<std::pair< unsigned, std::string >, 4> MapAndConstraints;
7484  MatchResult = MatchInstructionImpl(Operands, Kind, Inst,
7485                                     MapAndConstraints, ErrorInfo,
7486                                     /*matchingInlineAsm*/ false);
7487  switch (MatchResult) {
7488  default: break;
7489  case Match_Success:
7490    // Context sensitive operand constraints aren't handled by the matcher,
7491    // so check them here.
7492    if (validateInstruction(Inst, Operands)) {
7493      // Still progress the IT block, otherwise one wrong condition causes
7494      // nasty cascading errors.
7495      forwardITPosition();
7496      return true;
7497    }
7498
7499    // Some instructions need post-processing to, for example, tweak which
7500    // encoding is selected. Loop on it while changes happen so the
7501    // individual transformations can chain off each other. E.g.,
7502    // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7503    while (processInstruction(Inst, Operands))
7504      ;
7505
7506    // Only move forward at the very end so that everything in validate
7507    // and process gets a consistent answer about whether we're in an IT
7508    // block.
7509    forwardITPosition();
7510
7511    // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7512    // doesn't actually encode.
7513    if (Inst.getOpcode() == ARM::ITasm)
7514      return false;
7515
7516    Inst.setLoc(IDLoc);
7517    Out.EmitInstruction(Inst);
7518    return false;
7519  case Match_MissingFeature: {
7520    assert(ErrorInfo && "Unknown missing feature!");
7521    // Special case the error message for the very common case where only
7522    // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7523    std::string Msg = "instruction requires:";
7524    unsigned Mask = 1;
7525    for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7526      if (ErrorInfo & Mask) {
7527        Msg += " ";
7528        Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7529      }
7530      Mask <<= 1;
7531    }
7532    return Error(IDLoc, Msg);
7533  }
7534  case Match_InvalidOperand: {
7535    SMLoc ErrorLoc = IDLoc;
7536    if (ErrorInfo != ~0U) {
7537      if (ErrorInfo >= Operands.size())
7538        return Error(IDLoc, "too few operands for instruction");
7539
7540      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7541      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7542    }
7543
7544    return Error(ErrorLoc, "invalid operand for instruction");
7545  }
7546  case Match_MnemonicFail:
7547    return Error(IDLoc, "invalid instruction",
7548                 ((ARMOperand*)Operands[0])->getLocRange());
7549  case Match_RequiresNotITBlock:
7550    return Error(IDLoc, "flag setting instruction only valid outside IT block");
7551  case Match_RequiresITBlock:
7552    return Error(IDLoc, "instruction only valid inside IT block");
7553  case Match_RequiresV6:
7554    return Error(IDLoc, "instruction variant requires ARMv6 or later");
7555  case Match_RequiresThumb2:
7556    return Error(IDLoc, "instruction variant requires Thumb2");
7557  case Match_ImmRange0_15: {
7558    SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7559    if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7560    return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7561  }
7562  }
7563
7564  llvm_unreachable("Implement any new match types added!");
7565}
7566
7567/// parseDirective parses the arm specific directives
7568bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7569  StringRef IDVal = DirectiveID.getIdentifier();
7570  if (IDVal == ".word")
7571    return parseDirectiveWord(4, DirectiveID.getLoc());
7572  else if (IDVal == ".thumb")
7573    return parseDirectiveThumb(DirectiveID.getLoc());
7574  else if (IDVal == ".arm")
7575    return parseDirectiveARM(DirectiveID.getLoc());
7576  else if (IDVal == ".thumb_func")
7577    return parseDirectiveThumbFunc(DirectiveID.getLoc());
7578  else if (IDVal == ".code")
7579    return parseDirectiveCode(DirectiveID.getLoc());
7580  else if (IDVal == ".syntax")
7581    return parseDirectiveSyntax(DirectiveID.getLoc());
7582  else if (IDVal == ".unreq")
7583    return parseDirectiveUnreq(DirectiveID.getLoc());
7584  else if (IDVal == ".arch")
7585    return parseDirectiveArch(DirectiveID.getLoc());
7586  else if (IDVal == ".eabi_attribute")
7587    return parseDirectiveEabiAttr(DirectiveID.getLoc());
7588  return true;
7589}
7590
7591/// parseDirectiveWord
7592///  ::= .word [ expression (, expression)* ]
7593bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7594  if (getLexer().isNot(AsmToken::EndOfStatement)) {
7595    for (;;) {
7596      const MCExpr *Value;
7597      if (getParser().ParseExpression(Value))
7598        return true;
7599
7600      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
7601
7602      if (getLexer().is(AsmToken::EndOfStatement))
7603        break;
7604
7605      // FIXME: Improve diagnostic.
7606      if (getLexer().isNot(AsmToken::Comma))
7607        return Error(L, "unexpected token in directive");
7608      Parser.Lex();
7609    }
7610  }
7611
7612  Parser.Lex();
7613  return false;
7614}
7615
7616/// parseDirectiveThumb
7617///  ::= .thumb
7618bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7619  if (getLexer().isNot(AsmToken::EndOfStatement))
7620    return Error(L, "unexpected token in directive");
7621  Parser.Lex();
7622
7623  if (!isThumb())
7624    SwitchMode();
7625  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7626  return false;
7627}
7628
7629/// parseDirectiveARM
7630///  ::= .arm
7631bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7632  if (getLexer().isNot(AsmToken::EndOfStatement))
7633    return Error(L, "unexpected token in directive");
7634  Parser.Lex();
7635
7636  if (isThumb())
7637    SwitchMode();
7638  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7639  return false;
7640}
7641
7642/// parseDirectiveThumbFunc
7643///  ::= .thumbfunc symbol_name
7644bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7645  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
7646  bool isMachO = MAI.hasSubsectionsViaSymbols();
7647  StringRef Name;
7648  bool needFuncName = true;
7649
7650  // Darwin asm has (optionally) function name after .thumb_func direction
7651  // ELF doesn't
7652  if (isMachO) {
7653    const AsmToken &Tok = Parser.getTok();
7654    if (Tok.isNot(AsmToken::EndOfStatement)) {
7655      if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7656        return Error(L, "unexpected token in .thumb_func directive");
7657      Name = Tok.getIdentifier();
7658      Parser.Lex(); // Consume the identifier token.
7659      needFuncName = false;
7660    }
7661  }
7662
7663  if (getLexer().isNot(AsmToken::EndOfStatement))
7664    return Error(L, "unexpected token in directive");
7665
7666  // Eat the end of statement and any blank lines that follow.
7667  while (getLexer().is(AsmToken::EndOfStatement))
7668    Parser.Lex();
7669
7670  // FIXME: assuming function name will be the line following .thumb_func
7671  // We really should be checking the next symbol definition even if there's
7672  // stuff in between.
7673  if (needFuncName) {
7674    Name = Parser.getTok().getIdentifier();
7675  }
7676
7677  // Mark symbol as a thumb symbol.
7678  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7679  getParser().getStreamer().EmitThumbFunc(Func);
7680  return false;
7681}
7682
7683/// parseDirectiveSyntax
7684///  ::= .syntax unified | divided
7685bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7686  const AsmToken &Tok = Parser.getTok();
7687  if (Tok.isNot(AsmToken::Identifier))
7688    return Error(L, "unexpected token in .syntax directive");
7689  StringRef Mode = Tok.getString();
7690  if (Mode == "unified" || Mode == "UNIFIED")
7691    Parser.Lex();
7692  else if (Mode == "divided" || Mode == "DIVIDED")
7693    return Error(L, "'.syntax divided' arm asssembly not supported");
7694  else
7695    return Error(L, "unrecognized syntax mode in .syntax directive");
7696
7697  if (getLexer().isNot(AsmToken::EndOfStatement))
7698    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7699  Parser.Lex();
7700
7701  // TODO tell the MC streamer the mode
7702  // getParser().getStreamer().Emit???();
7703  return false;
7704}
7705
7706/// parseDirectiveCode
7707///  ::= .code 16 | 32
7708bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7709  const AsmToken &Tok = Parser.getTok();
7710  if (Tok.isNot(AsmToken::Integer))
7711    return Error(L, "unexpected token in .code directive");
7712  int64_t Val = Parser.getTok().getIntVal();
7713  if (Val == 16)
7714    Parser.Lex();
7715  else if (Val == 32)
7716    Parser.Lex();
7717  else
7718    return Error(L, "invalid operand to .code directive");
7719
7720  if (getLexer().isNot(AsmToken::EndOfStatement))
7721    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7722  Parser.Lex();
7723
7724  if (Val == 16) {
7725    if (!isThumb())
7726      SwitchMode();
7727    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7728  } else {
7729    if (isThumb())
7730      SwitchMode();
7731    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7732  }
7733
7734  return false;
7735}
7736
7737/// parseDirectiveReq
7738///  ::= name .req registername
7739bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7740  Parser.Lex(); // Eat the '.req' token.
7741  unsigned Reg;
7742  SMLoc SRegLoc, ERegLoc;
7743  if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7744    Parser.EatToEndOfStatement();
7745    return Error(SRegLoc, "register name expected");
7746  }
7747
7748  // Shouldn't be anything else.
7749  if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7750    Parser.EatToEndOfStatement();
7751    return Error(Parser.getTok().getLoc(),
7752                 "unexpected input in .req directive.");
7753  }
7754
7755  Parser.Lex(); // Consume the EndOfStatement
7756
7757  if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7758    return Error(SRegLoc, "redefinition of '" + Name +
7759                          "' does not match original.");
7760
7761  return false;
7762}
7763
7764/// parseDirectiveUneq
7765///  ::= .unreq registername
7766bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7767  if (Parser.getTok().isNot(AsmToken::Identifier)) {
7768    Parser.EatToEndOfStatement();
7769    return Error(L, "unexpected input in .unreq directive.");
7770  }
7771  RegisterReqs.erase(Parser.getTok().getIdentifier());
7772  Parser.Lex(); // Eat the identifier.
7773  return false;
7774}
7775
7776/// parseDirectiveArch
7777///  ::= .arch token
7778bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7779  return true;
7780}
7781
7782/// parseDirectiveEabiAttr
7783///  ::= .eabi_attribute int, int
7784bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7785  return true;
7786}
7787
7788extern "C" void LLVMInitializeARMAsmLexer();
7789
7790/// Force static initialization.
7791extern "C" void LLVMInitializeARMAsmParser() {
7792  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
7793  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
7794  LLVMInitializeARMAsmLexer();
7795}
7796
7797#define GET_REGISTER_MATCHER
7798#define GET_SUBTARGET_FEATURE_NAME
7799#define GET_MATCHER_IMPLEMENTATION
7800#include "ARMGenAsmMatcher.inc"
7801