ARMAsmParser.cpp revision 25e0a87e9190cdca62aee5ac95cfc8ef44f35e92 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/MCTargetAsmParser.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/SourceMgr.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/ADT/BitVector.h"
30#include "llvm/ADT/OwningPtr.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/StringSwitch.h"
34#include "llvm/ADT/Twine.h"
35
36using namespace llvm;
37
38namespace {
39
40class ARMOperand;
41
42class ARMAsmParser : public MCTargetAsmParser {
43  MCSubtargetInfo &STI;
44  MCAsmParser &Parser;
45
46  struct {
47    ARMCC::CondCodes Cond;    // Condition for IT block.
48    unsigned Mask:4;          // Condition mask for instructions.
49                              // Starting at first 1 (from lsb).
50                              //   '1'  condition as indicated in IT.
51                              //   '0'  inverse of condition (else).
52                              // Count of instructions in IT block is
53                              // 4 - trailingzeroes(mask)
54
55    bool FirstCond;           // Explicit flag for when we're parsing the
56                              // First instruction in the IT block. It's
57                              // implied in the mask, so needs special
58                              // handling.
59
60    unsigned CurPosition;     // Current position in parsing of IT
61                              // block. In range [0,3]. Initialized
62                              // according to count of instructions in block.
63                              // ~0U if no active IT block.
64  } ITState;
65  bool inITBlock() { return ITState.CurPosition != ~0U;}
66  void forwardITPosition() {
67    if (!inITBlock()) return;
68    // Move to the next instruction in the IT block, if there is one. If not,
69    // mark the block as done.
70    unsigned TZ = CountTrailingZeros_32(ITState.Mask);
71    if (++ITState.CurPosition == 5 - TZ)
72      ITState.CurPosition = ~0U; // Done with the IT block after this.
73  }
74
75
76  MCAsmParser &getParser() const { return Parser; }
77  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
78
79  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
80  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
81
82  int tryParseRegister();
83  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
84  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
85  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
86  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
87  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
88  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
89  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
90                              unsigned &ShiftAmount);
91  bool parseDirectiveWord(unsigned Size, SMLoc L);
92  bool parseDirectiveThumb(SMLoc L);
93  bool parseDirectiveThumbFunc(SMLoc L);
94  bool parseDirectiveCode(SMLoc L);
95  bool parseDirectiveSyntax(SMLoc L);
96
97  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
98                          bool &CarrySetting, unsigned &ProcessorIMod,
99                          StringRef &ITMask);
100  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
101                             bool &CanAcceptPredicationCode);
102
103  bool isThumb() const {
104    // FIXME: Can tablegen auto-generate this?
105    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
106  }
107  bool isThumbOne() const {
108    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
109  }
110  bool isThumbTwo() const {
111    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
112  }
113  bool hasV6Ops() const {
114    return STI.getFeatureBits() & ARM::HasV6Ops;
115  }
116  bool hasV7Ops() const {
117    return STI.getFeatureBits() & ARM::HasV7Ops;
118  }
119  void SwitchMode() {
120    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
121    setAvailableFeatures(FB);
122  }
123  bool isMClass() const {
124    return STI.getFeatureBits() & ARM::FeatureMClass;
125  }
126
127  /// @name Auto-generated Match Functions
128  /// {
129
130#define GET_ASSEMBLER_HEADER
131#include "ARMGenAsmMatcher.inc"
132
133  /// }
134
135  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
136  OperandMatchResultTy parseCoprocNumOperand(
137    SmallVectorImpl<MCParsedAsmOperand*>&);
138  OperandMatchResultTy parseCoprocRegOperand(
139    SmallVectorImpl<MCParsedAsmOperand*>&);
140  OperandMatchResultTy parseCoprocOptionOperand(
141    SmallVectorImpl<MCParsedAsmOperand*>&);
142  OperandMatchResultTy parseMemBarrierOptOperand(
143    SmallVectorImpl<MCParsedAsmOperand*>&);
144  OperandMatchResultTy parseProcIFlagsOperand(
145    SmallVectorImpl<MCParsedAsmOperand*>&);
146  OperandMatchResultTy parseMSRMaskOperand(
147    SmallVectorImpl<MCParsedAsmOperand*>&);
148  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
149                                   StringRef Op, int Low, int High);
150  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
151    return parsePKHImm(O, "lsl", 0, 31);
152  }
153  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
154    return parsePKHImm(O, "asr", 1, 32);
155  }
156  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
157  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
158  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
159  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
160  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
161  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
162  OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
163  OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
164
165  // Asm Match Converter Methods
166  bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
167                    const SmallVectorImpl<MCParsedAsmOperand*> &);
168  bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
169                    const SmallVectorImpl<MCParsedAsmOperand*> &);
170  bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
171                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
172  bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
173                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
174  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
175                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
176  bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
177                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
178  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
179                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
180  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
181                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
182  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
183                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
184  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
185                             const SmallVectorImpl<MCParsedAsmOperand*> &);
186  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
187                             const SmallVectorImpl<MCParsedAsmOperand*> &);
188  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
189                             const SmallVectorImpl<MCParsedAsmOperand*> &);
190  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
191                             const SmallVectorImpl<MCParsedAsmOperand*> &);
192  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
193                  const SmallVectorImpl<MCParsedAsmOperand*> &);
194  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
195                  const SmallVectorImpl<MCParsedAsmOperand*> &);
196  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
197                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
198  bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
199                        const SmallVectorImpl<MCParsedAsmOperand*> &);
200  bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
201                     const SmallVectorImpl<MCParsedAsmOperand*> &);
202  bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
203                        const SmallVectorImpl<MCParsedAsmOperand*> &);
204  bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
205                     const SmallVectorImpl<MCParsedAsmOperand*> &);
206  bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
207                        const SmallVectorImpl<MCParsedAsmOperand*> &);
208
209  bool validateInstruction(MCInst &Inst,
210                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
211  bool processInstruction(MCInst &Inst,
212                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
213  bool shouldOmitCCOutOperand(StringRef Mnemonic,
214                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
215
216public:
217  enum ARMMatchResultTy {
218    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
219    Match_RequiresNotITBlock,
220    Match_RequiresV6,
221    Match_RequiresThumb2
222  };
223
224  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
225    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
226    MCAsmParserExtension::Initialize(_Parser);
227
228    // Initialize the set of available features.
229    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
230
231    // Not in an ITBlock to start with.
232    ITState.CurPosition = ~0U;
233  }
234
235  // Implementation of the MCTargetAsmParser interface:
236  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
237  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
238                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
239  bool ParseDirective(AsmToken DirectiveID);
240
241  unsigned checkTargetMatchPredicate(MCInst &Inst);
242
243  bool MatchAndEmitInstruction(SMLoc IDLoc,
244                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
245                               MCStreamer &Out);
246};
247} // end anonymous namespace
248
249namespace {
250
251/// ARMOperand - Instances of this class represent a parsed ARM machine
252/// instruction.
253class ARMOperand : public MCParsedAsmOperand {
254  enum KindTy {
255    k_CondCode,
256    k_CCOut,
257    k_ITCondMask,
258    k_CoprocNum,
259    k_CoprocReg,
260    k_CoprocOption,
261    k_Immediate,
262    k_FPImmediate,
263    k_MemBarrierOpt,
264    k_Memory,
265    k_PostIndexRegister,
266    k_MSRMask,
267    k_ProcIFlags,
268    k_VectorIndex,
269    k_Register,
270    k_RegisterList,
271    k_DPRRegisterList,
272    k_SPRRegisterList,
273    k_VectorList,
274    k_ShiftedRegister,
275    k_ShiftedImmediate,
276    k_ShifterImmediate,
277    k_RotateImmediate,
278    k_BitfieldDescriptor,
279    k_Token
280  } Kind;
281
282  SMLoc StartLoc, EndLoc;
283  SmallVector<unsigned, 8> Registers;
284
285  union {
286    struct {
287      ARMCC::CondCodes Val;
288    } CC;
289
290    struct {
291      unsigned Val;
292    } Cop;
293
294    struct {
295      unsigned Val;
296    } CoprocOption;
297
298    struct {
299      unsigned Mask:4;
300    } ITMask;
301
302    struct {
303      ARM_MB::MemBOpt Val;
304    } MBOpt;
305
306    struct {
307      ARM_PROC::IFlags Val;
308    } IFlags;
309
310    struct {
311      unsigned Val;
312    } MMask;
313
314    struct {
315      const char *Data;
316      unsigned Length;
317    } Tok;
318
319    struct {
320      unsigned RegNum;
321    } Reg;
322
323    // A vector register list is a sequential list of 1 to 4 registers.
324    struct {
325      unsigned RegNum;
326      unsigned Count;
327    } VectorList;
328
329    struct {
330      unsigned Val;
331    } VectorIndex;
332
333    struct {
334      const MCExpr *Val;
335    } Imm;
336
337    struct {
338      unsigned Val;       // encoded 8-bit representation
339    } FPImm;
340
341    /// Combined record for all forms of ARM address expressions.
342    struct {
343      unsigned BaseRegNum;
344      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
345      // was specified.
346      const MCConstantExpr *OffsetImm;  // Offset immediate value
347      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
348      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
349      unsigned ShiftImm;        // shift for OffsetReg.
350      unsigned Alignment;       // 0 = no alignment specified
351                                // n = alignment in bytes (8, 16, or 32)
352      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
353    } Memory;
354
355    struct {
356      unsigned RegNum;
357      bool isAdd;
358      ARM_AM::ShiftOpc ShiftTy;
359      unsigned ShiftImm;
360    } PostIdxReg;
361
362    struct {
363      bool isASR;
364      unsigned Imm;
365    } ShifterImm;
366    struct {
367      ARM_AM::ShiftOpc ShiftTy;
368      unsigned SrcReg;
369      unsigned ShiftReg;
370      unsigned ShiftImm;
371    } RegShiftedReg;
372    struct {
373      ARM_AM::ShiftOpc ShiftTy;
374      unsigned SrcReg;
375      unsigned ShiftImm;
376    } RegShiftedImm;
377    struct {
378      unsigned Imm;
379    } RotImm;
380    struct {
381      unsigned LSB;
382      unsigned Width;
383    } Bitfield;
384  };
385
386  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
387public:
388  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
389    Kind = o.Kind;
390    StartLoc = o.StartLoc;
391    EndLoc = o.EndLoc;
392    switch (Kind) {
393    case k_CondCode:
394      CC = o.CC;
395      break;
396    case k_ITCondMask:
397      ITMask = o.ITMask;
398      break;
399    case k_Token:
400      Tok = o.Tok;
401      break;
402    case k_CCOut:
403    case k_Register:
404      Reg = o.Reg;
405      break;
406    case k_RegisterList:
407    case k_DPRRegisterList:
408    case k_SPRRegisterList:
409      Registers = o.Registers;
410      break;
411    case k_VectorList:
412      VectorList = o.VectorList;
413      break;
414    case k_CoprocNum:
415    case k_CoprocReg:
416      Cop = o.Cop;
417      break;
418    case k_CoprocOption:
419      CoprocOption = o.CoprocOption;
420      break;
421    case k_Immediate:
422      Imm = o.Imm;
423      break;
424    case k_FPImmediate:
425      FPImm = o.FPImm;
426      break;
427    case k_MemBarrierOpt:
428      MBOpt = o.MBOpt;
429      break;
430    case k_Memory:
431      Memory = o.Memory;
432      break;
433    case k_PostIndexRegister:
434      PostIdxReg = o.PostIdxReg;
435      break;
436    case k_MSRMask:
437      MMask = o.MMask;
438      break;
439    case k_ProcIFlags:
440      IFlags = o.IFlags;
441      break;
442    case k_ShifterImmediate:
443      ShifterImm = o.ShifterImm;
444      break;
445    case k_ShiftedRegister:
446      RegShiftedReg = o.RegShiftedReg;
447      break;
448    case k_ShiftedImmediate:
449      RegShiftedImm = o.RegShiftedImm;
450      break;
451    case k_RotateImmediate:
452      RotImm = o.RotImm;
453      break;
454    case k_BitfieldDescriptor:
455      Bitfield = o.Bitfield;
456      break;
457    case k_VectorIndex:
458      VectorIndex = o.VectorIndex;
459      break;
460    }
461  }
462
463  /// getStartLoc - Get the location of the first token of this operand.
464  SMLoc getStartLoc() const { return StartLoc; }
465  /// getEndLoc - Get the location of the last token of this operand.
466  SMLoc getEndLoc() const { return EndLoc; }
467
468  ARMCC::CondCodes getCondCode() const {
469    assert(Kind == k_CondCode && "Invalid access!");
470    return CC.Val;
471  }
472
473  unsigned getCoproc() const {
474    assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
475    return Cop.Val;
476  }
477
478  StringRef getToken() const {
479    assert(Kind == k_Token && "Invalid access!");
480    return StringRef(Tok.Data, Tok.Length);
481  }
482
483  unsigned getReg() const {
484    assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
485    return Reg.RegNum;
486  }
487
488  const SmallVectorImpl<unsigned> &getRegList() const {
489    assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
490            Kind == k_SPRRegisterList) && "Invalid access!");
491    return Registers;
492  }
493
494  const MCExpr *getImm() const {
495    assert(Kind == k_Immediate && "Invalid access!");
496    return Imm.Val;
497  }
498
499  unsigned getFPImm() const {
500    assert(Kind == k_FPImmediate && "Invalid access!");
501    return FPImm.Val;
502  }
503
504  unsigned getVectorIndex() const {
505    assert(Kind == k_VectorIndex && "Invalid access!");
506    return VectorIndex.Val;
507  }
508
509  ARM_MB::MemBOpt getMemBarrierOpt() const {
510    assert(Kind == k_MemBarrierOpt && "Invalid access!");
511    return MBOpt.Val;
512  }
513
514  ARM_PROC::IFlags getProcIFlags() const {
515    assert(Kind == k_ProcIFlags && "Invalid access!");
516    return IFlags.Val;
517  }
518
519  unsigned getMSRMask() const {
520    assert(Kind == k_MSRMask && "Invalid access!");
521    return MMask.Val;
522  }
523
524  bool isCoprocNum() const { return Kind == k_CoprocNum; }
525  bool isCoprocReg() const { return Kind == k_CoprocReg; }
526  bool isCoprocOption() const { return Kind == k_CoprocOption; }
527  bool isCondCode() const { return Kind == k_CondCode; }
528  bool isCCOut() const { return Kind == k_CCOut; }
529  bool isITMask() const { return Kind == k_ITCondMask; }
530  bool isITCondCode() const { return Kind == k_CondCode; }
531  bool isImm() const { return Kind == k_Immediate; }
532  bool isFPImm() const { return Kind == k_FPImmediate; }
533  bool isImm8s4() const {
534    if (Kind != k_Immediate)
535      return false;
536    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
537    if (!CE) return false;
538    int64_t Value = CE->getValue();
539    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
540  }
541  bool isImm0_1020s4() const {
542    if (Kind != k_Immediate)
543      return false;
544    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
545    if (!CE) return false;
546    int64_t Value = CE->getValue();
547    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
548  }
549  bool isImm0_508s4() const {
550    if (Kind != k_Immediate)
551      return false;
552    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
553    if (!CE) return false;
554    int64_t Value = CE->getValue();
555    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
556  }
557  bool isImm0_255() const {
558    if (Kind != k_Immediate)
559      return false;
560    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
561    if (!CE) return false;
562    int64_t Value = CE->getValue();
563    return Value >= 0 && Value < 256;
564  }
565  bool isImm0_7() const {
566    if (Kind != k_Immediate)
567      return false;
568    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
569    if (!CE) return false;
570    int64_t Value = CE->getValue();
571    return Value >= 0 && Value < 8;
572  }
573  bool isImm0_15() const {
574    if (Kind != k_Immediate)
575      return false;
576    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
577    if (!CE) return false;
578    int64_t Value = CE->getValue();
579    return Value >= 0 && Value < 16;
580  }
581  bool isImm0_31() const {
582    if (Kind != k_Immediate)
583      return false;
584    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
585    if (!CE) return false;
586    int64_t Value = CE->getValue();
587    return Value >= 0 && Value < 32;
588  }
589  bool isImm1_16() const {
590    if (Kind != k_Immediate)
591      return false;
592    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
593    if (!CE) return false;
594    int64_t Value = CE->getValue();
595    return Value > 0 && Value < 17;
596  }
597  bool isImm1_32() const {
598    if (Kind != k_Immediate)
599      return false;
600    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
601    if (!CE) return false;
602    int64_t Value = CE->getValue();
603    return Value > 0 && Value < 33;
604  }
605  bool isImm0_32() const {
606    if (Kind != k_Immediate)
607      return false;
608    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
609    if (!CE) return false;
610    int64_t Value = CE->getValue();
611    return Value >= 0 && Value < 33;
612  }
613  bool isImm0_65535() const {
614    if (Kind != k_Immediate)
615      return false;
616    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
617    if (!CE) return false;
618    int64_t Value = CE->getValue();
619    return Value >= 0 && Value < 65536;
620  }
621  bool isImm0_65535Expr() const {
622    if (Kind != k_Immediate)
623      return false;
624    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
625    // If it's not a constant expression, it'll generate a fixup and be
626    // handled later.
627    if (!CE) return true;
628    int64_t Value = CE->getValue();
629    return Value >= 0 && Value < 65536;
630  }
631  bool isImm24bit() const {
632    if (Kind != k_Immediate)
633      return false;
634    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
635    if (!CE) return false;
636    int64_t Value = CE->getValue();
637    return Value >= 0 && Value <= 0xffffff;
638  }
639  bool isImmThumbSR() const {
640    if (Kind != k_Immediate)
641      return false;
642    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
643    if (!CE) return false;
644    int64_t Value = CE->getValue();
645    return Value > 0 && Value < 33;
646  }
647  bool isPKHLSLImm() const {
648    if (Kind != k_Immediate)
649      return false;
650    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
651    if (!CE) return false;
652    int64_t Value = CE->getValue();
653    return Value >= 0 && Value < 32;
654  }
655  bool isPKHASRImm() const {
656    if (Kind != k_Immediate)
657      return false;
658    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
659    if (!CE) return false;
660    int64_t Value = CE->getValue();
661    return Value > 0 && Value <= 32;
662  }
663  bool isARMSOImm() const {
664    if (Kind != k_Immediate)
665      return false;
666    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
667    if (!CE) return false;
668    int64_t Value = CE->getValue();
669    return ARM_AM::getSOImmVal(Value) != -1;
670  }
671  bool isARMSOImmNot() const {
672    if (Kind != k_Immediate)
673      return false;
674    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
675    if (!CE) return false;
676    int64_t Value = CE->getValue();
677    return ARM_AM::getSOImmVal(~Value) != -1;
678  }
679  bool isT2SOImm() const {
680    if (Kind != k_Immediate)
681      return false;
682    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
683    if (!CE) return false;
684    int64_t Value = CE->getValue();
685    return ARM_AM::getT2SOImmVal(Value) != -1;
686  }
687  bool isT2SOImmNot() const {
688    if (Kind != k_Immediate)
689      return false;
690    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
691    if (!CE) return false;
692    int64_t Value = CE->getValue();
693    return ARM_AM::getT2SOImmVal(~Value) != -1;
694  }
695  bool isSetEndImm() const {
696    if (Kind != k_Immediate)
697      return false;
698    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
699    if (!CE) return false;
700    int64_t Value = CE->getValue();
701    return Value == 1 || Value == 0;
702  }
703  bool isReg() const { return Kind == k_Register; }
704  bool isRegList() const { return Kind == k_RegisterList; }
705  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
706  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
707  bool isToken() const { return Kind == k_Token; }
708  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
709  bool isMemory() const { return Kind == k_Memory; }
710  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
711  bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
712  bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
713  bool isRotImm() const { return Kind == k_RotateImmediate; }
714  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
715  bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
716  bool isPostIdxReg() const {
717    return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
718  }
719  bool isMemNoOffset(bool alignOK = false) const {
720    if (!isMemory())
721      return false;
722    // No offset of any kind.
723    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
724     (alignOK || Memory.Alignment == 0);
725  }
726  bool isAlignedMemory() const {
727    return isMemNoOffset(true);
728  }
729  bool isAddrMode2() const {
730    if (!isMemory() || Memory.Alignment != 0) return false;
731    // Check for register offset.
732    if (Memory.OffsetRegNum) return true;
733    // Immediate offset in range [-4095, 4095].
734    if (!Memory.OffsetImm) return true;
735    int64_t Val = Memory.OffsetImm->getValue();
736    return Val > -4096 && Val < 4096;
737  }
738  bool isAM2OffsetImm() const {
739    if (Kind != k_Immediate)
740      return false;
741    // Immediate offset in range [-4095, 4095].
742    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
743    if (!CE) return false;
744    int64_t Val = CE->getValue();
745    return Val > -4096 && Val < 4096;
746  }
747  bool isAddrMode3() const {
748    if (!isMemory() || Memory.Alignment != 0) return false;
749    // No shifts are legal for AM3.
750    if (Memory.ShiftType != ARM_AM::no_shift) return false;
751    // Check for register offset.
752    if (Memory.OffsetRegNum) return true;
753    // Immediate offset in range [-255, 255].
754    if (!Memory.OffsetImm) return true;
755    int64_t Val = Memory.OffsetImm->getValue();
756    return Val > -256 && Val < 256;
757  }
758  bool isAM3Offset() const {
759    if (Kind != k_Immediate && Kind != k_PostIndexRegister)
760      return false;
761    if (Kind == k_PostIndexRegister)
762      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
763    // Immediate offset in range [-255, 255].
764    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
765    if (!CE) return false;
766    int64_t Val = CE->getValue();
767    // Special case, #-0 is INT32_MIN.
768    return (Val > -256 && Val < 256) || Val == INT32_MIN;
769  }
770  bool isAddrMode5() const {
771    // If we have an immediate that's not a constant, treat it as a label
772    // reference needing a fixup. If it is a constant, it's something else
773    // and we reject it.
774    if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
775      return true;
776    if (!isMemory() || Memory.Alignment != 0) return false;
777    // Check for register offset.
778    if (Memory.OffsetRegNum) return false;
779    // Immediate offset in range [-1020, 1020] and a multiple of 4.
780    if (!Memory.OffsetImm) return true;
781    int64_t Val = Memory.OffsetImm->getValue();
782    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
783      Val == INT32_MIN;
784  }
785  bool isMemTBB() const {
786    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
787        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
788      return false;
789    return true;
790  }
791  bool isMemTBH() const {
792    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
793        Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
794        Memory.Alignment != 0 )
795      return false;
796    return true;
797  }
798  bool isMemRegOffset() const {
799    if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
800      return false;
801    return true;
802  }
803  bool isT2MemRegOffset() const {
804    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
805        Memory.Alignment != 0)
806      return false;
807    // Only lsl #{0, 1, 2, 3} allowed.
808    if (Memory.ShiftType == ARM_AM::no_shift)
809      return true;
810    if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
811      return false;
812    return true;
813  }
814  bool isMemThumbRR() const {
815    // Thumb reg+reg addressing is simple. Just two registers, a base and
816    // an offset. No shifts, negations or any other complicating factors.
817    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
818        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
819      return false;
820    return isARMLowRegister(Memory.BaseRegNum) &&
821      (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
822  }
823  bool isMemThumbRIs4() const {
824    if (!isMemory() || Memory.OffsetRegNum != 0 ||
825        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
826      return false;
827    // Immediate offset, multiple of 4 in range [0, 124].
828    if (!Memory.OffsetImm) return true;
829    int64_t Val = Memory.OffsetImm->getValue();
830    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
831  }
832  bool isMemThumbRIs2() const {
833    if (!isMemory() || Memory.OffsetRegNum != 0 ||
834        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
835      return false;
836    // Immediate offset, multiple of 4 in range [0, 62].
837    if (!Memory.OffsetImm) return true;
838    int64_t Val = Memory.OffsetImm->getValue();
839    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
840  }
841  bool isMemThumbRIs1() const {
842    if (!isMemory() || Memory.OffsetRegNum != 0 ||
843        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
844      return false;
845    // Immediate offset in range [0, 31].
846    if (!Memory.OffsetImm) return true;
847    int64_t Val = Memory.OffsetImm->getValue();
848    return Val >= 0 && Val <= 31;
849  }
850  bool isMemThumbSPI() const {
851    if (!isMemory() || Memory.OffsetRegNum != 0 ||
852        Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
853      return false;
854    // Immediate offset, multiple of 4 in range [0, 1020].
855    if (!Memory.OffsetImm) return true;
856    int64_t Val = Memory.OffsetImm->getValue();
857    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
858  }
859  bool isMemImm8s4Offset() const {
860    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
861      return false;
862    // Immediate offset a multiple of 4 in range [-1020, 1020].
863    if (!Memory.OffsetImm) return true;
864    int64_t Val = Memory.OffsetImm->getValue();
865    return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
866  }
867  bool isMemImm0_1020s4Offset() const {
868    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
869      return false;
870    // Immediate offset a multiple of 4 in range [0, 1020].
871    if (!Memory.OffsetImm) return true;
872    int64_t Val = Memory.OffsetImm->getValue();
873    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
874  }
875  bool isMemImm8Offset() const {
876    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
877      return false;
878    // Immediate offset in range [-255, 255].
879    if (!Memory.OffsetImm) return true;
880    int64_t Val = Memory.OffsetImm->getValue();
881    return (Val == INT32_MIN) || (Val > -256 && Val < 256);
882  }
883  bool isMemPosImm8Offset() const {
884    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
885      return false;
886    // Immediate offset in range [0, 255].
887    if (!Memory.OffsetImm) return true;
888    int64_t Val = Memory.OffsetImm->getValue();
889    return Val >= 0 && Val < 256;
890  }
891  bool isMemNegImm8Offset() const {
892    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
893      return false;
894    // Immediate offset in range [-255, -1].
895    if (!Memory.OffsetImm) return true;
896    int64_t Val = Memory.OffsetImm->getValue();
897    return Val > -256 && Val < 0;
898  }
899  bool isMemUImm12Offset() const {
900    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
901      return false;
902    // Immediate offset in range [0, 4095].
903    if (!Memory.OffsetImm) return true;
904    int64_t Val = Memory.OffsetImm->getValue();
905    return (Val >= 0 && Val < 4096);
906  }
907  bool isMemImm12Offset() const {
908    // If we have an immediate that's not a constant, treat it as a label
909    // reference needing a fixup. If it is a constant, it's something else
910    // and we reject it.
911    if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
912      return true;
913
914    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
915      return false;
916    // Immediate offset in range [-4095, 4095].
917    if (!Memory.OffsetImm) return true;
918    int64_t Val = Memory.OffsetImm->getValue();
919    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
920  }
921  bool isPostIdxImm8() const {
922    if (Kind != k_Immediate)
923      return false;
924    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
925    if (!CE) return false;
926    int64_t Val = CE->getValue();
927    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
928  }
929  bool isPostIdxImm8s4() const {
930    if (Kind != k_Immediate)
931      return false;
932    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
933    if (!CE) return false;
934    int64_t Val = CE->getValue();
935    return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
936      (Val == INT32_MIN);
937  }
938
939  bool isMSRMask() const { return Kind == k_MSRMask; }
940  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
941
942  // NEON operands.
943  bool isVecListOneD() const {
944    if (Kind != k_VectorList) return false;
945    return VectorList.Count == 1;
946  }
947
948  bool isVecListTwoD() const {
949    if (Kind != k_VectorList) return false;
950    return VectorList.Count == 2;
951  }
952
953  bool isVecListThreeD() const {
954    if (Kind != k_VectorList) return false;
955    return VectorList.Count == 3;
956  }
957
958  bool isVecListFourD() const {
959    if (Kind != k_VectorList) return false;
960    return VectorList.Count == 4;
961  }
962
963  bool isVecListTwoQ() const {
964    if (Kind != k_VectorList) return false;
965    //FIXME: We haven't taught the parser to handle by-two register lists
966    // yet, so don't pretend to know one.
967    return VectorList.Count == 2 && false;
968  }
969
970  bool isVectorIndex8() const {
971    if (Kind != k_VectorIndex) return false;
972    return VectorIndex.Val < 8;
973  }
974  bool isVectorIndex16() const {
975    if (Kind != k_VectorIndex) return false;
976    return VectorIndex.Val < 4;
977  }
978  bool isVectorIndex32() const {
979    if (Kind != k_VectorIndex) return false;
980    return VectorIndex.Val < 2;
981  }
982
983  bool isNEONi8splat() const {
984    if (Kind != k_Immediate)
985      return false;
986    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
987    // Must be a constant.
988    if (!CE) return false;
989    int64_t Value = CE->getValue();
990    // i8 value splatted across 8 bytes. The immediate is just the 8 byte
991    // value.
992    return Value >= 0 && Value < 256;
993  }
994
995  bool isNEONi16splat() const {
996    if (Kind != k_Immediate)
997      return false;
998    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
999    // Must be a constant.
1000    if (!CE) return false;
1001    int64_t Value = CE->getValue();
1002    // i16 value in the range [0,255] or [0x0100, 0xff00]
1003    return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1004  }
1005
1006  bool isNEONi32splat() const {
1007    if (Kind != k_Immediate)
1008      return false;
1009    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1010    // Must be a constant.
1011    if (!CE) return false;
1012    int64_t Value = CE->getValue();
1013    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1014    return (Value >= 0 && Value < 256) ||
1015      (Value >= 0x0100 && Value <= 0xff00) ||
1016      (Value >= 0x010000 && Value <= 0xff0000) ||
1017      (Value >= 0x01000000 && Value <= 0xff000000);
1018  }
1019
1020  bool isNEONi32vmov() const {
1021    if (Kind != k_Immediate)
1022      return false;
1023    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1024    // Must be a constant.
1025    if (!CE) return false;
1026    int64_t Value = CE->getValue();
1027    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1028    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1029    return (Value >= 0 && Value < 256) ||
1030      (Value >= 0x0100 && Value <= 0xff00) ||
1031      (Value >= 0x010000 && Value <= 0xff0000) ||
1032      (Value >= 0x01000000 && Value <= 0xff000000) ||
1033      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1034      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1035  }
1036
1037  bool isNEONi64splat() const {
1038    if (Kind != k_Immediate)
1039      return false;
1040    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1041    // Must be a constant.
1042    if (!CE) return false;
1043    uint64_t Value = CE->getValue();
1044    // i64 value with each byte being either 0 or 0xff.
1045    for (unsigned i = 0; i < 8; ++i)
1046      if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1047    return true;
1048  }
1049
1050  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1051    // Add as immediates when possible.  Null MCExpr = 0.
1052    if (Expr == 0)
1053      Inst.addOperand(MCOperand::CreateImm(0));
1054    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1055      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1056    else
1057      Inst.addOperand(MCOperand::CreateExpr(Expr));
1058  }
1059
1060  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1061    assert(N == 2 && "Invalid number of operands!");
1062    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1063    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1064    Inst.addOperand(MCOperand::CreateReg(RegNum));
1065  }
1066
1067  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1068    assert(N == 1 && "Invalid number of operands!");
1069    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1070  }
1071
1072  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1073    assert(N == 1 && "Invalid number of operands!");
1074    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1075  }
1076
1077  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1078    assert(N == 1 && "Invalid number of operands!");
1079    Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1080  }
1081
1082  void addITMaskOperands(MCInst &Inst, unsigned N) const {
1083    assert(N == 1 && "Invalid number of operands!");
1084    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1085  }
1086
1087  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1088    assert(N == 1 && "Invalid number of operands!");
1089    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1090  }
1091
1092  void addCCOutOperands(MCInst &Inst, unsigned N) const {
1093    assert(N == 1 && "Invalid number of operands!");
1094    Inst.addOperand(MCOperand::CreateReg(getReg()));
1095  }
1096
1097  void addRegOperands(MCInst &Inst, unsigned N) const {
1098    assert(N == 1 && "Invalid number of operands!");
1099    Inst.addOperand(MCOperand::CreateReg(getReg()));
1100  }
1101
1102  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1103    assert(N == 3 && "Invalid number of operands!");
1104    assert(isRegShiftedReg() &&
1105           "addRegShiftedRegOperands() on non RegShiftedReg!");
1106    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1107    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1108    Inst.addOperand(MCOperand::CreateImm(
1109      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1110  }
1111
1112  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1113    assert(N == 2 && "Invalid number of operands!");
1114    assert(isRegShiftedImm() &&
1115           "addRegShiftedImmOperands() on non RegShiftedImm!");
1116    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1117    Inst.addOperand(MCOperand::CreateImm(
1118      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
1119  }
1120
1121  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1122    assert(N == 1 && "Invalid number of operands!");
1123    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1124                                         ShifterImm.Imm));
1125  }
1126
1127  void addRegListOperands(MCInst &Inst, unsigned N) const {
1128    assert(N == 1 && "Invalid number of operands!");
1129    const SmallVectorImpl<unsigned> &RegList = getRegList();
1130    for (SmallVectorImpl<unsigned>::const_iterator
1131           I = RegList.begin(), E = RegList.end(); I != E; ++I)
1132      Inst.addOperand(MCOperand::CreateReg(*I));
1133  }
1134
1135  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1136    addRegListOperands(Inst, N);
1137  }
1138
1139  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1140    addRegListOperands(Inst, N);
1141  }
1142
1143  void addRotImmOperands(MCInst &Inst, unsigned N) const {
1144    assert(N == 1 && "Invalid number of operands!");
1145    // Encoded as val>>3. The printer handles display as 8, 16, 24.
1146    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1147  }
1148
1149  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1150    assert(N == 1 && "Invalid number of operands!");
1151    // Munge the lsb/width into a bitfield mask.
1152    unsigned lsb = Bitfield.LSB;
1153    unsigned width = Bitfield.Width;
1154    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1155    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1156                      (32 - (lsb + width)));
1157    Inst.addOperand(MCOperand::CreateImm(Mask));
1158  }
1159
1160  void addImmOperands(MCInst &Inst, unsigned N) const {
1161    assert(N == 1 && "Invalid number of operands!");
1162    addExpr(Inst, getImm());
1163  }
1164
1165  void addFPImmOperands(MCInst &Inst, unsigned N) const {
1166    assert(N == 1 && "Invalid number of operands!");
1167    Inst.addOperand(MCOperand::CreateImm(getFPImm()));
1168  }
1169
1170  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1171    assert(N == 1 && "Invalid number of operands!");
1172    // FIXME: We really want to scale the value here, but the LDRD/STRD
1173    // instruction don't encode operands that way yet.
1174    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1175    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1176  }
1177
1178  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1179    assert(N == 1 && "Invalid number of operands!");
1180    // The immediate is scaled by four in the encoding and is stored
1181    // in the MCInst as such. Lop off the low two bits here.
1182    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1183    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1184  }
1185
1186  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1187    assert(N == 1 && "Invalid number of operands!");
1188    // The immediate is scaled by four in the encoding and is stored
1189    // in the MCInst as such. Lop off the low two bits here.
1190    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1191    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1192  }
1193
1194  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1195    assert(N == 1 && "Invalid number of operands!");
1196    // The constant encodes as the immediate-1, and we store in the instruction
1197    // the bits as encoded, so subtract off one here.
1198    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1199    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1200  }
1201
1202  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1203    assert(N == 1 && "Invalid number of operands!");
1204    // The constant encodes as the immediate-1, and we store in the instruction
1205    // the bits as encoded, so subtract off one here.
1206    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1207    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1208  }
1209
1210  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1211    assert(N == 1 && "Invalid number of operands!");
1212    // The constant encodes as the immediate, except for 32, which encodes as
1213    // zero.
1214    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1215    unsigned Imm = CE->getValue();
1216    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1217  }
1218
1219  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1220    assert(N == 1 && "Invalid number of operands!");
1221    // An ASR value of 32 encodes as 0, so that's how we want to add it to
1222    // the instruction as well.
1223    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1224    int Val = CE->getValue();
1225    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1226  }
1227
1228  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1229    assert(N == 1 && "Invalid number of operands!");
1230    // The operand is actually a t2_so_imm, but we have its bitwise
1231    // negation in the assembly source, so twiddle it here.
1232    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1233    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1234  }
1235
1236  void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1237    assert(N == 1 && "Invalid number of operands!");
1238    // The operand is actually a so_imm, but we have its bitwise
1239    // negation in the assembly source, so twiddle it here.
1240    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1241    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1242  }
1243
1244  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1245    assert(N == 1 && "Invalid number of operands!");
1246    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1247  }
1248
1249  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1250    assert(N == 1 && "Invalid number of operands!");
1251    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1252  }
1253
1254  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1255    assert(N == 2 && "Invalid number of operands!");
1256    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1257    Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1258  }
1259
1260  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1261    assert(N == 3 && "Invalid number of operands!");
1262    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1263    if (!Memory.OffsetRegNum) {
1264      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1265      // Special case for #-0
1266      if (Val == INT32_MIN) Val = 0;
1267      if (Val < 0) Val = -Val;
1268      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1269    } else {
1270      // For register offset, we encode the shift type and negation flag
1271      // here.
1272      Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1273                              Memory.ShiftImm, Memory.ShiftType);
1274    }
1275    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1276    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1277    Inst.addOperand(MCOperand::CreateImm(Val));
1278  }
1279
1280  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1281    assert(N == 2 && "Invalid number of operands!");
1282    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1283    assert(CE && "non-constant AM2OffsetImm operand!");
1284    int32_t Val = CE->getValue();
1285    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1286    // Special case for #-0
1287    if (Val == INT32_MIN) Val = 0;
1288    if (Val < 0) Val = -Val;
1289    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1290    Inst.addOperand(MCOperand::CreateReg(0));
1291    Inst.addOperand(MCOperand::CreateImm(Val));
1292  }
1293
1294  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1295    assert(N == 3 && "Invalid number of operands!");
1296    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1297    if (!Memory.OffsetRegNum) {
1298      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1299      // Special case for #-0
1300      if (Val == INT32_MIN) Val = 0;
1301      if (Val < 0) Val = -Val;
1302      Val = ARM_AM::getAM3Opc(AddSub, Val);
1303    } else {
1304      // For register offset, we encode the shift type and negation flag
1305      // here.
1306      Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1307    }
1308    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1309    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1310    Inst.addOperand(MCOperand::CreateImm(Val));
1311  }
1312
1313  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1314    assert(N == 2 && "Invalid number of operands!");
1315    if (Kind == k_PostIndexRegister) {
1316      int32_t Val =
1317        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1318      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1319      Inst.addOperand(MCOperand::CreateImm(Val));
1320      return;
1321    }
1322
1323    // Constant offset.
1324    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1325    int32_t Val = CE->getValue();
1326    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1327    // Special case for #-0
1328    if (Val == INT32_MIN) Val = 0;
1329    if (Val < 0) Val = -Val;
1330    Val = ARM_AM::getAM3Opc(AddSub, Val);
1331    Inst.addOperand(MCOperand::CreateReg(0));
1332    Inst.addOperand(MCOperand::CreateImm(Val));
1333  }
1334
1335  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1336    assert(N == 2 && "Invalid number of operands!");
1337    // If we have an immediate that's not a constant, treat it as a label
1338    // reference needing a fixup. If it is a constant, it's something else
1339    // and we reject it.
1340    if (isImm()) {
1341      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1342      Inst.addOperand(MCOperand::CreateImm(0));
1343      return;
1344    }
1345
1346    // The lower two bits are always zero and as such are not encoded.
1347    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1348    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1349    // Special case for #-0
1350    if (Val == INT32_MIN) Val = 0;
1351    if (Val < 0) Val = -Val;
1352    Val = ARM_AM::getAM5Opc(AddSub, Val);
1353    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1354    Inst.addOperand(MCOperand::CreateImm(Val));
1355  }
1356
1357  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1358    assert(N == 2 && "Invalid number of operands!");
1359    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1360    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1361    Inst.addOperand(MCOperand::CreateImm(Val));
1362  }
1363
1364  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1365    assert(N == 2 && "Invalid number of operands!");
1366    // The lower two bits are always zero and as such are not encoded.
1367    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1368    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1369    Inst.addOperand(MCOperand::CreateImm(Val));
1370  }
1371
1372  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1373    assert(N == 2 && "Invalid number of operands!");
1374    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1375    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1376    Inst.addOperand(MCOperand::CreateImm(Val));
1377  }
1378
1379  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1380    addMemImm8OffsetOperands(Inst, N);
1381  }
1382
1383  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1384    addMemImm8OffsetOperands(Inst, N);
1385  }
1386
1387  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1388    assert(N == 2 && "Invalid number of operands!");
1389    // If this is an immediate, it's a label reference.
1390    if (Kind == k_Immediate) {
1391      addExpr(Inst, getImm());
1392      Inst.addOperand(MCOperand::CreateImm(0));
1393      return;
1394    }
1395
1396    // Otherwise, it's a normal memory reg+offset.
1397    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1398    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1399    Inst.addOperand(MCOperand::CreateImm(Val));
1400  }
1401
1402  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1403    assert(N == 2 && "Invalid number of operands!");
1404    // If this is an immediate, it's a label reference.
1405    if (Kind == k_Immediate) {
1406      addExpr(Inst, getImm());
1407      Inst.addOperand(MCOperand::CreateImm(0));
1408      return;
1409    }
1410
1411    // Otherwise, it's a normal memory reg+offset.
1412    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1413    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1414    Inst.addOperand(MCOperand::CreateImm(Val));
1415  }
1416
1417  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1418    assert(N == 2 && "Invalid number of operands!");
1419    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1420    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1421  }
1422
1423  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1424    assert(N == 2 && "Invalid number of operands!");
1425    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1426    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1427  }
1428
1429  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1430    assert(N == 3 && "Invalid number of operands!");
1431    unsigned Val =
1432      ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1433                        Memory.ShiftImm, Memory.ShiftType);
1434    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1435    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1436    Inst.addOperand(MCOperand::CreateImm(Val));
1437  }
1438
1439  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1440    assert(N == 3 && "Invalid number of operands!");
1441    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1442    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1443    Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1444  }
1445
1446  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1447    assert(N == 2 && "Invalid number of operands!");
1448    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1449    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1450  }
1451
1452  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1453    assert(N == 2 && "Invalid number of operands!");
1454    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1455    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1456    Inst.addOperand(MCOperand::CreateImm(Val));
1457  }
1458
1459  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1460    assert(N == 2 && "Invalid number of operands!");
1461    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1462    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1463    Inst.addOperand(MCOperand::CreateImm(Val));
1464  }
1465
1466  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1467    assert(N == 2 && "Invalid number of operands!");
1468    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1469    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1470    Inst.addOperand(MCOperand::CreateImm(Val));
1471  }
1472
1473  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1474    assert(N == 2 && "Invalid number of operands!");
1475    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1476    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1477    Inst.addOperand(MCOperand::CreateImm(Val));
1478  }
1479
1480  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1481    assert(N == 1 && "Invalid number of operands!");
1482    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1483    assert(CE && "non-constant post-idx-imm8 operand!");
1484    int Imm = CE->getValue();
1485    bool isAdd = Imm >= 0;
1486    if (Imm == INT32_MIN) Imm = 0;
1487    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1488    Inst.addOperand(MCOperand::CreateImm(Imm));
1489  }
1490
1491  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1492    assert(N == 1 && "Invalid number of operands!");
1493    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1494    assert(CE && "non-constant post-idx-imm8s4 operand!");
1495    int Imm = CE->getValue();
1496    bool isAdd = Imm >= 0;
1497    if (Imm == INT32_MIN) Imm = 0;
1498    // Immediate is scaled by 4.
1499    Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1500    Inst.addOperand(MCOperand::CreateImm(Imm));
1501  }
1502
1503  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1504    assert(N == 2 && "Invalid number of operands!");
1505    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1506    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1507  }
1508
1509  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1510    assert(N == 2 && "Invalid number of operands!");
1511    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1512    // The sign, shift type, and shift amount are encoded in a single operand
1513    // using the AM2 encoding helpers.
1514    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1515    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1516                                     PostIdxReg.ShiftTy);
1517    Inst.addOperand(MCOperand::CreateImm(Imm));
1518  }
1519
1520  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1521    assert(N == 1 && "Invalid number of operands!");
1522    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1523  }
1524
1525  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1526    assert(N == 1 && "Invalid number of operands!");
1527    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1528  }
1529
1530  void addVecListOneDOperands(MCInst &Inst, unsigned N) const {
1531    assert(N == 1 && "Invalid number of operands!");
1532    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1533  }
1534
1535  void addVecListTwoDOperands(MCInst &Inst, unsigned N) const {
1536    assert(N == 1 && "Invalid number of operands!");
1537    // Only the first register actually goes on the instruction. The rest
1538    // are implied by the opcode.
1539    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1540  }
1541
1542  void addVecListThreeDOperands(MCInst &Inst, unsigned N) const {
1543    assert(N == 1 && "Invalid number of operands!");
1544    // Only the first register actually goes on the instruction. The rest
1545    // are implied by the opcode.
1546    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1547  }
1548
1549  void addVecListFourDOperands(MCInst &Inst, unsigned N) const {
1550    assert(N == 1 && "Invalid number of operands!");
1551    // Only the first register actually goes on the instruction. The rest
1552    // are implied by the opcode.
1553    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1554  }
1555
1556  void addVecListTwoQOperands(MCInst &Inst, unsigned N) const {
1557    assert(N == 1 && "Invalid number of operands!");
1558    // Only the first register actually goes on the instruction. The rest
1559    // are implied by the opcode.
1560    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1561  }
1562
1563  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1564    assert(N == 1 && "Invalid number of operands!");
1565    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1566  }
1567
1568  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1569    assert(N == 1 && "Invalid number of operands!");
1570    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1571  }
1572
1573  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1574    assert(N == 1 && "Invalid number of operands!");
1575    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1576  }
1577
1578  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1579    assert(N == 1 && "Invalid number of operands!");
1580    // The immediate encodes the type of constant as well as the value.
1581    // Mask in that this is an i8 splat.
1582    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1583    Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1584  }
1585
1586  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1587    assert(N == 1 && "Invalid number of operands!");
1588    // The immediate encodes the type of constant as well as the value.
1589    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1590    unsigned Value = CE->getValue();
1591    if (Value >= 256)
1592      Value = (Value >> 8) | 0xa00;
1593    else
1594      Value |= 0x800;
1595    Inst.addOperand(MCOperand::CreateImm(Value));
1596  }
1597
1598  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
1599    assert(N == 1 && "Invalid number of operands!");
1600    // The immediate encodes the type of constant as well as the value.
1601    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1602    unsigned Value = CE->getValue();
1603    if (Value >= 256 && Value <= 0xff00)
1604      Value = (Value >> 8) | 0x200;
1605    else if (Value > 0xffff && Value <= 0xff0000)
1606      Value = (Value >> 16) | 0x400;
1607    else if (Value > 0xffffff)
1608      Value = (Value >> 24) | 0x600;
1609    Inst.addOperand(MCOperand::CreateImm(Value));
1610  }
1611
1612  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
1613    assert(N == 1 && "Invalid number of operands!");
1614    // The immediate encodes the type of constant as well as the value.
1615    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1616    unsigned Value = CE->getValue();
1617    if (Value >= 256 && Value <= 0xffff)
1618      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
1619    else if (Value > 0xffff && Value <= 0xffffff)
1620      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
1621    else if (Value > 0xffffff)
1622      Value = (Value >> 24) | 0x600;
1623    Inst.addOperand(MCOperand::CreateImm(Value));
1624  }
1625
1626  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
1627    assert(N == 1 && "Invalid number of operands!");
1628    // The immediate encodes the type of constant as well as the value.
1629    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1630    uint64_t Value = CE->getValue();
1631    unsigned Imm = 0;
1632    for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
1633      Imm |= (Value & 1) << i;
1634    }
1635    Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
1636  }
1637
1638  virtual void print(raw_ostream &OS) const;
1639
1640  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1641    ARMOperand *Op = new ARMOperand(k_ITCondMask);
1642    Op->ITMask.Mask = Mask;
1643    Op->StartLoc = S;
1644    Op->EndLoc = S;
1645    return Op;
1646  }
1647
1648  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1649    ARMOperand *Op = new ARMOperand(k_CondCode);
1650    Op->CC.Val = CC;
1651    Op->StartLoc = S;
1652    Op->EndLoc = S;
1653    return Op;
1654  }
1655
1656  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1657    ARMOperand *Op = new ARMOperand(k_CoprocNum);
1658    Op->Cop.Val = CopVal;
1659    Op->StartLoc = S;
1660    Op->EndLoc = S;
1661    return Op;
1662  }
1663
1664  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1665    ARMOperand *Op = new ARMOperand(k_CoprocReg);
1666    Op->Cop.Val = CopVal;
1667    Op->StartLoc = S;
1668    Op->EndLoc = S;
1669    return Op;
1670  }
1671
1672  static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
1673    ARMOperand *Op = new ARMOperand(k_CoprocOption);
1674    Op->Cop.Val = Val;
1675    Op->StartLoc = S;
1676    Op->EndLoc = E;
1677    return Op;
1678  }
1679
1680  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1681    ARMOperand *Op = new ARMOperand(k_CCOut);
1682    Op->Reg.RegNum = RegNum;
1683    Op->StartLoc = S;
1684    Op->EndLoc = S;
1685    return Op;
1686  }
1687
1688  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1689    ARMOperand *Op = new ARMOperand(k_Token);
1690    Op->Tok.Data = Str.data();
1691    Op->Tok.Length = Str.size();
1692    Op->StartLoc = S;
1693    Op->EndLoc = S;
1694    return Op;
1695  }
1696
1697  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1698    ARMOperand *Op = new ARMOperand(k_Register);
1699    Op->Reg.RegNum = RegNum;
1700    Op->StartLoc = S;
1701    Op->EndLoc = E;
1702    return Op;
1703  }
1704
1705  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1706                                           unsigned SrcReg,
1707                                           unsigned ShiftReg,
1708                                           unsigned ShiftImm,
1709                                           SMLoc S, SMLoc E) {
1710    ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
1711    Op->RegShiftedReg.ShiftTy = ShTy;
1712    Op->RegShiftedReg.SrcReg = SrcReg;
1713    Op->RegShiftedReg.ShiftReg = ShiftReg;
1714    Op->RegShiftedReg.ShiftImm = ShiftImm;
1715    Op->StartLoc = S;
1716    Op->EndLoc = E;
1717    return Op;
1718  }
1719
1720  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1721                                            unsigned SrcReg,
1722                                            unsigned ShiftImm,
1723                                            SMLoc S, SMLoc E) {
1724    ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
1725    Op->RegShiftedImm.ShiftTy = ShTy;
1726    Op->RegShiftedImm.SrcReg = SrcReg;
1727    Op->RegShiftedImm.ShiftImm = ShiftImm;
1728    Op->StartLoc = S;
1729    Op->EndLoc = E;
1730    return Op;
1731  }
1732
1733  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1734                                   SMLoc S, SMLoc E) {
1735    ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
1736    Op->ShifterImm.isASR = isASR;
1737    Op->ShifterImm.Imm = Imm;
1738    Op->StartLoc = S;
1739    Op->EndLoc = E;
1740    return Op;
1741  }
1742
1743  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1744    ARMOperand *Op = new ARMOperand(k_RotateImmediate);
1745    Op->RotImm.Imm = Imm;
1746    Op->StartLoc = S;
1747    Op->EndLoc = E;
1748    return Op;
1749  }
1750
1751  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1752                                    SMLoc S, SMLoc E) {
1753    ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
1754    Op->Bitfield.LSB = LSB;
1755    Op->Bitfield.Width = Width;
1756    Op->StartLoc = S;
1757    Op->EndLoc = E;
1758    return Op;
1759  }
1760
1761  static ARMOperand *
1762  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1763                SMLoc StartLoc, SMLoc EndLoc) {
1764    KindTy Kind = k_RegisterList;
1765
1766    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
1767      Kind = k_DPRRegisterList;
1768    else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
1769             contains(Regs.front().first))
1770      Kind = k_SPRRegisterList;
1771
1772    ARMOperand *Op = new ARMOperand(Kind);
1773    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1774           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1775      Op->Registers.push_back(I->first);
1776    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1777    Op->StartLoc = StartLoc;
1778    Op->EndLoc = EndLoc;
1779    return Op;
1780  }
1781
1782  static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
1783                                      SMLoc S, SMLoc E) {
1784    ARMOperand *Op = new ARMOperand(k_VectorList);
1785    Op->VectorList.RegNum = RegNum;
1786    Op->VectorList.Count = Count;
1787    Op->StartLoc = S;
1788    Op->EndLoc = E;
1789    return Op;
1790  }
1791
1792  static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
1793                                       MCContext &Ctx) {
1794    ARMOperand *Op = new ARMOperand(k_VectorIndex);
1795    Op->VectorIndex.Val = Idx;
1796    Op->StartLoc = S;
1797    Op->EndLoc = E;
1798    return Op;
1799  }
1800
1801  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1802    ARMOperand *Op = new ARMOperand(k_Immediate);
1803    Op->Imm.Val = Val;
1804    Op->StartLoc = S;
1805    Op->EndLoc = E;
1806    return Op;
1807  }
1808
1809  static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) {
1810    ARMOperand *Op = new ARMOperand(k_FPImmediate);
1811    Op->FPImm.Val = Val;
1812    Op->StartLoc = S;
1813    Op->EndLoc = S;
1814    return Op;
1815  }
1816
1817  static ARMOperand *CreateMem(unsigned BaseRegNum,
1818                               const MCConstantExpr *OffsetImm,
1819                               unsigned OffsetRegNum,
1820                               ARM_AM::ShiftOpc ShiftType,
1821                               unsigned ShiftImm,
1822                               unsigned Alignment,
1823                               bool isNegative,
1824                               SMLoc S, SMLoc E) {
1825    ARMOperand *Op = new ARMOperand(k_Memory);
1826    Op->Memory.BaseRegNum = BaseRegNum;
1827    Op->Memory.OffsetImm = OffsetImm;
1828    Op->Memory.OffsetRegNum = OffsetRegNum;
1829    Op->Memory.ShiftType = ShiftType;
1830    Op->Memory.ShiftImm = ShiftImm;
1831    Op->Memory.Alignment = Alignment;
1832    Op->Memory.isNegative = isNegative;
1833    Op->StartLoc = S;
1834    Op->EndLoc = E;
1835    return Op;
1836  }
1837
1838  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1839                                      ARM_AM::ShiftOpc ShiftTy,
1840                                      unsigned ShiftImm,
1841                                      SMLoc S, SMLoc E) {
1842    ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
1843    Op->PostIdxReg.RegNum = RegNum;
1844    Op->PostIdxReg.isAdd = isAdd;
1845    Op->PostIdxReg.ShiftTy = ShiftTy;
1846    Op->PostIdxReg.ShiftImm = ShiftImm;
1847    Op->StartLoc = S;
1848    Op->EndLoc = E;
1849    return Op;
1850  }
1851
1852  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1853    ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
1854    Op->MBOpt.Val = Opt;
1855    Op->StartLoc = S;
1856    Op->EndLoc = S;
1857    return Op;
1858  }
1859
1860  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1861    ARMOperand *Op = new ARMOperand(k_ProcIFlags);
1862    Op->IFlags.Val = IFlags;
1863    Op->StartLoc = S;
1864    Op->EndLoc = S;
1865    return Op;
1866  }
1867
1868  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1869    ARMOperand *Op = new ARMOperand(k_MSRMask);
1870    Op->MMask.Val = MMask;
1871    Op->StartLoc = S;
1872    Op->EndLoc = S;
1873    return Op;
1874  }
1875};
1876
1877} // end anonymous namespace.
1878
1879void ARMOperand::print(raw_ostream &OS) const {
1880  switch (Kind) {
1881  case k_FPImmediate:
1882    OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm())
1883       << ") >";
1884    break;
1885  case k_CondCode:
1886    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1887    break;
1888  case k_CCOut:
1889    OS << "<ccout " << getReg() << ">";
1890    break;
1891  case k_ITCondMask: {
1892    static const char *MaskStr[] = {
1893      "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
1894      "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
1895    };
1896    assert((ITMask.Mask & 0xf) == ITMask.Mask);
1897    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1898    break;
1899  }
1900  case k_CoprocNum:
1901    OS << "<coprocessor number: " << getCoproc() << ">";
1902    break;
1903  case k_CoprocReg:
1904    OS << "<coprocessor register: " << getCoproc() << ">";
1905    break;
1906  case k_CoprocOption:
1907    OS << "<coprocessor option: " << CoprocOption.Val << ">";
1908    break;
1909  case k_MSRMask:
1910    OS << "<mask: " << getMSRMask() << ">";
1911    break;
1912  case k_Immediate:
1913    getImm()->print(OS);
1914    break;
1915  case k_MemBarrierOpt:
1916    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1917    break;
1918  case k_Memory:
1919    OS << "<memory "
1920       << " base:" << Memory.BaseRegNum;
1921    OS << ">";
1922    break;
1923  case k_PostIndexRegister:
1924    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1925       << PostIdxReg.RegNum;
1926    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1927      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1928         << PostIdxReg.ShiftImm;
1929    OS << ">";
1930    break;
1931  case k_ProcIFlags: {
1932    OS << "<ARM_PROC::";
1933    unsigned IFlags = getProcIFlags();
1934    for (int i=2; i >= 0; --i)
1935      if (IFlags & (1 << i))
1936        OS << ARM_PROC::IFlagsToString(1 << i);
1937    OS << ">";
1938    break;
1939  }
1940  case k_Register:
1941    OS << "<register " << getReg() << ">";
1942    break;
1943  case k_ShifterImmediate:
1944    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1945       << " #" << ShifterImm.Imm << ">";
1946    break;
1947  case k_ShiftedRegister:
1948    OS << "<so_reg_reg "
1949       << RegShiftedReg.SrcReg
1950       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1951       << ", " << RegShiftedReg.ShiftReg << ", "
1952       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1953       << ">";
1954    break;
1955  case k_ShiftedImmediate:
1956    OS << "<so_reg_imm "
1957       << RegShiftedImm.SrcReg
1958       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1959       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1960       << ">";
1961    break;
1962  case k_RotateImmediate:
1963    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1964    break;
1965  case k_BitfieldDescriptor:
1966    OS << "<bitfield " << "lsb: " << Bitfield.LSB
1967       << ", width: " << Bitfield.Width << ">";
1968    break;
1969  case k_RegisterList:
1970  case k_DPRRegisterList:
1971  case k_SPRRegisterList: {
1972    OS << "<register_list ";
1973
1974    const SmallVectorImpl<unsigned> &RegList = getRegList();
1975    for (SmallVectorImpl<unsigned>::const_iterator
1976           I = RegList.begin(), E = RegList.end(); I != E; ) {
1977      OS << *I;
1978      if (++I < E) OS << ", ";
1979    }
1980
1981    OS << ">";
1982    break;
1983  }
1984  case k_VectorList:
1985    OS << "<vector_list " << VectorList.Count << " * "
1986       << VectorList.RegNum << ">";
1987    break;
1988  case k_Token:
1989    OS << "'" << getToken() << "'";
1990    break;
1991  case k_VectorIndex:
1992    OS << "<vectorindex " << getVectorIndex() << ">";
1993    break;
1994  }
1995}
1996
1997/// @name Auto-generated Match Functions
1998/// {
1999
2000static unsigned MatchRegisterName(StringRef Name);
2001
2002/// }
2003
2004bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2005                                 SMLoc &StartLoc, SMLoc &EndLoc) {
2006  RegNo = tryParseRegister();
2007
2008  return (RegNo == (unsigned)-1);
2009}
2010
2011/// Try to parse a register name.  The token must be an Identifier when called,
2012/// and if it is a register name the token is eaten and the register number is
2013/// returned.  Otherwise return -1.
2014///
2015int ARMAsmParser::tryParseRegister() {
2016  const AsmToken &Tok = Parser.getTok();
2017  if (Tok.isNot(AsmToken::Identifier)) return -1;
2018
2019  // FIXME: Validate register for the current architecture; we have to do
2020  // validation later, so maybe there is no need for this here.
2021  std::string lowerCase = Tok.getString().lower();
2022  unsigned RegNum = MatchRegisterName(lowerCase);
2023  if (!RegNum) {
2024    RegNum = StringSwitch<unsigned>(lowerCase)
2025      .Case("r13", ARM::SP)
2026      .Case("r14", ARM::LR)
2027      .Case("r15", ARM::PC)
2028      .Case("ip", ARM::R12)
2029      .Default(0);
2030  }
2031  if (!RegNum) return -1;
2032
2033  Parser.Lex(); // Eat identifier token.
2034
2035  return RegNum;
2036}
2037
2038// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2039// If a recoverable error occurs, return 1. If an irrecoverable error
2040// occurs, return -1. An irrecoverable error is one where tokens have been
2041// consumed in the process of trying to parse the shifter (i.e., when it is
2042// indeed a shifter operand, but malformed).
2043int ARMAsmParser::tryParseShiftRegister(
2044                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2045  SMLoc S = Parser.getTok().getLoc();
2046  const AsmToken &Tok = Parser.getTok();
2047  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2048
2049  std::string lowerCase = Tok.getString().lower();
2050  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2051      .Case("lsl", ARM_AM::lsl)
2052      .Case("lsr", ARM_AM::lsr)
2053      .Case("asr", ARM_AM::asr)
2054      .Case("ror", ARM_AM::ror)
2055      .Case("rrx", ARM_AM::rrx)
2056      .Default(ARM_AM::no_shift);
2057
2058  if (ShiftTy == ARM_AM::no_shift)
2059    return 1;
2060
2061  Parser.Lex(); // Eat the operator.
2062
2063  // The source register for the shift has already been added to the
2064  // operand list, so we need to pop it off and combine it into the shifted
2065  // register operand instead.
2066  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2067  if (!PrevOp->isReg())
2068    return Error(PrevOp->getStartLoc(), "shift must be of a register");
2069  int SrcReg = PrevOp->getReg();
2070  int64_t Imm = 0;
2071  int ShiftReg = 0;
2072  if (ShiftTy == ARM_AM::rrx) {
2073    // RRX Doesn't have an explicit shift amount. The encoder expects
2074    // the shift register to be the same as the source register. Seems odd,
2075    // but OK.
2076    ShiftReg = SrcReg;
2077  } else {
2078    // Figure out if this is shifted by a constant or a register (for non-RRX).
2079    if (Parser.getTok().is(AsmToken::Hash)) {
2080      Parser.Lex(); // Eat hash.
2081      SMLoc ImmLoc = Parser.getTok().getLoc();
2082      const MCExpr *ShiftExpr = 0;
2083      if (getParser().ParseExpression(ShiftExpr)) {
2084        Error(ImmLoc, "invalid immediate shift value");
2085        return -1;
2086      }
2087      // The expression must be evaluatable as an immediate.
2088      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2089      if (!CE) {
2090        Error(ImmLoc, "invalid immediate shift value");
2091        return -1;
2092      }
2093      // Range check the immediate.
2094      // lsl, ror: 0 <= imm <= 31
2095      // lsr, asr: 0 <= imm <= 32
2096      Imm = CE->getValue();
2097      if (Imm < 0 ||
2098          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2099          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2100        Error(ImmLoc, "immediate shift value out of range");
2101        return -1;
2102      }
2103    } else if (Parser.getTok().is(AsmToken::Identifier)) {
2104      ShiftReg = tryParseRegister();
2105      SMLoc L = Parser.getTok().getLoc();
2106      if (ShiftReg == -1) {
2107        Error (L, "expected immediate or register in shift operand");
2108        return -1;
2109      }
2110    } else {
2111      Error (Parser.getTok().getLoc(),
2112                    "expected immediate or register in shift operand");
2113      return -1;
2114    }
2115  }
2116
2117  if (ShiftReg && ShiftTy != ARM_AM::rrx)
2118    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2119                                                         ShiftReg, Imm,
2120                                               S, Parser.getTok().getLoc()));
2121  else
2122    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2123                                               S, Parser.getTok().getLoc()));
2124
2125  return 0;
2126}
2127
2128
2129/// Try to parse a register name.  The token must be an Identifier when called.
2130/// If it's a register, an AsmOperand is created. Another AsmOperand is created
2131/// if there is a "writeback". 'true' if it's not a register.
2132///
2133/// TODO this is likely to change to allow different register types and or to
2134/// parse for a specific register type.
2135bool ARMAsmParser::
2136tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2137  SMLoc S = Parser.getTok().getLoc();
2138  int RegNo = tryParseRegister();
2139  if (RegNo == -1)
2140    return true;
2141
2142  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2143
2144  const AsmToken &ExclaimTok = Parser.getTok();
2145  if (ExclaimTok.is(AsmToken::Exclaim)) {
2146    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2147                                               ExclaimTok.getLoc()));
2148    Parser.Lex(); // Eat exclaim token
2149    return false;
2150  }
2151
2152  // Also check for an index operand. This is only legal for vector registers,
2153  // but that'll get caught OK in operand matching, so we don't need to
2154  // explicitly filter everything else out here.
2155  if (Parser.getTok().is(AsmToken::LBrac)) {
2156    SMLoc SIdx = Parser.getTok().getLoc();
2157    Parser.Lex(); // Eat left bracket token.
2158
2159    const MCExpr *ImmVal;
2160    if (getParser().ParseExpression(ImmVal))
2161      return MatchOperand_ParseFail;
2162    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2163    if (!MCE) {
2164      TokError("immediate value expected for vector index");
2165      return MatchOperand_ParseFail;
2166    }
2167
2168    SMLoc E = Parser.getTok().getLoc();
2169    if (Parser.getTok().isNot(AsmToken::RBrac)) {
2170      Error(E, "']' expected");
2171      return MatchOperand_ParseFail;
2172    }
2173
2174    Parser.Lex(); // Eat right bracket token.
2175
2176    Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2177                                                     SIdx, E,
2178                                                     getContext()));
2179  }
2180
2181  return false;
2182}
2183
2184/// MatchCoprocessorOperandName - Try to parse an coprocessor related
2185/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2186/// "c5", ...
2187static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2188  // Use the same layout as the tablegen'erated register name matcher. Ugly,
2189  // but efficient.
2190  switch (Name.size()) {
2191  default: break;
2192  case 2:
2193    if (Name[0] != CoprocOp)
2194      return -1;
2195    switch (Name[1]) {
2196    default:  return -1;
2197    case '0': return 0;
2198    case '1': return 1;
2199    case '2': return 2;
2200    case '3': return 3;
2201    case '4': return 4;
2202    case '5': return 5;
2203    case '6': return 6;
2204    case '7': return 7;
2205    case '8': return 8;
2206    case '9': return 9;
2207    }
2208    break;
2209  case 3:
2210    if (Name[0] != CoprocOp || Name[1] != '1')
2211      return -1;
2212    switch (Name[2]) {
2213    default:  return -1;
2214    case '0': return 10;
2215    case '1': return 11;
2216    case '2': return 12;
2217    case '3': return 13;
2218    case '4': return 14;
2219    case '5': return 15;
2220    }
2221    break;
2222  }
2223
2224  return -1;
2225}
2226
2227/// parseITCondCode - Try to parse a condition code for an IT instruction.
2228ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2229parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2230  SMLoc S = Parser.getTok().getLoc();
2231  const AsmToken &Tok = Parser.getTok();
2232  if (!Tok.is(AsmToken::Identifier))
2233    return MatchOperand_NoMatch;
2234  unsigned CC = StringSwitch<unsigned>(Tok.getString())
2235    .Case("eq", ARMCC::EQ)
2236    .Case("ne", ARMCC::NE)
2237    .Case("hs", ARMCC::HS)
2238    .Case("cs", ARMCC::HS)
2239    .Case("lo", ARMCC::LO)
2240    .Case("cc", ARMCC::LO)
2241    .Case("mi", ARMCC::MI)
2242    .Case("pl", ARMCC::PL)
2243    .Case("vs", ARMCC::VS)
2244    .Case("vc", ARMCC::VC)
2245    .Case("hi", ARMCC::HI)
2246    .Case("ls", ARMCC::LS)
2247    .Case("ge", ARMCC::GE)
2248    .Case("lt", ARMCC::LT)
2249    .Case("gt", ARMCC::GT)
2250    .Case("le", ARMCC::LE)
2251    .Case("al", ARMCC::AL)
2252    .Default(~0U);
2253  if (CC == ~0U)
2254    return MatchOperand_NoMatch;
2255  Parser.Lex(); // Eat the token.
2256
2257  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2258
2259  return MatchOperand_Success;
2260}
2261
2262/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2263/// token must be an Identifier when called, and if it is a coprocessor
2264/// number, the token is eaten and the operand is added to the operand list.
2265ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2266parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2267  SMLoc S = Parser.getTok().getLoc();
2268  const AsmToken &Tok = Parser.getTok();
2269  if (Tok.isNot(AsmToken::Identifier))
2270    return MatchOperand_NoMatch;
2271
2272  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2273  if (Num == -1)
2274    return MatchOperand_NoMatch;
2275
2276  Parser.Lex(); // Eat identifier token.
2277  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2278  return MatchOperand_Success;
2279}
2280
2281/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2282/// token must be an Identifier when called, and if it is a coprocessor
2283/// number, the token is eaten and the operand is added to the operand list.
2284ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2285parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2286  SMLoc S = Parser.getTok().getLoc();
2287  const AsmToken &Tok = Parser.getTok();
2288  if (Tok.isNot(AsmToken::Identifier))
2289    return MatchOperand_NoMatch;
2290
2291  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2292  if (Reg == -1)
2293    return MatchOperand_NoMatch;
2294
2295  Parser.Lex(); // Eat identifier token.
2296  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2297  return MatchOperand_Success;
2298}
2299
2300/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2301/// coproc_option : '{' imm0_255 '}'
2302ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2303parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2304  SMLoc S = Parser.getTok().getLoc();
2305
2306  // If this isn't a '{', this isn't a coprocessor immediate operand.
2307  if (Parser.getTok().isNot(AsmToken::LCurly))
2308    return MatchOperand_NoMatch;
2309  Parser.Lex(); // Eat the '{'
2310
2311  const MCExpr *Expr;
2312  SMLoc Loc = Parser.getTok().getLoc();
2313  if (getParser().ParseExpression(Expr)) {
2314    Error(Loc, "illegal expression");
2315    return MatchOperand_ParseFail;
2316  }
2317  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2318  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2319    Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2320    return MatchOperand_ParseFail;
2321  }
2322  int Val = CE->getValue();
2323
2324  // Check for and consume the closing '}'
2325  if (Parser.getTok().isNot(AsmToken::RCurly))
2326    return MatchOperand_ParseFail;
2327  SMLoc E = Parser.getTok().getLoc();
2328  Parser.Lex(); // Eat the '}'
2329
2330  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2331  return MatchOperand_Success;
2332}
2333
2334// For register list parsing, we need to map from raw GPR register numbering
2335// to the enumeration values. The enumeration values aren't sorted by
2336// register number due to our using "sp", "lr" and "pc" as canonical names.
2337static unsigned getNextRegister(unsigned Reg) {
2338  // If this is a GPR, we need to do it manually, otherwise we can rely
2339  // on the sort ordering of the enumeration since the other reg-classes
2340  // are sane.
2341  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2342    return Reg + 1;
2343  switch(Reg) {
2344  default: assert(0 && "Invalid GPR number!");
2345  case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
2346  case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
2347  case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
2348  case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
2349  case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
2350  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2351  case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
2352  case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
2353  }
2354}
2355
2356// Return the low-subreg of a given Q register.
2357static unsigned getDRegFromQReg(unsigned QReg) {
2358  switch (QReg) {
2359  default: llvm_unreachable("expected a Q register!");
2360  case ARM::Q0:  return ARM::D0;
2361  case ARM::Q1:  return ARM::D2;
2362  case ARM::Q2:  return ARM::D4;
2363  case ARM::Q3:  return ARM::D6;
2364  case ARM::Q4:  return ARM::D8;
2365  case ARM::Q5:  return ARM::D10;
2366  case ARM::Q6:  return ARM::D12;
2367  case ARM::Q7:  return ARM::D14;
2368  case ARM::Q8:  return ARM::D16;
2369  case ARM::Q9:  return ARM::D18;
2370  case ARM::Q10: return ARM::D20;
2371  case ARM::Q11: return ARM::D22;
2372  case ARM::Q12: return ARM::D24;
2373  case ARM::Q13: return ARM::D26;
2374  case ARM::Q14: return ARM::D28;
2375  case ARM::Q15: return ARM::D30;
2376  }
2377}
2378
2379/// Parse a register list.
2380bool ARMAsmParser::
2381parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2382  assert(Parser.getTok().is(AsmToken::LCurly) &&
2383         "Token is not a Left Curly Brace");
2384  SMLoc S = Parser.getTok().getLoc();
2385  Parser.Lex(); // Eat '{' token.
2386  SMLoc RegLoc = Parser.getTok().getLoc();
2387
2388  // Check the first register in the list to see what register class
2389  // this is a list of.
2390  int Reg = tryParseRegister();
2391  if (Reg == -1)
2392    return Error(RegLoc, "register expected");
2393
2394  // The reglist instructions have at most 16 registers, so reserve
2395  // space for that many.
2396  SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2397
2398  // Allow Q regs and just interpret them as the two D sub-registers.
2399  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2400    Reg = getDRegFromQReg(Reg);
2401    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2402    ++Reg;
2403  }
2404  const MCRegisterClass *RC;
2405  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2406    RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2407  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2408    RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2409  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2410    RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2411  else
2412    return Error(RegLoc, "invalid register in register list");
2413
2414  // Store the register.
2415  Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2416
2417  // This starts immediately after the first register token in the list,
2418  // so we can see either a comma or a minus (range separator) as a legal
2419  // next token.
2420  while (Parser.getTok().is(AsmToken::Comma) ||
2421         Parser.getTok().is(AsmToken::Minus)) {
2422    if (Parser.getTok().is(AsmToken::Minus)) {
2423      Parser.Lex(); // Eat the comma.
2424      SMLoc EndLoc = Parser.getTok().getLoc();
2425      int EndReg = tryParseRegister();
2426      if (EndReg == -1)
2427        return Error(EndLoc, "register expected");
2428      // Allow Q regs and just interpret them as the two D sub-registers.
2429      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2430        EndReg = getDRegFromQReg(EndReg) + 1;
2431      // If the register is the same as the start reg, there's nothing
2432      // more to do.
2433      if (Reg == EndReg)
2434        continue;
2435      // The register must be in the same register class as the first.
2436      if (!RC->contains(EndReg))
2437        return Error(EndLoc, "invalid register in register list");
2438      // Ranges must go from low to high.
2439      if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
2440        return Error(EndLoc, "bad range in register list");
2441
2442      // Add all the registers in the range to the register list.
2443      while (Reg != EndReg) {
2444        Reg = getNextRegister(Reg);
2445        Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2446      }
2447      continue;
2448    }
2449    Parser.Lex(); // Eat the comma.
2450    RegLoc = Parser.getTok().getLoc();
2451    int OldReg = Reg;
2452    Reg = tryParseRegister();
2453    if (Reg == -1)
2454      return Error(RegLoc, "register expected");
2455    // Allow Q regs and just interpret them as the two D sub-registers.
2456    bool isQReg = false;
2457    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2458      Reg = getDRegFromQReg(Reg);
2459      isQReg = true;
2460    }
2461    // The register must be in the same register class as the first.
2462    if (!RC->contains(Reg))
2463      return Error(RegLoc, "invalid register in register list");
2464    // List must be monotonically increasing.
2465    if (getARMRegisterNumbering(Reg) <= getARMRegisterNumbering(OldReg))
2466      return Error(RegLoc, "register list not in ascending order");
2467    // VFP register lists must also be contiguous.
2468    // It's OK to use the enumeration values directly here rather, as the
2469    // VFP register classes have the enum sorted properly.
2470    if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2471        Reg != OldReg + 1)
2472      return Error(RegLoc, "non-contiguous register range");
2473    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2474    if (isQReg)
2475      Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2476  }
2477
2478  SMLoc E = Parser.getTok().getLoc();
2479  if (Parser.getTok().isNot(AsmToken::RCurly))
2480    return Error(E, "'}' expected");
2481  Parser.Lex(); // Eat '}' token.
2482
2483  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2484  return false;
2485}
2486
2487// parse a vector register list
2488ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2489parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2490  if(Parser.getTok().isNot(AsmToken::LCurly))
2491    return MatchOperand_NoMatch;
2492
2493  SMLoc S = Parser.getTok().getLoc();
2494  Parser.Lex(); // Eat '{' token.
2495  SMLoc RegLoc = Parser.getTok().getLoc();
2496
2497  int Reg = tryParseRegister();
2498  if (Reg == -1) {
2499    Error(RegLoc, "register expected");
2500    return MatchOperand_ParseFail;
2501  }
2502  unsigned Count = 1;
2503  unsigned FirstReg = Reg;
2504  // The list is of D registers, but we also allow Q regs and just interpret
2505  // them as the two D sub-registers.
2506  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2507    FirstReg = Reg = getDRegFromQReg(Reg);
2508    ++Reg;
2509    ++Count;
2510  }
2511
2512  while (Parser.getTok().is(AsmToken::Comma)) {
2513    Parser.Lex(); // Eat the comma.
2514    RegLoc = Parser.getTok().getLoc();
2515    int OldReg = Reg;
2516    Reg = tryParseRegister();
2517    if (Reg == -1) {
2518      Error(RegLoc, "register expected");
2519      return MatchOperand_ParseFail;
2520    }
2521    // vector register lists must be contiguous.
2522    // It's OK to use the enumeration values directly here rather, as the
2523    // VFP register classes have the enum sorted properly.
2524    //
2525    // The list is of D registers, but we also allow Q regs and just interpret
2526    // them as the two D sub-registers.
2527    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2528      Reg = getDRegFromQReg(Reg);
2529      if (Reg != OldReg + 1) {
2530        Error(RegLoc, "non-contiguous register range");
2531        return MatchOperand_ParseFail;
2532      }
2533      ++Reg;
2534      Count += 2;
2535      continue;
2536    }
2537    // Normal D register. Just check that it's contiguous and keep going.
2538    if (Reg != OldReg + 1) {
2539      Error(RegLoc, "non-contiguous register range");
2540      return MatchOperand_ParseFail;
2541    }
2542    ++Count;
2543  }
2544
2545  SMLoc E = Parser.getTok().getLoc();
2546  if (Parser.getTok().isNot(AsmToken::RCurly)) {
2547    Error(E, "'}' expected");
2548    return MatchOperand_ParseFail;
2549  }
2550  Parser.Lex(); // Eat '}' token.
2551
2552  Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, S, E));
2553  return MatchOperand_Success;
2554}
2555
2556/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
2557ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2558parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2559  SMLoc S = Parser.getTok().getLoc();
2560  const AsmToken &Tok = Parser.getTok();
2561  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2562  StringRef OptStr = Tok.getString();
2563
2564  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
2565    .Case("sy",    ARM_MB::SY)
2566    .Case("st",    ARM_MB::ST)
2567    .Case("sh",    ARM_MB::ISH)
2568    .Case("ish",   ARM_MB::ISH)
2569    .Case("shst",  ARM_MB::ISHST)
2570    .Case("ishst", ARM_MB::ISHST)
2571    .Case("nsh",   ARM_MB::NSH)
2572    .Case("un",    ARM_MB::NSH)
2573    .Case("nshst", ARM_MB::NSHST)
2574    .Case("unst",  ARM_MB::NSHST)
2575    .Case("osh",   ARM_MB::OSH)
2576    .Case("oshst", ARM_MB::OSHST)
2577    .Default(~0U);
2578
2579  if (Opt == ~0U)
2580    return MatchOperand_NoMatch;
2581
2582  Parser.Lex(); // Eat identifier token.
2583  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
2584  return MatchOperand_Success;
2585}
2586
2587/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
2588ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2589parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2590  SMLoc S = Parser.getTok().getLoc();
2591  const AsmToken &Tok = Parser.getTok();
2592  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2593  StringRef IFlagsStr = Tok.getString();
2594
2595  // An iflags string of "none" is interpreted to mean that none of the AIF
2596  // bits are set.  Not a terribly useful instruction, but a valid encoding.
2597  unsigned IFlags = 0;
2598  if (IFlagsStr != "none") {
2599        for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
2600      unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
2601        .Case("a", ARM_PROC::A)
2602        .Case("i", ARM_PROC::I)
2603        .Case("f", ARM_PROC::F)
2604        .Default(~0U);
2605
2606      // If some specific iflag is already set, it means that some letter is
2607      // present more than once, this is not acceptable.
2608      if (Flag == ~0U || (IFlags & Flag))
2609        return MatchOperand_NoMatch;
2610
2611      IFlags |= Flag;
2612    }
2613  }
2614
2615  Parser.Lex(); // Eat identifier token.
2616  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
2617  return MatchOperand_Success;
2618}
2619
2620/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
2621ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2622parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2623  SMLoc S = Parser.getTok().getLoc();
2624  const AsmToken &Tok = Parser.getTok();
2625  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2626  StringRef Mask = Tok.getString();
2627
2628  if (isMClass()) {
2629    // See ARMv6-M 10.1.1
2630    unsigned FlagsVal = StringSwitch<unsigned>(Mask)
2631      .Case("apsr", 0)
2632      .Case("iapsr", 1)
2633      .Case("eapsr", 2)
2634      .Case("xpsr", 3)
2635      .Case("ipsr", 5)
2636      .Case("epsr", 6)
2637      .Case("iepsr", 7)
2638      .Case("msp", 8)
2639      .Case("psp", 9)
2640      .Case("primask", 16)
2641      .Case("basepri", 17)
2642      .Case("basepri_max", 18)
2643      .Case("faultmask", 19)
2644      .Case("control", 20)
2645      .Default(~0U);
2646
2647    if (FlagsVal == ~0U)
2648      return MatchOperand_NoMatch;
2649
2650    if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
2651      // basepri, basepri_max and faultmask only valid for V7m.
2652      return MatchOperand_NoMatch;
2653
2654    Parser.Lex(); // Eat identifier token.
2655    Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2656    return MatchOperand_Success;
2657  }
2658
2659  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
2660  size_t Start = 0, Next = Mask.find('_');
2661  StringRef Flags = "";
2662  std::string SpecReg = Mask.slice(Start, Next).lower();
2663  if (Next != StringRef::npos)
2664    Flags = Mask.slice(Next+1, Mask.size());
2665
2666  // FlagsVal contains the complete mask:
2667  // 3-0: Mask
2668  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2669  unsigned FlagsVal = 0;
2670
2671  if (SpecReg == "apsr") {
2672    FlagsVal = StringSwitch<unsigned>(Flags)
2673    .Case("nzcvq",  0x8) // same as CPSR_f
2674    .Case("g",      0x4) // same as CPSR_s
2675    .Case("nzcvqg", 0xc) // same as CPSR_fs
2676    .Default(~0U);
2677
2678    if (FlagsVal == ~0U) {
2679      if (!Flags.empty())
2680        return MatchOperand_NoMatch;
2681      else
2682        FlagsVal = 8; // No flag
2683    }
2684  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
2685    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
2686      Flags = "fc";
2687    for (int i = 0, e = Flags.size(); i != e; ++i) {
2688      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
2689      .Case("c", 1)
2690      .Case("x", 2)
2691      .Case("s", 4)
2692      .Case("f", 8)
2693      .Default(~0U);
2694
2695      // If some specific flag is already set, it means that some letter is
2696      // present more than once, this is not acceptable.
2697      if (FlagsVal == ~0U || (FlagsVal & Flag))
2698        return MatchOperand_NoMatch;
2699      FlagsVal |= Flag;
2700    }
2701  } else // No match for special register.
2702    return MatchOperand_NoMatch;
2703
2704  // Special register without flags is NOT equivalent to "fc" flags.
2705  // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
2706  // two lines would enable gas compatibility at the expense of breaking
2707  // round-tripping.
2708  //
2709  // if (!FlagsVal)
2710  //  FlagsVal = 0x9;
2711
2712  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2713  if (SpecReg == "spsr")
2714    FlagsVal |= 16;
2715
2716  Parser.Lex(); // Eat identifier token.
2717  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2718  return MatchOperand_Success;
2719}
2720
2721ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2722parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
2723            int Low, int High) {
2724  const AsmToken &Tok = Parser.getTok();
2725  if (Tok.isNot(AsmToken::Identifier)) {
2726    Error(Parser.getTok().getLoc(), Op + " operand expected.");
2727    return MatchOperand_ParseFail;
2728  }
2729  StringRef ShiftName = Tok.getString();
2730  std::string LowerOp = Op.lower();
2731  std::string UpperOp = Op.upper();
2732  if (ShiftName != LowerOp && ShiftName != UpperOp) {
2733    Error(Parser.getTok().getLoc(), Op + " operand expected.");
2734    return MatchOperand_ParseFail;
2735  }
2736  Parser.Lex(); // Eat shift type token.
2737
2738  // There must be a '#' and a shift amount.
2739  if (Parser.getTok().isNot(AsmToken::Hash)) {
2740    Error(Parser.getTok().getLoc(), "'#' expected");
2741    return MatchOperand_ParseFail;
2742  }
2743  Parser.Lex(); // Eat hash token.
2744
2745  const MCExpr *ShiftAmount;
2746  SMLoc Loc = Parser.getTok().getLoc();
2747  if (getParser().ParseExpression(ShiftAmount)) {
2748    Error(Loc, "illegal expression");
2749    return MatchOperand_ParseFail;
2750  }
2751  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2752  if (!CE) {
2753    Error(Loc, "constant expression expected");
2754    return MatchOperand_ParseFail;
2755  }
2756  int Val = CE->getValue();
2757  if (Val < Low || Val > High) {
2758    Error(Loc, "immediate value out of range");
2759    return MatchOperand_ParseFail;
2760  }
2761
2762  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
2763
2764  return MatchOperand_Success;
2765}
2766
2767ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2768parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2769  const AsmToken &Tok = Parser.getTok();
2770  SMLoc S = Tok.getLoc();
2771  if (Tok.isNot(AsmToken::Identifier)) {
2772    Error(Tok.getLoc(), "'be' or 'le' operand expected");
2773    return MatchOperand_ParseFail;
2774  }
2775  int Val = StringSwitch<int>(Tok.getString())
2776    .Case("be", 1)
2777    .Case("le", 0)
2778    .Default(-1);
2779  Parser.Lex(); // Eat the token.
2780
2781  if (Val == -1) {
2782    Error(Tok.getLoc(), "'be' or 'le' operand expected");
2783    return MatchOperand_ParseFail;
2784  }
2785  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2786                                                                  getContext()),
2787                                           S, Parser.getTok().getLoc()));
2788  return MatchOperand_Success;
2789}
2790
2791/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2792/// instructions. Legal values are:
2793///     lsl #n  'n' in [0,31]
2794///     asr #n  'n' in [1,32]
2795///             n == 32 encoded as n == 0.
2796ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2797parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2798  const AsmToken &Tok = Parser.getTok();
2799  SMLoc S = Tok.getLoc();
2800  if (Tok.isNot(AsmToken::Identifier)) {
2801    Error(S, "shift operator 'asr' or 'lsl' expected");
2802    return MatchOperand_ParseFail;
2803  }
2804  StringRef ShiftName = Tok.getString();
2805  bool isASR;
2806  if (ShiftName == "lsl" || ShiftName == "LSL")
2807    isASR = false;
2808  else if (ShiftName == "asr" || ShiftName == "ASR")
2809    isASR = true;
2810  else {
2811    Error(S, "shift operator 'asr' or 'lsl' expected");
2812    return MatchOperand_ParseFail;
2813  }
2814  Parser.Lex(); // Eat the operator.
2815
2816  // A '#' and a shift amount.
2817  if (Parser.getTok().isNot(AsmToken::Hash)) {
2818    Error(Parser.getTok().getLoc(), "'#' expected");
2819    return MatchOperand_ParseFail;
2820  }
2821  Parser.Lex(); // Eat hash token.
2822
2823  const MCExpr *ShiftAmount;
2824  SMLoc E = Parser.getTok().getLoc();
2825  if (getParser().ParseExpression(ShiftAmount)) {
2826    Error(E, "malformed shift expression");
2827    return MatchOperand_ParseFail;
2828  }
2829  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2830  if (!CE) {
2831    Error(E, "shift amount must be an immediate");
2832    return MatchOperand_ParseFail;
2833  }
2834
2835  int64_t Val = CE->getValue();
2836  if (isASR) {
2837    // Shift amount must be in [1,32]
2838    if (Val < 1 || Val > 32) {
2839      Error(E, "'asr' shift amount must be in range [1,32]");
2840      return MatchOperand_ParseFail;
2841    }
2842    // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
2843    if (isThumb() && Val == 32) {
2844      Error(E, "'asr #32' shift amount not allowed in Thumb mode");
2845      return MatchOperand_ParseFail;
2846    }
2847    if (Val == 32) Val = 0;
2848  } else {
2849    // Shift amount must be in [1,32]
2850    if (Val < 0 || Val > 31) {
2851      Error(E, "'lsr' shift amount must be in range [0,31]");
2852      return MatchOperand_ParseFail;
2853    }
2854  }
2855
2856  E = Parser.getTok().getLoc();
2857  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2858
2859  return MatchOperand_Success;
2860}
2861
2862/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2863/// of instructions. Legal values are:
2864///     ror #n  'n' in {0, 8, 16, 24}
2865ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2866parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2867  const AsmToken &Tok = Parser.getTok();
2868  SMLoc S = Tok.getLoc();
2869  if (Tok.isNot(AsmToken::Identifier))
2870    return MatchOperand_NoMatch;
2871  StringRef ShiftName = Tok.getString();
2872  if (ShiftName != "ror" && ShiftName != "ROR")
2873    return MatchOperand_NoMatch;
2874  Parser.Lex(); // Eat the operator.
2875
2876  // A '#' and a rotate amount.
2877  if (Parser.getTok().isNot(AsmToken::Hash)) {
2878    Error(Parser.getTok().getLoc(), "'#' expected");
2879    return MatchOperand_ParseFail;
2880  }
2881  Parser.Lex(); // Eat hash token.
2882
2883  const MCExpr *ShiftAmount;
2884  SMLoc E = Parser.getTok().getLoc();
2885  if (getParser().ParseExpression(ShiftAmount)) {
2886    Error(E, "malformed rotate expression");
2887    return MatchOperand_ParseFail;
2888  }
2889  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2890  if (!CE) {
2891    Error(E, "rotate amount must be an immediate");
2892    return MatchOperand_ParseFail;
2893  }
2894
2895  int64_t Val = CE->getValue();
2896  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2897  // normally, zero is represented in asm by omitting the rotate operand
2898  // entirely.
2899  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2900    Error(E, "'ror' rotate amount must be 8, 16, or 24");
2901    return MatchOperand_ParseFail;
2902  }
2903
2904  E = Parser.getTok().getLoc();
2905  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2906
2907  return MatchOperand_Success;
2908}
2909
2910ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2911parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2912  SMLoc S = Parser.getTok().getLoc();
2913  // The bitfield descriptor is really two operands, the LSB and the width.
2914  if (Parser.getTok().isNot(AsmToken::Hash)) {
2915    Error(Parser.getTok().getLoc(), "'#' expected");
2916    return MatchOperand_ParseFail;
2917  }
2918  Parser.Lex(); // Eat hash token.
2919
2920  const MCExpr *LSBExpr;
2921  SMLoc E = Parser.getTok().getLoc();
2922  if (getParser().ParseExpression(LSBExpr)) {
2923    Error(E, "malformed immediate expression");
2924    return MatchOperand_ParseFail;
2925  }
2926  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2927  if (!CE) {
2928    Error(E, "'lsb' operand must be an immediate");
2929    return MatchOperand_ParseFail;
2930  }
2931
2932  int64_t LSB = CE->getValue();
2933  // The LSB must be in the range [0,31]
2934  if (LSB < 0 || LSB > 31) {
2935    Error(E, "'lsb' operand must be in the range [0,31]");
2936    return MatchOperand_ParseFail;
2937  }
2938  E = Parser.getTok().getLoc();
2939
2940  // Expect another immediate operand.
2941  if (Parser.getTok().isNot(AsmToken::Comma)) {
2942    Error(Parser.getTok().getLoc(), "too few operands");
2943    return MatchOperand_ParseFail;
2944  }
2945  Parser.Lex(); // Eat hash token.
2946  if (Parser.getTok().isNot(AsmToken::Hash)) {
2947    Error(Parser.getTok().getLoc(), "'#' expected");
2948    return MatchOperand_ParseFail;
2949  }
2950  Parser.Lex(); // Eat hash token.
2951
2952  const MCExpr *WidthExpr;
2953  if (getParser().ParseExpression(WidthExpr)) {
2954    Error(E, "malformed immediate expression");
2955    return MatchOperand_ParseFail;
2956  }
2957  CE = dyn_cast<MCConstantExpr>(WidthExpr);
2958  if (!CE) {
2959    Error(E, "'width' operand must be an immediate");
2960    return MatchOperand_ParseFail;
2961  }
2962
2963  int64_t Width = CE->getValue();
2964  // The LSB must be in the range [1,32-lsb]
2965  if (Width < 1 || Width > 32 - LSB) {
2966    Error(E, "'width' operand must be in the range [1,32-lsb]");
2967    return MatchOperand_ParseFail;
2968  }
2969  E = Parser.getTok().getLoc();
2970
2971  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2972
2973  return MatchOperand_Success;
2974}
2975
2976ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2977parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2978  // Check for a post-index addressing register operand. Specifically:
2979  // postidx_reg := '+' register {, shift}
2980  //              | '-' register {, shift}
2981  //              | register {, shift}
2982
2983  // This method must return MatchOperand_NoMatch without consuming any tokens
2984  // in the case where there is no match, as other alternatives take other
2985  // parse methods.
2986  AsmToken Tok = Parser.getTok();
2987  SMLoc S = Tok.getLoc();
2988  bool haveEaten = false;
2989  bool isAdd = true;
2990  int Reg = -1;
2991  if (Tok.is(AsmToken::Plus)) {
2992    Parser.Lex(); // Eat the '+' token.
2993    haveEaten = true;
2994  } else if (Tok.is(AsmToken::Minus)) {
2995    Parser.Lex(); // Eat the '-' token.
2996    isAdd = false;
2997    haveEaten = true;
2998  }
2999  if (Parser.getTok().is(AsmToken::Identifier))
3000    Reg = tryParseRegister();
3001  if (Reg == -1) {
3002    if (!haveEaten)
3003      return MatchOperand_NoMatch;
3004    Error(Parser.getTok().getLoc(), "register expected");
3005    return MatchOperand_ParseFail;
3006  }
3007  SMLoc E = Parser.getTok().getLoc();
3008
3009  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3010  unsigned ShiftImm = 0;
3011  if (Parser.getTok().is(AsmToken::Comma)) {
3012    Parser.Lex(); // Eat the ','.
3013    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3014      return MatchOperand_ParseFail;
3015  }
3016
3017  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3018                                                  ShiftImm, S, E));
3019
3020  return MatchOperand_Success;
3021}
3022
3023ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3024parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3025  // Check for a post-index addressing register operand. Specifically:
3026  // am3offset := '+' register
3027  //              | '-' register
3028  //              | register
3029  //              | # imm
3030  //              | # + imm
3031  //              | # - imm
3032
3033  // This method must return MatchOperand_NoMatch without consuming any tokens
3034  // in the case where there is no match, as other alternatives take other
3035  // parse methods.
3036  AsmToken Tok = Parser.getTok();
3037  SMLoc S = Tok.getLoc();
3038
3039  // Do immediates first, as we always parse those if we have a '#'.
3040  if (Parser.getTok().is(AsmToken::Hash)) {
3041    Parser.Lex(); // Eat the '#'.
3042    // Explicitly look for a '-', as we need to encode negative zero
3043    // differently.
3044    bool isNegative = Parser.getTok().is(AsmToken::Minus);
3045    const MCExpr *Offset;
3046    if (getParser().ParseExpression(Offset))
3047      return MatchOperand_ParseFail;
3048    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3049    if (!CE) {
3050      Error(S, "constant expression expected");
3051      return MatchOperand_ParseFail;
3052    }
3053    SMLoc E = Tok.getLoc();
3054    // Negative zero is encoded as the flag value INT32_MIN.
3055    int32_t Val = CE->getValue();
3056    if (isNegative && Val == 0)
3057      Val = INT32_MIN;
3058
3059    Operands.push_back(
3060      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3061
3062    return MatchOperand_Success;
3063  }
3064
3065
3066  bool haveEaten = false;
3067  bool isAdd = true;
3068  int Reg = -1;
3069  if (Tok.is(AsmToken::Plus)) {
3070    Parser.Lex(); // Eat the '+' token.
3071    haveEaten = true;
3072  } else if (Tok.is(AsmToken::Minus)) {
3073    Parser.Lex(); // Eat the '-' token.
3074    isAdd = false;
3075    haveEaten = true;
3076  }
3077  if (Parser.getTok().is(AsmToken::Identifier))
3078    Reg = tryParseRegister();
3079  if (Reg == -1) {
3080    if (!haveEaten)
3081      return MatchOperand_NoMatch;
3082    Error(Parser.getTok().getLoc(), "register expected");
3083    return MatchOperand_ParseFail;
3084  }
3085  SMLoc E = Parser.getTok().getLoc();
3086
3087  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3088                                                  0, S, E));
3089
3090  return MatchOperand_Success;
3091}
3092
3093/// cvtT2LdrdPre - Convert parsed operands to MCInst.
3094/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3095/// when they refer multiple MIOperands inside a single one.
3096bool ARMAsmParser::
3097cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3098             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3099  // Rt, Rt2
3100  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3101  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3102  // Create a writeback register dummy placeholder.
3103  Inst.addOperand(MCOperand::CreateReg(0));
3104  // addr
3105  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3106  // pred
3107  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3108  return true;
3109}
3110
3111/// cvtT2StrdPre - Convert parsed operands to MCInst.
3112/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3113/// when they refer multiple MIOperands inside a single one.
3114bool ARMAsmParser::
3115cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3116             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3117  // Create a writeback register dummy placeholder.
3118  Inst.addOperand(MCOperand::CreateReg(0));
3119  // Rt, Rt2
3120  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3121  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3122  // addr
3123  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3124  // pred
3125  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3126  return true;
3127}
3128
3129/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3130/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3131/// when they refer multiple MIOperands inside a single one.
3132bool ARMAsmParser::
3133cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3134                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3135  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3136
3137  // Create a writeback register dummy placeholder.
3138  Inst.addOperand(MCOperand::CreateImm(0));
3139
3140  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3141  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3142  return true;
3143}
3144
3145/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3146/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3147/// when they refer multiple MIOperands inside a single one.
3148bool ARMAsmParser::
3149cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3150                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3151  // Create a writeback register dummy placeholder.
3152  Inst.addOperand(MCOperand::CreateImm(0));
3153  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3154  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3155  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3156  return true;
3157}
3158
3159/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3160/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3161/// when they refer multiple MIOperands inside a single one.
3162bool ARMAsmParser::
3163cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3164                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3165  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3166
3167  // Create a writeback register dummy placeholder.
3168  Inst.addOperand(MCOperand::CreateImm(0));
3169
3170  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3171  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3172  return true;
3173}
3174
3175/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3176/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3177/// when they refer multiple MIOperands inside a single one.
3178bool ARMAsmParser::
3179cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3180                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3181  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3182
3183  // Create a writeback register dummy placeholder.
3184  Inst.addOperand(MCOperand::CreateImm(0));
3185
3186  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3187  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3188  return true;
3189}
3190
3191
3192/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3193/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3194/// when they refer multiple MIOperands inside a single one.
3195bool ARMAsmParser::
3196cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3197                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3198  // Create a writeback register dummy placeholder.
3199  Inst.addOperand(MCOperand::CreateImm(0));
3200  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3201  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3202  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3203  return true;
3204}
3205
3206/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3207/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3208/// when they refer multiple MIOperands inside a single one.
3209bool ARMAsmParser::
3210cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3211                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3212  // Create a writeback register dummy placeholder.
3213  Inst.addOperand(MCOperand::CreateImm(0));
3214  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3215  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3216  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3217  return true;
3218}
3219
3220/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3221/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3222/// when they refer multiple MIOperands inside a single one.
3223bool ARMAsmParser::
3224cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3225                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3226  // Create a writeback register dummy placeholder.
3227  Inst.addOperand(MCOperand::CreateImm(0));
3228  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3229  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3230  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3231  return true;
3232}
3233
3234/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
3235/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3236/// when they refer multiple MIOperands inside a single one.
3237bool ARMAsmParser::
3238cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3239                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3240  // Rt
3241  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3242  // Create a writeback register dummy placeholder.
3243  Inst.addOperand(MCOperand::CreateImm(0));
3244  // addr
3245  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3246  // offset
3247  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3248  // pred
3249  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3250  return true;
3251}
3252
3253/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
3254/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3255/// when they refer multiple MIOperands inside a single one.
3256bool ARMAsmParser::
3257cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3258                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3259  // Rt
3260  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3261  // Create a writeback register dummy placeholder.
3262  Inst.addOperand(MCOperand::CreateImm(0));
3263  // addr
3264  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3265  // offset
3266  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3267  // pred
3268  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3269  return true;
3270}
3271
3272/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
3273/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3274/// when they refer multiple MIOperands inside a single one.
3275bool ARMAsmParser::
3276cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3277                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3278  // Create a writeback register dummy placeholder.
3279  Inst.addOperand(MCOperand::CreateImm(0));
3280  // Rt
3281  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3282  // addr
3283  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3284  // offset
3285  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3286  // pred
3287  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3288  return true;
3289}
3290
3291/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
3292/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3293/// when they refer multiple MIOperands inside a single one.
3294bool ARMAsmParser::
3295cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3296                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3297  // Create a writeback register dummy placeholder.
3298  Inst.addOperand(MCOperand::CreateImm(0));
3299  // Rt
3300  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3301  // addr
3302  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3303  // offset
3304  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3305  // pred
3306  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3307  return true;
3308}
3309
3310/// cvtLdrdPre - Convert parsed operands to MCInst.
3311/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3312/// when they refer multiple MIOperands inside a single one.
3313bool ARMAsmParser::
3314cvtLdrdPre(MCInst &Inst, unsigned Opcode,
3315           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3316  // Rt, Rt2
3317  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3318  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3319  // Create a writeback register dummy placeholder.
3320  Inst.addOperand(MCOperand::CreateImm(0));
3321  // addr
3322  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3323  // pred
3324  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3325  return true;
3326}
3327
3328/// cvtStrdPre - Convert parsed operands to MCInst.
3329/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3330/// when they refer multiple MIOperands inside a single one.
3331bool ARMAsmParser::
3332cvtStrdPre(MCInst &Inst, unsigned Opcode,
3333           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3334  // Create a writeback register dummy placeholder.
3335  Inst.addOperand(MCOperand::CreateImm(0));
3336  // Rt, Rt2
3337  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3338  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3339  // addr
3340  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3341  // pred
3342  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3343  return true;
3344}
3345
3346/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3347/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3348/// when they refer multiple MIOperands inside a single one.
3349bool ARMAsmParser::
3350cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3351                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3352  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3353  // Create a writeback register dummy placeholder.
3354  Inst.addOperand(MCOperand::CreateImm(0));
3355  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3356  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3357  return true;
3358}
3359
3360/// cvtThumbMultiple- Convert parsed operands to MCInst.
3361/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3362/// when they refer multiple MIOperands inside a single one.
3363bool ARMAsmParser::
3364cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
3365           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3366  // The second source operand must be the same register as the destination
3367  // operand.
3368  if (Operands.size() == 6 &&
3369      (((ARMOperand*)Operands[3])->getReg() !=
3370       ((ARMOperand*)Operands[5])->getReg()) &&
3371      (((ARMOperand*)Operands[3])->getReg() !=
3372       ((ARMOperand*)Operands[4])->getReg())) {
3373    Error(Operands[3]->getStartLoc(),
3374          "destination register must match source register");
3375    return false;
3376  }
3377  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3378  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
3379  // If we have a three-operand form, make sure to set Rn to be the operand
3380  // that isn't the same as Rd.
3381  unsigned RegOp = 4;
3382  if (Operands.size() == 6 &&
3383      ((ARMOperand*)Operands[4])->getReg() ==
3384        ((ARMOperand*)Operands[3])->getReg())
3385    RegOp = 5;
3386  ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
3387  Inst.addOperand(Inst.getOperand(0));
3388  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
3389
3390  return true;
3391}
3392
3393bool ARMAsmParser::
3394cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
3395              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3396  // Vd
3397  ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3398  // Create a writeback register dummy placeholder.
3399  Inst.addOperand(MCOperand::CreateImm(0));
3400  // Vn
3401  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3402  // pred
3403  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3404  return true;
3405}
3406
3407bool ARMAsmParser::
3408cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
3409                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3410  // Vd
3411  ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3412  // Create a writeback register dummy placeholder.
3413  Inst.addOperand(MCOperand::CreateImm(0));
3414  // Vn
3415  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3416  // Vm
3417  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3418  // pred
3419  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3420  return true;
3421}
3422
3423bool ARMAsmParser::
3424cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
3425              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3426  // Create a writeback register dummy placeholder.
3427  Inst.addOperand(MCOperand::CreateImm(0));
3428  // Vn
3429  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3430  // Vt
3431  ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3432  // pred
3433  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3434  return true;
3435}
3436
3437bool ARMAsmParser::
3438cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
3439                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3440  // Create a writeback register dummy placeholder.
3441  Inst.addOperand(MCOperand::CreateImm(0));
3442  // Vn
3443  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3444  // Vm
3445  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3446  // Vt
3447  ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3448  // pred
3449  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3450  return true;
3451}
3452
3453/// Parse an ARM memory expression, return false if successful else return true
3454/// or an error.  The first token must be a '[' when called.
3455bool ARMAsmParser::
3456parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3457  SMLoc S, E;
3458  assert(Parser.getTok().is(AsmToken::LBrac) &&
3459         "Token is not a Left Bracket");
3460  S = Parser.getTok().getLoc();
3461  Parser.Lex(); // Eat left bracket token.
3462
3463  const AsmToken &BaseRegTok = Parser.getTok();
3464  int BaseRegNum = tryParseRegister();
3465  if (BaseRegNum == -1)
3466    return Error(BaseRegTok.getLoc(), "register expected");
3467
3468  // The next token must either be a comma or a closing bracket.
3469  const AsmToken &Tok = Parser.getTok();
3470  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
3471    return Error(Tok.getLoc(), "malformed memory operand");
3472
3473  if (Tok.is(AsmToken::RBrac)) {
3474    E = Tok.getLoc();
3475    Parser.Lex(); // Eat right bracket token.
3476
3477    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
3478                                             0, 0, false, S, E));
3479
3480    // If there's a pre-indexing writeback marker, '!', just add it as a token
3481    // operand. It's rather odd, but syntactically valid.
3482    if (Parser.getTok().is(AsmToken::Exclaim)) {
3483      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3484      Parser.Lex(); // Eat the '!'.
3485    }
3486
3487    return false;
3488  }
3489
3490  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
3491  Parser.Lex(); // Eat the comma.
3492
3493  // If we have a ':', it's an alignment specifier.
3494  if (Parser.getTok().is(AsmToken::Colon)) {
3495    Parser.Lex(); // Eat the ':'.
3496    E = Parser.getTok().getLoc();
3497
3498    const MCExpr *Expr;
3499    if (getParser().ParseExpression(Expr))
3500     return true;
3501
3502    // The expression has to be a constant. Memory references with relocations
3503    // don't come through here, as they use the <label> forms of the relevant
3504    // instructions.
3505    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3506    if (!CE)
3507      return Error (E, "constant expression expected");
3508
3509    unsigned Align = 0;
3510    switch (CE->getValue()) {
3511    default:
3512      return Error(E, "alignment specifier must be 64, 128, or 256 bits");
3513    case 64:  Align = 8; break;
3514    case 128: Align = 16; break;
3515    case 256: Align = 32; break;
3516    }
3517
3518    // Now we should have the closing ']'
3519    E = Parser.getTok().getLoc();
3520    if (Parser.getTok().isNot(AsmToken::RBrac))
3521      return Error(E, "']' expected");
3522    Parser.Lex(); // Eat right bracket token.
3523
3524    // Don't worry about range checking the value here. That's handled by
3525    // the is*() predicates.
3526    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
3527                                             ARM_AM::no_shift, 0, Align,
3528                                             false, S, E));
3529
3530    // If there's a pre-indexing writeback marker, '!', just add it as a token
3531    // operand.
3532    if (Parser.getTok().is(AsmToken::Exclaim)) {
3533      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3534      Parser.Lex(); // Eat the '!'.
3535    }
3536
3537    return false;
3538  }
3539
3540  // If we have a '#', it's an immediate offset, else assume it's a register
3541  // offset.
3542  if (Parser.getTok().is(AsmToken::Hash)) {
3543    Parser.Lex(); // Eat the '#'.
3544    E = Parser.getTok().getLoc();
3545
3546    bool isNegative = getParser().getTok().is(AsmToken::Minus);
3547    const MCExpr *Offset;
3548    if (getParser().ParseExpression(Offset))
3549     return true;
3550
3551    // The expression has to be a constant. Memory references with relocations
3552    // don't come through here, as they use the <label> forms of the relevant
3553    // instructions.
3554    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3555    if (!CE)
3556      return Error (E, "constant expression expected");
3557
3558    // If the constant was #-0, represent it as INT32_MIN.
3559    int32_t Val = CE->getValue();
3560    if (isNegative && Val == 0)
3561      CE = MCConstantExpr::Create(INT32_MIN, getContext());
3562
3563    // Now we should have the closing ']'
3564    E = Parser.getTok().getLoc();
3565    if (Parser.getTok().isNot(AsmToken::RBrac))
3566      return Error(E, "']' expected");
3567    Parser.Lex(); // Eat right bracket token.
3568
3569    // Don't worry about range checking the value here. That's handled by
3570    // the is*() predicates.
3571    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
3572                                             ARM_AM::no_shift, 0, 0,
3573                                             false, S, E));
3574
3575    // If there's a pre-indexing writeback marker, '!', just add it as a token
3576    // operand.
3577    if (Parser.getTok().is(AsmToken::Exclaim)) {
3578      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3579      Parser.Lex(); // Eat the '!'.
3580    }
3581
3582    return false;
3583  }
3584
3585  // The register offset is optionally preceded by a '+' or '-'
3586  bool isNegative = false;
3587  if (Parser.getTok().is(AsmToken::Minus)) {
3588    isNegative = true;
3589    Parser.Lex(); // Eat the '-'.
3590  } else if (Parser.getTok().is(AsmToken::Plus)) {
3591    // Nothing to do.
3592    Parser.Lex(); // Eat the '+'.
3593  }
3594
3595  E = Parser.getTok().getLoc();
3596  int OffsetRegNum = tryParseRegister();
3597  if (OffsetRegNum == -1)
3598    return Error(E, "register expected");
3599
3600  // If there's a shift operator, handle it.
3601  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
3602  unsigned ShiftImm = 0;
3603  if (Parser.getTok().is(AsmToken::Comma)) {
3604    Parser.Lex(); // Eat the ','.
3605    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
3606      return true;
3607  }
3608
3609  // Now we should have the closing ']'
3610  E = Parser.getTok().getLoc();
3611  if (Parser.getTok().isNot(AsmToken::RBrac))
3612    return Error(E, "']' expected");
3613  Parser.Lex(); // Eat right bracket token.
3614
3615  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
3616                                           ShiftType, ShiftImm, 0, isNegative,
3617                                           S, E));
3618
3619  // If there's a pre-indexing writeback marker, '!', just add it as a token
3620  // operand.
3621  if (Parser.getTok().is(AsmToken::Exclaim)) {
3622    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3623    Parser.Lex(); // Eat the '!'.
3624  }
3625
3626  return false;
3627}
3628
3629/// parseMemRegOffsetShift - one of these two:
3630///   ( lsl | lsr | asr | ror ) , # shift_amount
3631///   rrx
3632/// return true if it parses a shift otherwise it returns false.
3633bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
3634                                          unsigned &Amount) {
3635  SMLoc Loc = Parser.getTok().getLoc();
3636  const AsmToken &Tok = Parser.getTok();
3637  if (Tok.isNot(AsmToken::Identifier))
3638    return true;
3639  StringRef ShiftName = Tok.getString();
3640  if (ShiftName == "lsl" || ShiftName == "LSL")
3641    St = ARM_AM::lsl;
3642  else if (ShiftName == "lsr" || ShiftName == "LSR")
3643    St = ARM_AM::lsr;
3644  else if (ShiftName == "asr" || ShiftName == "ASR")
3645    St = ARM_AM::asr;
3646  else if (ShiftName == "ror" || ShiftName == "ROR")
3647    St = ARM_AM::ror;
3648  else if (ShiftName == "rrx" || ShiftName == "RRX")
3649    St = ARM_AM::rrx;
3650  else
3651    return Error(Loc, "illegal shift operator");
3652  Parser.Lex(); // Eat shift type token.
3653
3654  // rrx stands alone.
3655  Amount = 0;
3656  if (St != ARM_AM::rrx) {
3657    Loc = Parser.getTok().getLoc();
3658    // A '#' and a shift amount.
3659    const AsmToken &HashTok = Parser.getTok();
3660    if (HashTok.isNot(AsmToken::Hash))
3661      return Error(HashTok.getLoc(), "'#' expected");
3662    Parser.Lex(); // Eat hash token.
3663
3664    const MCExpr *Expr;
3665    if (getParser().ParseExpression(Expr))
3666      return true;
3667    // Range check the immediate.
3668    // lsl, ror: 0 <= imm <= 31
3669    // lsr, asr: 0 <= imm <= 32
3670    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3671    if (!CE)
3672      return Error(Loc, "shift amount must be an immediate");
3673    int64_t Imm = CE->getValue();
3674    if (Imm < 0 ||
3675        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
3676        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
3677      return Error(Loc, "immediate shift value out of range");
3678    Amount = Imm;
3679  }
3680
3681  return false;
3682}
3683
3684/// parseFPImm - A floating point immediate expression operand.
3685ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3686parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3687  SMLoc S = Parser.getTok().getLoc();
3688
3689  if (Parser.getTok().isNot(AsmToken::Hash))
3690    return MatchOperand_NoMatch;
3691
3692  // Disambiguate the VMOV forms that can accept an FP immediate.
3693  // vmov.f32 <sreg>, #imm
3694  // vmov.f64 <dreg>, #imm
3695  // vmov.f32 <dreg>, #imm  @ vector f32x2
3696  // vmov.f32 <qreg>, #imm  @ vector f32x4
3697  //
3698  // There are also the NEON VMOV instructions which expect an
3699  // integer constant. Make sure we don't try to parse an FPImm
3700  // for these:
3701  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
3702  ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
3703  if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
3704                           TyOp->getToken() != ".f64"))
3705    return MatchOperand_NoMatch;
3706
3707  Parser.Lex(); // Eat the '#'.
3708
3709  // Handle negation, as that still comes through as a separate token.
3710  bool isNegative = false;
3711  if (Parser.getTok().is(AsmToken::Minus)) {
3712    isNegative = true;
3713    Parser.Lex();
3714  }
3715  const AsmToken &Tok = Parser.getTok();
3716  if (Tok.is(AsmToken::Real)) {
3717    APFloat RealVal(APFloat::IEEEdouble, Tok.getString());
3718    uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
3719    // If we had a '-' in front, toggle the sign bit.
3720    IntVal ^= (uint64_t)isNegative << 63;
3721    int Val = ARM_AM::getFP64Imm(APInt(64, IntVal));
3722    Parser.Lex(); // Eat the token.
3723    if (Val == -1) {
3724      TokError("floating point value out of range");
3725      return MatchOperand_ParseFail;
3726    }
3727    Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
3728    return MatchOperand_Success;
3729  }
3730  if (Tok.is(AsmToken::Integer)) {
3731    int64_t Val = Tok.getIntVal();
3732    Parser.Lex(); // Eat the token.
3733    if (Val > 255 || Val < 0) {
3734      TokError("encoded floating point value out of range");
3735      return MatchOperand_ParseFail;
3736    }
3737    Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
3738    return MatchOperand_Success;
3739  }
3740
3741  TokError("invalid floating point immediate");
3742  return MatchOperand_ParseFail;
3743}
3744/// Parse a arm instruction operand.  For now this parses the operand regardless
3745/// of the mnemonic.
3746bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3747                                StringRef Mnemonic) {
3748  SMLoc S, E;
3749
3750  // Check if the current operand has a custom associated parser, if so, try to
3751  // custom parse the operand, or fallback to the general approach.
3752  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
3753  if (ResTy == MatchOperand_Success)
3754    return false;
3755  // If there wasn't a custom match, try the generic matcher below. Otherwise,
3756  // there was a match, but an error occurred, in which case, just return that
3757  // the operand parsing failed.
3758  if (ResTy == MatchOperand_ParseFail)
3759    return true;
3760
3761  switch (getLexer().getKind()) {
3762  default:
3763    Error(Parser.getTok().getLoc(), "unexpected token in operand");
3764    return true;
3765  case AsmToken::Identifier: {
3766    // If this is VMRS, check for the apsr_nzcv operand.
3767    if (!tryParseRegisterWithWriteBack(Operands))
3768      return false;
3769    int Res = tryParseShiftRegister(Operands);
3770    if (Res == 0) // success
3771      return false;
3772    else if (Res == -1) // irrecoverable error
3773      return true;
3774    if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") {
3775      S = Parser.getTok().getLoc();
3776      Parser.Lex();
3777      Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S));
3778      return false;
3779    }
3780
3781    // Fall though for the Identifier case that is not a register or a
3782    // special name.
3783  }
3784  case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
3785  case AsmToken::Integer: // things like 1f and 2b as a branch targets
3786  case AsmToken::String:  // quoted label names.
3787  case AsmToken::Dot: {   // . as a branch target
3788    // This was not a register so parse other operands that start with an
3789    // identifier (like labels) as expressions and create them as immediates.
3790    const MCExpr *IdVal;
3791    S = Parser.getTok().getLoc();
3792    if (getParser().ParseExpression(IdVal))
3793      return true;
3794    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3795    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
3796    return false;
3797  }
3798  case AsmToken::LBrac:
3799    return parseMemory(Operands);
3800  case AsmToken::LCurly:
3801    return parseRegisterList(Operands);
3802  case AsmToken::Hash: {
3803    // #42 -> immediate.
3804    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
3805    S = Parser.getTok().getLoc();
3806    Parser.Lex();
3807    bool isNegative = Parser.getTok().is(AsmToken::Minus);
3808    const MCExpr *ImmVal;
3809    if (getParser().ParseExpression(ImmVal))
3810      return true;
3811    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
3812    if (CE) {
3813      int32_t Val = CE->getValue();
3814      if (isNegative && Val == 0)
3815        ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
3816    }
3817    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3818    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
3819    return false;
3820  }
3821  case AsmToken::Colon: {
3822    // ":lower16:" and ":upper16:" expression prefixes
3823    // FIXME: Check it's an expression prefix,
3824    // e.g. (FOO - :lower16:BAR) isn't legal.
3825    ARMMCExpr::VariantKind RefKind;
3826    if (parsePrefix(RefKind))
3827      return true;
3828
3829    const MCExpr *SubExprVal;
3830    if (getParser().ParseExpression(SubExprVal))
3831      return true;
3832
3833    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
3834                                                   getContext());
3835    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3836    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
3837    return false;
3838  }
3839  }
3840}
3841
3842// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
3843//  :lower16: and :upper16:.
3844bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
3845  RefKind = ARMMCExpr::VK_ARM_None;
3846
3847  // :lower16: and :upper16: modifiers
3848  assert(getLexer().is(AsmToken::Colon) && "expected a :");
3849  Parser.Lex(); // Eat ':'
3850
3851  if (getLexer().isNot(AsmToken::Identifier)) {
3852    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
3853    return true;
3854  }
3855
3856  StringRef IDVal = Parser.getTok().getIdentifier();
3857  if (IDVal == "lower16") {
3858    RefKind = ARMMCExpr::VK_ARM_LO16;
3859  } else if (IDVal == "upper16") {
3860    RefKind = ARMMCExpr::VK_ARM_HI16;
3861  } else {
3862    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
3863    return true;
3864  }
3865  Parser.Lex();
3866
3867  if (getLexer().isNot(AsmToken::Colon)) {
3868    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
3869    return true;
3870  }
3871  Parser.Lex(); // Eat the last ':'
3872  return false;
3873}
3874
3875/// \brief Given a mnemonic, split out possible predication code and carry
3876/// setting letters to form a canonical mnemonic and flags.
3877//
3878// FIXME: Would be nice to autogen this.
3879// FIXME: This is a bit of a maze of special cases.
3880StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
3881                                      unsigned &PredicationCode,
3882                                      bool &CarrySetting,
3883                                      unsigned &ProcessorIMod,
3884                                      StringRef &ITMask) {
3885  PredicationCode = ARMCC::AL;
3886  CarrySetting = false;
3887  ProcessorIMod = 0;
3888
3889  // Ignore some mnemonics we know aren't predicated forms.
3890  //
3891  // FIXME: Would be nice to autogen this.
3892  if ((Mnemonic == "movs" && isThumb()) ||
3893      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
3894      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
3895      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
3896      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
3897      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
3898      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
3899      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
3900    return Mnemonic;
3901
3902  // First, split out any predication code. Ignore mnemonics we know aren't
3903  // predicated but do have a carry-set and so weren't caught above.
3904  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
3905      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
3906      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
3907      Mnemonic != "sbcs" && Mnemonic != "rscs") {
3908    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
3909      .Case("eq", ARMCC::EQ)
3910      .Case("ne", ARMCC::NE)
3911      .Case("hs", ARMCC::HS)
3912      .Case("cs", ARMCC::HS)
3913      .Case("lo", ARMCC::LO)
3914      .Case("cc", ARMCC::LO)
3915      .Case("mi", ARMCC::MI)
3916      .Case("pl", ARMCC::PL)
3917      .Case("vs", ARMCC::VS)
3918      .Case("vc", ARMCC::VC)
3919      .Case("hi", ARMCC::HI)
3920      .Case("ls", ARMCC::LS)
3921      .Case("ge", ARMCC::GE)
3922      .Case("lt", ARMCC::LT)
3923      .Case("gt", ARMCC::GT)
3924      .Case("le", ARMCC::LE)
3925      .Case("al", ARMCC::AL)
3926      .Default(~0U);
3927    if (CC != ~0U) {
3928      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
3929      PredicationCode = CC;
3930    }
3931  }
3932
3933  // Next, determine if we have a carry setting bit. We explicitly ignore all
3934  // the instructions we know end in 's'.
3935  if (Mnemonic.endswith("s") &&
3936      !(Mnemonic == "cps" || Mnemonic == "mls" ||
3937        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
3938        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
3939        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
3940        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
3941        (Mnemonic == "movs" && isThumb()))) {
3942    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
3943    CarrySetting = true;
3944  }
3945
3946  // The "cps" instruction can have a interrupt mode operand which is glued into
3947  // the mnemonic. Check if this is the case, split it and parse the imod op
3948  if (Mnemonic.startswith("cps")) {
3949    // Split out any imod code.
3950    unsigned IMod =
3951      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
3952      .Case("ie", ARM_PROC::IE)
3953      .Case("id", ARM_PROC::ID)
3954      .Default(~0U);
3955    if (IMod != ~0U) {
3956      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
3957      ProcessorIMod = IMod;
3958    }
3959  }
3960
3961  // The "it" instruction has the condition mask on the end of the mnemonic.
3962  if (Mnemonic.startswith("it")) {
3963    ITMask = Mnemonic.slice(2, Mnemonic.size());
3964    Mnemonic = Mnemonic.slice(0, 2);
3965  }
3966
3967  return Mnemonic;
3968}
3969
3970/// \brief Given a canonical mnemonic, determine if the instruction ever allows
3971/// inclusion of carry set or predication code operands.
3972//
3973// FIXME: It would be nice to autogen this.
3974void ARMAsmParser::
3975getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
3976                      bool &CanAcceptPredicationCode) {
3977  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
3978      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
3979      Mnemonic == "add" || Mnemonic == "adc" ||
3980      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
3981      Mnemonic == "orr" || Mnemonic == "mvn" ||
3982      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
3983      Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
3984      (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
3985                      Mnemonic == "mla" || Mnemonic == "smlal" ||
3986                      Mnemonic == "umlal" || Mnemonic == "umull"))) {
3987    CanAcceptCarrySet = true;
3988  } else
3989    CanAcceptCarrySet = false;
3990
3991  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
3992      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
3993      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
3994      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
3995      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
3996      (Mnemonic == "clrex" && !isThumb()) ||
3997      (Mnemonic == "nop" && isThumbOne()) ||
3998      ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
3999        Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4000        Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4001      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4002       !isThumb()) ||
4003      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4004    CanAcceptPredicationCode = false;
4005  } else
4006    CanAcceptPredicationCode = true;
4007
4008  if (isThumb()) {
4009    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4010        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4011      CanAcceptPredicationCode = false;
4012  }
4013}
4014
4015bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4016                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4017  // FIXME: This is all horribly hacky. We really need a better way to deal
4018  // with optional operands like this in the matcher table.
4019
4020  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4021  // another does not. Specifically, the MOVW instruction does not. So we
4022  // special case it here and remove the defaulted (non-setting) cc_out
4023  // operand if that's the instruction we're trying to match.
4024  //
4025  // We do this as post-processing of the explicit operands rather than just
4026  // conditionally adding the cc_out in the first place because we need
4027  // to check the type of the parsed immediate operand.
4028  if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4029      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4030      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4031      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4032    return true;
4033
4034  // Register-register 'add' for thumb does not have a cc_out operand
4035  // when there are only two register operands.
4036  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4037      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4038      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4039      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4040    return true;
4041  // Register-register 'add' for thumb does not have a cc_out operand
4042  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4043  // have to check the immediate range here since Thumb2 has a variant
4044  // that can handle a different range and has a cc_out operand.
4045  if (((isThumb() && Mnemonic == "add") ||
4046       (isThumbTwo() && Mnemonic == "sub")) &&
4047      Operands.size() == 6 &&
4048      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4049      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4050      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4051      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4052      (static_cast<ARMOperand*>(Operands[5])->isReg() ||
4053       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4054    return true;
4055  // For Thumb2, add/sub immediate does not have a cc_out operand for the
4056  // imm0_4095 variant. That's the least-preferred variant when
4057  // selecting via the generic "add" mnemonic, so to know that we
4058  // should remove the cc_out operand, we have to explicitly check that
4059  // it's not one of the other variants. Ugh.
4060  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4061      Operands.size() == 6 &&
4062      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4063      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4064      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4065    // Nest conditions rather than one big 'if' statement for readability.
4066    //
4067    // If either register is a high reg, it's either one of the SP
4068    // variants (handled above) or a 32-bit encoding, so we just
4069    // check against T3.
4070    if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4071         !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4072        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4073      return false;
4074    // If both registers are low, we're in an IT block, and the immediate is
4075    // in range, we should use encoding T1 instead, which has a cc_out.
4076    if (inITBlock() &&
4077        isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4078        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4079        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4080      return false;
4081
4082    // Otherwise, we use encoding T4, which does not have a cc_out
4083    // operand.
4084    return true;
4085  }
4086
4087  // The thumb2 multiply instruction doesn't have a CCOut register, so
4088  // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4089  // use the 16-bit encoding or not.
4090  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4091      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4092      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4093      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4094      static_cast<ARMOperand*>(Operands[5])->isReg() &&
4095      // If the registers aren't low regs, the destination reg isn't the
4096      // same as one of the source regs, or the cc_out operand is zero
4097      // outside of an IT block, we have to use the 32-bit encoding, so
4098      // remove the cc_out operand.
4099      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4100       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4101       !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4102       !inITBlock() ||
4103       (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4104        static_cast<ARMOperand*>(Operands[5])->getReg() &&
4105        static_cast<ARMOperand*>(Operands[3])->getReg() !=
4106        static_cast<ARMOperand*>(Operands[4])->getReg())))
4107    return true;
4108
4109  // Also check the 'mul' syntax variant that doesn't specify an explicit
4110  // destination register.
4111  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4112      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4113      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4114      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4115      // If the registers aren't low regs  or the cc_out operand is zero
4116      // outside of an IT block, we have to use the 32-bit encoding, so
4117      // remove the cc_out operand.
4118      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4119       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4120       !inITBlock()))
4121    return true;
4122
4123
4124
4125  // Register-register 'add/sub' for thumb does not have a cc_out operand
4126  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4127  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4128  // right, this will result in better diagnostics (which operand is off)
4129  // anyway.
4130  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4131      (Operands.size() == 5 || Operands.size() == 6) &&
4132      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4133      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4134      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4135    return true;
4136
4137  return false;
4138}
4139
4140static bool isDataTypeToken(StringRef Tok) {
4141  return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4142    Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4143    Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4144    Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4145    Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4146    Tok == ".f" || Tok == ".d";
4147}
4148
4149// FIXME: This bit should probably be handled via an explicit match class
4150// in the .td files that matches the suffix instead of having it be
4151// a literal string token the way it is now.
4152static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4153  return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4154}
4155
4156/// Parse an arm instruction mnemonic followed by its operands.
4157bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4158                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4159  // Create the leading tokens for the mnemonic, split by '.' characters.
4160  size_t Start = 0, Next = Name.find('.');
4161  StringRef Mnemonic = Name.slice(Start, Next);
4162
4163  // Split out the predication code and carry setting flag from the mnemonic.
4164  unsigned PredicationCode;
4165  unsigned ProcessorIMod;
4166  bool CarrySetting;
4167  StringRef ITMask;
4168  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
4169                           ProcessorIMod, ITMask);
4170
4171  // In Thumb1, only the branch (B) instruction can be predicated.
4172  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
4173    Parser.EatToEndOfStatement();
4174    return Error(NameLoc, "conditional execution not supported in Thumb1");
4175  }
4176
4177  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
4178
4179  // Handle the IT instruction ITMask. Convert it to a bitmask. This
4180  // is the mask as it will be for the IT encoding if the conditional
4181  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
4182  // where the conditional bit0 is zero, the instruction post-processing
4183  // will adjust the mask accordingly.
4184  if (Mnemonic == "it") {
4185    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
4186    if (ITMask.size() > 3) {
4187      Parser.EatToEndOfStatement();
4188      return Error(Loc, "too many conditions on IT instruction");
4189    }
4190    unsigned Mask = 8;
4191    for (unsigned i = ITMask.size(); i != 0; --i) {
4192      char pos = ITMask[i - 1];
4193      if (pos != 't' && pos != 'e') {
4194        Parser.EatToEndOfStatement();
4195        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
4196      }
4197      Mask >>= 1;
4198      if (ITMask[i - 1] == 't')
4199        Mask |= 8;
4200    }
4201    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
4202  }
4203
4204  // FIXME: This is all a pretty gross hack. We should automatically handle
4205  // optional operands like this via tblgen.
4206
4207  // Next, add the CCOut and ConditionCode operands, if needed.
4208  //
4209  // For mnemonics which can ever incorporate a carry setting bit or predication
4210  // code, our matching model involves us always generating CCOut and
4211  // ConditionCode operands to match the mnemonic "as written" and then we let
4212  // the matcher deal with finding the right instruction or generating an
4213  // appropriate error.
4214  bool CanAcceptCarrySet, CanAcceptPredicationCode;
4215  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
4216
4217  // If we had a carry-set on an instruction that can't do that, issue an
4218  // error.
4219  if (!CanAcceptCarrySet && CarrySetting) {
4220    Parser.EatToEndOfStatement();
4221    return Error(NameLoc, "instruction '" + Mnemonic +
4222                 "' can not set flags, but 's' suffix specified");
4223  }
4224  // If we had a predication code on an instruction that can't do that, issue an
4225  // error.
4226  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
4227    Parser.EatToEndOfStatement();
4228    return Error(NameLoc, "instruction '" + Mnemonic +
4229                 "' is not predicable, but condition code specified");
4230  }
4231
4232  // Add the carry setting operand, if necessary.
4233  if (CanAcceptCarrySet) {
4234    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
4235    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
4236                                               Loc));
4237  }
4238
4239  // Add the predication code operand, if necessary.
4240  if (CanAcceptPredicationCode) {
4241    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
4242                                      CarrySetting);
4243    Operands.push_back(ARMOperand::CreateCondCode(
4244                         ARMCC::CondCodes(PredicationCode), Loc));
4245  }
4246
4247  // Add the processor imod operand, if necessary.
4248  if (ProcessorIMod) {
4249    Operands.push_back(ARMOperand::CreateImm(
4250          MCConstantExpr::Create(ProcessorIMod, getContext()),
4251                                 NameLoc, NameLoc));
4252  }
4253
4254  // Add the remaining tokens in the mnemonic.
4255  while (Next != StringRef::npos) {
4256    Start = Next;
4257    Next = Name.find('.', Start + 1);
4258    StringRef ExtraToken = Name.slice(Start, Next);
4259
4260    // Some NEON instructions have an optional datatype suffix that is
4261    // completely ignored. Check for that.
4262    if (isDataTypeToken(ExtraToken) &&
4263        doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
4264      continue;
4265
4266    if (ExtraToken != ".n") {
4267      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
4268      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
4269    }
4270  }
4271
4272  // Read the remaining operands.
4273  if (getLexer().isNot(AsmToken::EndOfStatement)) {
4274    // Read the first operand.
4275    if (parseOperand(Operands, Mnemonic)) {
4276      Parser.EatToEndOfStatement();
4277      return true;
4278    }
4279
4280    while (getLexer().is(AsmToken::Comma)) {
4281      Parser.Lex();  // Eat the comma.
4282
4283      // Parse and remember the operand.
4284      if (parseOperand(Operands, Mnemonic)) {
4285        Parser.EatToEndOfStatement();
4286        return true;
4287      }
4288    }
4289  }
4290
4291  if (getLexer().isNot(AsmToken::EndOfStatement)) {
4292    SMLoc Loc = getLexer().getLoc();
4293    Parser.EatToEndOfStatement();
4294    return Error(Loc, "unexpected token in argument list");
4295  }
4296
4297  Parser.Lex(); // Consume the EndOfStatement
4298
4299  // Some instructions, mostly Thumb, have forms for the same mnemonic that
4300  // do and don't have a cc_out optional-def operand. With some spot-checks
4301  // of the operand list, we can figure out which variant we're trying to
4302  // parse and adjust accordingly before actually matching. We shouldn't ever
4303  // try to remove a cc_out operand that was explicitly set on the the
4304  // mnemonic, of course (CarrySetting == true). Reason number #317 the
4305  // table driven matcher doesn't fit well with the ARM instruction set.
4306  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
4307    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4308    Operands.erase(Operands.begin() + 1);
4309    delete Op;
4310  }
4311
4312  // ARM mode 'blx' need special handling, as the register operand version
4313  // is predicable, but the label operand version is not. So, we can't rely
4314  // on the Mnemonic based checking to correctly figure out when to put
4315  // a k_CondCode operand in the list. If we're trying to match the label
4316  // version, remove the k_CondCode operand here.
4317  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
4318      static_cast<ARMOperand*>(Operands[2])->isImm()) {
4319    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4320    Operands.erase(Operands.begin() + 1);
4321    delete Op;
4322  }
4323
4324  // The vector-compare-to-zero instructions have a literal token "#0" at
4325  // the end that comes to here as an immediate operand. Convert it to a
4326  // token to play nicely with the matcher.
4327  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
4328      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
4329      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4330    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4331    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4332    if (CE && CE->getValue() == 0) {
4333      Operands.erase(Operands.begin() + 5);
4334      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4335      delete Op;
4336    }
4337  }
4338  // VCMP{E} does the same thing, but with a different operand count.
4339  if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
4340      static_cast<ARMOperand*>(Operands[4])->isImm()) {
4341    ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
4342    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4343    if (CE && CE->getValue() == 0) {
4344      Operands.erase(Operands.begin() + 4);
4345      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4346      delete Op;
4347    }
4348  }
4349  // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
4350  // end. Convert it to a token here.
4351  if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
4352      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4353    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4354    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4355    if (CE && CE->getValue() == 0) {
4356      Operands.erase(Operands.begin() + 5);
4357      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4358      delete Op;
4359    }
4360  }
4361
4362  return false;
4363}
4364
4365// Validate context-sensitive operand constraints.
4366
4367// return 'true' if register list contains non-low GPR registers,
4368// 'false' otherwise. If Reg is in the register list or is HiReg, set
4369// 'containsReg' to true.
4370static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
4371                                 unsigned HiReg, bool &containsReg) {
4372  containsReg = false;
4373  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4374    unsigned OpReg = Inst.getOperand(i).getReg();
4375    if (OpReg == Reg)
4376      containsReg = true;
4377    // Anything other than a low register isn't legal here.
4378    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
4379      return true;
4380  }
4381  return false;
4382}
4383
4384// Check if the specified regisgter is in the register list of the inst,
4385// starting at the indicated operand number.
4386static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
4387  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4388    unsigned OpReg = Inst.getOperand(i).getReg();
4389    if (OpReg == Reg)
4390      return true;
4391  }
4392  return false;
4393}
4394
4395// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
4396// the ARMInsts array) instead. Getting that here requires awkward
4397// API changes, though. Better way?
4398namespace llvm {
4399extern const MCInstrDesc ARMInsts[];
4400}
4401static const MCInstrDesc &getInstDesc(unsigned Opcode) {
4402  return ARMInsts[Opcode];
4403}
4404
4405// FIXME: We would really like to be able to tablegen'erate this.
4406bool ARMAsmParser::
4407validateInstruction(MCInst &Inst,
4408                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4409  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
4410  SMLoc Loc = Operands[0]->getStartLoc();
4411  // Check the IT block state first.
4412  // NOTE: In Thumb mode, the BKPT instruction has the interesting property of
4413  // being allowed in IT blocks, but not being predicable.  It just always
4414  // executes.
4415  if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
4416    unsigned bit = 1;
4417    if (ITState.FirstCond)
4418      ITState.FirstCond = false;
4419    else
4420      bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
4421    // The instruction must be predicable.
4422    if (!MCID.isPredicable())
4423      return Error(Loc, "instructions in IT block must be predicable");
4424    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
4425    unsigned ITCond = bit ? ITState.Cond :
4426      ARMCC::getOppositeCondition(ITState.Cond);
4427    if (Cond != ITCond) {
4428      // Find the condition code Operand to get its SMLoc information.
4429      SMLoc CondLoc;
4430      for (unsigned i = 1; i < Operands.size(); ++i)
4431        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
4432          CondLoc = Operands[i]->getStartLoc();
4433      return Error(CondLoc, "incorrect condition in IT block; got '" +
4434                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
4435                   "', but expected '" +
4436                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
4437    }
4438  // Check for non-'al' condition codes outside of the IT block.
4439  } else if (isThumbTwo() && MCID.isPredicable() &&
4440             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
4441             ARMCC::AL && Inst.getOpcode() != ARM::tB &&
4442             Inst.getOpcode() != ARM::t2B)
4443    return Error(Loc, "predicated instructions must be in IT block");
4444
4445  switch (Inst.getOpcode()) {
4446  case ARM::LDRD:
4447  case ARM::LDRD_PRE:
4448  case ARM::LDRD_POST:
4449  case ARM::LDREXD: {
4450    // Rt2 must be Rt + 1.
4451    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4452    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4453    if (Rt2 != Rt + 1)
4454      return Error(Operands[3]->getStartLoc(),
4455                   "destination operands must be sequential");
4456    return false;
4457  }
4458  case ARM::STRD: {
4459    // Rt2 must be Rt + 1.
4460    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4461    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4462    if (Rt2 != Rt + 1)
4463      return Error(Operands[3]->getStartLoc(),
4464                   "source operands must be sequential");
4465    return false;
4466  }
4467  case ARM::STRD_PRE:
4468  case ARM::STRD_POST:
4469  case ARM::STREXD: {
4470    // Rt2 must be Rt + 1.
4471    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4472    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
4473    if (Rt2 != Rt + 1)
4474      return Error(Operands[3]->getStartLoc(),
4475                   "source operands must be sequential");
4476    return false;
4477  }
4478  case ARM::SBFX:
4479  case ARM::UBFX: {
4480    // width must be in range [1, 32-lsb]
4481    unsigned lsb = Inst.getOperand(2).getImm();
4482    unsigned widthm1 = Inst.getOperand(3).getImm();
4483    if (widthm1 >= 32 - lsb)
4484      return Error(Operands[5]->getStartLoc(),
4485                   "bitfield width must be in range [1,32-lsb]");
4486    return false;
4487  }
4488  case ARM::tLDMIA: {
4489    // If we're parsing Thumb2, the .w variant is available and handles
4490    // most cases that are normally illegal for a Thumb1 LDM
4491    // instruction. We'll make the transformation in processInstruction()
4492    // if necessary.
4493    //
4494    // Thumb LDM instructions are writeback iff the base register is not
4495    // in the register list.
4496    unsigned Rn = Inst.getOperand(0).getReg();
4497    bool hasWritebackToken =
4498      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
4499       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
4500    bool listContainsBase;
4501    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
4502      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
4503                   "registers must be in range r0-r7");
4504    // If we should have writeback, then there should be a '!' token.
4505    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
4506      return Error(Operands[2]->getStartLoc(),
4507                   "writeback operator '!' expected");
4508    // If we should not have writeback, there must not be a '!'. This is
4509    // true even for the 32-bit wide encodings.
4510    if (listContainsBase && hasWritebackToken)
4511      return Error(Operands[3]->getStartLoc(),
4512                   "writeback operator '!' not allowed when base register "
4513                   "in register list");
4514
4515    break;
4516  }
4517  case ARM::t2LDMIA_UPD: {
4518    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
4519      return Error(Operands[4]->getStartLoc(),
4520                   "writeback operator '!' not allowed when base register "
4521                   "in register list");
4522    break;
4523  }
4524  // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
4525  // so only issue a diagnostic for thumb1. The instructions will be
4526  // switched to the t2 encodings in processInstruction() if necessary.
4527  case ARM::tPOP: {
4528    bool listContainsBase;
4529    if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
4530        !isThumbTwo())
4531      return Error(Operands[2]->getStartLoc(),
4532                   "registers must be in range r0-r7 or pc");
4533    break;
4534  }
4535  case ARM::tPUSH: {
4536    bool listContainsBase;
4537    if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
4538        !isThumbTwo())
4539      return Error(Operands[2]->getStartLoc(),
4540                   "registers must be in range r0-r7 or lr");
4541    break;
4542  }
4543  case ARM::tSTMIA_UPD: {
4544    bool listContainsBase;
4545    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
4546      return Error(Operands[4]->getStartLoc(),
4547                   "registers must be in range r0-r7");
4548    break;
4549  }
4550  }
4551
4552  return false;
4553}
4554
4555bool ARMAsmParser::
4556processInstruction(MCInst &Inst,
4557                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4558  switch (Inst.getOpcode()) {
4559  // Handle the MOV complex aliases.
4560  case ARM::ASRi:
4561  case ARM::LSRi:
4562  case ARM::LSLi:
4563  case ARM::RORi: {
4564    ARM_AM::ShiftOpc ShiftTy;
4565    unsigned Amt = Inst.getOperand(2).getImm();
4566    switch(Inst.getOpcode()) {
4567    default: llvm_unreachable("unexpected opcode!");
4568    case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
4569    case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
4570    case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
4571    case ARM::RORi: ShiftTy = ARM_AM::ror; break;
4572    }
4573    // A shift by zero is a plain MOVr, not a MOVsi.
4574    unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
4575    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
4576    MCInst TmpInst;
4577    TmpInst.setOpcode(Opc);
4578    TmpInst.addOperand(Inst.getOperand(0)); // Rd
4579    TmpInst.addOperand(Inst.getOperand(1)); // Rn
4580    if (Opc == ARM::MOVsi)
4581      TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
4582    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
4583    TmpInst.addOperand(Inst.getOperand(4));
4584    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
4585    Inst = TmpInst;
4586    return true;
4587  }
4588  case ARM::t2LDMIA_UPD: {
4589    // If this is a load of a single register, then we should use
4590    // a post-indexed LDR instruction instead, per the ARM ARM.
4591    if (Inst.getNumOperands() != 5)
4592      return false;
4593    MCInst TmpInst;
4594    TmpInst.setOpcode(ARM::t2LDR_POST);
4595    TmpInst.addOperand(Inst.getOperand(4)); // Rt
4596    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4597    TmpInst.addOperand(Inst.getOperand(1)); // Rn
4598    TmpInst.addOperand(MCOperand::CreateImm(4));
4599    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4600    TmpInst.addOperand(Inst.getOperand(3));
4601    Inst = TmpInst;
4602    return true;
4603  }
4604  case ARM::t2STMDB_UPD: {
4605    // If this is a store of a single register, then we should use
4606    // a pre-indexed STR instruction instead, per the ARM ARM.
4607    if (Inst.getNumOperands() != 5)
4608      return false;
4609    MCInst TmpInst;
4610    TmpInst.setOpcode(ARM::t2STR_PRE);
4611    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4612    TmpInst.addOperand(Inst.getOperand(4)); // Rt
4613    TmpInst.addOperand(Inst.getOperand(1)); // Rn
4614    TmpInst.addOperand(MCOperand::CreateImm(-4));
4615    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4616    TmpInst.addOperand(Inst.getOperand(3));
4617    Inst = TmpInst;
4618    return true;
4619  }
4620  case ARM::LDMIA_UPD:
4621    // If this is a load of a single register via a 'pop', then we should use
4622    // a post-indexed LDR instruction instead, per the ARM ARM.
4623    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
4624        Inst.getNumOperands() == 5) {
4625      MCInst TmpInst;
4626      TmpInst.setOpcode(ARM::LDR_POST_IMM);
4627      TmpInst.addOperand(Inst.getOperand(4)); // Rt
4628      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4629      TmpInst.addOperand(Inst.getOperand(1)); // Rn
4630      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
4631      TmpInst.addOperand(MCOperand::CreateImm(4));
4632      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4633      TmpInst.addOperand(Inst.getOperand(3));
4634      Inst = TmpInst;
4635      return true;
4636    }
4637    break;
4638  case ARM::STMDB_UPD:
4639    // If this is a store of a single register via a 'push', then we should use
4640    // a pre-indexed STR instruction instead, per the ARM ARM.
4641    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
4642        Inst.getNumOperands() == 5) {
4643      MCInst TmpInst;
4644      TmpInst.setOpcode(ARM::STR_PRE_IMM);
4645      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4646      TmpInst.addOperand(Inst.getOperand(4)); // Rt
4647      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
4648      TmpInst.addOperand(MCOperand::CreateImm(-4));
4649      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4650      TmpInst.addOperand(Inst.getOperand(3));
4651      Inst = TmpInst;
4652    }
4653    break;
4654  case ARM::tADDi8:
4655    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
4656    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
4657    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
4658    // to encoding T1 if <Rd> is omitted."
4659    if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
4660      Inst.setOpcode(ARM::tADDi3);
4661      return true;
4662    }
4663    break;
4664  case ARM::tSUBi8:
4665    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
4666    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
4667    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
4668    // to encoding T1 if <Rd> is omitted."
4669    if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
4670      Inst.setOpcode(ARM::tSUBi3);
4671      return true;
4672    }
4673    break;
4674  case ARM::tB:
4675    // A Thumb conditional branch outside of an IT block is a tBcc.
4676    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
4677      Inst.setOpcode(ARM::tBcc);
4678      return true;
4679    }
4680    break;
4681  case ARM::t2B:
4682    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
4683    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
4684      Inst.setOpcode(ARM::t2Bcc);
4685      return true;
4686    }
4687    break;
4688  case ARM::t2Bcc:
4689    // If the conditional is AL or we're in an IT block, we really want t2B.
4690    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
4691      Inst.setOpcode(ARM::t2B);
4692      return true;
4693    }
4694    break;
4695  case ARM::tBcc:
4696    // If the conditional is AL, we really want tB.
4697    if (Inst.getOperand(1).getImm() == ARMCC::AL) {
4698      Inst.setOpcode(ARM::tB);
4699      return true;
4700    }
4701    break;
4702  case ARM::tLDMIA: {
4703    // If the register list contains any high registers, or if the writeback
4704    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
4705    // instead if we're in Thumb2. Otherwise, this should have generated
4706    // an error in validateInstruction().
4707    unsigned Rn = Inst.getOperand(0).getReg();
4708    bool hasWritebackToken =
4709      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
4710       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
4711    bool listContainsBase;
4712    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
4713        (!listContainsBase && !hasWritebackToken) ||
4714        (listContainsBase && hasWritebackToken)) {
4715      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
4716      assert (isThumbTwo());
4717      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
4718      // If we're switching to the updating version, we need to insert
4719      // the writeback tied operand.
4720      if (hasWritebackToken)
4721        Inst.insert(Inst.begin(),
4722                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
4723      return true;
4724    }
4725    break;
4726  }
4727  case ARM::tSTMIA_UPD: {
4728    // If the register list contains any high registers, we need to use
4729    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
4730    // should have generated an error in validateInstruction().
4731    unsigned Rn = Inst.getOperand(0).getReg();
4732    bool listContainsBase;
4733    if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
4734      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
4735      assert (isThumbTwo());
4736      Inst.setOpcode(ARM::t2STMIA_UPD);
4737      return true;
4738    }
4739    break;
4740  }
4741  case ARM::tPOP: {
4742    bool listContainsBase;
4743    // If the register list contains any high registers, we need to use
4744    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
4745    // should have generated an error in validateInstruction().
4746    if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
4747      return false;
4748    assert (isThumbTwo());
4749    Inst.setOpcode(ARM::t2LDMIA_UPD);
4750    // Add the base register and writeback operands.
4751    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
4752    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
4753    return true;
4754  }
4755  case ARM::tPUSH: {
4756    bool listContainsBase;
4757    if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
4758      return false;
4759    assert (isThumbTwo());
4760    Inst.setOpcode(ARM::t2STMDB_UPD);
4761    // Add the base register and writeback operands.
4762    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
4763    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
4764    return true;
4765  }
4766  case ARM::t2MOVi: {
4767    // If we can use the 16-bit encoding and the user didn't explicitly
4768    // request the 32-bit variant, transform it here.
4769    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4770        Inst.getOperand(1).getImm() <= 255 &&
4771        ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
4772         Inst.getOperand(4).getReg() == ARM::CPSR) ||
4773        (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
4774        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4775         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4776      // The operands aren't in the same order for tMOVi8...
4777      MCInst TmpInst;
4778      TmpInst.setOpcode(ARM::tMOVi8);
4779      TmpInst.addOperand(Inst.getOperand(0));
4780      TmpInst.addOperand(Inst.getOperand(4));
4781      TmpInst.addOperand(Inst.getOperand(1));
4782      TmpInst.addOperand(Inst.getOperand(2));
4783      TmpInst.addOperand(Inst.getOperand(3));
4784      Inst = TmpInst;
4785      return true;
4786    }
4787    break;
4788  }
4789  case ARM::t2MOVr: {
4790    // If we can use the 16-bit encoding and the user didn't explicitly
4791    // request the 32-bit variant, transform it here.
4792    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4793        isARMLowRegister(Inst.getOperand(1).getReg()) &&
4794        Inst.getOperand(2).getImm() == ARMCC::AL &&
4795        Inst.getOperand(4).getReg() == ARM::CPSR &&
4796        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4797         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4798      // The operands aren't the same for tMOV[S]r... (no cc_out)
4799      MCInst TmpInst;
4800      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
4801      TmpInst.addOperand(Inst.getOperand(0));
4802      TmpInst.addOperand(Inst.getOperand(1));
4803      TmpInst.addOperand(Inst.getOperand(2));
4804      TmpInst.addOperand(Inst.getOperand(3));
4805      Inst = TmpInst;
4806      return true;
4807    }
4808    break;
4809  }
4810  case ARM::t2SXTH:
4811  case ARM::t2SXTB:
4812  case ARM::t2UXTH:
4813  case ARM::t2UXTB: {
4814    // If we can use the 16-bit encoding and the user didn't explicitly
4815    // request the 32-bit variant, transform it here.
4816    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4817        isARMLowRegister(Inst.getOperand(1).getReg()) &&
4818        Inst.getOperand(2).getImm() == 0 &&
4819        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4820         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4821      unsigned NewOpc;
4822      switch (Inst.getOpcode()) {
4823      default: llvm_unreachable("Illegal opcode!");
4824      case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
4825      case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
4826      case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
4827      case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
4828      }
4829      // The operands aren't the same for thumb1 (no rotate operand).
4830      MCInst TmpInst;
4831      TmpInst.setOpcode(NewOpc);
4832      TmpInst.addOperand(Inst.getOperand(0));
4833      TmpInst.addOperand(Inst.getOperand(1));
4834      TmpInst.addOperand(Inst.getOperand(3));
4835      TmpInst.addOperand(Inst.getOperand(4));
4836      Inst = TmpInst;
4837      return true;
4838    }
4839    break;
4840  }
4841  case ARM::t2IT: {
4842    // The mask bits for all but the first condition are represented as
4843    // the low bit of the condition code value implies 't'. We currently
4844    // always have 1 implies 't', so XOR toggle the bits if the low bit
4845    // of the condition code is zero. The encoding also expects the low
4846    // bit of the condition to be encoded as bit 4 of the mask operand,
4847    // so mask that in if needed
4848    MCOperand &MO = Inst.getOperand(1);
4849    unsigned Mask = MO.getImm();
4850    unsigned OrigMask = Mask;
4851    unsigned TZ = CountTrailingZeros_32(Mask);
4852    if ((Inst.getOperand(0).getImm() & 1) == 0) {
4853      assert(Mask && TZ <= 3 && "illegal IT mask value!");
4854      for (unsigned i = 3; i != TZ; --i)
4855        Mask ^= 1 << i;
4856    } else
4857      Mask |= 0x10;
4858    MO.setImm(Mask);
4859
4860    // Set up the IT block state according to the IT instruction we just
4861    // matched.
4862    assert(!inITBlock() && "nested IT blocks?!");
4863    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
4864    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
4865    ITState.CurPosition = 0;
4866    ITState.FirstCond = true;
4867    break;
4868  }
4869  }
4870  return false;
4871}
4872
4873unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
4874  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
4875  // suffix depending on whether they're in an IT block or not.
4876  unsigned Opc = Inst.getOpcode();
4877  const MCInstrDesc &MCID = getInstDesc(Opc);
4878  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
4879    assert(MCID.hasOptionalDef() &&
4880           "optionally flag setting instruction missing optional def operand");
4881    assert(MCID.NumOperands == Inst.getNumOperands() &&
4882           "operand count mismatch!");
4883    // Find the optional-def operand (cc_out).
4884    unsigned OpNo;
4885    for (OpNo = 0;
4886         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
4887         ++OpNo)
4888      ;
4889    // If we're parsing Thumb1, reject it completely.
4890    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
4891      return Match_MnemonicFail;
4892    // If we're parsing Thumb2, which form is legal depends on whether we're
4893    // in an IT block.
4894    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
4895        !inITBlock())
4896      return Match_RequiresITBlock;
4897    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
4898        inITBlock())
4899      return Match_RequiresNotITBlock;
4900  }
4901  // Some high-register supporting Thumb1 encodings only allow both registers
4902  // to be from r0-r7 when in Thumb2.
4903  else if (Opc == ARM::tADDhirr && isThumbOne() &&
4904           isARMLowRegister(Inst.getOperand(1).getReg()) &&
4905           isARMLowRegister(Inst.getOperand(2).getReg()))
4906    return Match_RequiresThumb2;
4907  // Others only require ARMv6 or later.
4908  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
4909           isARMLowRegister(Inst.getOperand(0).getReg()) &&
4910           isARMLowRegister(Inst.getOperand(1).getReg()))
4911    return Match_RequiresV6;
4912  return Match_Success;
4913}
4914
4915bool ARMAsmParser::
4916MatchAndEmitInstruction(SMLoc IDLoc,
4917                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4918                        MCStreamer &Out) {
4919  MCInst Inst;
4920  unsigned ErrorInfo;
4921  unsigned MatchResult;
4922  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
4923  switch (MatchResult) {
4924  default: break;
4925  case Match_Success:
4926    // Context sensitive operand constraints aren't handled by the matcher,
4927    // so check them here.
4928    if (validateInstruction(Inst, Operands)) {
4929      // Still progress the IT block, otherwise one wrong condition causes
4930      // nasty cascading errors.
4931      forwardITPosition();
4932      return true;
4933    }
4934
4935    // Some instructions need post-processing to, for example, tweak which
4936    // encoding is selected. Loop on it while changes happen so the
4937    // individual transformations can chain off each other. E.g.,
4938    // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
4939    while (processInstruction(Inst, Operands))
4940      ;
4941
4942    // Only move forward at the very end so that everything in validate
4943    // and process gets a consistent answer about whether we're in an IT
4944    // block.
4945    forwardITPosition();
4946
4947    Out.EmitInstruction(Inst);
4948    return false;
4949  case Match_MissingFeature:
4950    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
4951    return true;
4952  case Match_InvalidOperand: {
4953    SMLoc ErrorLoc = IDLoc;
4954    if (ErrorInfo != ~0U) {
4955      if (ErrorInfo >= Operands.size())
4956        return Error(IDLoc, "too few operands for instruction");
4957
4958      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
4959      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
4960    }
4961
4962    return Error(ErrorLoc, "invalid operand for instruction");
4963  }
4964  case Match_MnemonicFail:
4965    return Error(IDLoc, "invalid instruction");
4966  case Match_ConversionFail:
4967    // The converter function will have already emited a diagnostic.
4968    return true;
4969  case Match_RequiresNotITBlock:
4970    return Error(IDLoc, "flag setting instruction only valid outside IT block");
4971  case Match_RequiresITBlock:
4972    return Error(IDLoc, "instruction only valid inside IT block");
4973  case Match_RequiresV6:
4974    return Error(IDLoc, "instruction variant requires ARMv6 or later");
4975  case Match_RequiresThumb2:
4976    return Error(IDLoc, "instruction variant requires Thumb2");
4977  }
4978
4979  llvm_unreachable("Implement any new match types added!");
4980  return true;
4981}
4982
4983/// parseDirective parses the arm specific directives
4984bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
4985  StringRef IDVal = DirectiveID.getIdentifier();
4986  if (IDVal == ".word")
4987    return parseDirectiveWord(4, DirectiveID.getLoc());
4988  else if (IDVal == ".thumb")
4989    return parseDirectiveThumb(DirectiveID.getLoc());
4990  else if (IDVal == ".thumb_func")
4991    return parseDirectiveThumbFunc(DirectiveID.getLoc());
4992  else if (IDVal == ".code")
4993    return parseDirectiveCode(DirectiveID.getLoc());
4994  else if (IDVal == ".syntax")
4995    return parseDirectiveSyntax(DirectiveID.getLoc());
4996  return true;
4997}
4998
4999/// parseDirectiveWord
5000///  ::= .word [ expression (, expression)* ]
5001bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
5002  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5003    for (;;) {
5004      const MCExpr *Value;
5005      if (getParser().ParseExpression(Value))
5006        return true;
5007
5008      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
5009
5010      if (getLexer().is(AsmToken::EndOfStatement))
5011        break;
5012
5013      // FIXME: Improve diagnostic.
5014      if (getLexer().isNot(AsmToken::Comma))
5015        return Error(L, "unexpected token in directive");
5016      Parser.Lex();
5017    }
5018  }
5019
5020  Parser.Lex();
5021  return false;
5022}
5023
5024/// parseDirectiveThumb
5025///  ::= .thumb
5026bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
5027  if (getLexer().isNot(AsmToken::EndOfStatement))
5028    return Error(L, "unexpected token in directive");
5029  Parser.Lex();
5030
5031  // TODO: set thumb mode
5032  // TODO: tell the MC streamer the mode
5033  // getParser().getStreamer().Emit???();
5034  return false;
5035}
5036
5037/// parseDirectiveThumbFunc
5038///  ::= .thumbfunc symbol_name
5039bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
5040  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
5041  bool isMachO = MAI.hasSubsectionsViaSymbols();
5042  StringRef Name;
5043
5044  // Darwin asm has function name after .thumb_func direction
5045  // ELF doesn't
5046  if (isMachO) {
5047    const AsmToken &Tok = Parser.getTok();
5048    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
5049      return Error(L, "unexpected token in .thumb_func directive");
5050    Name = Tok.getIdentifier();
5051    Parser.Lex(); // Consume the identifier token.
5052  }
5053
5054 if (getLexer().isNot(AsmToken::EndOfStatement))
5055    return Error(L, "unexpected token in directive");
5056  Parser.Lex();
5057
5058  // FIXME: assuming function name will be the line following .thumb_func
5059  if (!isMachO) {
5060    Name = Parser.getTok().getIdentifier();
5061  }
5062
5063  // Mark symbol as a thumb symbol.
5064  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
5065  getParser().getStreamer().EmitThumbFunc(Func);
5066  return false;
5067}
5068
5069/// parseDirectiveSyntax
5070///  ::= .syntax unified | divided
5071bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
5072  const AsmToken &Tok = Parser.getTok();
5073  if (Tok.isNot(AsmToken::Identifier))
5074    return Error(L, "unexpected token in .syntax directive");
5075  StringRef Mode = Tok.getString();
5076  if (Mode == "unified" || Mode == "UNIFIED")
5077    Parser.Lex();
5078  else if (Mode == "divided" || Mode == "DIVIDED")
5079    return Error(L, "'.syntax divided' arm asssembly not supported");
5080  else
5081    return Error(L, "unrecognized syntax mode in .syntax directive");
5082
5083  if (getLexer().isNot(AsmToken::EndOfStatement))
5084    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
5085  Parser.Lex();
5086
5087  // TODO tell the MC streamer the mode
5088  // getParser().getStreamer().Emit???();
5089  return false;
5090}
5091
5092/// parseDirectiveCode
5093///  ::= .code 16 | 32
5094bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
5095  const AsmToken &Tok = Parser.getTok();
5096  if (Tok.isNot(AsmToken::Integer))
5097    return Error(L, "unexpected token in .code directive");
5098  int64_t Val = Parser.getTok().getIntVal();
5099  if (Val == 16)
5100    Parser.Lex();
5101  else if (Val == 32)
5102    Parser.Lex();
5103  else
5104    return Error(L, "invalid operand to .code directive");
5105
5106  if (getLexer().isNot(AsmToken::EndOfStatement))
5107    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
5108  Parser.Lex();
5109
5110  if (Val == 16) {
5111    if (!isThumb())
5112      SwitchMode();
5113    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
5114  } else {
5115    if (isThumb())
5116      SwitchMode();
5117    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
5118  }
5119
5120  return false;
5121}
5122
5123extern "C" void LLVMInitializeARMAsmLexer();
5124
5125/// Force static initialization.
5126extern "C" void LLVMInitializeARMAsmParser() {
5127  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
5128  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
5129  LLVMInitializeARMAsmLexer();
5130}
5131
5132#define GET_REGISTER_MATCHER
5133#define GET_MATCHER_IMPLEMENTATION
5134#include "ARMGenAsmMatcher.inc"
5135