ARMAsmParser.cpp revision 275944afb55086d0b4b20d4d831de7c1c7507925 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "ARM.h"
11#include "ARMBaseRegisterInfo.h"
12#include "ARMSubtarget.h"
13#include "MCTargetDesc/ARMAddressingModes.h"
14#include "MCTargetDesc/ARMMCExpr.h"
15#include "llvm/MC/MCParser/MCAsmLexer.h"
16#include "llvm/MC/MCParser/MCAsmParser.h"
17#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
18#include "llvm/MC/MCAsmInfo.h"
19#include "llvm/MC/MCContext.h"
20#include "llvm/MC/MCStreamer.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/TargetAsmParser.h"
25#include "llvm/Target/TargetRegistry.h"
26#include "llvm/Support/SourceMgr.h"
27#include "llvm/Support/raw_ostream.h"
28#include "llvm/ADT/OwningPtr.h"
29#include "llvm/ADT/SmallVector.h"
30#include "llvm/ADT/StringExtras.h"
31#include "llvm/ADT/StringSwitch.h"
32#include "llvm/ADT/Twine.h"
33
34using namespace llvm;
35
36namespace {
37
38class ARMOperand;
39
40class ARMAsmParser : public TargetAsmParser {
41  MCSubtargetInfo &STI;
42  MCAsmParser &Parser;
43
44  MCAsmParser &getParser() const { return Parser; }
45  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
46
47  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
48  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
49
50  int TryParseRegister();
51  virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
52  bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
53  int TryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
54  bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
55  bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &,
56                   ARMII::AddrMode AddrMode);
57  bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
58  bool ParsePrefix(ARMMCExpr::VariantKind &RefKind);
59  const MCExpr *ApplyPrefixToExpr(const MCExpr *E,
60                                  MCSymbolRefExpr::VariantKind Variant);
61
62
63  bool ParseMemoryOffsetReg(bool &Negative,
64                            bool &OffsetRegShifted,
65                            enum ARM_AM::ShiftOpc &ShiftType,
66                            const MCExpr *&ShiftAmount,
67                            const MCExpr *&Offset,
68                            bool &OffsetIsReg,
69                            int &OffsetRegNum,
70                            SMLoc &E);
71  bool ParseShift(enum ARM_AM::ShiftOpc &St,
72                  const MCExpr *&ShiftAmount, SMLoc &E);
73  bool ParseDirectiveWord(unsigned Size, SMLoc L);
74  bool ParseDirectiveThumb(SMLoc L);
75  bool ParseDirectiveThumbFunc(SMLoc L);
76  bool ParseDirectiveCode(SMLoc L);
77  bool ParseDirectiveSyntax(SMLoc L);
78
79  bool MatchAndEmitInstruction(SMLoc IDLoc,
80                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
81                               MCStreamer &Out);
82  StringRef SplitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
83                          bool &CarrySetting, unsigned &ProcessorIMod);
84  void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
85                             bool &CanAcceptPredicationCode);
86
87  bool isThumb() const {
88    // FIXME: Can tablegen auto-generate this?
89    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
90  }
91  bool isThumbOne() const {
92    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
93  }
94  void SwitchMode() {
95    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
96    setAvailableFeatures(FB);
97  }
98
99  /// @name Auto-generated Match Functions
100  /// {
101
102#define GET_ASSEMBLER_HEADER
103#include "ARMGenAsmMatcher.inc"
104
105  /// }
106
107  OperandMatchResultTy parseCoprocNumOperand(
108    SmallVectorImpl<MCParsedAsmOperand*>&);
109  OperandMatchResultTy parseCoprocRegOperand(
110    SmallVectorImpl<MCParsedAsmOperand*>&);
111  OperandMatchResultTy parseMemBarrierOptOperand(
112    SmallVectorImpl<MCParsedAsmOperand*>&);
113  OperandMatchResultTy parseProcIFlagsOperand(
114    SmallVectorImpl<MCParsedAsmOperand*>&);
115  OperandMatchResultTy parseMSRMaskOperand(
116    SmallVectorImpl<MCParsedAsmOperand*>&);
117  OperandMatchResultTy parseMemMode2Operand(
118    SmallVectorImpl<MCParsedAsmOperand*>&);
119  OperandMatchResultTy parseMemMode3Operand(
120    SmallVectorImpl<MCParsedAsmOperand*>&);
121  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
122                                   StringRef Op, int Low, int High);
123  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
124    return parsePKHImm(O, "lsl", 0, 31);
125  }
126  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
127    return parsePKHImm(O, "asr", 1, 32);
128  }
129  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
130
131  // Asm Match Converter Methods
132  bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
133                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
134  bool CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
135                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
136  bool CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
137                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
138  bool CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
139                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
140
141public:
142  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
143    : TargetAsmParser(), STI(_STI), Parser(_Parser) {
144    MCAsmParserExtension::Initialize(_Parser);
145
146    // Initialize the set of available features.
147    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
148  }
149
150  virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
151                                SmallVectorImpl<MCParsedAsmOperand*> &Operands);
152  virtual bool ParseDirective(AsmToken DirectiveID);
153};
154} // end anonymous namespace
155
156namespace llvm {
157  // FIXME: TableGen this?
158  extern MCRegisterClass ARMMCRegisterClasses[]; // In ARMGenRegisterInfo.inc.
159}
160
161namespace {
162
163/// ARMOperand - Instances of this class represent a parsed ARM machine
164/// instruction.
165class ARMOperand : public MCParsedAsmOperand {
166  enum KindTy {
167    CondCode,
168    CCOut,
169    CoprocNum,
170    CoprocReg,
171    Immediate,
172    MemBarrierOpt,
173    Memory,
174    MSRMask,
175    ProcIFlags,
176    Register,
177    RegisterList,
178    DPRRegisterList,
179    SPRRegisterList,
180    ShiftedRegister,
181    ShiftedImmediate,
182    Shifter,
183    Token
184  } Kind;
185
186  SMLoc StartLoc, EndLoc;
187  SmallVector<unsigned, 8> Registers;
188
189  union {
190    struct {
191      ARMCC::CondCodes Val;
192    } CC;
193
194    struct {
195      ARM_MB::MemBOpt Val;
196    } MBOpt;
197
198    struct {
199      unsigned Val;
200    } Cop;
201
202    struct {
203      ARM_PROC::IFlags Val;
204    } IFlags;
205
206    struct {
207      unsigned Val;
208    } MMask;
209
210    struct {
211      const char *Data;
212      unsigned Length;
213    } Tok;
214
215    struct {
216      unsigned RegNum;
217    } Reg;
218
219    struct {
220      const MCExpr *Val;
221    } Imm;
222
223    /// Combined record for all forms of ARM address expressions.
224    struct {
225      ARMII::AddrMode AddrMode;
226      unsigned BaseRegNum;
227      union {
228        unsigned RegNum;     ///< Offset register num, when OffsetIsReg.
229        const MCExpr *Value; ///< Offset value, when !OffsetIsReg.
230      } Offset;
231      const MCExpr *ShiftAmount;     // used when OffsetRegShifted is true
232      enum ARM_AM::ShiftOpc ShiftType; // used when OffsetRegShifted is true
233      unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true
234      unsigned Preindexed       : 1;
235      unsigned Postindexed      : 1;
236      unsigned OffsetIsReg      : 1;
237      unsigned Negative         : 1; // only used when OffsetIsReg is true
238      unsigned Writeback        : 1;
239    } Mem;
240
241    struct {
242      ARM_AM::ShiftOpc ShiftTy;
243      unsigned Imm;
244    } Shift;
245    struct {
246      ARM_AM::ShiftOpc ShiftTy;
247      unsigned SrcReg;
248      unsigned ShiftReg;
249      unsigned ShiftImm;
250    } RegShiftedReg;
251    struct {
252      ARM_AM::ShiftOpc ShiftTy;
253      unsigned SrcReg;
254      unsigned ShiftImm;
255    } RegShiftedImm;
256  };
257
258  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
259public:
260  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
261    Kind = o.Kind;
262    StartLoc = o.StartLoc;
263    EndLoc = o.EndLoc;
264    switch (Kind) {
265    case CondCode:
266      CC = o.CC;
267      break;
268    case Token:
269      Tok = o.Tok;
270      break;
271    case CCOut:
272    case Register:
273      Reg = o.Reg;
274      break;
275    case RegisterList:
276    case DPRRegisterList:
277    case SPRRegisterList:
278      Registers = o.Registers;
279      break;
280    case CoprocNum:
281    case CoprocReg:
282      Cop = o.Cop;
283      break;
284    case Immediate:
285      Imm = o.Imm;
286      break;
287    case MemBarrierOpt:
288      MBOpt = o.MBOpt;
289      break;
290    case Memory:
291      Mem = o.Mem;
292      break;
293    case MSRMask:
294      MMask = o.MMask;
295      break;
296    case ProcIFlags:
297      IFlags = o.IFlags;
298      break;
299    case Shifter:
300      Shift = o.Shift;
301      break;
302    case ShiftedRegister:
303      RegShiftedReg = o.RegShiftedReg;
304      break;
305    case ShiftedImmediate:
306      RegShiftedImm = o.RegShiftedImm;
307      break;
308    }
309  }
310
311  /// getStartLoc - Get the location of the first token of this operand.
312  SMLoc getStartLoc() const { return StartLoc; }
313  /// getEndLoc - Get the location of the last token of this operand.
314  SMLoc getEndLoc() const { return EndLoc; }
315
316  ARMCC::CondCodes getCondCode() const {
317    assert(Kind == CondCode && "Invalid access!");
318    return CC.Val;
319  }
320
321  unsigned getCoproc() const {
322    assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
323    return Cop.Val;
324  }
325
326  StringRef getToken() const {
327    assert(Kind == Token && "Invalid access!");
328    return StringRef(Tok.Data, Tok.Length);
329  }
330
331  unsigned getReg() const {
332    assert((Kind == Register || Kind == CCOut) && "Invalid access!");
333    return Reg.RegNum;
334  }
335
336  const SmallVectorImpl<unsigned> &getRegList() const {
337    assert((Kind == RegisterList || Kind == DPRRegisterList ||
338            Kind == SPRRegisterList) && "Invalid access!");
339    return Registers;
340  }
341
342  const MCExpr *getImm() const {
343    assert(Kind == Immediate && "Invalid access!");
344    return Imm.Val;
345  }
346
347  ARM_MB::MemBOpt getMemBarrierOpt() const {
348    assert(Kind == MemBarrierOpt && "Invalid access!");
349    return MBOpt.Val;
350  }
351
352  ARM_PROC::IFlags getProcIFlags() const {
353    assert(Kind == ProcIFlags && "Invalid access!");
354    return IFlags.Val;
355  }
356
357  unsigned getMSRMask() const {
358    assert(Kind == MSRMask && "Invalid access!");
359    return MMask.Val;
360  }
361
362  /// @name Memory Operand Accessors
363  /// @{
364  ARMII::AddrMode getMemAddrMode() const {
365    return Mem.AddrMode;
366  }
367  unsigned getMemBaseRegNum() const {
368    return Mem.BaseRegNum;
369  }
370  unsigned getMemOffsetRegNum() const {
371    assert(Mem.OffsetIsReg && "Invalid access!");
372    return Mem.Offset.RegNum;
373  }
374  const MCExpr *getMemOffset() const {
375    assert(!Mem.OffsetIsReg && "Invalid access!");
376    return Mem.Offset.Value;
377  }
378  unsigned getMemOffsetRegShifted() const {
379    assert(Mem.OffsetIsReg && "Invalid access!");
380    return Mem.OffsetRegShifted;
381  }
382  const MCExpr *getMemShiftAmount() const {
383    assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
384    return Mem.ShiftAmount;
385  }
386  enum ARM_AM::ShiftOpc getMemShiftType() const {
387    assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
388    return Mem.ShiftType;
389  }
390  bool getMemPreindexed() const { return Mem.Preindexed; }
391  bool getMemPostindexed() const { return Mem.Postindexed; }
392  bool getMemOffsetIsReg() const { return Mem.OffsetIsReg; }
393  bool getMemNegative() const { return Mem.Negative; }
394  bool getMemWriteback() const { return Mem.Writeback; }
395
396  /// @}
397
398  bool isCoprocNum() const { return Kind == CoprocNum; }
399  bool isCoprocReg() const { return Kind == CoprocReg; }
400  bool isCondCode() const { return Kind == CondCode; }
401  bool isCCOut() const { return Kind == CCOut; }
402  bool isImm() const { return Kind == Immediate; }
403  bool isImm0_255() const {
404    if (Kind != Immediate)
405      return false;
406    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
407    if (!CE) return false;
408    int64_t Value = CE->getValue();
409    return Value >= 0 && Value < 256;
410  }
411  bool isImm0_7() const {
412    if (Kind != Immediate)
413      return false;
414    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
415    if (!CE) return false;
416    int64_t Value = CE->getValue();
417    return Value >= 0 && Value < 8;
418  }
419  bool isImm0_15() const {
420    if (Kind != Immediate)
421      return false;
422    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
423    if (!CE) return false;
424    int64_t Value = CE->getValue();
425    return Value >= 0 && Value < 16;
426  }
427  bool isImm0_31() const {
428    if (Kind != Immediate)
429      return false;
430    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
431    if (!CE) return false;
432    int64_t Value = CE->getValue();
433    return Value >= 0 && Value < 32;
434  }
435  bool isImm1_32() const {
436    if (Kind != Immediate)
437      return false;
438    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
439    if (!CE) return false;
440    int64_t Value = CE->getValue();
441    return Value > 0 && Value < 33;
442  }
443  bool isImm0_65535() const {
444    if (Kind != Immediate)
445      return false;
446    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
447    if (!CE) return false;
448    int64_t Value = CE->getValue();
449    return Value >= 0 && Value < 65536;
450  }
451  bool isImm0_65535Expr() const {
452    if (Kind != Immediate)
453      return false;
454    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
455    // If it's not a constant expression, it'll generate a fixup and be
456    // handled later.
457    if (!CE) return true;
458    int64_t Value = CE->getValue();
459    return Value >= 0 && Value < 65536;
460  }
461  bool isPKHLSLImm() const {
462    if (Kind != Immediate)
463      return false;
464    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
465    if (!CE) return false;
466    int64_t Value = CE->getValue();
467    return Value >= 0 && Value < 32;
468  }
469  bool isPKHASRImm() const {
470    if (Kind != Immediate)
471      return false;
472    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
473    if (!CE) return false;
474    int64_t Value = CE->getValue();
475    return Value > 0 && Value <= 32;
476  }
477  bool isARMSOImm() const {
478    if (Kind != Immediate)
479      return false;
480    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
481    if (!CE) return false;
482    int64_t Value = CE->getValue();
483    return ARM_AM::getSOImmVal(Value) != -1;
484  }
485  bool isT2SOImm() const {
486    if (Kind != Immediate)
487      return false;
488    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
489    if (!CE) return false;
490    int64_t Value = CE->getValue();
491    return ARM_AM::getT2SOImmVal(Value) != -1;
492  }
493  bool isSetEndImm() const {
494    if (Kind != Immediate)
495      return false;
496    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
497    if (!CE) return false;
498    int64_t Value = CE->getValue();
499    return Value == 1 || Value == 0;
500  }
501  bool isReg() const { return Kind == Register; }
502  bool isRegList() const { return Kind == RegisterList; }
503  bool isDPRRegList() const { return Kind == DPRRegisterList; }
504  bool isSPRRegList() const { return Kind == SPRRegisterList; }
505  bool isToken() const { return Kind == Token; }
506  bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
507  bool isMemory() const { return Kind == Memory; }
508  bool isShifter() const { return Kind == Shifter; }
509  bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
510  bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
511  bool isMemMode2() const {
512    if (getMemAddrMode() != ARMII::AddrMode2)
513      return false;
514
515    if (getMemOffsetIsReg())
516      return true;
517
518    if (getMemNegative() &&
519        !(getMemPostindexed() || getMemPreindexed()))
520      return false;
521
522    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
523    if (!CE) return false;
524    int64_t Value = CE->getValue();
525
526    // The offset must be in the range 0-4095 (imm12).
527    if (Value > 4095 || Value < -4095)
528      return false;
529
530    return true;
531  }
532  bool isMemMode3() const {
533    if (getMemAddrMode() != ARMII::AddrMode3)
534      return false;
535
536    if (getMemOffsetIsReg()) {
537      if (getMemOffsetRegShifted())
538        return false; // No shift with offset reg allowed
539      return true;
540    }
541
542    if (getMemNegative() &&
543        !(getMemPostindexed() || getMemPreindexed()))
544      return false;
545
546    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
547    if (!CE) return false;
548    int64_t Value = CE->getValue();
549
550    // The offset must be in the range 0-255 (imm8).
551    if (Value > 255 || Value < -255)
552      return false;
553
554    return true;
555  }
556  bool isMemMode5() const {
557    if (!isMemory() || getMemOffsetIsReg() || getMemWriteback() ||
558        getMemNegative())
559      return false;
560
561    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
562    if (!CE) return false;
563
564    // The offset must be a multiple of 4 in the range 0-1020.
565    int64_t Value = CE->getValue();
566    return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
567  }
568  bool isMemMode7() const {
569    if (!isMemory() ||
570        getMemPreindexed() ||
571        getMemPostindexed() ||
572        getMemOffsetIsReg() ||
573        getMemNegative() ||
574        getMemWriteback())
575      return false;
576
577    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
578    if (!CE) return false;
579
580    if (CE->getValue())
581      return false;
582
583    return true;
584  }
585  bool isMemModeRegThumb() const {
586    if (!isMemory() || !getMemOffsetIsReg() || getMemWriteback())
587      return false;
588    return true;
589  }
590  bool isMemModeImmThumb() const {
591    if (!isMemory() || getMemOffsetIsReg() || getMemWriteback())
592      return false;
593
594    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
595    if (!CE) return false;
596
597    // The offset must be a multiple of 4 in the range 0-124.
598    uint64_t Value = CE->getValue();
599    return ((Value & 0x3) == 0 && Value <= 124);
600  }
601  bool isMSRMask() const { return Kind == MSRMask; }
602  bool isProcIFlags() const { return Kind == ProcIFlags; }
603
604  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
605    // Add as immediates when possible.  Null MCExpr = 0.
606    if (Expr == 0)
607      Inst.addOperand(MCOperand::CreateImm(0));
608    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
609      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
610    else
611      Inst.addOperand(MCOperand::CreateExpr(Expr));
612  }
613
614  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
615    assert(N == 2 && "Invalid number of operands!");
616    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
617    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
618    Inst.addOperand(MCOperand::CreateReg(RegNum));
619  }
620
621  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
622    assert(N == 1 && "Invalid number of operands!");
623    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
624  }
625
626  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
627    assert(N == 1 && "Invalid number of operands!");
628    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
629  }
630
631  void addCCOutOperands(MCInst &Inst, unsigned N) const {
632    assert(N == 1 && "Invalid number of operands!");
633    Inst.addOperand(MCOperand::CreateReg(getReg()));
634  }
635
636  void addRegOperands(MCInst &Inst, unsigned N) const {
637    assert(N == 1 && "Invalid number of operands!");
638    Inst.addOperand(MCOperand::CreateReg(getReg()));
639  }
640
641  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
642    assert(N == 3 && "Invalid number of operands!");
643    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
644    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
645    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
646    Inst.addOperand(MCOperand::CreateImm(
647      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
648  }
649
650  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
651    assert(N == 2 && "Invalid number of operands!");
652    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
653    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
654    Inst.addOperand(MCOperand::CreateImm(
655      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
656  }
657
658
659  void addShifterOperands(MCInst &Inst, unsigned N) const {
660    assert(N == 1 && "Invalid number of operands!");
661    Inst.addOperand(MCOperand::CreateImm(
662      ARM_AM::getSORegOpc(Shift.ShiftTy, 0)));
663  }
664
665  void addRegListOperands(MCInst &Inst, unsigned N) const {
666    assert(N == 1 && "Invalid number of operands!");
667    const SmallVectorImpl<unsigned> &RegList = getRegList();
668    for (SmallVectorImpl<unsigned>::const_iterator
669           I = RegList.begin(), E = RegList.end(); I != E; ++I)
670      Inst.addOperand(MCOperand::CreateReg(*I));
671  }
672
673  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
674    addRegListOperands(Inst, N);
675  }
676
677  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
678    addRegListOperands(Inst, N);
679  }
680
681  void addImmOperands(MCInst &Inst, unsigned N) const {
682    assert(N == 1 && "Invalid number of operands!");
683    addExpr(Inst, getImm());
684  }
685
686  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
687    assert(N == 1 && "Invalid number of operands!");
688    addExpr(Inst, getImm());
689  }
690
691  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
692    assert(N == 1 && "Invalid number of operands!");
693    addExpr(Inst, getImm());
694  }
695
696  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
697    assert(N == 1 && "Invalid number of operands!");
698    addExpr(Inst, getImm());
699  }
700
701  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
702    assert(N == 1 && "Invalid number of operands!");
703    addExpr(Inst, getImm());
704  }
705
706  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
707    assert(N == 1 && "Invalid number of operands!");
708    // The constant encodes as the immediate-1, and we store in the instruction
709    // the bits as encoded, so subtract off one here.
710    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
711    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
712  }
713
714  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
715    assert(N == 1 && "Invalid number of operands!");
716    addExpr(Inst, getImm());
717  }
718
719  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
720    assert(N == 1 && "Invalid number of operands!");
721    addExpr(Inst, getImm());
722  }
723
724  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
725    assert(N == 1 && "Invalid number of operands!");
726    addExpr(Inst, getImm());
727  }
728
729  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
730    assert(N == 1 && "Invalid number of operands!");
731    // An ASR value of 32 encodes as 0, so that's how we want to add it to
732    // the instruction as well.
733    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
734    int Val = CE->getValue();
735    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
736  }
737
738  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
739    assert(N == 1 && "Invalid number of operands!");
740    addExpr(Inst, getImm());
741  }
742
743  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
744    assert(N == 1 && "Invalid number of operands!");
745    addExpr(Inst, getImm());
746  }
747
748  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
749    assert(N == 1 && "Invalid number of operands!");
750    addExpr(Inst, getImm());
751  }
752
753  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
754    assert(N == 1 && "Invalid number of operands!");
755    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
756  }
757
758  void addMemMode7Operands(MCInst &Inst, unsigned N) const {
759    assert(N == 1 && isMemMode7() && "Invalid number of operands!");
760    Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
761
762    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
763    (void)CE;
764    assert((CE || CE->getValue() == 0) &&
765           "No offset operand support in mode 7");
766  }
767
768  void addMemMode2Operands(MCInst &Inst, unsigned N) const {
769    assert(isMemMode2() && "Invalid mode or number of operands!");
770    Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
771    unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1);
772
773    if (getMemOffsetIsReg()) {
774      Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
775
776      ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
777      ARM_AM::ShiftOpc ShOpc = ARM_AM::no_shift;
778      int64_t ShiftAmount = 0;
779
780      if (getMemOffsetRegShifted()) {
781        ShOpc = getMemShiftType();
782        const MCConstantExpr *CE =
783                   dyn_cast<MCConstantExpr>(getMemShiftAmount());
784        ShiftAmount = CE->getValue();
785      }
786
787      Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(AMOpc, ShiftAmount,
788                                           ShOpc, IdxMode)));
789      return;
790    }
791
792    // Create a operand placeholder to always yield the same number of operands.
793    Inst.addOperand(MCOperand::CreateReg(0));
794
795    // FIXME: #-0 is encoded differently than #0. Does the parser preserve
796    // the difference?
797    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
798    assert(CE && "Non-constant mode 2 offset operand!");
799    int64_t Offset = CE->getValue();
800
801    if (Offset >= 0)
802      Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::add,
803                                           Offset, ARM_AM::no_shift, IdxMode)));
804    else
805      Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::sub,
806                                          -Offset, ARM_AM::no_shift, IdxMode)));
807  }
808
809  void addMemMode3Operands(MCInst &Inst, unsigned N) const {
810    assert(isMemMode3() && "Invalid mode or number of operands!");
811    Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
812    unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1);
813
814    if (getMemOffsetIsReg()) {
815      Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
816
817      ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
818      Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(AMOpc, 0,
819                                                             IdxMode)));
820      return;
821    }
822
823    // Create a operand placeholder to always yield the same number of operands.
824    Inst.addOperand(MCOperand::CreateReg(0));
825
826    // FIXME: #-0 is encoded differently than #0. Does the parser preserve
827    // the difference?
828    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
829    assert(CE && "Non-constant mode 3 offset operand!");
830    int64_t Offset = CE->getValue();
831
832    if (Offset >= 0)
833      Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::add,
834                                           Offset, IdxMode)));
835    else
836      Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::sub,
837                                           -Offset, IdxMode)));
838  }
839
840  void addMemMode5Operands(MCInst &Inst, unsigned N) const {
841    assert(N == 2 && isMemMode5() && "Invalid number of operands!");
842
843    Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
844    assert(!getMemOffsetIsReg() && "Invalid mode 5 operand");
845
846    // FIXME: #-0 is encoded differently than #0. Does the parser preserve
847    // the difference?
848    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
849    assert(CE && "Non-constant mode 5 offset operand!");
850
851    // The MCInst offset operand doesn't include the low two bits (like
852    // the instruction encoding).
853    int64_t Offset = CE->getValue() / 4;
854    if (Offset >= 0)
855      Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
856                                                             Offset)));
857    else
858      Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
859                                                             -Offset)));
860  }
861
862  void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
863    assert(N == 2 && isMemModeRegThumb() && "Invalid number of operands!");
864    Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
865    Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
866  }
867
868  void addMemModeImmThumbOperands(MCInst &Inst, unsigned N) const {
869    assert(N == 2 && isMemModeImmThumb() && "Invalid number of operands!");
870    Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
871    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
872    assert(CE && "Non-constant mode offset operand!");
873    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
874  }
875
876  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
877    assert(N == 1 && "Invalid number of operands!");
878    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
879  }
880
881  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
882    assert(N == 1 && "Invalid number of operands!");
883    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
884  }
885
886  virtual void print(raw_ostream &OS) const;
887
888  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
889    ARMOperand *Op = new ARMOperand(CondCode);
890    Op->CC.Val = CC;
891    Op->StartLoc = S;
892    Op->EndLoc = S;
893    return Op;
894  }
895
896  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
897    ARMOperand *Op = new ARMOperand(CoprocNum);
898    Op->Cop.Val = CopVal;
899    Op->StartLoc = S;
900    Op->EndLoc = S;
901    return Op;
902  }
903
904  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
905    ARMOperand *Op = new ARMOperand(CoprocReg);
906    Op->Cop.Val = CopVal;
907    Op->StartLoc = S;
908    Op->EndLoc = S;
909    return Op;
910  }
911
912  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
913    ARMOperand *Op = new ARMOperand(CCOut);
914    Op->Reg.RegNum = RegNum;
915    Op->StartLoc = S;
916    Op->EndLoc = S;
917    return Op;
918  }
919
920  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
921    ARMOperand *Op = new ARMOperand(Token);
922    Op->Tok.Data = Str.data();
923    Op->Tok.Length = Str.size();
924    Op->StartLoc = S;
925    Op->EndLoc = S;
926    return Op;
927  }
928
929  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
930    ARMOperand *Op = new ARMOperand(Register);
931    Op->Reg.RegNum = RegNum;
932    Op->StartLoc = S;
933    Op->EndLoc = E;
934    return Op;
935  }
936
937  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
938                                           unsigned SrcReg,
939                                           unsigned ShiftReg,
940                                           unsigned ShiftImm,
941                                           SMLoc S, SMLoc E) {
942    ARMOperand *Op = new ARMOperand(ShiftedRegister);
943    Op->RegShiftedReg.ShiftTy = ShTy;
944    Op->RegShiftedReg.SrcReg = SrcReg;
945    Op->RegShiftedReg.ShiftReg = ShiftReg;
946    Op->RegShiftedReg.ShiftImm = ShiftImm;
947    Op->StartLoc = S;
948    Op->EndLoc = E;
949    return Op;
950  }
951
952  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
953                                            unsigned SrcReg,
954                                            unsigned ShiftImm,
955                                            SMLoc S, SMLoc E) {
956    ARMOperand *Op = new ARMOperand(ShiftedImmediate);
957    Op->RegShiftedImm.ShiftTy = ShTy;
958    Op->RegShiftedImm.SrcReg = SrcReg;
959    Op->RegShiftedImm.ShiftImm = ShiftImm;
960    Op->StartLoc = S;
961    Op->EndLoc = E;
962    return Op;
963  }
964
965  static ARMOperand *CreateShifter(ARM_AM::ShiftOpc ShTy,
966                                   SMLoc S, SMLoc E) {
967    ARMOperand *Op = new ARMOperand(Shifter);
968    Op->Shift.ShiftTy = ShTy;
969    Op->StartLoc = S;
970    Op->EndLoc = E;
971    return Op;
972  }
973
974  static ARMOperand *
975  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
976                SMLoc StartLoc, SMLoc EndLoc) {
977    KindTy Kind = RegisterList;
978
979    if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
980        contains(Regs.front().first))
981      Kind = DPRRegisterList;
982    else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
983             contains(Regs.front().first))
984      Kind = SPRRegisterList;
985
986    ARMOperand *Op = new ARMOperand(Kind);
987    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
988           I = Regs.begin(), E = Regs.end(); I != E; ++I)
989      Op->Registers.push_back(I->first);
990    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
991    Op->StartLoc = StartLoc;
992    Op->EndLoc = EndLoc;
993    return Op;
994  }
995
996  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
997    ARMOperand *Op = new ARMOperand(Immediate);
998    Op->Imm.Val = Val;
999    Op->StartLoc = S;
1000    Op->EndLoc = E;
1001    return Op;
1002  }
1003
1004  static ARMOperand *CreateMem(ARMII::AddrMode AddrMode, unsigned BaseRegNum,
1005                               bool OffsetIsReg, const MCExpr *Offset,
1006                               int OffsetRegNum, bool OffsetRegShifted,
1007                               enum ARM_AM::ShiftOpc ShiftType,
1008                               const MCExpr *ShiftAmount, bool Preindexed,
1009                               bool Postindexed, bool Negative, bool Writeback,
1010                               SMLoc S, SMLoc E) {
1011    assert((OffsetRegNum == -1 || OffsetIsReg) &&
1012           "OffsetRegNum must imply OffsetIsReg!");
1013    assert((!OffsetRegShifted || OffsetIsReg) &&
1014           "OffsetRegShifted must imply OffsetIsReg!");
1015    assert((Offset || OffsetIsReg) &&
1016           "Offset must exists unless register offset is used!");
1017    assert((!ShiftAmount || (OffsetIsReg && OffsetRegShifted)) &&
1018           "Cannot have shift amount without shifted register offset!");
1019    assert((!Offset || !OffsetIsReg) &&
1020           "Cannot have expression offset and register offset!");
1021
1022    ARMOperand *Op = new ARMOperand(Memory);
1023    Op->Mem.AddrMode = AddrMode;
1024    Op->Mem.BaseRegNum = BaseRegNum;
1025    Op->Mem.OffsetIsReg = OffsetIsReg;
1026    if (OffsetIsReg)
1027      Op->Mem.Offset.RegNum = OffsetRegNum;
1028    else
1029      Op->Mem.Offset.Value = Offset;
1030    Op->Mem.OffsetRegShifted = OffsetRegShifted;
1031    Op->Mem.ShiftType = ShiftType;
1032    Op->Mem.ShiftAmount = ShiftAmount;
1033    Op->Mem.Preindexed = Preindexed;
1034    Op->Mem.Postindexed = Postindexed;
1035    Op->Mem.Negative = Negative;
1036    Op->Mem.Writeback = Writeback;
1037
1038    Op->StartLoc = S;
1039    Op->EndLoc = E;
1040    return Op;
1041  }
1042
1043  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1044    ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1045    Op->MBOpt.Val = Opt;
1046    Op->StartLoc = S;
1047    Op->EndLoc = S;
1048    return Op;
1049  }
1050
1051  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1052    ARMOperand *Op = new ARMOperand(ProcIFlags);
1053    Op->IFlags.Val = IFlags;
1054    Op->StartLoc = S;
1055    Op->EndLoc = S;
1056    return Op;
1057  }
1058
1059  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1060    ARMOperand *Op = new ARMOperand(MSRMask);
1061    Op->MMask.Val = MMask;
1062    Op->StartLoc = S;
1063    Op->EndLoc = S;
1064    return Op;
1065  }
1066};
1067
1068} // end anonymous namespace.
1069
1070void ARMOperand::print(raw_ostream &OS) const {
1071  switch (Kind) {
1072  case CondCode:
1073    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1074    break;
1075  case CCOut:
1076    OS << "<ccout " << getReg() << ">";
1077    break;
1078  case CoprocNum:
1079    OS << "<coprocessor number: " << getCoproc() << ">";
1080    break;
1081  case CoprocReg:
1082    OS << "<coprocessor register: " << getCoproc() << ">";
1083    break;
1084  case MSRMask:
1085    OS << "<mask: " << getMSRMask() << ">";
1086    break;
1087  case Immediate:
1088    getImm()->print(OS);
1089    break;
1090  case MemBarrierOpt:
1091    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1092    break;
1093  case Memory:
1094    OS << "<memory "
1095       << "am:" << ARMII::AddrModeToString(getMemAddrMode())
1096       << " base:" << getMemBaseRegNum();
1097    if (getMemOffsetIsReg()) {
1098      OS << " offset:<register " << getMemOffsetRegNum();
1099      if (getMemOffsetRegShifted()) {
1100        OS << " offset-shift-type:" << getMemShiftType();
1101        OS << " offset-shift-amount:" << *getMemShiftAmount();
1102      }
1103    } else {
1104      OS << " offset:" << *getMemOffset();
1105    }
1106    if (getMemOffsetIsReg())
1107      OS << " (offset-is-reg)";
1108    if (getMemPreindexed())
1109      OS << " (pre-indexed)";
1110    if (getMemPostindexed())
1111      OS << " (post-indexed)";
1112    if (getMemNegative())
1113      OS << " (negative)";
1114    if (getMemWriteback())
1115      OS << " (writeback)";
1116    OS << ">";
1117    break;
1118  case ProcIFlags: {
1119    OS << "<ARM_PROC::";
1120    unsigned IFlags = getProcIFlags();
1121    for (int i=2; i >= 0; --i)
1122      if (IFlags & (1 << i))
1123        OS << ARM_PROC::IFlagsToString(1 << i);
1124    OS << ">";
1125    break;
1126  }
1127  case Register:
1128    OS << "<register " << getReg() << ">";
1129    break;
1130  case Shifter:
1131    OS << "<shifter " << ARM_AM::getShiftOpcStr(Shift.ShiftTy) << ">";
1132    break;
1133  case ShiftedRegister:
1134    OS << "<so_reg_reg "
1135       << RegShiftedReg.SrcReg
1136       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1137       << ", " << RegShiftedReg.ShiftReg << ", "
1138       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1139       << ">";
1140    break;
1141  case ShiftedImmediate:
1142    OS << "<so_reg_imm "
1143       << RegShiftedImm.SrcReg
1144       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1145       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1146       << ">";
1147    break;
1148  case RegisterList:
1149  case DPRRegisterList:
1150  case SPRRegisterList: {
1151    OS << "<register_list ";
1152
1153    const SmallVectorImpl<unsigned> &RegList = getRegList();
1154    for (SmallVectorImpl<unsigned>::const_iterator
1155           I = RegList.begin(), E = RegList.end(); I != E; ) {
1156      OS << *I;
1157      if (++I < E) OS << ", ";
1158    }
1159
1160    OS << ">";
1161    break;
1162  }
1163  case Token:
1164    OS << "'" << getToken() << "'";
1165    break;
1166  }
1167}
1168
1169/// @name Auto-generated Match Functions
1170/// {
1171
1172static unsigned MatchRegisterName(StringRef Name);
1173
1174/// }
1175
1176bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1177                                 SMLoc &StartLoc, SMLoc &EndLoc) {
1178  RegNo = TryParseRegister();
1179
1180  return (RegNo == (unsigned)-1);
1181}
1182
1183/// Try to parse a register name.  The token must be an Identifier when called,
1184/// and if it is a register name the token is eaten and the register number is
1185/// returned.  Otherwise return -1.
1186///
1187int ARMAsmParser::TryParseRegister() {
1188  const AsmToken &Tok = Parser.getTok();
1189  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1190
1191  // FIXME: Validate register for the current architecture; we have to do
1192  // validation later, so maybe there is no need for this here.
1193  std::string upperCase = Tok.getString().str();
1194  std::string lowerCase = LowercaseString(upperCase);
1195  unsigned RegNum = MatchRegisterName(lowerCase);
1196  if (!RegNum) {
1197    RegNum = StringSwitch<unsigned>(lowerCase)
1198      .Case("r13", ARM::SP)
1199      .Case("r14", ARM::LR)
1200      .Case("r15", ARM::PC)
1201      .Case("ip", ARM::R12)
1202      .Default(0);
1203  }
1204  if (!RegNum) return -1;
1205
1206  Parser.Lex(); // Eat identifier token.
1207  return RegNum;
1208}
1209
1210// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
1211// If a recoverable error occurs, return 1. If an irrecoverable error
1212// occurs, return -1. An irrecoverable error is one where tokens have been
1213// consumed in the process of trying to parse the shifter (i.e., when it is
1214// indeed a shifter operand, but malformed).
1215int ARMAsmParser::TryParseShiftRegister(
1216                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1217  SMLoc S = Parser.getTok().getLoc();
1218  const AsmToken &Tok = Parser.getTok();
1219  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1220
1221  std::string upperCase = Tok.getString().str();
1222  std::string lowerCase = LowercaseString(upperCase);
1223  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1224      .Case("lsl", ARM_AM::lsl)
1225      .Case("lsr", ARM_AM::lsr)
1226      .Case("asr", ARM_AM::asr)
1227      .Case("ror", ARM_AM::ror)
1228      .Case("rrx", ARM_AM::rrx)
1229      .Default(ARM_AM::no_shift);
1230
1231  if (ShiftTy == ARM_AM::no_shift)
1232    return 1;
1233
1234  Parser.Lex(); // Eat the operator.
1235
1236  // The source register for the shift has already been added to the
1237  // operand list, so we need to pop it off and combine it into the shifted
1238  // register operand instead.
1239  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1240  if (!PrevOp->isReg())
1241    return Error(PrevOp->getStartLoc(), "shift must be of a register");
1242  int SrcReg = PrevOp->getReg();
1243  int64_t Imm = 0;
1244  int ShiftReg = 0;
1245  if (ShiftTy == ARM_AM::rrx) {
1246    // RRX Doesn't have an explicit shift amount. The encoder expects
1247    // the shift register to be the same as the source register. Seems odd,
1248    // but OK.
1249    ShiftReg = SrcReg;
1250  } else {
1251    // Figure out if this is shifted by a constant or a register (for non-RRX).
1252    if (Parser.getTok().is(AsmToken::Hash)) {
1253      Parser.Lex(); // Eat hash.
1254      SMLoc ImmLoc = Parser.getTok().getLoc();
1255      const MCExpr *ShiftExpr = 0;
1256      if (getParser().ParseExpression(ShiftExpr)) {
1257        Error(ImmLoc, "invalid immediate shift value");
1258        return -1;
1259      }
1260      // The expression must be evaluatable as an immediate.
1261      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1262      if (!CE) {
1263        Error(ImmLoc, "invalid immediate shift value");
1264        return -1;
1265      }
1266      // Range check the immediate.
1267      // lsl, ror: 0 <= imm <= 31
1268      // lsr, asr: 0 <= imm <= 32
1269      Imm = CE->getValue();
1270      if (Imm < 0 ||
1271          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1272          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1273        Error(ImmLoc, "immediate shift value out of range");
1274        return -1;
1275      }
1276    } else if (Parser.getTok().is(AsmToken::Identifier)) {
1277      ShiftReg = TryParseRegister();
1278      SMLoc L = Parser.getTok().getLoc();
1279      if (ShiftReg == -1) {
1280        Error (L, "expected immediate or register in shift operand");
1281        return -1;
1282      }
1283    } else {
1284      Error (Parser.getTok().getLoc(),
1285                    "expected immediate or register in shift operand");
1286      return -1;
1287    }
1288  }
1289
1290  if (ShiftReg && ShiftTy != ARM_AM::rrx)
1291    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1292                                                         ShiftReg, Imm,
1293                                               S, Parser.getTok().getLoc()));
1294  else
1295    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1296                                               S, Parser.getTok().getLoc()));
1297
1298  return 0;
1299}
1300
1301
1302/// Try to parse a register name.  The token must be an Identifier when called.
1303/// If it's a register, an AsmOperand is created. Another AsmOperand is created
1304/// if there is a "writeback". 'true' if it's not a register.
1305///
1306/// TODO this is likely to change to allow different register types and or to
1307/// parse for a specific register type.
1308bool ARMAsmParser::
1309TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1310  SMLoc S = Parser.getTok().getLoc();
1311  int RegNo = TryParseRegister();
1312  if (RegNo == -1)
1313    return true;
1314
1315  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1316
1317  const AsmToken &ExclaimTok = Parser.getTok();
1318  if (ExclaimTok.is(AsmToken::Exclaim)) {
1319    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1320                                               ExclaimTok.getLoc()));
1321    Parser.Lex(); // Eat exclaim token
1322  }
1323
1324  return false;
1325}
1326
1327/// MatchCoprocessorOperandName - Try to parse an coprocessor related
1328/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1329/// "c5", ...
1330static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1331  // Use the same layout as the tablegen'erated register name matcher. Ugly,
1332  // but efficient.
1333  switch (Name.size()) {
1334  default: break;
1335  case 2:
1336    if (Name[0] != CoprocOp)
1337      return -1;
1338    switch (Name[1]) {
1339    default:  return -1;
1340    case '0': return 0;
1341    case '1': return 1;
1342    case '2': return 2;
1343    case '3': return 3;
1344    case '4': return 4;
1345    case '5': return 5;
1346    case '6': return 6;
1347    case '7': return 7;
1348    case '8': return 8;
1349    case '9': return 9;
1350    }
1351    break;
1352  case 3:
1353    if (Name[0] != CoprocOp || Name[1] != '1')
1354      return -1;
1355    switch (Name[2]) {
1356    default:  return -1;
1357    case '0': return 10;
1358    case '1': return 11;
1359    case '2': return 12;
1360    case '3': return 13;
1361    case '4': return 14;
1362    case '5': return 15;
1363    }
1364    break;
1365  }
1366
1367  return -1;
1368}
1369
1370/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1371/// token must be an Identifier when called, and if it is a coprocessor
1372/// number, the token is eaten and the operand is added to the operand list.
1373ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1374parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1375  SMLoc S = Parser.getTok().getLoc();
1376  const AsmToken &Tok = Parser.getTok();
1377  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1378
1379  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1380  if (Num == -1)
1381    return MatchOperand_NoMatch;
1382
1383  Parser.Lex(); // Eat identifier token.
1384  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1385  return MatchOperand_Success;
1386}
1387
1388/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1389/// token must be an Identifier when called, and if it is a coprocessor
1390/// number, the token is eaten and the operand is added to the operand list.
1391ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1392parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1393  SMLoc S = Parser.getTok().getLoc();
1394  const AsmToken &Tok = Parser.getTok();
1395  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1396
1397  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1398  if (Reg == -1)
1399    return MatchOperand_NoMatch;
1400
1401  Parser.Lex(); // Eat identifier token.
1402  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1403  return MatchOperand_Success;
1404}
1405
1406/// Parse a register list, return it if successful else return null.  The first
1407/// token must be a '{' when called.
1408bool ARMAsmParser::
1409ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1410  assert(Parser.getTok().is(AsmToken::LCurly) &&
1411         "Token is not a Left Curly Brace");
1412  SMLoc S = Parser.getTok().getLoc();
1413
1414  // Read the rest of the registers in the list.
1415  unsigned PrevRegNum = 0;
1416  SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1417
1418  do {
1419    bool IsRange = Parser.getTok().is(AsmToken::Minus);
1420    Parser.Lex(); // Eat non-identifier token.
1421
1422    const AsmToken &RegTok = Parser.getTok();
1423    SMLoc RegLoc = RegTok.getLoc();
1424    if (RegTok.isNot(AsmToken::Identifier)) {
1425      Error(RegLoc, "register expected");
1426      return true;
1427    }
1428
1429    int RegNum = TryParseRegister();
1430    if (RegNum == -1) {
1431      Error(RegLoc, "register expected");
1432      return true;
1433    }
1434
1435    if (IsRange) {
1436      int Reg = PrevRegNum;
1437      do {
1438        ++Reg;
1439        Registers.push_back(std::make_pair(Reg, RegLoc));
1440      } while (Reg != RegNum);
1441    } else {
1442      Registers.push_back(std::make_pair(RegNum, RegLoc));
1443    }
1444
1445    PrevRegNum = RegNum;
1446  } while (Parser.getTok().is(AsmToken::Comma) ||
1447           Parser.getTok().is(AsmToken::Minus));
1448
1449  // Process the right curly brace of the list.
1450  const AsmToken &RCurlyTok = Parser.getTok();
1451  if (RCurlyTok.isNot(AsmToken::RCurly)) {
1452    Error(RCurlyTok.getLoc(), "'}' expected");
1453    return true;
1454  }
1455
1456  SMLoc E = RCurlyTok.getLoc();
1457  Parser.Lex(); // Eat right curly brace token.
1458
1459  // Verify the register list.
1460  SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1461    RI = Registers.begin(), RE = Registers.end();
1462
1463  unsigned HighRegNum = getARMRegisterNumbering(RI->first);
1464  bool EmittedWarning = false;
1465
1466  DenseMap<unsigned, bool> RegMap;
1467  RegMap[HighRegNum] = true;
1468
1469  for (++RI; RI != RE; ++RI) {
1470    const std::pair<unsigned, SMLoc> &RegInfo = *RI;
1471    unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1472
1473    if (RegMap[Reg]) {
1474      Error(RegInfo.second, "register duplicated in register list");
1475      return true;
1476    }
1477
1478    if (!EmittedWarning && Reg < HighRegNum)
1479      Warning(RegInfo.second,
1480              "register not in ascending order in register list");
1481
1482    RegMap[Reg] = true;
1483    HighRegNum = std::max(Reg, HighRegNum);
1484  }
1485
1486  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1487  return false;
1488}
1489
1490/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1491ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1492parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1493  SMLoc S = Parser.getTok().getLoc();
1494  const AsmToken &Tok = Parser.getTok();
1495  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1496  StringRef OptStr = Tok.getString();
1497
1498  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1499    .Case("sy",    ARM_MB::SY)
1500    .Case("st",    ARM_MB::ST)
1501    .Case("sh",    ARM_MB::ISH)
1502    .Case("ish",   ARM_MB::ISH)
1503    .Case("shst",  ARM_MB::ISHST)
1504    .Case("ishst", ARM_MB::ISHST)
1505    .Case("nsh",   ARM_MB::NSH)
1506    .Case("un",    ARM_MB::NSH)
1507    .Case("nshst", ARM_MB::NSHST)
1508    .Case("unst",  ARM_MB::NSHST)
1509    .Case("osh",   ARM_MB::OSH)
1510    .Case("oshst", ARM_MB::OSHST)
1511    .Default(~0U);
1512
1513  if (Opt == ~0U)
1514    return MatchOperand_NoMatch;
1515
1516  Parser.Lex(); // Eat identifier token.
1517  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1518  return MatchOperand_Success;
1519}
1520
1521/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1522ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1523parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1524  SMLoc S = Parser.getTok().getLoc();
1525  const AsmToken &Tok = Parser.getTok();
1526  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1527  StringRef IFlagsStr = Tok.getString();
1528
1529  unsigned IFlags = 0;
1530  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1531    unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1532    .Case("a", ARM_PROC::A)
1533    .Case("i", ARM_PROC::I)
1534    .Case("f", ARM_PROC::F)
1535    .Default(~0U);
1536
1537    // If some specific iflag is already set, it means that some letter is
1538    // present more than once, this is not acceptable.
1539    if (Flag == ~0U || (IFlags & Flag))
1540      return MatchOperand_NoMatch;
1541
1542    IFlags |= Flag;
1543  }
1544
1545  Parser.Lex(); // Eat identifier token.
1546  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1547  return MatchOperand_Success;
1548}
1549
1550/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1551ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1552parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1553  SMLoc S = Parser.getTok().getLoc();
1554  const AsmToken &Tok = Parser.getTok();
1555  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1556  StringRef Mask = Tok.getString();
1557
1558  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1559  size_t Start = 0, Next = Mask.find('_');
1560  StringRef Flags = "";
1561  std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1562  if (Next != StringRef::npos)
1563    Flags = Mask.slice(Next+1, Mask.size());
1564
1565  // FlagsVal contains the complete mask:
1566  // 3-0: Mask
1567  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1568  unsigned FlagsVal = 0;
1569
1570  if (SpecReg == "apsr") {
1571    FlagsVal = StringSwitch<unsigned>(Flags)
1572    .Case("nzcvq",  0x8) // same as CPSR_f
1573    .Case("g",      0x4) // same as CPSR_s
1574    .Case("nzcvqg", 0xc) // same as CPSR_fs
1575    .Default(~0U);
1576
1577    if (FlagsVal == ~0U) {
1578      if (!Flags.empty())
1579        return MatchOperand_NoMatch;
1580      else
1581        FlagsVal = 0; // No flag
1582    }
1583  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1584    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1585      Flags = "fc";
1586    for (int i = 0, e = Flags.size(); i != e; ++i) {
1587      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1588      .Case("c", 1)
1589      .Case("x", 2)
1590      .Case("s", 4)
1591      .Case("f", 8)
1592      .Default(~0U);
1593
1594      // If some specific flag is already set, it means that some letter is
1595      // present more than once, this is not acceptable.
1596      if (FlagsVal == ~0U || (FlagsVal & Flag))
1597        return MatchOperand_NoMatch;
1598      FlagsVal |= Flag;
1599    }
1600  } else // No match for special register.
1601    return MatchOperand_NoMatch;
1602
1603  // Special register without flags are equivalent to "fc" flags.
1604  if (!FlagsVal)
1605    FlagsVal = 0x9;
1606
1607  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1608  if (SpecReg == "spsr")
1609    FlagsVal |= 16;
1610
1611  Parser.Lex(); // Eat identifier token.
1612  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1613  return MatchOperand_Success;
1614}
1615
1616/// parseMemMode2Operand - Try to parse memory addressing mode 2 operand.
1617ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1618parseMemMode2Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1619  assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
1620
1621  if (ParseMemory(Operands, ARMII::AddrMode2))
1622    return MatchOperand_NoMatch;
1623
1624  return MatchOperand_Success;
1625}
1626
1627/// parseMemMode3Operand - Try to parse memory addressing mode 3 operand.
1628ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1629parseMemMode3Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1630  assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
1631
1632  if (ParseMemory(Operands, ARMII::AddrMode3))
1633    return MatchOperand_NoMatch;
1634
1635  return MatchOperand_Success;
1636}
1637
1638ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1639parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1640            int Low, int High) {
1641  const AsmToken &Tok = Parser.getTok();
1642  if (Tok.isNot(AsmToken::Identifier)) {
1643    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1644    return MatchOperand_ParseFail;
1645  }
1646  StringRef ShiftName = Tok.getString();
1647  std::string LowerOp = LowercaseString(Op);
1648  std::string UpperOp = UppercaseString(Op);
1649  if (ShiftName != LowerOp && ShiftName != UpperOp) {
1650    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1651    return MatchOperand_ParseFail;
1652  }
1653  Parser.Lex(); // Eat shift type token.
1654
1655  // There must be a '#' and a shift amount.
1656  if (Parser.getTok().isNot(AsmToken::Hash)) {
1657    Error(Parser.getTok().getLoc(), "'#' expected");
1658    return MatchOperand_ParseFail;
1659  }
1660  Parser.Lex(); // Eat hash token.
1661
1662  const MCExpr *ShiftAmount;
1663  SMLoc Loc = Parser.getTok().getLoc();
1664  if (getParser().ParseExpression(ShiftAmount)) {
1665    Error(Loc, "illegal expression");
1666    return MatchOperand_ParseFail;
1667  }
1668  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1669  if (!CE) {
1670    Error(Loc, "constant expression expected");
1671    return MatchOperand_ParseFail;
1672  }
1673  int Val = CE->getValue();
1674  if (Val < Low || Val > High) {
1675    Error(Loc, "immediate value out of range");
1676    return MatchOperand_ParseFail;
1677  }
1678
1679  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1680
1681  return MatchOperand_Success;
1682}
1683
1684ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1685parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1686  const AsmToken &Tok = Parser.getTok();
1687  SMLoc S = Tok.getLoc();
1688  if (Tok.isNot(AsmToken::Identifier)) {
1689    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1690    return MatchOperand_ParseFail;
1691  }
1692  int Val = StringSwitch<int>(Tok.getString())
1693    .Case("be", 1)
1694    .Case("le", 0)
1695    .Default(-1);
1696  Parser.Lex(); // Eat the token.
1697
1698  if (Val == -1) {
1699    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1700    return MatchOperand_ParseFail;
1701  }
1702  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1703                                                                  getContext()),
1704                                           S, Parser.getTok().getLoc()));
1705  return MatchOperand_Success;
1706}
1707
1708/// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
1709/// Needed here because the Asm Gen Matcher can't handle properly tied operands
1710/// when they refer multiple MIOperands inside a single one.
1711bool ARMAsmParser::
1712CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
1713                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1714  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1715
1716  // Create a writeback register dummy placeholder.
1717  Inst.addOperand(MCOperand::CreateImm(0));
1718
1719  ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
1720  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1721  return true;
1722}
1723
1724/// CvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
1725/// Needed here because the Asm Gen Matcher can't handle properly tied operands
1726/// when they refer multiple MIOperands inside a single one.
1727bool ARMAsmParser::
1728CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
1729                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1730  // Create a writeback register dummy placeholder.
1731  Inst.addOperand(MCOperand::CreateImm(0));
1732  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1733  ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
1734  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1735  return true;
1736}
1737
1738/// CvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
1739/// Needed here because the Asm Gen Matcher can't handle properly tied operands
1740/// when they refer multiple MIOperands inside a single one.
1741bool ARMAsmParser::
1742CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
1743                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1744  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1745
1746  // Create a writeback register dummy placeholder.
1747  Inst.addOperand(MCOperand::CreateImm(0));
1748
1749  ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
1750  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1751  return true;
1752}
1753
1754/// CvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
1755/// Needed here because the Asm Gen Matcher can't handle properly tied operands
1756/// when they refer multiple MIOperands inside a single one.
1757bool ARMAsmParser::
1758CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
1759                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1760  // Create a writeback register dummy placeholder.
1761  Inst.addOperand(MCOperand::CreateImm(0));
1762  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1763  ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
1764  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1765  return true;
1766}
1767
1768/// Parse an ARM memory expression, return false if successful else return true
1769/// or an error.  The first token must be a '[' when called.
1770///
1771/// TODO Only preindexing and postindexing addressing are started, unindexed
1772/// with option, etc are still to do.
1773bool ARMAsmParser::
1774ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1775            ARMII::AddrMode AddrMode = ARMII::AddrModeNone) {
1776  SMLoc S, E;
1777  assert(Parser.getTok().is(AsmToken::LBrac) &&
1778         "Token is not a Left Bracket");
1779  S = Parser.getTok().getLoc();
1780  Parser.Lex(); // Eat left bracket token.
1781
1782  const AsmToken &BaseRegTok = Parser.getTok();
1783  if (BaseRegTok.isNot(AsmToken::Identifier)) {
1784    Error(BaseRegTok.getLoc(), "register expected");
1785    return true;
1786  }
1787  int BaseRegNum = TryParseRegister();
1788  if (BaseRegNum == -1) {
1789    Error(BaseRegTok.getLoc(), "register expected");
1790    return true;
1791  }
1792
1793  // The next token must either be a comma or a closing bracket.
1794  const AsmToken &Tok = Parser.getTok();
1795  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
1796    return true;
1797
1798  bool Preindexed = false;
1799  bool Postindexed = false;
1800  bool OffsetIsReg = false;
1801  bool Negative = false;
1802  bool Writeback = false;
1803  ARMOperand *WBOp = 0;
1804  int OffsetRegNum = -1;
1805  bool OffsetRegShifted = false;
1806  enum ARM_AM::ShiftOpc ShiftType = ARM_AM::lsl;
1807  const MCExpr *ShiftAmount = 0;
1808  const MCExpr *Offset = 0;
1809
1810  // First look for preindexed address forms, that is after the "[Rn" we now
1811  // have to see if the next token is a comma.
1812  if (Tok.is(AsmToken::Comma)) {
1813    Preindexed = true;
1814    Parser.Lex(); // Eat comma token.
1815
1816    if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
1817                             Offset, OffsetIsReg, OffsetRegNum, E))
1818      return true;
1819    const AsmToken &RBracTok = Parser.getTok();
1820    if (RBracTok.isNot(AsmToken::RBrac)) {
1821      Error(RBracTok.getLoc(), "']' expected");
1822      return true;
1823    }
1824    E = RBracTok.getLoc();
1825    Parser.Lex(); // Eat right bracket token.
1826
1827    const AsmToken &ExclaimTok = Parser.getTok();
1828    if (ExclaimTok.is(AsmToken::Exclaim)) {
1829      // None of addrmode3 instruction uses "!"
1830      if (AddrMode == ARMII::AddrMode3)
1831        return true;
1832
1833      WBOp = ARMOperand::CreateToken(ExclaimTok.getString(),
1834                                     ExclaimTok.getLoc());
1835      Writeback = true;
1836      Parser.Lex(); // Eat exclaim token
1837    } else { // In addressing mode 2, pre-indexed mode always end with "!"
1838      if (AddrMode == ARMII::AddrMode2)
1839        Preindexed = false;
1840    }
1841  } else {
1842    // The "[Rn" we have so far was not followed by a comma.
1843
1844    // If there's anything other than the right brace, this is a post indexing
1845    // addressing form.
1846    E = Tok.getLoc();
1847    Parser.Lex(); // Eat right bracket token.
1848
1849    const AsmToken &NextTok = Parser.getTok();
1850
1851    if (NextTok.isNot(AsmToken::EndOfStatement)) {
1852      Postindexed = true;
1853      Writeback = true;
1854
1855      if (NextTok.isNot(AsmToken::Comma)) {
1856        Error(NextTok.getLoc(), "',' expected");
1857        return true;
1858      }
1859
1860      Parser.Lex(); // Eat comma token.
1861
1862      if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
1863                               ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
1864                               E))
1865        return true;
1866    }
1867  }
1868
1869  // Force Offset to exist if used.
1870  if (!OffsetIsReg) {
1871    if (!Offset)
1872      Offset = MCConstantExpr::Create(0, getContext());
1873  } else {
1874    if (AddrMode == ARMII::AddrMode3 && OffsetRegShifted) {
1875      Error(E, "shift amount not supported");
1876      return true;
1877    }
1878  }
1879
1880  Operands.push_back(ARMOperand::CreateMem(AddrMode, BaseRegNum, OffsetIsReg,
1881                                     Offset, OffsetRegNum, OffsetRegShifted,
1882                                     ShiftType, ShiftAmount, Preindexed,
1883                                     Postindexed, Negative, Writeback, S, E));
1884  if (WBOp)
1885    Operands.push_back(WBOp);
1886
1887  return false;
1888}
1889
1890/// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
1891/// we will parse the following (were +/- means that a plus or minus is
1892/// optional):
1893///   +/-Rm
1894///   +/-Rm, shift
1895///   #offset
1896/// we return false on success or an error otherwise.
1897bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
1898                                        bool &OffsetRegShifted,
1899                                        enum ARM_AM::ShiftOpc &ShiftType,
1900                                        const MCExpr *&ShiftAmount,
1901                                        const MCExpr *&Offset,
1902                                        bool &OffsetIsReg,
1903                                        int &OffsetRegNum,
1904                                        SMLoc &E) {
1905  Negative = false;
1906  OffsetRegShifted = false;
1907  OffsetIsReg = false;
1908  OffsetRegNum = -1;
1909  const AsmToken &NextTok = Parser.getTok();
1910  E = NextTok.getLoc();
1911  if (NextTok.is(AsmToken::Plus))
1912    Parser.Lex(); // Eat plus token.
1913  else if (NextTok.is(AsmToken::Minus)) {
1914    Negative = true;
1915    Parser.Lex(); // Eat minus token
1916  }
1917  // See if there is a register following the "[Rn," or "[Rn]," we have so far.
1918  const AsmToken &OffsetRegTok = Parser.getTok();
1919  if (OffsetRegTok.is(AsmToken::Identifier)) {
1920    SMLoc CurLoc = OffsetRegTok.getLoc();
1921    OffsetRegNum = TryParseRegister();
1922    if (OffsetRegNum != -1) {
1923      OffsetIsReg = true;
1924      E = CurLoc;
1925    }
1926  }
1927
1928  // If we parsed a register as the offset then there can be a shift after that.
1929  if (OffsetRegNum != -1) {
1930    // Look for a comma then a shift
1931    const AsmToken &Tok = Parser.getTok();
1932    if (Tok.is(AsmToken::Comma)) {
1933      Parser.Lex(); // Eat comma token.
1934
1935      const AsmToken &Tok = Parser.getTok();
1936      if (ParseShift(ShiftType, ShiftAmount, E))
1937        return Error(Tok.getLoc(), "shift expected");
1938      OffsetRegShifted = true;
1939    }
1940  }
1941  else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
1942    // Look for #offset following the "[Rn," or "[Rn],"
1943    const AsmToken &HashTok = Parser.getTok();
1944    if (HashTok.isNot(AsmToken::Hash))
1945      return Error(HashTok.getLoc(), "'#' expected");
1946
1947    Parser.Lex(); // Eat hash token.
1948
1949    if (getParser().ParseExpression(Offset))
1950     return true;
1951    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1952  }
1953  return false;
1954}
1955
1956/// ParseShift as one of these two:
1957///   ( lsl | lsr | asr | ror ) , # shift_amount
1958///   rrx
1959/// and returns true if it parses a shift otherwise it returns false.
1960bool ARMAsmParser::ParseShift(ARM_AM::ShiftOpc &St,
1961                              const MCExpr *&ShiftAmount, SMLoc &E) {
1962  const AsmToken &Tok = Parser.getTok();
1963  if (Tok.isNot(AsmToken::Identifier))
1964    return true;
1965  StringRef ShiftName = Tok.getString();
1966  if (ShiftName == "lsl" || ShiftName == "LSL")
1967    St = ARM_AM::lsl;
1968  else if (ShiftName == "lsr" || ShiftName == "LSR")
1969    St = ARM_AM::lsr;
1970  else if (ShiftName == "asr" || ShiftName == "ASR")
1971    St = ARM_AM::asr;
1972  else if (ShiftName == "ror" || ShiftName == "ROR")
1973    St = ARM_AM::ror;
1974  else if (ShiftName == "rrx" || ShiftName == "RRX")
1975    St = ARM_AM::rrx;
1976  else
1977    return true;
1978  Parser.Lex(); // Eat shift type token.
1979
1980  // Rrx stands alone.
1981  if (St == ARM_AM::rrx)
1982    return false;
1983
1984  // Otherwise, there must be a '#' and a shift amount.
1985  const AsmToken &HashTok = Parser.getTok();
1986  if (HashTok.isNot(AsmToken::Hash))
1987    return Error(HashTok.getLoc(), "'#' expected");
1988  Parser.Lex(); // Eat hash token.
1989
1990  if (getParser().ParseExpression(ShiftAmount))
1991    return true;
1992
1993  return false;
1994}
1995
1996/// Parse a arm instruction operand.  For now this parses the operand regardless
1997/// of the mnemonic.
1998bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1999                                StringRef Mnemonic) {
2000  SMLoc S, E;
2001
2002  // Check if the current operand has a custom associated parser, if so, try to
2003  // custom parse the operand, or fallback to the general approach.
2004  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2005  if (ResTy == MatchOperand_Success)
2006    return false;
2007  // If there wasn't a custom match, try the generic matcher below. Otherwise,
2008  // there was a match, but an error occurred, in which case, just return that
2009  // the operand parsing failed.
2010  if (ResTy == MatchOperand_ParseFail)
2011    return true;
2012
2013  switch (getLexer().getKind()) {
2014  default:
2015    Error(Parser.getTok().getLoc(), "unexpected token in operand");
2016    return true;
2017  case AsmToken::Identifier: {
2018    if (!TryParseRegisterWithWriteBack(Operands))
2019      return false;
2020    int Res = TryParseShiftRegister(Operands);
2021    if (Res == 0) // success
2022      return false;
2023    else if (Res == -1) // irrecoverable error
2024      return true;
2025
2026    // Fall though for the Identifier case that is not a register or a
2027    // special name.
2028  }
2029  case AsmToken::Integer: // things like 1f and 2b as a branch targets
2030  case AsmToken::Dot: {   // . as a branch target
2031    // This was not a register so parse other operands that start with an
2032    // identifier (like labels) as expressions and create them as immediates.
2033    const MCExpr *IdVal;
2034    S = Parser.getTok().getLoc();
2035    if (getParser().ParseExpression(IdVal))
2036      return true;
2037    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2038    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2039    return false;
2040  }
2041  case AsmToken::LBrac:
2042    return ParseMemory(Operands);
2043  case AsmToken::LCurly:
2044    return ParseRegisterList(Operands);
2045  case AsmToken::Hash:
2046    // #42 -> immediate.
2047    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2048    S = Parser.getTok().getLoc();
2049    Parser.Lex();
2050    const MCExpr *ImmVal;
2051    if (getParser().ParseExpression(ImmVal))
2052      return true;
2053    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2054    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2055    return false;
2056  case AsmToken::Colon: {
2057    // ":lower16:" and ":upper16:" expression prefixes
2058    // FIXME: Check it's an expression prefix,
2059    // e.g. (FOO - :lower16:BAR) isn't legal.
2060    ARMMCExpr::VariantKind RefKind;
2061    if (ParsePrefix(RefKind))
2062      return true;
2063
2064    const MCExpr *SubExprVal;
2065    if (getParser().ParseExpression(SubExprVal))
2066      return true;
2067
2068    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2069                                                   getContext());
2070    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2071    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2072    return false;
2073  }
2074  }
2075}
2076
2077// ParsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2078//  :lower16: and :upper16:.
2079bool ARMAsmParser::ParsePrefix(ARMMCExpr::VariantKind &RefKind) {
2080  RefKind = ARMMCExpr::VK_ARM_None;
2081
2082  // :lower16: and :upper16: modifiers
2083  assert(getLexer().is(AsmToken::Colon) && "expected a :");
2084  Parser.Lex(); // Eat ':'
2085
2086  if (getLexer().isNot(AsmToken::Identifier)) {
2087    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2088    return true;
2089  }
2090
2091  StringRef IDVal = Parser.getTok().getIdentifier();
2092  if (IDVal == "lower16") {
2093    RefKind = ARMMCExpr::VK_ARM_LO16;
2094  } else if (IDVal == "upper16") {
2095    RefKind = ARMMCExpr::VK_ARM_HI16;
2096  } else {
2097    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2098    return true;
2099  }
2100  Parser.Lex();
2101
2102  if (getLexer().isNot(AsmToken::Colon)) {
2103    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2104    return true;
2105  }
2106  Parser.Lex(); // Eat the last ':'
2107  return false;
2108}
2109
2110const MCExpr *
2111ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E,
2112                                MCSymbolRefExpr::VariantKind Variant) {
2113  // Recurse over the given expression, rebuilding it to apply the given variant
2114  // to the leftmost symbol.
2115  if (Variant == MCSymbolRefExpr::VK_None)
2116    return E;
2117
2118  switch (E->getKind()) {
2119  case MCExpr::Target:
2120    llvm_unreachable("Can't handle target expr yet");
2121  case MCExpr::Constant:
2122    llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2123
2124  case MCExpr::SymbolRef: {
2125    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2126
2127    if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2128      return 0;
2129
2130    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2131  }
2132
2133  case MCExpr::Unary:
2134    llvm_unreachable("Can't handle unary expressions yet");
2135
2136  case MCExpr::Binary: {
2137    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2138    const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant);
2139    const MCExpr *RHS = BE->getRHS();
2140    if (!LHS)
2141      return 0;
2142
2143    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2144  }
2145  }
2146
2147  assert(0 && "Invalid expression kind!");
2148  return 0;
2149}
2150
2151/// \brief Given a mnemonic, split out possible predication code and carry
2152/// setting letters to form a canonical mnemonic and flags.
2153//
2154// FIXME: Would be nice to autogen this.
2155StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic,
2156                                      unsigned &PredicationCode,
2157                                      bool &CarrySetting,
2158                                      unsigned &ProcessorIMod) {
2159  PredicationCode = ARMCC::AL;
2160  CarrySetting = false;
2161  ProcessorIMod = 0;
2162
2163  // Ignore some mnemonics we know aren't predicated forms.
2164  //
2165  // FIXME: Would be nice to autogen this.
2166  if ((Mnemonic == "movs" && isThumb()) ||
2167      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
2168      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
2169      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
2170      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
2171      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
2172      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
2173      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2174    return Mnemonic;
2175
2176  // First, split out any predication code. Ignore mnemonics we know aren't
2177  // predicated but do have a carry-set and so weren't caught above.
2178  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2179      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls") {
2180    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2181      .Case("eq", ARMCC::EQ)
2182      .Case("ne", ARMCC::NE)
2183      .Case("hs", ARMCC::HS)
2184      .Case("cs", ARMCC::HS)
2185      .Case("lo", ARMCC::LO)
2186      .Case("cc", ARMCC::LO)
2187      .Case("mi", ARMCC::MI)
2188      .Case("pl", ARMCC::PL)
2189      .Case("vs", ARMCC::VS)
2190      .Case("vc", ARMCC::VC)
2191      .Case("hi", ARMCC::HI)
2192      .Case("ls", ARMCC::LS)
2193      .Case("ge", ARMCC::GE)
2194      .Case("lt", ARMCC::LT)
2195      .Case("gt", ARMCC::GT)
2196      .Case("le", ARMCC::LE)
2197      .Case("al", ARMCC::AL)
2198      .Default(~0U);
2199    if (CC != ~0U) {
2200      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2201      PredicationCode = CC;
2202    }
2203  }
2204
2205  // Next, determine if we have a carry setting bit. We explicitly ignore all
2206  // the instructions we know end in 's'.
2207  if (Mnemonic.endswith("s") &&
2208      !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" ||
2209        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2210        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2211        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2212        Mnemonic == "vrsqrts" || (Mnemonic == "movs" && isThumb()))) {
2213    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2214    CarrySetting = true;
2215  }
2216
2217  // The "cps" instruction can have a interrupt mode operand which is glued into
2218  // the mnemonic. Check if this is the case, split it and parse the imod op
2219  if (Mnemonic.startswith("cps")) {
2220    // Split out any imod code.
2221    unsigned IMod =
2222      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2223      .Case("ie", ARM_PROC::IE)
2224      .Case("id", ARM_PROC::ID)
2225      .Default(~0U);
2226    if (IMod != ~0U) {
2227      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2228      ProcessorIMod = IMod;
2229    }
2230  }
2231
2232  return Mnemonic;
2233}
2234
2235/// \brief Given a canonical mnemonic, determine if the instruction ever allows
2236/// inclusion of carry set or predication code operands.
2237//
2238// FIXME: It would be nice to autogen this.
2239void ARMAsmParser::
2240GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2241                      bool &CanAcceptPredicationCode) {
2242  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2243      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2244      Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2245      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2246      Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2247      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2248      Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2249      Mnemonic == "eor" || Mnemonic == "smlal" ||
2250      (Mnemonic == "mov" && !isThumbOne())) {
2251    CanAcceptCarrySet = true;
2252  } else {
2253    CanAcceptCarrySet = false;
2254  }
2255
2256  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2257      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2258      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2259      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2260      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2261      Mnemonic == "setend" ||
2262      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2263    CanAcceptPredicationCode = false;
2264  } else {
2265    CanAcceptPredicationCode = true;
2266  }
2267
2268  if (isThumb())
2269    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2270        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2271      CanAcceptPredicationCode = false;
2272}
2273
2274/// Parse an arm instruction mnemonic followed by its operands.
2275bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2276                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2277  // Create the leading tokens for the mnemonic, split by '.' characters.
2278  size_t Start = 0, Next = Name.find('.');
2279  StringRef Mnemonic = Name.slice(Start, Next);
2280
2281  // Split out the predication code and carry setting flag from the mnemonic.
2282  unsigned PredicationCode;
2283  unsigned ProcessorIMod;
2284  bool CarrySetting;
2285  Mnemonic = SplitMnemonic(Mnemonic, PredicationCode, CarrySetting,
2286                           ProcessorIMod);
2287
2288  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
2289
2290  // FIXME: This is all a pretty gross hack. We should automatically handle
2291  // optional operands like this via tblgen.
2292
2293  // Next, add the CCOut and ConditionCode operands, if needed.
2294  //
2295  // For mnemonics which can ever incorporate a carry setting bit or predication
2296  // code, our matching model involves us always generating CCOut and
2297  // ConditionCode operands to match the mnemonic "as written" and then we let
2298  // the matcher deal with finding the right instruction or generating an
2299  // appropriate error.
2300  bool CanAcceptCarrySet, CanAcceptPredicationCode;
2301  GetMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
2302
2303  // If we had a carry-set on an instruction that can't do that, issue an
2304  // error.
2305  if (!CanAcceptCarrySet && CarrySetting) {
2306    Parser.EatToEndOfStatement();
2307    return Error(NameLoc, "instruction '" + Mnemonic +
2308                 "' can not set flags, but 's' suffix specified");
2309  }
2310  // If we had a predication code on an instruction that can't do that, issue an
2311  // error.
2312  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
2313    Parser.EatToEndOfStatement();
2314    return Error(NameLoc, "instruction '" + Mnemonic +
2315                 "' is not predicable, but condition code specified");
2316  }
2317
2318  // Add the carry setting operand, if necessary.
2319  //
2320  // FIXME: It would be awesome if we could somehow invent a location such that
2321  // match errors on this operand would print a nice diagnostic about how the
2322  // 's' character in the mnemonic resulted in a CCOut operand.
2323  if (CanAcceptCarrySet)
2324    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
2325                                               NameLoc));
2326
2327  // Add the predication code operand, if necessary.
2328  if (CanAcceptPredicationCode) {
2329    Operands.push_back(ARMOperand::CreateCondCode(
2330                         ARMCC::CondCodes(PredicationCode), NameLoc));
2331  }
2332
2333  // Add the processor imod operand, if necessary.
2334  if (ProcessorIMod) {
2335    Operands.push_back(ARMOperand::CreateImm(
2336          MCConstantExpr::Create(ProcessorIMod, getContext()),
2337                                 NameLoc, NameLoc));
2338  } else {
2339    // This mnemonic can't ever accept a imod, but the user wrote
2340    // one (or misspelled another mnemonic).
2341
2342    // FIXME: Issue a nice error.
2343  }
2344
2345  // Add the remaining tokens in the mnemonic.
2346  while (Next != StringRef::npos) {
2347    Start = Next;
2348    Next = Name.find('.', Start + 1);
2349    StringRef ExtraToken = Name.slice(Start, Next);
2350
2351    Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
2352  }
2353
2354  // Read the remaining operands.
2355  if (getLexer().isNot(AsmToken::EndOfStatement)) {
2356    // Read the first operand.
2357    if (ParseOperand(Operands, Mnemonic)) {
2358      Parser.EatToEndOfStatement();
2359      return true;
2360    }
2361
2362    while (getLexer().is(AsmToken::Comma)) {
2363      Parser.Lex();  // Eat the comma.
2364
2365      // Parse and remember the operand.
2366      if (ParseOperand(Operands, Mnemonic)) {
2367        Parser.EatToEndOfStatement();
2368        return true;
2369      }
2370    }
2371  }
2372
2373  if (getLexer().isNot(AsmToken::EndOfStatement)) {
2374    Parser.EatToEndOfStatement();
2375    return TokError("unexpected token in argument list");
2376  }
2377
2378  Parser.Lex(); // Consume the EndOfStatement
2379
2380
2381  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2382  // another does not. Specifically, the MOVW instruction does not. So we
2383  // special case it here and remove the defaulted (non-setting) cc_out
2384  // operand if that's the instruction we're trying to match.
2385  //
2386  // We do this post-processing of the explicit operands rather than just
2387  // conditionally adding the cc_out in the first place because we need
2388  // to check the type of the parsed immediate operand.
2389  if (Mnemonic == "mov" && Operands.size() > 4 &&
2390      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
2391      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
2392      static_cast<ARMOperand*>(Operands[1])->getReg() == 0) {
2393    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2394    Operands.erase(Operands.begin() + 1);
2395    delete Op;
2396  }
2397
2398  return false;
2399}
2400
2401bool ARMAsmParser::
2402MatchAndEmitInstruction(SMLoc IDLoc,
2403                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2404                        MCStreamer &Out) {
2405  MCInst Inst;
2406  unsigned ErrorInfo;
2407  MatchResultTy MatchResult;
2408  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
2409  switch (MatchResult) {
2410  case Match_Success:
2411    Out.EmitInstruction(Inst);
2412    return false;
2413  case Match_MissingFeature:
2414    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
2415    return true;
2416  case Match_InvalidOperand: {
2417    SMLoc ErrorLoc = IDLoc;
2418    if (ErrorInfo != ~0U) {
2419      if (ErrorInfo >= Operands.size())
2420        return Error(IDLoc, "too few operands for instruction");
2421
2422      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
2423      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
2424    }
2425
2426    return Error(ErrorLoc, "invalid operand for instruction");
2427  }
2428  case Match_MnemonicFail:
2429    return Error(IDLoc, "unrecognized instruction mnemonic");
2430  case Match_ConversionFail:
2431    return Error(IDLoc, "unable to convert operands to instruction");
2432  }
2433
2434  llvm_unreachable("Implement any new match types added!");
2435  return true;
2436}
2437
2438/// ParseDirective parses the arm specific directives
2439bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
2440  StringRef IDVal = DirectiveID.getIdentifier();
2441  if (IDVal == ".word")
2442    return ParseDirectiveWord(4, DirectiveID.getLoc());
2443  else if (IDVal == ".thumb")
2444    return ParseDirectiveThumb(DirectiveID.getLoc());
2445  else if (IDVal == ".thumb_func")
2446    return ParseDirectiveThumbFunc(DirectiveID.getLoc());
2447  else if (IDVal == ".code")
2448    return ParseDirectiveCode(DirectiveID.getLoc());
2449  else if (IDVal == ".syntax")
2450    return ParseDirectiveSyntax(DirectiveID.getLoc());
2451  return true;
2452}
2453
2454/// ParseDirectiveWord
2455///  ::= .word [ expression (, expression)* ]
2456bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
2457  if (getLexer().isNot(AsmToken::EndOfStatement)) {
2458    for (;;) {
2459      const MCExpr *Value;
2460      if (getParser().ParseExpression(Value))
2461        return true;
2462
2463      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
2464
2465      if (getLexer().is(AsmToken::EndOfStatement))
2466        break;
2467
2468      // FIXME: Improve diagnostic.
2469      if (getLexer().isNot(AsmToken::Comma))
2470        return Error(L, "unexpected token in directive");
2471      Parser.Lex();
2472    }
2473  }
2474
2475  Parser.Lex();
2476  return false;
2477}
2478
2479/// ParseDirectiveThumb
2480///  ::= .thumb
2481bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
2482  if (getLexer().isNot(AsmToken::EndOfStatement))
2483    return Error(L, "unexpected token in directive");
2484  Parser.Lex();
2485
2486  // TODO: set thumb mode
2487  // TODO: tell the MC streamer the mode
2488  // getParser().getStreamer().Emit???();
2489  return false;
2490}
2491
2492/// ParseDirectiveThumbFunc
2493///  ::= .thumbfunc symbol_name
2494bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
2495  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
2496  bool isMachO = MAI.hasSubsectionsViaSymbols();
2497  StringRef Name;
2498
2499  // Darwin asm has function name after .thumb_func direction
2500  // ELF doesn't
2501  if (isMachO) {
2502    const AsmToken &Tok = Parser.getTok();
2503    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
2504      return Error(L, "unexpected token in .thumb_func directive");
2505    Name = Tok.getString();
2506    Parser.Lex(); // Consume the identifier token.
2507  }
2508
2509  if (getLexer().isNot(AsmToken::EndOfStatement))
2510    return Error(L, "unexpected token in directive");
2511  Parser.Lex();
2512
2513  // FIXME: assuming function name will be the line following .thumb_func
2514  if (!isMachO) {
2515    Name = Parser.getTok().getString();
2516  }
2517
2518  // Mark symbol as a thumb symbol.
2519  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
2520  getParser().getStreamer().EmitThumbFunc(Func);
2521  return false;
2522}
2523
2524/// ParseDirectiveSyntax
2525///  ::= .syntax unified | divided
2526bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
2527  const AsmToken &Tok = Parser.getTok();
2528  if (Tok.isNot(AsmToken::Identifier))
2529    return Error(L, "unexpected token in .syntax directive");
2530  StringRef Mode = Tok.getString();
2531  if (Mode == "unified" || Mode == "UNIFIED")
2532    Parser.Lex();
2533  else if (Mode == "divided" || Mode == "DIVIDED")
2534    return Error(L, "'.syntax divided' arm asssembly not supported");
2535  else
2536    return Error(L, "unrecognized syntax mode in .syntax directive");
2537
2538  if (getLexer().isNot(AsmToken::EndOfStatement))
2539    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
2540  Parser.Lex();
2541
2542  // TODO tell the MC streamer the mode
2543  // getParser().getStreamer().Emit???();
2544  return false;
2545}
2546
2547/// ParseDirectiveCode
2548///  ::= .code 16 | 32
2549bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
2550  const AsmToken &Tok = Parser.getTok();
2551  if (Tok.isNot(AsmToken::Integer))
2552    return Error(L, "unexpected token in .code directive");
2553  int64_t Val = Parser.getTok().getIntVal();
2554  if (Val == 16)
2555    Parser.Lex();
2556  else if (Val == 32)
2557    Parser.Lex();
2558  else
2559    return Error(L, "invalid operand to .code directive");
2560
2561  if (getLexer().isNot(AsmToken::EndOfStatement))
2562    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
2563  Parser.Lex();
2564
2565  if (Val == 16) {
2566    if (!isThumb())
2567      SwitchMode();
2568    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
2569  } else {
2570    if (isThumb())
2571      SwitchMode();
2572    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
2573  }
2574
2575  return false;
2576}
2577
2578extern "C" void LLVMInitializeARMAsmLexer();
2579
2580/// Force static initialization.
2581extern "C" void LLVMInitializeARMAsmParser() {
2582  RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
2583  RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
2584  LLVMInitializeARMAsmLexer();
2585}
2586
2587#define GET_REGISTER_MATCHER
2588#define GET_MATCHER_IMPLEMENTATION
2589#include "ARMGenAsmMatcher.inc"
2590