ARMAsmParser.cpp revision 280dfad48940a0a51726308dd3daa3b1b0d18705 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/MCTargetAsmParser.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/SourceMgr.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/ADT/BitVector.h"
30#include "llvm/ADT/OwningPtr.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/StringExtras.h"
34#include "llvm/ADT/StringSwitch.h"
35#include "llvm/ADT/Twine.h"
36
37using namespace llvm;
38
39namespace {
40
41class ARMOperand;
42
43class ARMAsmParser : public MCTargetAsmParser {
44  MCSubtargetInfo &STI;
45  MCAsmParser &Parser;
46
47  struct {
48    ARMCC::CondCodes Cond;    // Condition for IT block.
49    unsigned Mask:4;          // Condition mask for instructions.
50                              // Starting at first 1 (from lsb).
51                              //   '1'  condition as indicated in IT.
52                              //   '0'  inverse of condition (else).
53                              // Count of instructions in IT block is
54                              // 4 - trailingzeroes(mask)
55
56    bool FirstCond;           // Explicit flag for when we're parsing the
57                              // First instruction in the IT block. It's
58                              // implied in the mask, so needs special
59                              // handling.
60
61    unsigned CurPosition;     // Current position in parsing of IT
62                              // block. In range [0,3]. Initialized
63                              // according to count of instructions in block.
64                              // ~0U if no active IT block.
65  } ITState;
66  bool inITBlock() { return ITState.CurPosition != ~0U;}
67  void forwardITPosition() {
68    if (!inITBlock()) return;
69    // Move to the next instruction in the IT block, if there is one. If not,
70    // mark the block as done.
71    unsigned TZ = CountTrailingZeros_32(ITState.Mask);
72    if (++ITState.CurPosition == 5 - TZ)
73      ITState.CurPosition = ~0U; // Done with the IT block after this.
74  }
75
76
77  MCAsmParser &getParser() const { return Parser; }
78  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
79
80  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
81  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
82
83  int tryParseRegister();
84  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
85  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
86  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
87  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
88  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
89  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
90  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
91                              unsigned &ShiftAmount);
92  bool parseDirectiveWord(unsigned Size, SMLoc L);
93  bool parseDirectiveThumb(SMLoc L);
94  bool parseDirectiveThumbFunc(SMLoc L);
95  bool parseDirectiveCode(SMLoc L);
96  bool parseDirectiveSyntax(SMLoc L);
97
98  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
99                          bool &CarrySetting, unsigned &ProcessorIMod,
100                          StringRef &ITMask);
101  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
102                             bool &CanAcceptPredicationCode);
103
104  bool isThumb() const {
105    // FIXME: Can tablegen auto-generate this?
106    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
107  }
108  bool isThumbOne() const {
109    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
110  }
111  bool isThumbTwo() const {
112    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
113  }
114  bool hasV6Ops() const {
115    return STI.getFeatureBits() & ARM::HasV6Ops;
116  }
117  bool hasV7Ops() const {
118    return STI.getFeatureBits() & ARM::HasV7Ops;
119  }
120  void SwitchMode() {
121    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
122    setAvailableFeatures(FB);
123  }
124  bool isMClass() const {
125    return STI.getFeatureBits() & ARM::FeatureMClass;
126  }
127
128  /// @name Auto-generated Match Functions
129  /// {
130
131#define GET_ASSEMBLER_HEADER
132#include "ARMGenAsmMatcher.inc"
133
134  /// }
135
136  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
137  OperandMatchResultTy parseCoprocNumOperand(
138    SmallVectorImpl<MCParsedAsmOperand*>&);
139  OperandMatchResultTy parseCoprocRegOperand(
140    SmallVectorImpl<MCParsedAsmOperand*>&);
141  OperandMatchResultTy parseCoprocOptionOperand(
142    SmallVectorImpl<MCParsedAsmOperand*>&);
143  OperandMatchResultTy parseMemBarrierOptOperand(
144    SmallVectorImpl<MCParsedAsmOperand*>&);
145  OperandMatchResultTy parseProcIFlagsOperand(
146    SmallVectorImpl<MCParsedAsmOperand*>&);
147  OperandMatchResultTy parseMSRMaskOperand(
148    SmallVectorImpl<MCParsedAsmOperand*>&);
149  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
150                                   StringRef Op, int Low, int High);
151  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
152    return parsePKHImm(O, "lsl", 0, 31);
153  }
154  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
155    return parsePKHImm(O, "asr", 1, 32);
156  }
157  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
158  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
159  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
160  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
161  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
162  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
163  OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
164  OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
165
166  // Asm Match Converter Methods
167  bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
168                    const SmallVectorImpl<MCParsedAsmOperand*> &);
169  bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
170                    const SmallVectorImpl<MCParsedAsmOperand*> &);
171  bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
172                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
173  bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
174                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
175  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
176                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
177  bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
178                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
179  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
180                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
181  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
182                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
183  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
184                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
185  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
186                             const SmallVectorImpl<MCParsedAsmOperand*> &);
187  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
188                             const SmallVectorImpl<MCParsedAsmOperand*> &);
189  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
190                             const SmallVectorImpl<MCParsedAsmOperand*> &);
191  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
192                             const SmallVectorImpl<MCParsedAsmOperand*> &);
193  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
194                  const SmallVectorImpl<MCParsedAsmOperand*> &);
195  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
196                  const SmallVectorImpl<MCParsedAsmOperand*> &);
197  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
198                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
199  bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
200                        const SmallVectorImpl<MCParsedAsmOperand*> &);
201
202  bool validateInstruction(MCInst &Inst,
203                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
204  void processInstruction(MCInst &Inst,
205                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
206  bool shouldOmitCCOutOperand(StringRef Mnemonic,
207                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
208
209public:
210  enum ARMMatchResultTy {
211    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
212    Match_RequiresNotITBlock,
213    Match_RequiresV6,
214    Match_RequiresThumb2
215  };
216
217  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
218    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
219    MCAsmParserExtension::Initialize(_Parser);
220
221    // Initialize the set of available features.
222    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
223
224    // Not in an ITBlock to start with.
225    ITState.CurPosition = ~0U;
226  }
227
228  // Implementation of the MCTargetAsmParser interface:
229  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
230  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
231                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
232  bool ParseDirective(AsmToken DirectiveID);
233
234  unsigned checkTargetMatchPredicate(MCInst &Inst);
235
236  bool MatchAndEmitInstruction(SMLoc IDLoc,
237                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
238                               MCStreamer &Out);
239};
240} // end anonymous namespace
241
242namespace {
243
244/// ARMOperand - Instances of this class represent a parsed ARM machine
245/// instruction.
246class ARMOperand : public MCParsedAsmOperand {
247  enum KindTy {
248    k_CondCode,
249    k_CCOut,
250    k_ITCondMask,
251    k_CoprocNum,
252    k_CoprocReg,
253    k_CoprocOption,
254    k_Immediate,
255    k_FPImmediate,
256    k_MemBarrierOpt,
257    k_Memory,
258    k_PostIndexRegister,
259    k_MSRMask,
260    k_ProcIFlags,
261    k_VectorIndex,
262    k_Register,
263    k_RegisterList,
264    k_DPRRegisterList,
265    k_SPRRegisterList,
266    k_VectorList,
267    k_ShiftedRegister,
268    k_ShiftedImmediate,
269    k_ShifterImmediate,
270    k_RotateImmediate,
271    k_BitfieldDescriptor,
272    k_Token
273  } Kind;
274
275  SMLoc StartLoc, EndLoc;
276  SmallVector<unsigned, 8> Registers;
277
278  union {
279    struct {
280      ARMCC::CondCodes Val;
281    } CC;
282
283    struct {
284      unsigned Val;
285    } Cop;
286
287    struct {
288      unsigned Val;
289    } CoprocOption;
290
291    struct {
292      unsigned Mask:4;
293    } ITMask;
294
295    struct {
296      ARM_MB::MemBOpt Val;
297    } MBOpt;
298
299    struct {
300      ARM_PROC::IFlags Val;
301    } IFlags;
302
303    struct {
304      unsigned Val;
305    } MMask;
306
307    struct {
308      const char *Data;
309      unsigned Length;
310    } Tok;
311
312    struct {
313      unsigned RegNum;
314    } Reg;
315
316    // A vector register list is a sequential list of 1 to 4 registers.
317    struct {
318      unsigned RegNum;
319      unsigned Count;
320    } VectorList;
321
322    struct {
323      unsigned Val;
324    } VectorIndex;
325
326    struct {
327      const MCExpr *Val;
328    } Imm;
329
330    struct {
331      unsigned Val;       // encoded 8-bit representation
332    } FPImm;
333
334    /// Combined record for all forms of ARM address expressions.
335    struct {
336      unsigned BaseRegNum;
337      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
338      // was specified.
339      const MCConstantExpr *OffsetImm;  // Offset immediate value
340      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
341      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
342      unsigned ShiftImm;        // shift for OffsetReg.
343      unsigned Alignment;       // 0 = no alignment specified
344                                // n = alignment in bytes (8, 16, or 32)
345      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
346    } Memory;
347
348    struct {
349      unsigned RegNum;
350      bool isAdd;
351      ARM_AM::ShiftOpc ShiftTy;
352      unsigned ShiftImm;
353    } PostIdxReg;
354
355    struct {
356      bool isASR;
357      unsigned Imm;
358    } ShifterImm;
359    struct {
360      ARM_AM::ShiftOpc ShiftTy;
361      unsigned SrcReg;
362      unsigned ShiftReg;
363      unsigned ShiftImm;
364    } RegShiftedReg;
365    struct {
366      ARM_AM::ShiftOpc ShiftTy;
367      unsigned SrcReg;
368      unsigned ShiftImm;
369    } RegShiftedImm;
370    struct {
371      unsigned Imm;
372    } RotImm;
373    struct {
374      unsigned LSB;
375      unsigned Width;
376    } Bitfield;
377  };
378
379  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
380public:
381  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
382    Kind = o.Kind;
383    StartLoc = o.StartLoc;
384    EndLoc = o.EndLoc;
385    switch (Kind) {
386    case k_CondCode:
387      CC = o.CC;
388      break;
389    case k_ITCondMask:
390      ITMask = o.ITMask;
391      break;
392    case k_Token:
393      Tok = o.Tok;
394      break;
395    case k_CCOut:
396    case k_Register:
397      Reg = o.Reg;
398      break;
399    case k_RegisterList:
400    case k_DPRRegisterList:
401    case k_SPRRegisterList:
402      Registers = o.Registers;
403      break;
404    case k_VectorList:
405      VectorList = o.VectorList;
406      break;
407    case k_CoprocNum:
408    case k_CoprocReg:
409      Cop = o.Cop;
410      break;
411    case k_CoprocOption:
412      CoprocOption = o.CoprocOption;
413      break;
414    case k_Immediate:
415      Imm = o.Imm;
416      break;
417    case k_FPImmediate:
418      FPImm = o.FPImm;
419      break;
420    case k_MemBarrierOpt:
421      MBOpt = o.MBOpt;
422      break;
423    case k_Memory:
424      Memory = o.Memory;
425      break;
426    case k_PostIndexRegister:
427      PostIdxReg = o.PostIdxReg;
428      break;
429    case k_MSRMask:
430      MMask = o.MMask;
431      break;
432    case k_ProcIFlags:
433      IFlags = o.IFlags;
434      break;
435    case k_ShifterImmediate:
436      ShifterImm = o.ShifterImm;
437      break;
438    case k_ShiftedRegister:
439      RegShiftedReg = o.RegShiftedReg;
440      break;
441    case k_ShiftedImmediate:
442      RegShiftedImm = o.RegShiftedImm;
443      break;
444    case k_RotateImmediate:
445      RotImm = o.RotImm;
446      break;
447    case k_BitfieldDescriptor:
448      Bitfield = o.Bitfield;
449      break;
450    case k_VectorIndex:
451      VectorIndex = o.VectorIndex;
452      break;
453    }
454  }
455
456  /// getStartLoc - Get the location of the first token of this operand.
457  SMLoc getStartLoc() const { return StartLoc; }
458  /// getEndLoc - Get the location of the last token of this operand.
459  SMLoc getEndLoc() const { return EndLoc; }
460
461  ARMCC::CondCodes getCondCode() const {
462    assert(Kind == k_CondCode && "Invalid access!");
463    return CC.Val;
464  }
465
466  unsigned getCoproc() const {
467    assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
468    return Cop.Val;
469  }
470
471  StringRef getToken() const {
472    assert(Kind == k_Token && "Invalid access!");
473    return StringRef(Tok.Data, Tok.Length);
474  }
475
476  unsigned getReg() const {
477    assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
478    return Reg.RegNum;
479  }
480
481  const SmallVectorImpl<unsigned> &getRegList() const {
482    assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
483            Kind == k_SPRRegisterList) && "Invalid access!");
484    return Registers;
485  }
486
487  const MCExpr *getImm() const {
488    assert(Kind == k_Immediate && "Invalid access!");
489    return Imm.Val;
490  }
491
492  unsigned getFPImm() const {
493    assert(Kind == k_FPImmediate && "Invalid access!");
494    return FPImm.Val;
495  }
496
497  unsigned getVectorIndex() const {
498    assert(Kind == k_VectorIndex && "Invalid access!");
499    return VectorIndex.Val;
500  }
501
502  ARM_MB::MemBOpt getMemBarrierOpt() const {
503    assert(Kind == k_MemBarrierOpt && "Invalid access!");
504    return MBOpt.Val;
505  }
506
507  ARM_PROC::IFlags getProcIFlags() const {
508    assert(Kind == k_ProcIFlags && "Invalid access!");
509    return IFlags.Val;
510  }
511
512  unsigned getMSRMask() const {
513    assert(Kind == k_MSRMask && "Invalid access!");
514    return MMask.Val;
515  }
516
517  bool isCoprocNum() const { return Kind == k_CoprocNum; }
518  bool isCoprocReg() const { return Kind == k_CoprocReg; }
519  bool isCoprocOption() const { return Kind == k_CoprocOption; }
520  bool isCondCode() const { return Kind == k_CondCode; }
521  bool isCCOut() const { return Kind == k_CCOut; }
522  bool isITMask() const { return Kind == k_ITCondMask; }
523  bool isITCondCode() const { return Kind == k_CondCode; }
524  bool isImm() const { return Kind == k_Immediate; }
525  bool isFPImm() const { return Kind == k_FPImmediate; }
526  bool isImm8s4() const {
527    if (Kind != k_Immediate)
528      return false;
529    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
530    if (!CE) return false;
531    int64_t Value = CE->getValue();
532    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
533  }
534  bool isImm0_1020s4() const {
535    if (Kind != k_Immediate)
536      return false;
537    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
538    if (!CE) return false;
539    int64_t Value = CE->getValue();
540    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
541  }
542  bool isImm0_508s4() const {
543    if (Kind != k_Immediate)
544      return false;
545    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
546    if (!CE) return false;
547    int64_t Value = CE->getValue();
548    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
549  }
550  bool isImm0_255() const {
551    if (Kind != k_Immediate)
552      return false;
553    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
554    if (!CE) return false;
555    int64_t Value = CE->getValue();
556    return Value >= 0 && Value < 256;
557  }
558  bool isImm0_7() const {
559    if (Kind != k_Immediate)
560      return false;
561    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
562    if (!CE) return false;
563    int64_t Value = CE->getValue();
564    return Value >= 0 && Value < 8;
565  }
566  bool isImm0_15() const {
567    if (Kind != k_Immediate)
568      return false;
569    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
570    if (!CE) return false;
571    int64_t Value = CE->getValue();
572    return Value >= 0 && Value < 16;
573  }
574  bool isImm0_31() const {
575    if (Kind != k_Immediate)
576      return false;
577    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
578    if (!CE) return false;
579    int64_t Value = CE->getValue();
580    return Value >= 0 && Value < 32;
581  }
582  bool isImm1_16() const {
583    if (Kind != k_Immediate)
584      return false;
585    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
586    if (!CE) return false;
587    int64_t Value = CE->getValue();
588    return Value > 0 && Value < 17;
589  }
590  bool isImm1_32() const {
591    if (Kind != k_Immediate)
592      return false;
593    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
594    if (!CE) return false;
595    int64_t Value = CE->getValue();
596    return Value > 0 && Value < 33;
597  }
598  bool isImm0_65535() const {
599    if (Kind != k_Immediate)
600      return false;
601    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
602    if (!CE) return false;
603    int64_t Value = CE->getValue();
604    return Value >= 0 && Value < 65536;
605  }
606  bool isImm0_65535Expr() const {
607    if (Kind != k_Immediate)
608      return false;
609    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
610    // If it's not a constant expression, it'll generate a fixup and be
611    // handled later.
612    if (!CE) return true;
613    int64_t Value = CE->getValue();
614    return Value >= 0 && Value < 65536;
615  }
616  bool isImm24bit() const {
617    if (Kind != k_Immediate)
618      return false;
619    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
620    if (!CE) return false;
621    int64_t Value = CE->getValue();
622    return Value >= 0 && Value <= 0xffffff;
623  }
624  bool isImmThumbSR() const {
625    if (Kind != k_Immediate)
626      return false;
627    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
628    if (!CE) return false;
629    int64_t Value = CE->getValue();
630    return Value > 0 && Value < 33;
631  }
632  bool isPKHLSLImm() const {
633    if (Kind != k_Immediate)
634      return false;
635    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
636    if (!CE) return false;
637    int64_t Value = CE->getValue();
638    return Value >= 0 && Value < 32;
639  }
640  bool isPKHASRImm() const {
641    if (Kind != k_Immediate)
642      return false;
643    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
644    if (!CE) return false;
645    int64_t Value = CE->getValue();
646    return Value > 0 && Value <= 32;
647  }
648  bool isARMSOImm() const {
649    if (Kind != k_Immediate)
650      return false;
651    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
652    if (!CE) return false;
653    int64_t Value = CE->getValue();
654    return ARM_AM::getSOImmVal(Value) != -1;
655  }
656  bool isT2SOImm() const {
657    if (Kind != k_Immediate)
658      return false;
659    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
660    if (!CE) return false;
661    int64_t Value = CE->getValue();
662    return ARM_AM::getT2SOImmVal(Value) != -1;
663  }
664  bool isSetEndImm() const {
665    if (Kind != k_Immediate)
666      return false;
667    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
668    if (!CE) return false;
669    int64_t Value = CE->getValue();
670    return Value == 1 || Value == 0;
671  }
672  bool isReg() const { return Kind == k_Register; }
673  bool isRegList() const { return Kind == k_RegisterList; }
674  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
675  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
676  bool isToken() const { return Kind == k_Token; }
677  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
678  bool isMemory() const { return Kind == k_Memory; }
679  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
680  bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
681  bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
682  bool isRotImm() const { return Kind == k_RotateImmediate; }
683  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
684  bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
685  bool isPostIdxReg() const {
686    return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
687  }
688  bool isMemNoOffset(bool alignOK = false) const {
689    if (!isMemory())
690      return false;
691    // No offset of any kind.
692    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
693     (alignOK || Memory.Alignment == 0);
694  }
695  bool isAlignedMemory() const {
696    return isMemNoOffset(true);
697  }
698  bool isAddrMode2() const {
699    if (!isMemory() || Memory.Alignment != 0) return false;
700    // Check for register offset.
701    if (Memory.OffsetRegNum) return true;
702    // Immediate offset in range [-4095, 4095].
703    if (!Memory.OffsetImm) return true;
704    int64_t Val = Memory.OffsetImm->getValue();
705    return Val > -4096 && Val < 4096;
706  }
707  bool isAM2OffsetImm() const {
708    if (Kind != k_Immediate)
709      return false;
710    // Immediate offset in range [-4095, 4095].
711    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
712    if (!CE) return false;
713    int64_t Val = CE->getValue();
714    return Val > -4096 && Val < 4096;
715  }
716  bool isAddrMode3() const {
717    if (!isMemory() || Memory.Alignment != 0) return false;
718    // No shifts are legal for AM3.
719    if (Memory.ShiftType != ARM_AM::no_shift) return false;
720    // Check for register offset.
721    if (Memory.OffsetRegNum) return true;
722    // Immediate offset in range [-255, 255].
723    if (!Memory.OffsetImm) return true;
724    int64_t Val = Memory.OffsetImm->getValue();
725    return Val > -256 && Val < 256;
726  }
727  bool isAM3Offset() const {
728    if (Kind != k_Immediate && Kind != k_PostIndexRegister)
729      return false;
730    if (Kind == k_PostIndexRegister)
731      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
732    // Immediate offset in range [-255, 255].
733    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
734    if (!CE) return false;
735    int64_t Val = CE->getValue();
736    // Special case, #-0 is INT32_MIN.
737    return (Val > -256 && Val < 256) || Val == INT32_MIN;
738  }
739  bool isAddrMode5() const {
740    if (!isMemory() || Memory.Alignment != 0) return false;
741    // Check for register offset.
742    if (Memory.OffsetRegNum) return false;
743    // Immediate offset in range [-1020, 1020] and a multiple of 4.
744    if (!Memory.OffsetImm) return true;
745    int64_t Val = Memory.OffsetImm->getValue();
746    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
747           Val == INT32_MIN;
748  }
749  bool isMemTBB() const {
750    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
751        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
752      return false;
753    return true;
754  }
755  bool isMemTBH() const {
756    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
757        Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
758        Memory.Alignment != 0 )
759      return false;
760    return true;
761  }
762  bool isMemRegOffset() const {
763    if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
764      return false;
765    return true;
766  }
767  bool isT2MemRegOffset() const {
768    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
769        Memory.Alignment != 0)
770      return false;
771    // Only lsl #{0, 1, 2, 3} allowed.
772    if (Memory.ShiftType == ARM_AM::no_shift)
773      return true;
774    if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
775      return false;
776    return true;
777  }
778  bool isMemThumbRR() const {
779    // Thumb reg+reg addressing is simple. Just two registers, a base and
780    // an offset. No shifts, negations or any other complicating factors.
781    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
782        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
783      return false;
784    return isARMLowRegister(Memory.BaseRegNum) &&
785      (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
786  }
787  bool isMemThumbRIs4() const {
788    if (!isMemory() || Memory.OffsetRegNum != 0 ||
789        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
790      return false;
791    // Immediate offset, multiple of 4 in range [0, 124].
792    if (!Memory.OffsetImm) return true;
793    int64_t Val = Memory.OffsetImm->getValue();
794    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
795  }
796  bool isMemThumbRIs2() const {
797    if (!isMemory() || Memory.OffsetRegNum != 0 ||
798        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
799      return false;
800    // Immediate offset, multiple of 4 in range [0, 62].
801    if (!Memory.OffsetImm) return true;
802    int64_t Val = Memory.OffsetImm->getValue();
803    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
804  }
805  bool isMemThumbRIs1() const {
806    if (!isMemory() || Memory.OffsetRegNum != 0 ||
807        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
808      return false;
809    // Immediate offset in range [0, 31].
810    if (!Memory.OffsetImm) return true;
811    int64_t Val = Memory.OffsetImm->getValue();
812    return Val >= 0 && Val <= 31;
813  }
814  bool isMemThumbSPI() const {
815    if (!isMemory() || Memory.OffsetRegNum != 0 ||
816        Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
817      return false;
818    // Immediate offset, multiple of 4 in range [0, 1020].
819    if (!Memory.OffsetImm) return true;
820    int64_t Val = Memory.OffsetImm->getValue();
821    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
822  }
823  bool isMemImm8s4Offset() const {
824    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
825      return false;
826    // Immediate offset a multiple of 4 in range [-1020, 1020].
827    if (!Memory.OffsetImm) return true;
828    int64_t Val = Memory.OffsetImm->getValue();
829    return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
830  }
831  bool isMemImm0_1020s4Offset() const {
832    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
833      return false;
834    // Immediate offset a multiple of 4 in range [0, 1020].
835    if (!Memory.OffsetImm) return true;
836    int64_t Val = Memory.OffsetImm->getValue();
837    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
838  }
839  bool isMemImm8Offset() const {
840    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
841      return false;
842    // Immediate offset in range [-255, 255].
843    if (!Memory.OffsetImm) return true;
844    int64_t Val = Memory.OffsetImm->getValue();
845    return (Val == INT32_MIN) || (Val > -256 && Val < 256);
846  }
847  bool isMemPosImm8Offset() const {
848    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
849      return false;
850    // Immediate offset in range [0, 255].
851    if (!Memory.OffsetImm) return true;
852    int64_t Val = Memory.OffsetImm->getValue();
853    return Val >= 0 && Val < 256;
854  }
855  bool isMemNegImm8Offset() const {
856    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
857      return false;
858    // Immediate offset in range [-255, -1].
859    if (!Memory.OffsetImm) return true;
860    int64_t Val = Memory.OffsetImm->getValue();
861    return Val > -256 && Val < 0;
862  }
863  bool isMemUImm12Offset() const {
864    // If we have an immediate that's not a constant, treat it as a label
865    // reference needing a fixup. If it is a constant, it's something else
866    // and we reject it.
867    if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
868      return true;
869
870    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
871      return false;
872    // Immediate offset in range [0, 4095].
873    if (!Memory.OffsetImm) return true;
874    int64_t Val = Memory.OffsetImm->getValue();
875    return (Val >= 0 && Val < 4096);
876  }
877  bool isMemImm12Offset() const {
878    // If we have an immediate that's not a constant, treat it as a label
879    // reference needing a fixup. If it is a constant, it's something else
880    // and we reject it.
881    if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
882      return true;
883
884    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
885      return false;
886    // Immediate offset in range [-4095, 4095].
887    if (!Memory.OffsetImm) return true;
888    int64_t Val = Memory.OffsetImm->getValue();
889    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
890  }
891  bool isPostIdxImm8() const {
892    if (Kind != k_Immediate)
893      return false;
894    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
895    if (!CE) return false;
896    int64_t Val = CE->getValue();
897    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
898  }
899  bool isPostIdxImm8s4() const {
900    if (Kind != k_Immediate)
901      return false;
902    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
903    if (!CE) return false;
904    int64_t Val = CE->getValue();
905    return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
906      (Val == INT32_MIN);
907  }
908
909  bool isMSRMask() const { return Kind == k_MSRMask; }
910  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
911
912  // NEON operands.
913  bool isVecListOneD() const {
914    if (Kind != k_VectorList) return false;
915    return VectorList.Count == 1;
916  }
917
918  bool isVecListTwoD() const {
919    if (Kind != k_VectorList) return false;
920    return VectorList.Count == 2;
921  }
922
923  bool isVectorIndex8() const {
924    if (Kind != k_VectorIndex) return false;
925    return VectorIndex.Val < 8;
926  }
927  bool isVectorIndex16() const {
928    if (Kind != k_VectorIndex) return false;
929    return VectorIndex.Val < 4;
930  }
931  bool isVectorIndex32() const {
932    if (Kind != k_VectorIndex) return false;
933    return VectorIndex.Val < 2;
934  }
935
936  bool isNEONi8splat() const {
937    if (Kind != k_Immediate)
938      return false;
939    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
940    // Must be a constant.
941    if (!CE) return false;
942    int64_t Value = CE->getValue();
943    // i8 value splatted across 8 bytes. The immediate is just the 8 byte
944    // value.
945    return Value >= 0 && Value < 256;
946  }
947
948  bool isNEONi16splat() const {
949    if (Kind != k_Immediate)
950      return false;
951    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
952    // Must be a constant.
953    if (!CE) return false;
954    int64_t Value = CE->getValue();
955    // i16 value in the range [0,255] or [0x0100, 0xff00]
956    return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
957  }
958
959  bool isNEONi32splat() const {
960    if (Kind != k_Immediate)
961      return false;
962    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
963    // Must be a constant.
964    if (!CE) return false;
965    int64_t Value = CE->getValue();
966    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
967    return (Value >= 0 && Value < 256) ||
968      (Value >= 0x0100 && Value <= 0xff00) ||
969      (Value >= 0x010000 && Value <= 0xff0000) ||
970      (Value >= 0x01000000 && Value <= 0xff000000);
971  }
972
973  bool isNEONi32vmov() const {
974    if (Kind != k_Immediate)
975      return false;
976    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
977    // Must be a constant.
978    if (!CE) return false;
979    int64_t Value = CE->getValue();
980    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
981    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
982    return (Value >= 0 && Value < 256) ||
983      (Value >= 0x0100 && Value <= 0xff00) ||
984      (Value >= 0x010000 && Value <= 0xff0000) ||
985      (Value >= 0x01000000 && Value <= 0xff000000) ||
986      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
987      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
988  }
989
990  bool isNEONi64splat() const {
991    if (Kind != k_Immediate)
992      return false;
993    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
994    // Must be a constant.
995    if (!CE) return false;
996    uint64_t Value = CE->getValue();
997    // i64 value with each byte being either 0 or 0xff.
998    for (unsigned i = 0; i < 8; ++i)
999      if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1000    return true;
1001  }
1002
1003  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1004    // Add as immediates when possible.  Null MCExpr = 0.
1005    if (Expr == 0)
1006      Inst.addOperand(MCOperand::CreateImm(0));
1007    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1008      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1009    else
1010      Inst.addOperand(MCOperand::CreateExpr(Expr));
1011  }
1012
1013  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1014    assert(N == 2 && "Invalid number of operands!");
1015    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1016    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1017    Inst.addOperand(MCOperand::CreateReg(RegNum));
1018  }
1019
1020  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1021    assert(N == 1 && "Invalid number of operands!");
1022    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1023  }
1024
1025  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1026    assert(N == 1 && "Invalid number of operands!");
1027    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1028  }
1029
1030  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1031    assert(N == 1 && "Invalid number of operands!");
1032    Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1033  }
1034
1035  void addITMaskOperands(MCInst &Inst, unsigned N) const {
1036    assert(N == 1 && "Invalid number of operands!");
1037    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1038  }
1039
1040  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1041    assert(N == 1 && "Invalid number of operands!");
1042    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1043  }
1044
1045  void addCCOutOperands(MCInst &Inst, unsigned N) const {
1046    assert(N == 1 && "Invalid number of operands!");
1047    Inst.addOperand(MCOperand::CreateReg(getReg()));
1048  }
1049
1050  void addRegOperands(MCInst &Inst, unsigned N) const {
1051    assert(N == 1 && "Invalid number of operands!");
1052    Inst.addOperand(MCOperand::CreateReg(getReg()));
1053  }
1054
1055  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1056    assert(N == 3 && "Invalid number of operands!");
1057    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
1058    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1059    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1060    Inst.addOperand(MCOperand::CreateImm(
1061      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1062  }
1063
1064  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1065    assert(N == 2 && "Invalid number of operands!");
1066    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
1067    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1068    Inst.addOperand(MCOperand::CreateImm(
1069      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
1070  }
1071
1072  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1073    assert(N == 1 && "Invalid number of operands!");
1074    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1075                                         ShifterImm.Imm));
1076  }
1077
1078  void addRegListOperands(MCInst &Inst, unsigned N) const {
1079    assert(N == 1 && "Invalid number of operands!");
1080    const SmallVectorImpl<unsigned> &RegList = getRegList();
1081    for (SmallVectorImpl<unsigned>::const_iterator
1082           I = RegList.begin(), E = RegList.end(); I != E; ++I)
1083      Inst.addOperand(MCOperand::CreateReg(*I));
1084  }
1085
1086  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1087    addRegListOperands(Inst, N);
1088  }
1089
1090  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1091    addRegListOperands(Inst, N);
1092  }
1093
1094  void addRotImmOperands(MCInst &Inst, unsigned N) const {
1095    assert(N == 1 && "Invalid number of operands!");
1096    // Encoded as val>>3. The printer handles display as 8, 16, 24.
1097    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1098  }
1099
1100  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1101    assert(N == 1 && "Invalid number of operands!");
1102    // Munge the lsb/width into a bitfield mask.
1103    unsigned lsb = Bitfield.LSB;
1104    unsigned width = Bitfield.Width;
1105    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1106    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1107                      (32 - (lsb + width)));
1108    Inst.addOperand(MCOperand::CreateImm(Mask));
1109  }
1110
1111  void addImmOperands(MCInst &Inst, unsigned N) const {
1112    assert(N == 1 && "Invalid number of operands!");
1113    addExpr(Inst, getImm());
1114  }
1115
1116  void addFPImmOperands(MCInst &Inst, unsigned N) const {
1117    assert(N == 1 && "Invalid number of operands!");
1118    Inst.addOperand(MCOperand::CreateImm(getFPImm()));
1119  }
1120
1121  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1122    assert(N == 1 && "Invalid number of operands!");
1123    // FIXME: We really want to scale the value here, but the LDRD/STRD
1124    // instruction don't encode operands that way yet.
1125    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1126    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1127  }
1128
1129  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1130    assert(N == 1 && "Invalid number of operands!");
1131    // The immediate is scaled by four in the encoding and is stored
1132    // in the MCInst as such. Lop off the low two bits here.
1133    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1134    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1135  }
1136
1137  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1138    assert(N == 1 && "Invalid number of operands!");
1139    // The immediate is scaled by four in the encoding and is stored
1140    // in the MCInst as such. Lop off the low two bits here.
1141    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1142    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1143  }
1144
1145  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
1146    assert(N == 1 && "Invalid number of operands!");
1147    addExpr(Inst, getImm());
1148  }
1149
1150  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
1151    assert(N == 1 && "Invalid number of operands!");
1152    addExpr(Inst, getImm());
1153  }
1154
1155  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
1156    assert(N == 1 && "Invalid number of operands!");
1157    addExpr(Inst, getImm());
1158  }
1159
1160  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
1161    assert(N == 1 && "Invalid number of operands!");
1162    addExpr(Inst, getImm());
1163  }
1164
1165  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1166    assert(N == 1 && "Invalid number of operands!");
1167    // The constant encodes as the immediate-1, and we store in the instruction
1168    // the bits as encoded, so subtract off one here.
1169    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1170    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1171  }
1172
1173  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1174    assert(N == 1 && "Invalid number of operands!");
1175    // The constant encodes as the immediate-1, and we store in the instruction
1176    // the bits as encoded, so subtract off one here.
1177    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1178    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1179  }
1180
1181  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
1182    assert(N == 1 && "Invalid number of operands!");
1183    addExpr(Inst, getImm());
1184  }
1185
1186  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
1187    assert(N == 1 && "Invalid number of operands!");
1188    addExpr(Inst, getImm());
1189  }
1190
1191  void addImm24bitOperands(MCInst &Inst, unsigned N) const {
1192    assert(N == 1 && "Invalid number of operands!");
1193    addExpr(Inst, getImm());
1194  }
1195
1196  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1197    assert(N == 1 && "Invalid number of operands!");
1198    // The constant encodes as the immediate, except for 32, which encodes as
1199    // zero.
1200    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1201    unsigned Imm = CE->getValue();
1202    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1203  }
1204
1205  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
1206    assert(N == 1 && "Invalid number of operands!");
1207    addExpr(Inst, getImm());
1208  }
1209
1210  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1211    assert(N == 1 && "Invalid number of operands!");
1212    // An ASR value of 32 encodes as 0, so that's how we want to add it to
1213    // the instruction as well.
1214    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1215    int Val = CE->getValue();
1216    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1217  }
1218
1219  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
1220    assert(N == 1 && "Invalid number of operands!");
1221    addExpr(Inst, getImm());
1222  }
1223
1224  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
1225    assert(N == 1 && "Invalid number of operands!");
1226    addExpr(Inst, getImm());
1227  }
1228
1229  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
1230    assert(N == 1 && "Invalid number of operands!");
1231    addExpr(Inst, getImm());
1232  }
1233
1234  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1235    assert(N == 1 && "Invalid number of operands!");
1236    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1237  }
1238
1239  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1240    assert(N == 1 && "Invalid number of operands!");
1241    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1242  }
1243
1244  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1245    assert(N == 2 && "Invalid number of operands!");
1246    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1247    Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1248  }
1249
1250  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1251    assert(N == 3 && "Invalid number of operands!");
1252    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1253    if (!Memory.OffsetRegNum) {
1254      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1255      // Special case for #-0
1256      if (Val == INT32_MIN) Val = 0;
1257      if (Val < 0) Val = -Val;
1258      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1259    } else {
1260      // For register offset, we encode the shift type and negation flag
1261      // here.
1262      Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1263                              Memory.ShiftImm, Memory.ShiftType);
1264    }
1265    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1266    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1267    Inst.addOperand(MCOperand::CreateImm(Val));
1268  }
1269
1270  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1271    assert(N == 2 && "Invalid number of operands!");
1272    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1273    assert(CE && "non-constant AM2OffsetImm operand!");
1274    int32_t Val = CE->getValue();
1275    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1276    // Special case for #-0
1277    if (Val == INT32_MIN) Val = 0;
1278    if (Val < 0) Val = -Val;
1279    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1280    Inst.addOperand(MCOperand::CreateReg(0));
1281    Inst.addOperand(MCOperand::CreateImm(Val));
1282  }
1283
1284  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1285    assert(N == 3 && "Invalid number of operands!");
1286    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1287    if (!Memory.OffsetRegNum) {
1288      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1289      // Special case for #-0
1290      if (Val == INT32_MIN) Val = 0;
1291      if (Val < 0) Val = -Val;
1292      Val = ARM_AM::getAM3Opc(AddSub, Val);
1293    } else {
1294      // For register offset, we encode the shift type and negation flag
1295      // here.
1296      Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1297    }
1298    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1299    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1300    Inst.addOperand(MCOperand::CreateImm(Val));
1301  }
1302
1303  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1304    assert(N == 2 && "Invalid number of operands!");
1305    if (Kind == k_PostIndexRegister) {
1306      int32_t Val =
1307        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1308      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1309      Inst.addOperand(MCOperand::CreateImm(Val));
1310      return;
1311    }
1312
1313    // Constant offset.
1314    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1315    int32_t Val = CE->getValue();
1316    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1317    // Special case for #-0
1318    if (Val == INT32_MIN) Val = 0;
1319    if (Val < 0) Val = -Val;
1320    Val = ARM_AM::getAM3Opc(AddSub, Val);
1321    Inst.addOperand(MCOperand::CreateReg(0));
1322    Inst.addOperand(MCOperand::CreateImm(Val));
1323  }
1324
1325  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1326    assert(N == 2 && "Invalid number of operands!");
1327    // The lower two bits are always zero and as such are not encoded.
1328    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1329    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1330    // Special case for #-0
1331    if (Val == INT32_MIN) Val = 0;
1332    if (Val < 0) Val = -Val;
1333    Val = ARM_AM::getAM5Opc(AddSub, Val);
1334    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1335    Inst.addOperand(MCOperand::CreateImm(Val));
1336  }
1337
1338  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1339    assert(N == 2 && "Invalid number of operands!");
1340    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1341    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1342    Inst.addOperand(MCOperand::CreateImm(Val));
1343  }
1344
1345  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1346    assert(N == 2 && "Invalid number of operands!");
1347    // The lower two bits are always zero and as such are not encoded.
1348    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1349    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1350    Inst.addOperand(MCOperand::CreateImm(Val));
1351  }
1352
1353  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1354    assert(N == 2 && "Invalid number of operands!");
1355    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1356    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1357    Inst.addOperand(MCOperand::CreateImm(Val));
1358  }
1359
1360  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1361    addMemImm8OffsetOperands(Inst, N);
1362  }
1363
1364  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1365    addMemImm8OffsetOperands(Inst, N);
1366  }
1367
1368  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1369    assert(N == 2 && "Invalid number of operands!");
1370    // If this is an immediate, it's a label reference.
1371    if (Kind == k_Immediate) {
1372      addExpr(Inst, getImm());
1373      Inst.addOperand(MCOperand::CreateImm(0));
1374      return;
1375    }
1376
1377    // Otherwise, it's a normal memory reg+offset.
1378    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1379    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1380    Inst.addOperand(MCOperand::CreateImm(Val));
1381  }
1382
1383  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1384    assert(N == 2 && "Invalid number of operands!");
1385    // If this is an immediate, it's a label reference.
1386    if (Kind == k_Immediate) {
1387      addExpr(Inst, getImm());
1388      Inst.addOperand(MCOperand::CreateImm(0));
1389      return;
1390    }
1391
1392    // Otherwise, it's a normal memory reg+offset.
1393    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1394    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1395    Inst.addOperand(MCOperand::CreateImm(Val));
1396  }
1397
1398  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1399    assert(N == 2 && "Invalid number of operands!");
1400    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1401    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1402  }
1403
1404  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1405    assert(N == 2 && "Invalid number of operands!");
1406    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1407    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1408  }
1409
1410  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1411    assert(N == 3 && "Invalid number of operands!");
1412    unsigned Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1413                                     Memory.ShiftImm, Memory.ShiftType);
1414    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1415    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1416    Inst.addOperand(MCOperand::CreateImm(Val));
1417  }
1418
1419  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1420    assert(N == 3 && "Invalid number of operands!");
1421    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1422    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1423    Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1424  }
1425
1426  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1427    assert(N == 2 && "Invalid number of operands!");
1428    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1429    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1430  }
1431
1432  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1433    assert(N == 2 && "Invalid number of operands!");
1434    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1435    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1436    Inst.addOperand(MCOperand::CreateImm(Val));
1437  }
1438
1439  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1440    assert(N == 2 && "Invalid number of operands!");
1441    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1442    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1443    Inst.addOperand(MCOperand::CreateImm(Val));
1444  }
1445
1446  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1447    assert(N == 2 && "Invalid number of operands!");
1448    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1449    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1450    Inst.addOperand(MCOperand::CreateImm(Val));
1451  }
1452
1453  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1454    assert(N == 2 && "Invalid number of operands!");
1455    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1456    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1457    Inst.addOperand(MCOperand::CreateImm(Val));
1458  }
1459
1460  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1461    assert(N == 1 && "Invalid number of operands!");
1462    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1463    assert(CE && "non-constant post-idx-imm8 operand!");
1464    int Imm = CE->getValue();
1465    bool isAdd = Imm >= 0;
1466    if (Imm == INT32_MIN) Imm = 0;
1467    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1468    Inst.addOperand(MCOperand::CreateImm(Imm));
1469  }
1470
1471  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1472    assert(N == 1 && "Invalid number of operands!");
1473    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1474    assert(CE && "non-constant post-idx-imm8s4 operand!");
1475    int Imm = CE->getValue();
1476    bool isAdd = Imm >= 0;
1477    if (Imm == INT32_MIN) Imm = 0;
1478    // Immediate is scaled by 4.
1479    Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1480    Inst.addOperand(MCOperand::CreateImm(Imm));
1481  }
1482
1483  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1484    assert(N == 2 && "Invalid number of operands!");
1485    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1486    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1487  }
1488
1489  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1490    assert(N == 2 && "Invalid number of operands!");
1491    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1492    // The sign, shift type, and shift amount are encoded in a single operand
1493    // using the AM2 encoding helpers.
1494    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1495    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1496                                     PostIdxReg.ShiftTy);
1497    Inst.addOperand(MCOperand::CreateImm(Imm));
1498  }
1499
1500  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1501    assert(N == 1 && "Invalid number of operands!");
1502    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1503  }
1504
1505  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1506    assert(N == 1 && "Invalid number of operands!");
1507    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1508  }
1509
1510  void addVecListOneDOperands(MCInst &Inst, unsigned N) const {
1511    assert(N == 1 && "Invalid number of operands!");
1512    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1513  }
1514
1515  void addVecListTwoDOperands(MCInst &Inst, unsigned N) const {
1516    assert(N == 1 && "Invalid number of operands!");
1517    // Only the first register actually goes on the instruction. The rest
1518    // are implied by the opcode.
1519    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1520  }
1521
1522  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1523    assert(N == 1 && "Invalid number of operands!");
1524    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1525  }
1526
1527  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1528    assert(N == 1 && "Invalid number of operands!");
1529    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1530  }
1531
1532  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1533    assert(N == 1 && "Invalid number of operands!");
1534    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1535  }
1536
1537  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1538    assert(N == 1 && "Invalid number of operands!");
1539    // The immediate encodes the type of constant as well as the value.
1540    // Mask in that this is an i8 splat.
1541    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1542    Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1543  }
1544
1545  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1546    assert(N == 1 && "Invalid number of operands!");
1547    // The immediate encodes the type of constant as well as the value.
1548    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1549    unsigned Value = CE->getValue();
1550    if (Value >= 256)
1551      Value = (Value >> 8) | 0xa00;
1552    else
1553      Value |= 0x800;
1554    Inst.addOperand(MCOperand::CreateImm(Value));
1555  }
1556
1557  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
1558    assert(N == 1 && "Invalid number of operands!");
1559    // The immediate encodes the type of constant as well as the value.
1560    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1561    unsigned Value = CE->getValue();
1562    if (Value >= 256 && Value <= 0xff00)
1563      Value = (Value >> 8) | 0x200;
1564    else if (Value > 0xffff && Value <= 0xff0000)
1565      Value = (Value >> 16) | 0x400;
1566    else if (Value > 0xffffff)
1567      Value = (Value >> 24) | 0x600;
1568    Inst.addOperand(MCOperand::CreateImm(Value));
1569  }
1570
1571  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
1572    assert(N == 1 && "Invalid number of operands!");
1573    // The immediate encodes the type of constant as well as the value.
1574    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1575    unsigned Value = CE->getValue();
1576    if (Value >= 256 && Value <= 0xffff)
1577      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
1578    else if (Value > 0xffff && Value <= 0xffffff)
1579      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
1580    else if (Value > 0xffffff)
1581      Value = (Value >> 24) | 0x600;
1582    Inst.addOperand(MCOperand::CreateImm(Value));
1583  }
1584
1585  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
1586    assert(N == 1 && "Invalid number of operands!");
1587    // The immediate encodes the type of constant as well as the value.
1588    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1589    uint64_t Value = CE->getValue();
1590    unsigned Imm = 0;
1591    for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
1592      Imm |= (Value & 1) << i;
1593    }
1594    Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
1595  }
1596
1597  virtual void print(raw_ostream &OS) const;
1598
1599  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1600    ARMOperand *Op = new ARMOperand(k_ITCondMask);
1601    Op->ITMask.Mask = Mask;
1602    Op->StartLoc = S;
1603    Op->EndLoc = S;
1604    return Op;
1605  }
1606
1607  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1608    ARMOperand *Op = new ARMOperand(k_CondCode);
1609    Op->CC.Val = CC;
1610    Op->StartLoc = S;
1611    Op->EndLoc = S;
1612    return Op;
1613  }
1614
1615  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1616    ARMOperand *Op = new ARMOperand(k_CoprocNum);
1617    Op->Cop.Val = CopVal;
1618    Op->StartLoc = S;
1619    Op->EndLoc = S;
1620    return Op;
1621  }
1622
1623  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1624    ARMOperand *Op = new ARMOperand(k_CoprocReg);
1625    Op->Cop.Val = CopVal;
1626    Op->StartLoc = S;
1627    Op->EndLoc = S;
1628    return Op;
1629  }
1630
1631  static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
1632    ARMOperand *Op = new ARMOperand(k_CoprocOption);
1633    Op->Cop.Val = Val;
1634    Op->StartLoc = S;
1635    Op->EndLoc = E;
1636    return Op;
1637  }
1638
1639  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1640    ARMOperand *Op = new ARMOperand(k_CCOut);
1641    Op->Reg.RegNum = RegNum;
1642    Op->StartLoc = S;
1643    Op->EndLoc = S;
1644    return Op;
1645  }
1646
1647  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1648    ARMOperand *Op = new ARMOperand(k_Token);
1649    Op->Tok.Data = Str.data();
1650    Op->Tok.Length = Str.size();
1651    Op->StartLoc = S;
1652    Op->EndLoc = S;
1653    return Op;
1654  }
1655
1656  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1657    ARMOperand *Op = new ARMOperand(k_Register);
1658    Op->Reg.RegNum = RegNum;
1659    Op->StartLoc = S;
1660    Op->EndLoc = E;
1661    return Op;
1662  }
1663
1664  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1665                                           unsigned SrcReg,
1666                                           unsigned ShiftReg,
1667                                           unsigned ShiftImm,
1668                                           SMLoc S, SMLoc E) {
1669    ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
1670    Op->RegShiftedReg.ShiftTy = ShTy;
1671    Op->RegShiftedReg.SrcReg = SrcReg;
1672    Op->RegShiftedReg.ShiftReg = ShiftReg;
1673    Op->RegShiftedReg.ShiftImm = ShiftImm;
1674    Op->StartLoc = S;
1675    Op->EndLoc = E;
1676    return Op;
1677  }
1678
1679  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1680                                            unsigned SrcReg,
1681                                            unsigned ShiftImm,
1682                                            SMLoc S, SMLoc E) {
1683    ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
1684    Op->RegShiftedImm.ShiftTy = ShTy;
1685    Op->RegShiftedImm.SrcReg = SrcReg;
1686    Op->RegShiftedImm.ShiftImm = ShiftImm;
1687    Op->StartLoc = S;
1688    Op->EndLoc = E;
1689    return Op;
1690  }
1691
1692  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1693                                   SMLoc S, SMLoc E) {
1694    ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
1695    Op->ShifterImm.isASR = isASR;
1696    Op->ShifterImm.Imm = Imm;
1697    Op->StartLoc = S;
1698    Op->EndLoc = E;
1699    return Op;
1700  }
1701
1702  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1703    ARMOperand *Op = new ARMOperand(k_RotateImmediate);
1704    Op->RotImm.Imm = Imm;
1705    Op->StartLoc = S;
1706    Op->EndLoc = E;
1707    return Op;
1708  }
1709
1710  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1711                                    SMLoc S, SMLoc E) {
1712    ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
1713    Op->Bitfield.LSB = LSB;
1714    Op->Bitfield.Width = Width;
1715    Op->StartLoc = S;
1716    Op->EndLoc = E;
1717    return Op;
1718  }
1719
1720  static ARMOperand *
1721  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1722                SMLoc StartLoc, SMLoc EndLoc) {
1723    KindTy Kind = k_RegisterList;
1724
1725    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
1726      Kind = k_DPRRegisterList;
1727    else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
1728             contains(Regs.front().first))
1729      Kind = k_SPRRegisterList;
1730
1731    ARMOperand *Op = new ARMOperand(Kind);
1732    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1733           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1734      Op->Registers.push_back(I->first);
1735    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1736    Op->StartLoc = StartLoc;
1737    Op->EndLoc = EndLoc;
1738    return Op;
1739  }
1740
1741  static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
1742                                      SMLoc S, SMLoc E) {
1743    ARMOperand *Op = new ARMOperand(k_VectorList);
1744    Op->VectorList.RegNum = RegNum;
1745    Op->VectorList.Count = Count;
1746    Op->StartLoc = S;
1747    Op->EndLoc = E;
1748    return Op;
1749  }
1750
1751  static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
1752                                       MCContext &Ctx) {
1753    ARMOperand *Op = new ARMOperand(k_VectorIndex);
1754    Op->VectorIndex.Val = Idx;
1755    Op->StartLoc = S;
1756    Op->EndLoc = E;
1757    return Op;
1758  }
1759
1760  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1761    ARMOperand *Op = new ARMOperand(k_Immediate);
1762    Op->Imm.Val = Val;
1763    Op->StartLoc = S;
1764    Op->EndLoc = E;
1765    return Op;
1766  }
1767
1768  static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) {
1769    ARMOperand *Op = new ARMOperand(k_FPImmediate);
1770    Op->FPImm.Val = Val;
1771    Op->StartLoc = S;
1772    Op->EndLoc = S;
1773    return Op;
1774  }
1775
1776  static ARMOperand *CreateMem(unsigned BaseRegNum,
1777                               const MCConstantExpr *OffsetImm,
1778                               unsigned OffsetRegNum,
1779                               ARM_AM::ShiftOpc ShiftType,
1780                               unsigned ShiftImm,
1781                               unsigned Alignment,
1782                               bool isNegative,
1783                               SMLoc S, SMLoc E) {
1784    ARMOperand *Op = new ARMOperand(k_Memory);
1785    Op->Memory.BaseRegNum = BaseRegNum;
1786    Op->Memory.OffsetImm = OffsetImm;
1787    Op->Memory.OffsetRegNum = OffsetRegNum;
1788    Op->Memory.ShiftType = ShiftType;
1789    Op->Memory.ShiftImm = ShiftImm;
1790    Op->Memory.Alignment = Alignment;
1791    Op->Memory.isNegative = isNegative;
1792    Op->StartLoc = S;
1793    Op->EndLoc = E;
1794    return Op;
1795  }
1796
1797  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1798                                      ARM_AM::ShiftOpc ShiftTy,
1799                                      unsigned ShiftImm,
1800                                      SMLoc S, SMLoc E) {
1801    ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
1802    Op->PostIdxReg.RegNum = RegNum;
1803    Op->PostIdxReg.isAdd = isAdd;
1804    Op->PostIdxReg.ShiftTy = ShiftTy;
1805    Op->PostIdxReg.ShiftImm = ShiftImm;
1806    Op->StartLoc = S;
1807    Op->EndLoc = E;
1808    return Op;
1809  }
1810
1811  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1812    ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
1813    Op->MBOpt.Val = Opt;
1814    Op->StartLoc = S;
1815    Op->EndLoc = S;
1816    return Op;
1817  }
1818
1819  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1820    ARMOperand *Op = new ARMOperand(k_ProcIFlags);
1821    Op->IFlags.Val = IFlags;
1822    Op->StartLoc = S;
1823    Op->EndLoc = S;
1824    return Op;
1825  }
1826
1827  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1828    ARMOperand *Op = new ARMOperand(k_MSRMask);
1829    Op->MMask.Val = MMask;
1830    Op->StartLoc = S;
1831    Op->EndLoc = S;
1832    return Op;
1833  }
1834};
1835
1836} // end anonymous namespace.
1837
1838void ARMOperand::print(raw_ostream &OS) const {
1839  switch (Kind) {
1840  case k_FPImmediate:
1841    OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm())
1842       << ") >";
1843    break;
1844  case k_CondCode:
1845    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1846    break;
1847  case k_CCOut:
1848    OS << "<ccout " << getReg() << ">";
1849    break;
1850  case k_ITCondMask: {
1851    static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)",
1852      "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)",
1853      "(tee)", "(eee)" };
1854    assert((ITMask.Mask & 0xf) == ITMask.Mask);
1855    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1856    break;
1857  }
1858  case k_CoprocNum:
1859    OS << "<coprocessor number: " << getCoproc() << ">";
1860    break;
1861  case k_CoprocReg:
1862    OS << "<coprocessor register: " << getCoproc() << ">";
1863    break;
1864  case k_CoprocOption:
1865    OS << "<coprocessor option: " << CoprocOption.Val << ">";
1866    break;
1867  case k_MSRMask:
1868    OS << "<mask: " << getMSRMask() << ">";
1869    break;
1870  case k_Immediate:
1871    getImm()->print(OS);
1872    break;
1873  case k_MemBarrierOpt:
1874    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1875    break;
1876  case k_Memory:
1877    OS << "<memory "
1878       << " base:" << Memory.BaseRegNum;
1879    OS << ">";
1880    break;
1881  case k_PostIndexRegister:
1882    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1883       << PostIdxReg.RegNum;
1884    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1885      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1886         << PostIdxReg.ShiftImm;
1887    OS << ">";
1888    break;
1889  case k_ProcIFlags: {
1890    OS << "<ARM_PROC::";
1891    unsigned IFlags = getProcIFlags();
1892    for (int i=2; i >= 0; --i)
1893      if (IFlags & (1 << i))
1894        OS << ARM_PROC::IFlagsToString(1 << i);
1895    OS << ">";
1896    break;
1897  }
1898  case k_Register:
1899    OS << "<register " << getReg() << ">";
1900    break;
1901  case k_ShifterImmediate:
1902    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1903       << " #" << ShifterImm.Imm << ">";
1904    break;
1905  case k_ShiftedRegister:
1906    OS << "<so_reg_reg "
1907       << RegShiftedReg.SrcReg
1908       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1909       << ", " << RegShiftedReg.ShiftReg << ", "
1910       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1911       << ">";
1912    break;
1913  case k_ShiftedImmediate:
1914    OS << "<so_reg_imm "
1915       << RegShiftedImm.SrcReg
1916       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1917       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1918       << ">";
1919    break;
1920  case k_RotateImmediate:
1921    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1922    break;
1923  case k_BitfieldDescriptor:
1924    OS << "<bitfield " << "lsb: " << Bitfield.LSB
1925       << ", width: " << Bitfield.Width << ">";
1926    break;
1927  case k_RegisterList:
1928  case k_DPRRegisterList:
1929  case k_SPRRegisterList: {
1930    OS << "<register_list ";
1931
1932    const SmallVectorImpl<unsigned> &RegList = getRegList();
1933    for (SmallVectorImpl<unsigned>::const_iterator
1934           I = RegList.begin(), E = RegList.end(); I != E; ) {
1935      OS << *I;
1936      if (++I < E) OS << ", ";
1937    }
1938
1939    OS << ">";
1940    break;
1941  }
1942  case k_VectorList:
1943    OS << "<vector_list " << VectorList.Count << " * "
1944       << VectorList.RegNum << ">";
1945    break;
1946  case k_Token:
1947    OS << "'" << getToken() << "'";
1948    break;
1949  case k_VectorIndex:
1950    OS << "<vectorindex " << getVectorIndex() << ">";
1951    break;
1952  }
1953}
1954
1955/// @name Auto-generated Match Functions
1956/// {
1957
1958static unsigned MatchRegisterName(StringRef Name);
1959
1960/// }
1961
1962bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1963                                 SMLoc &StartLoc, SMLoc &EndLoc) {
1964  RegNo = tryParseRegister();
1965
1966  return (RegNo == (unsigned)-1);
1967}
1968
1969/// Try to parse a register name.  The token must be an Identifier when called,
1970/// and if it is a register name the token is eaten and the register number is
1971/// returned.  Otherwise return -1.
1972///
1973int ARMAsmParser::tryParseRegister() {
1974  const AsmToken &Tok = Parser.getTok();
1975  if (Tok.isNot(AsmToken::Identifier)) return -1;
1976
1977  // FIXME: Validate register for the current architecture; we have to do
1978  // validation later, so maybe there is no need for this here.
1979  std::string upperCase = Tok.getString().str();
1980  std::string lowerCase = LowercaseString(upperCase);
1981  unsigned RegNum = MatchRegisterName(lowerCase);
1982  if (!RegNum) {
1983    RegNum = StringSwitch<unsigned>(lowerCase)
1984      .Case("r13", ARM::SP)
1985      .Case("r14", ARM::LR)
1986      .Case("r15", ARM::PC)
1987      .Case("ip", ARM::R12)
1988      .Default(0);
1989  }
1990  if (!RegNum) return -1;
1991
1992  Parser.Lex(); // Eat identifier token.
1993
1994  return RegNum;
1995}
1996
1997// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
1998// If a recoverable error occurs, return 1. If an irrecoverable error
1999// occurs, return -1. An irrecoverable error is one where tokens have been
2000// consumed in the process of trying to parse the shifter (i.e., when it is
2001// indeed a shifter operand, but malformed).
2002int ARMAsmParser::tryParseShiftRegister(
2003                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2004  SMLoc S = Parser.getTok().getLoc();
2005  const AsmToken &Tok = Parser.getTok();
2006  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2007
2008  std::string upperCase = Tok.getString().str();
2009  std::string lowerCase = LowercaseString(upperCase);
2010  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2011      .Case("lsl", ARM_AM::lsl)
2012      .Case("lsr", ARM_AM::lsr)
2013      .Case("asr", ARM_AM::asr)
2014      .Case("ror", ARM_AM::ror)
2015      .Case("rrx", ARM_AM::rrx)
2016      .Default(ARM_AM::no_shift);
2017
2018  if (ShiftTy == ARM_AM::no_shift)
2019    return 1;
2020
2021  Parser.Lex(); // Eat the operator.
2022
2023  // The source register for the shift has already been added to the
2024  // operand list, so we need to pop it off and combine it into the shifted
2025  // register operand instead.
2026  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2027  if (!PrevOp->isReg())
2028    return Error(PrevOp->getStartLoc(), "shift must be of a register");
2029  int SrcReg = PrevOp->getReg();
2030  int64_t Imm = 0;
2031  int ShiftReg = 0;
2032  if (ShiftTy == ARM_AM::rrx) {
2033    // RRX Doesn't have an explicit shift amount. The encoder expects
2034    // the shift register to be the same as the source register. Seems odd,
2035    // but OK.
2036    ShiftReg = SrcReg;
2037  } else {
2038    // Figure out if this is shifted by a constant or a register (for non-RRX).
2039    if (Parser.getTok().is(AsmToken::Hash)) {
2040      Parser.Lex(); // Eat hash.
2041      SMLoc ImmLoc = Parser.getTok().getLoc();
2042      const MCExpr *ShiftExpr = 0;
2043      if (getParser().ParseExpression(ShiftExpr)) {
2044        Error(ImmLoc, "invalid immediate shift value");
2045        return -1;
2046      }
2047      // The expression must be evaluatable as an immediate.
2048      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2049      if (!CE) {
2050        Error(ImmLoc, "invalid immediate shift value");
2051        return -1;
2052      }
2053      // Range check the immediate.
2054      // lsl, ror: 0 <= imm <= 31
2055      // lsr, asr: 0 <= imm <= 32
2056      Imm = CE->getValue();
2057      if (Imm < 0 ||
2058          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2059          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2060        Error(ImmLoc, "immediate shift value out of range");
2061        return -1;
2062      }
2063    } else if (Parser.getTok().is(AsmToken::Identifier)) {
2064      ShiftReg = tryParseRegister();
2065      SMLoc L = Parser.getTok().getLoc();
2066      if (ShiftReg == -1) {
2067        Error (L, "expected immediate or register in shift operand");
2068        return -1;
2069      }
2070    } else {
2071      Error (Parser.getTok().getLoc(),
2072                    "expected immediate or register in shift operand");
2073      return -1;
2074    }
2075  }
2076
2077  if (ShiftReg && ShiftTy != ARM_AM::rrx)
2078    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2079                                                         ShiftReg, Imm,
2080                                               S, Parser.getTok().getLoc()));
2081  else
2082    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2083                                               S, Parser.getTok().getLoc()));
2084
2085  return 0;
2086}
2087
2088
2089/// Try to parse a register name.  The token must be an Identifier when called.
2090/// If it's a register, an AsmOperand is created. Another AsmOperand is created
2091/// if there is a "writeback". 'true' if it's not a register.
2092///
2093/// TODO this is likely to change to allow different register types and or to
2094/// parse for a specific register type.
2095bool ARMAsmParser::
2096tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2097  SMLoc S = Parser.getTok().getLoc();
2098  int RegNo = tryParseRegister();
2099  if (RegNo == -1)
2100    return true;
2101
2102  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2103
2104  const AsmToken &ExclaimTok = Parser.getTok();
2105  if (ExclaimTok.is(AsmToken::Exclaim)) {
2106    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2107                                               ExclaimTok.getLoc()));
2108    Parser.Lex(); // Eat exclaim token
2109    return false;
2110  }
2111
2112  // Also check for an index operand. This is only legal for vector registers,
2113  // but that'll get caught OK in operand matching, so we don't need to
2114  // explicitly filter everything else out here.
2115  if (Parser.getTok().is(AsmToken::LBrac)) {
2116    SMLoc SIdx = Parser.getTok().getLoc();
2117    Parser.Lex(); // Eat left bracket token.
2118
2119    const MCExpr *ImmVal;
2120    if (getParser().ParseExpression(ImmVal))
2121      return MatchOperand_ParseFail;
2122    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2123    if (!MCE) {
2124      TokError("immediate value expected for vector index");
2125      return MatchOperand_ParseFail;
2126    }
2127
2128    SMLoc E = Parser.getTok().getLoc();
2129    if (Parser.getTok().isNot(AsmToken::RBrac)) {
2130      Error(E, "']' expected");
2131      return MatchOperand_ParseFail;
2132    }
2133
2134    Parser.Lex(); // Eat right bracket token.
2135
2136    Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2137                                                     SIdx, E,
2138                                                     getContext()));
2139  }
2140
2141  return false;
2142}
2143
2144/// MatchCoprocessorOperandName - Try to parse an coprocessor related
2145/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2146/// "c5", ...
2147static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2148  // Use the same layout as the tablegen'erated register name matcher. Ugly,
2149  // but efficient.
2150  switch (Name.size()) {
2151  default: break;
2152  case 2:
2153    if (Name[0] != CoprocOp)
2154      return -1;
2155    switch (Name[1]) {
2156    default:  return -1;
2157    case '0': return 0;
2158    case '1': return 1;
2159    case '2': return 2;
2160    case '3': return 3;
2161    case '4': return 4;
2162    case '5': return 5;
2163    case '6': return 6;
2164    case '7': return 7;
2165    case '8': return 8;
2166    case '9': return 9;
2167    }
2168    break;
2169  case 3:
2170    if (Name[0] != CoprocOp || Name[1] != '1')
2171      return -1;
2172    switch (Name[2]) {
2173    default:  return -1;
2174    case '0': return 10;
2175    case '1': return 11;
2176    case '2': return 12;
2177    case '3': return 13;
2178    case '4': return 14;
2179    case '5': return 15;
2180    }
2181    break;
2182  }
2183
2184  return -1;
2185}
2186
2187/// parseITCondCode - Try to parse a condition code for an IT instruction.
2188ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2189parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2190  SMLoc S = Parser.getTok().getLoc();
2191  const AsmToken &Tok = Parser.getTok();
2192  if (!Tok.is(AsmToken::Identifier))
2193    return MatchOperand_NoMatch;
2194  unsigned CC = StringSwitch<unsigned>(Tok.getString())
2195    .Case("eq", ARMCC::EQ)
2196    .Case("ne", ARMCC::NE)
2197    .Case("hs", ARMCC::HS)
2198    .Case("cs", ARMCC::HS)
2199    .Case("lo", ARMCC::LO)
2200    .Case("cc", ARMCC::LO)
2201    .Case("mi", ARMCC::MI)
2202    .Case("pl", ARMCC::PL)
2203    .Case("vs", ARMCC::VS)
2204    .Case("vc", ARMCC::VC)
2205    .Case("hi", ARMCC::HI)
2206    .Case("ls", ARMCC::LS)
2207    .Case("ge", ARMCC::GE)
2208    .Case("lt", ARMCC::LT)
2209    .Case("gt", ARMCC::GT)
2210    .Case("le", ARMCC::LE)
2211    .Case("al", ARMCC::AL)
2212    .Default(~0U);
2213  if (CC == ~0U)
2214    return MatchOperand_NoMatch;
2215  Parser.Lex(); // Eat the token.
2216
2217  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2218
2219  return MatchOperand_Success;
2220}
2221
2222/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2223/// token must be an Identifier when called, and if it is a coprocessor
2224/// number, the token is eaten and the operand is added to the operand list.
2225ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2226parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2227  SMLoc S = Parser.getTok().getLoc();
2228  const AsmToken &Tok = Parser.getTok();
2229  if (Tok.isNot(AsmToken::Identifier))
2230    return MatchOperand_NoMatch;
2231
2232  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2233  if (Num == -1)
2234    return MatchOperand_NoMatch;
2235
2236  Parser.Lex(); // Eat identifier token.
2237  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2238  return MatchOperand_Success;
2239}
2240
2241/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2242/// token must be an Identifier when called, and if it is a coprocessor
2243/// number, the token is eaten and the operand is added to the operand list.
2244ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2245parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2246  SMLoc S = Parser.getTok().getLoc();
2247  const AsmToken &Tok = Parser.getTok();
2248  if (Tok.isNot(AsmToken::Identifier))
2249    return MatchOperand_NoMatch;
2250
2251  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2252  if (Reg == -1)
2253    return MatchOperand_NoMatch;
2254
2255  Parser.Lex(); // Eat identifier token.
2256  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2257  return MatchOperand_Success;
2258}
2259
2260/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2261/// coproc_option : '{' imm0_255 '}'
2262ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2263parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2264  SMLoc S = Parser.getTok().getLoc();
2265
2266  // If this isn't a '{', this isn't a coprocessor immediate operand.
2267  if (Parser.getTok().isNot(AsmToken::LCurly))
2268    return MatchOperand_NoMatch;
2269  Parser.Lex(); // Eat the '{'
2270
2271  const MCExpr *Expr;
2272  SMLoc Loc = Parser.getTok().getLoc();
2273  if (getParser().ParseExpression(Expr)) {
2274    Error(Loc, "illegal expression");
2275    return MatchOperand_ParseFail;
2276  }
2277  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2278  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2279    Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2280    return MatchOperand_ParseFail;
2281  }
2282  int Val = CE->getValue();
2283
2284  // Check for and consume the closing '}'
2285  if (Parser.getTok().isNot(AsmToken::RCurly))
2286    return MatchOperand_ParseFail;
2287  SMLoc E = Parser.getTok().getLoc();
2288  Parser.Lex(); // Eat the '}'
2289
2290  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2291  return MatchOperand_Success;
2292}
2293
2294// For register list parsing, we need to map from raw GPR register numbering
2295// to the enumeration values. The enumeration values aren't sorted by
2296// register number due to our using "sp", "lr" and "pc" as canonical names.
2297static unsigned getNextRegister(unsigned Reg) {
2298  // If this is a GPR, we need to do it manually, otherwise we can rely
2299  // on the sort ordering of the enumeration since the other reg-classes
2300  // are sane.
2301  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2302    return Reg + 1;
2303  switch(Reg) {
2304  default: assert(0 && "Invalid GPR number!");
2305  case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
2306  case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
2307  case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
2308  case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
2309  case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
2310  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2311  case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
2312  case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
2313  }
2314}
2315
2316/// Parse a register list.
2317bool ARMAsmParser::
2318parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2319  assert(Parser.getTok().is(AsmToken::LCurly) &&
2320         "Token is not a Left Curly Brace");
2321  SMLoc S = Parser.getTok().getLoc();
2322  Parser.Lex(); // Eat '{' token.
2323  SMLoc RegLoc = Parser.getTok().getLoc();
2324
2325  // Check the first register in the list to see what register class
2326  // this is a list of.
2327  int Reg = tryParseRegister();
2328  if (Reg == -1)
2329    return Error(RegLoc, "register expected");
2330
2331  MCRegisterClass *RC;
2332  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2333    RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2334  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2335    RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2336  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2337    RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2338  else
2339    return Error(RegLoc, "invalid register in register list");
2340
2341  // The reglist instructions have at most 16 registers, so reserve
2342  // space for that many.
2343  SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2344  // Store the first register.
2345  Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2346
2347  // This starts immediately after the first register token in the list,
2348  // so we can see either a comma or a minus (range separator) as a legal
2349  // next token.
2350  while (Parser.getTok().is(AsmToken::Comma) ||
2351         Parser.getTok().is(AsmToken::Minus)) {
2352    if (Parser.getTok().is(AsmToken::Minus)) {
2353      Parser.Lex(); // Eat the comma.
2354      SMLoc EndLoc = Parser.getTok().getLoc();
2355      int EndReg = tryParseRegister();
2356      if (EndReg == -1)
2357        return Error(EndLoc, "register expected");
2358      // If the register is the same as the start reg, there's nothing
2359      // more to do.
2360      if (Reg == EndReg)
2361        continue;
2362      // The register must be in the same register class as the first.
2363      if (!RC->contains(EndReg))
2364        return Error(EndLoc, "invalid register in register list");
2365      // Ranges must go from low to high.
2366      if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
2367        return Error(EndLoc, "bad range in register list");
2368
2369      // Add all the registers in the range to the register list.
2370      while (Reg != EndReg) {
2371        Reg = getNextRegister(Reg);
2372        Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2373      }
2374      continue;
2375    }
2376    Parser.Lex(); // Eat the comma.
2377    RegLoc = Parser.getTok().getLoc();
2378    int OldReg = Reg;
2379    Reg = tryParseRegister();
2380    if (Reg == -1)
2381      return Error(RegLoc, "register expected");
2382    // The register must be in the same register class as the first.
2383    if (!RC->contains(Reg))
2384      return Error(RegLoc, "invalid register in register list");
2385    // List must be monotonically increasing.
2386    if (getARMRegisterNumbering(Reg) <= getARMRegisterNumbering(OldReg))
2387      return Error(RegLoc, "register list not in ascending order");
2388    // VFP register lists must also be contiguous.
2389    // It's OK to use the enumeration values directly here rather, as the
2390    // VFP register classes have the enum sorted properly.
2391    if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2392        Reg != OldReg + 1)
2393      return Error(RegLoc, "non-contiguous register range");
2394    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2395  }
2396
2397  SMLoc E = Parser.getTok().getLoc();
2398  if (Parser.getTok().isNot(AsmToken::RCurly))
2399    return Error(E, "'}' expected");
2400  Parser.Lex(); // Eat '}' token.
2401
2402  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2403  return false;
2404}
2405
2406// parse a vector register list
2407ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2408parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2409  if(Parser.getTok().isNot(AsmToken::LCurly))
2410    return MatchOperand_NoMatch;
2411
2412  SMLoc S = Parser.getTok().getLoc();
2413  Parser.Lex(); // Eat '{' token.
2414  SMLoc RegLoc = Parser.getTok().getLoc();
2415
2416  int Reg = tryParseRegister();
2417  if (Reg == -1) {
2418    Error(RegLoc, "register expected");
2419    return MatchOperand_ParseFail;
2420  }
2421
2422  unsigned FirstReg = Reg;
2423  unsigned Count = 1;
2424  while (Parser.getTok().is(AsmToken::Comma)) {
2425    Parser.Lex(); // Eat the comma.
2426    RegLoc = Parser.getTok().getLoc();
2427    int OldReg = Reg;
2428    Reg = tryParseRegister();
2429    if (Reg == -1) {
2430      Error(RegLoc, "register expected");
2431      return MatchOperand_ParseFail;
2432    }
2433    // vector register lists must also be contiguous.
2434    // It's OK to use the enumeration values directly here rather, as the
2435    // VFP register classes have the enum sorted properly.
2436    if (Reg != OldReg + 1) {
2437      Error(RegLoc, "non-contiguous register range");
2438      return MatchOperand_ParseFail;
2439    }
2440
2441    ++Count;
2442  }
2443
2444  SMLoc E = Parser.getTok().getLoc();
2445  if (Parser.getTok().isNot(AsmToken::RCurly)) {
2446    Error(E, "'}' expected");
2447    return MatchOperand_ParseFail;
2448  }
2449  Parser.Lex(); // Eat '}' token.
2450
2451  Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, S, E));
2452  return MatchOperand_Success;
2453}
2454
2455/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
2456ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2457parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2458  SMLoc S = Parser.getTok().getLoc();
2459  const AsmToken &Tok = Parser.getTok();
2460  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2461  StringRef OptStr = Tok.getString();
2462
2463  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
2464    .Case("sy",    ARM_MB::SY)
2465    .Case("st",    ARM_MB::ST)
2466    .Case("sh",    ARM_MB::ISH)
2467    .Case("ish",   ARM_MB::ISH)
2468    .Case("shst",  ARM_MB::ISHST)
2469    .Case("ishst", ARM_MB::ISHST)
2470    .Case("nsh",   ARM_MB::NSH)
2471    .Case("un",    ARM_MB::NSH)
2472    .Case("nshst", ARM_MB::NSHST)
2473    .Case("unst",  ARM_MB::NSHST)
2474    .Case("osh",   ARM_MB::OSH)
2475    .Case("oshst", ARM_MB::OSHST)
2476    .Default(~0U);
2477
2478  if (Opt == ~0U)
2479    return MatchOperand_NoMatch;
2480
2481  Parser.Lex(); // Eat identifier token.
2482  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
2483  return MatchOperand_Success;
2484}
2485
2486/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
2487ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2488parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2489  SMLoc S = Parser.getTok().getLoc();
2490  const AsmToken &Tok = Parser.getTok();
2491  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2492  StringRef IFlagsStr = Tok.getString();
2493
2494  // An iflags string of "none" is interpreted to mean that none of the AIF
2495  // bits are set.  Not a terribly useful instruction, but a valid encoding.
2496  unsigned IFlags = 0;
2497  if (IFlagsStr != "none") {
2498        for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
2499      unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
2500        .Case("a", ARM_PROC::A)
2501        .Case("i", ARM_PROC::I)
2502        .Case("f", ARM_PROC::F)
2503        .Default(~0U);
2504
2505      // If some specific iflag is already set, it means that some letter is
2506      // present more than once, this is not acceptable.
2507      if (Flag == ~0U || (IFlags & Flag))
2508        return MatchOperand_NoMatch;
2509
2510      IFlags |= Flag;
2511    }
2512  }
2513
2514  Parser.Lex(); // Eat identifier token.
2515  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
2516  return MatchOperand_Success;
2517}
2518
2519/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
2520ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2521parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2522  SMLoc S = Parser.getTok().getLoc();
2523  const AsmToken &Tok = Parser.getTok();
2524  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2525  StringRef Mask = Tok.getString();
2526
2527  if (isMClass()) {
2528    // See ARMv6-M 10.1.1
2529    unsigned FlagsVal = StringSwitch<unsigned>(Mask)
2530      .Case("apsr", 0)
2531      .Case("iapsr", 1)
2532      .Case("eapsr", 2)
2533      .Case("xpsr", 3)
2534      .Case("ipsr", 5)
2535      .Case("epsr", 6)
2536      .Case("iepsr", 7)
2537      .Case("msp", 8)
2538      .Case("psp", 9)
2539      .Case("primask", 16)
2540      .Case("basepri", 17)
2541      .Case("basepri_max", 18)
2542      .Case("faultmask", 19)
2543      .Case("control", 20)
2544      .Default(~0U);
2545
2546    if (FlagsVal == ~0U)
2547      return MatchOperand_NoMatch;
2548
2549    if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
2550      // basepri, basepri_max and faultmask only valid for V7m.
2551      return MatchOperand_NoMatch;
2552
2553    Parser.Lex(); // Eat identifier token.
2554    Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2555    return MatchOperand_Success;
2556  }
2557
2558  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
2559  size_t Start = 0, Next = Mask.find('_');
2560  StringRef Flags = "";
2561  std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
2562  if (Next != StringRef::npos)
2563    Flags = Mask.slice(Next+1, Mask.size());
2564
2565  // FlagsVal contains the complete mask:
2566  // 3-0: Mask
2567  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2568  unsigned FlagsVal = 0;
2569
2570  if (SpecReg == "apsr") {
2571    FlagsVal = StringSwitch<unsigned>(Flags)
2572    .Case("nzcvq",  0x8) // same as CPSR_f
2573    .Case("g",      0x4) // same as CPSR_s
2574    .Case("nzcvqg", 0xc) // same as CPSR_fs
2575    .Default(~0U);
2576
2577    if (FlagsVal == ~0U) {
2578      if (!Flags.empty())
2579        return MatchOperand_NoMatch;
2580      else
2581        FlagsVal = 8; // No flag
2582    }
2583  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
2584    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
2585      Flags = "fc";
2586    for (int i = 0, e = Flags.size(); i != e; ++i) {
2587      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
2588      .Case("c", 1)
2589      .Case("x", 2)
2590      .Case("s", 4)
2591      .Case("f", 8)
2592      .Default(~0U);
2593
2594      // If some specific flag is already set, it means that some letter is
2595      // present more than once, this is not acceptable.
2596      if (FlagsVal == ~0U || (FlagsVal & Flag))
2597        return MatchOperand_NoMatch;
2598      FlagsVal |= Flag;
2599    }
2600  } else // No match for special register.
2601    return MatchOperand_NoMatch;
2602
2603  // Special register without flags is NOT equivalent to "fc" flags.
2604  // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
2605  // two lines would enable gas compatibility at the expense of breaking
2606  // round-tripping.
2607  //
2608  // if (!FlagsVal)
2609  //  FlagsVal = 0x9;
2610
2611  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2612  if (SpecReg == "spsr")
2613    FlagsVal |= 16;
2614
2615  Parser.Lex(); // Eat identifier token.
2616  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2617  return MatchOperand_Success;
2618}
2619
2620ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2621parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
2622            int Low, int High) {
2623  const AsmToken &Tok = Parser.getTok();
2624  if (Tok.isNot(AsmToken::Identifier)) {
2625    Error(Parser.getTok().getLoc(), Op + " operand expected.");
2626    return MatchOperand_ParseFail;
2627  }
2628  StringRef ShiftName = Tok.getString();
2629  std::string LowerOp = LowercaseString(Op);
2630  std::string UpperOp = UppercaseString(Op);
2631  if (ShiftName != LowerOp && ShiftName != UpperOp) {
2632    Error(Parser.getTok().getLoc(), Op + " operand expected.");
2633    return MatchOperand_ParseFail;
2634  }
2635  Parser.Lex(); // Eat shift type token.
2636
2637  // There must be a '#' and a shift amount.
2638  if (Parser.getTok().isNot(AsmToken::Hash)) {
2639    Error(Parser.getTok().getLoc(), "'#' expected");
2640    return MatchOperand_ParseFail;
2641  }
2642  Parser.Lex(); // Eat hash token.
2643
2644  const MCExpr *ShiftAmount;
2645  SMLoc Loc = Parser.getTok().getLoc();
2646  if (getParser().ParseExpression(ShiftAmount)) {
2647    Error(Loc, "illegal expression");
2648    return MatchOperand_ParseFail;
2649  }
2650  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2651  if (!CE) {
2652    Error(Loc, "constant expression expected");
2653    return MatchOperand_ParseFail;
2654  }
2655  int Val = CE->getValue();
2656  if (Val < Low || Val > High) {
2657    Error(Loc, "immediate value out of range");
2658    return MatchOperand_ParseFail;
2659  }
2660
2661  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
2662
2663  return MatchOperand_Success;
2664}
2665
2666ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2667parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2668  const AsmToken &Tok = Parser.getTok();
2669  SMLoc S = Tok.getLoc();
2670  if (Tok.isNot(AsmToken::Identifier)) {
2671    Error(Tok.getLoc(), "'be' or 'le' operand expected");
2672    return MatchOperand_ParseFail;
2673  }
2674  int Val = StringSwitch<int>(Tok.getString())
2675    .Case("be", 1)
2676    .Case("le", 0)
2677    .Default(-1);
2678  Parser.Lex(); // Eat the token.
2679
2680  if (Val == -1) {
2681    Error(Tok.getLoc(), "'be' or 'le' operand expected");
2682    return MatchOperand_ParseFail;
2683  }
2684  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2685                                                                  getContext()),
2686                                           S, Parser.getTok().getLoc()));
2687  return MatchOperand_Success;
2688}
2689
2690/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2691/// instructions. Legal values are:
2692///     lsl #n  'n' in [0,31]
2693///     asr #n  'n' in [1,32]
2694///             n == 32 encoded as n == 0.
2695ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2696parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2697  const AsmToken &Tok = Parser.getTok();
2698  SMLoc S = Tok.getLoc();
2699  if (Tok.isNot(AsmToken::Identifier)) {
2700    Error(S, "shift operator 'asr' or 'lsl' expected");
2701    return MatchOperand_ParseFail;
2702  }
2703  StringRef ShiftName = Tok.getString();
2704  bool isASR;
2705  if (ShiftName == "lsl" || ShiftName == "LSL")
2706    isASR = false;
2707  else if (ShiftName == "asr" || ShiftName == "ASR")
2708    isASR = true;
2709  else {
2710    Error(S, "shift operator 'asr' or 'lsl' expected");
2711    return MatchOperand_ParseFail;
2712  }
2713  Parser.Lex(); // Eat the operator.
2714
2715  // A '#' and a shift amount.
2716  if (Parser.getTok().isNot(AsmToken::Hash)) {
2717    Error(Parser.getTok().getLoc(), "'#' expected");
2718    return MatchOperand_ParseFail;
2719  }
2720  Parser.Lex(); // Eat hash token.
2721
2722  const MCExpr *ShiftAmount;
2723  SMLoc E = Parser.getTok().getLoc();
2724  if (getParser().ParseExpression(ShiftAmount)) {
2725    Error(E, "malformed shift expression");
2726    return MatchOperand_ParseFail;
2727  }
2728  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2729  if (!CE) {
2730    Error(E, "shift amount must be an immediate");
2731    return MatchOperand_ParseFail;
2732  }
2733
2734  int64_t Val = CE->getValue();
2735  if (isASR) {
2736    // Shift amount must be in [1,32]
2737    if (Val < 1 || Val > 32) {
2738      Error(E, "'asr' shift amount must be in range [1,32]");
2739      return MatchOperand_ParseFail;
2740    }
2741    // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
2742    if (isThumb() && Val == 32) {
2743      Error(E, "'asr #32' shift amount not allowed in Thumb mode");
2744      return MatchOperand_ParseFail;
2745    }
2746    if (Val == 32) Val = 0;
2747  } else {
2748    // Shift amount must be in [1,32]
2749    if (Val < 0 || Val > 31) {
2750      Error(E, "'lsr' shift amount must be in range [0,31]");
2751      return MatchOperand_ParseFail;
2752    }
2753  }
2754
2755  E = Parser.getTok().getLoc();
2756  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2757
2758  return MatchOperand_Success;
2759}
2760
2761/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2762/// of instructions. Legal values are:
2763///     ror #n  'n' in {0, 8, 16, 24}
2764ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2765parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2766  const AsmToken &Tok = Parser.getTok();
2767  SMLoc S = Tok.getLoc();
2768  if (Tok.isNot(AsmToken::Identifier))
2769    return MatchOperand_NoMatch;
2770  StringRef ShiftName = Tok.getString();
2771  if (ShiftName != "ror" && ShiftName != "ROR")
2772    return MatchOperand_NoMatch;
2773  Parser.Lex(); // Eat the operator.
2774
2775  // A '#' and a rotate amount.
2776  if (Parser.getTok().isNot(AsmToken::Hash)) {
2777    Error(Parser.getTok().getLoc(), "'#' expected");
2778    return MatchOperand_ParseFail;
2779  }
2780  Parser.Lex(); // Eat hash token.
2781
2782  const MCExpr *ShiftAmount;
2783  SMLoc E = Parser.getTok().getLoc();
2784  if (getParser().ParseExpression(ShiftAmount)) {
2785    Error(E, "malformed rotate expression");
2786    return MatchOperand_ParseFail;
2787  }
2788  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2789  if (!CE) {
2790    Error(E, "rotate amount must be an immediate");
2791    return MatchOperand_ParseFail;
2792  }
2793
2794  int64_t Val = CE->getValue();
2795  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2796  // normally, zero is represented in asm by omitting the rotate operand
2797  // entirely.
2798  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2799    Error(E, "'ror' rotate amount must be 8, 16, or 24");
2800    return MatchOperand_ParseFail;
2801  }
2802
2803  E = Parser.getTok().getLoc();
2804  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2805
2806  return MatchOperand_Success;
2807}
2808
2809ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2810parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2811  SMLoc S = Parser.getTok().getLoc();
2812  // The bitfield descriptor is really two operands, the LSB and the width.
2813  if (Parser.getTok().isNot(AsmToken::Hash)) {
2814    Error(Parser.getTok().getLoc(), "'#' expected");
2815    return MatchOperand_ParseFail;
2816  }
2817  Parser.Lex(); // Eat hash token.
2818
2819  const MCExpr *LSBExpr;
2820  SMLoc E = Parser.getTok().getLoc();
2821  if (getParser().ParseExpression(LSBExpr)) {
2822    Error(E, "malformed immediate expression");
2823    return MatchOperand_ParseFail;
2824  }
2825  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2826  if (!CE) {
2827    Error(E, "'lsb' operand must be an immediate");
2828    return MatchOperand_ParseFail;
2829  }
2830
2831  int64_t LSB = CE->getValue();
2832  // The LSB must be in the range [0,31]
2833  if (LSB < 0 || LSB > 31) {
2834    Error(E, "'lsb' operand must be in the range [0,31]");
2835    return MatchOperand_ParseFail;
2836  }
2837  E = Parser.getTok().getLoc();
2838
2839  // Expect another immediate operand.
2840  if (Parser.getTok().isNot(AsmToken::Comma)) {
2841    Error(Parser.getTok().getLoc(), "too few operands");
2842    return MatchOperand_ParseFail;
2843  }
2844  Parser.Lex(); // Eat hash token.
2845  if (Parser.getTok().isNot(AsmToken::Hash)) {
2846    Error(Parser.getTok().getLoc(), "'#' expected");
2847    return MatchOperand_ParseFail;
2848  }
2849  Parser.Lex(); // Eat hash token.
2850
2851  const MCExpr *WidthExpr;
2852  if (getParser().ParseExpression(WidthExpr)) {
2853    Error(E, "malformed immediate expression");
2854    return MatchOperand_ParseFail;
2855  }
2856  CE = dyn_cast<MCConstantExpr>(WidthExpr);
2857  if (!CE) {
2858    Error(E, "'width' operand must be an immediate");
2859    return MatchOperand_ParseFail;
2860  }
2861
2862  int64_t Width = CE->getValue();
2863  // The LSB must be in the range [1,32-lsb]
2864  if (Width < 1 || Width > 32 - LSB) {
2865    Error(E, "'width' operand must be in the range [1,32-lsb]");
2866    return MatchOperand_ParseFail;
2867  }
2868  E = Parser.getTok().getLoc();
2869
2870  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2871
2872  return MatchOperand_Success;
2873}
2874
2875ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2876parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2877  // Check for a post-index addressing register operand. Specifically:
2878  // postidx_reg := '+' register {, shift}
2879  //              | '-' register {, shift}
2880  //              | register {, shift}
2881
2882  // This method must return MatchOperand_NoMatch without consuming any tokens
2883  // in the case where there is no match, as other alternatives take other
2884  // parse methods.
2885  AsmToken Tok = Parser.getTok();
2886  SMLoc S = Tok.getLoc();
2887  bool haveEaten = false;
2888  bool isAdd = true;
2889  int Reg = -1;
2890  if (Tok.is(AsmToken::Plus)) {
2891    Parser.Lex(); // Eat the '+' token.
2892    haveEaten = true;
2893  } else if (Tok.is(AsmToken::Minus)) {
2894    Parser.Lex(); // Eat the '-' token.
2895    isAdd = false;
2896    haveEaten = true;
2897  }
2898  if (Parser.getTok().is(AsmToken::Identifier))
2899    Reg = tryParseRegister();
2900  if (Reg == -1) {
2901    if (!haveEaten)
2902      return MatchOperand_NoMatch;
2903    Error(Parser.getTok().getLoc(), "register expected");
2904    return MatchOperand_ParseFail;
2905  }
2906  SMLoc E = Parser.getTok().getLoc();
2907
2908  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2909  unsigned ShiftImm = 0;
2910  if (Parser.getTok().is(AsmToken::Comma)) {
2911    Parser.Lex(); // Eat the ','.
2912    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2913      return MatchOperand_ParseFail;
2914  }
2915
2916  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2917                                                  ShiftImm, S, E));
2918
2919  return MatchOperand_Success;
2920}
2921
2922ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2923parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2924  // Check for a post-index addressing register operand. Specifically:
2925  // am3offset := '+' register
2926  //              | '-' register
2927  //              | register
2928  //              | # imm
2929  //              | # + imm
2930  //              | # - imm
2931
2932  // This method must return MatchOperand_NoMatch without consuming any tokens
2933  // in the case where there is no match, as other alternatives take other
2934  // parse methods.
2935  AsmToken Tok = Parser.getTok();
2936  SMLoc S = Tok.getLoc();
2937
2938  // Do immediates first, as we always parse those if we have a '#'.
2939  if (Parser.getTok().is(AsmToken::Hash)) {
2940    Parser.Lex(); // Eat the '#'.
2941    // Explicitly look for a '-', as we need to encode negative zero
2942    // differently.
2943    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2944    const MCExpr *Offset;
2945    if (getParser().ParseExpression(Offset))
2946      return MatchOperand_ParseFail;
2947    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2948    if (!CE) {
2949      Error(S, "constant expression expected");
2950      return MatchOperand_ParseFail;
2951    }
2952    SMLoc E = Tok.getLoc();
2953    // Negative zero is encoded as the flag value INT32_MIN.
2954    int32_t Val = CE->getValue();
2955    if (isNegative && Val == 0)
2956      Val = INT32_MIN;
2957
2958    Operands.push_back(
2959      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2960
2961    return MatchOperand_Success;
2962  }
2963
2964
2965  bool haveEaten = false;
2966  bool isAdd = true;
2967  int Reg = -1;
2968  if (Tok.is(AsmToken::Plus)) {
2969    Parser.Lex(); // Eat the '+' token.
2970    haveEaten = true;
2971  } else if (Tok.is(AsmToken::Minus)) {
2972    Parser.Lex(); // Eat the '-' token.
2973    isAdd = false;
2974    haveEaten = true;
2975  }
2976  if (Parser.getTok().is(AsmToken::Identifier))
2977    Reg = tryParseRegister();
2978  if (Reg == -1) {
2979    if (!haveEaten)
2980      return MatchOperand_NoMatch;
2981    Error(Parser.getTok().getLoc(), "register expected");
2982    return MatchOperand_ParseFail;
2983  }
2984  SMLoc E = Parser.getTok().getLoc();
2985
2986  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2987                                                  0, S, E));
2988
2989  return MatchOperand_Success;
2990}
2991
2992/// cvtT2LdrdPre - Convert parsed operands to MCInst.
2993/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2994/// when they refer multiple MIOperands inside a single one.
2995bool ARMAsmParser::
2996cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
2997             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2998  // Rt, Rt2
2999  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3000  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3001  // Create a writeback register dummy placeholder.
3002  Inst.addOperand(MCOperand::CreateReg(0));
3003  // addr
3004  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3005  // pred
3006  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3007  return true;
3008}
3009
3010/// cvtT2StrdPre - Convert parsed operands to MCInst.
3011/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3012/// when they refer multiple MIOperands inside a single one.
3013bool ARMAsmParser::
3014cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3015             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3016  // Create a writeback register dummy placeholder.
3017  Inst.addOperand(MCOperand::CreateReg(0));
3018  // Rt, Rt2
3019  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3020  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3021  // addr
3022  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3023  // pred
3024  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3025  return true;
3026}
3027
3028/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3029/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3030/// when they refer multiple MIOperands inside a single one.
3031bool ARMAsmParser::
3032cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3033                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3034  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3035
3036  // Create a writeback register dummy placeholder.
3037  Inst.addOperand(MCOperand::CreateImm(0));
3038
3039  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3040  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3041  return true;
3042}
3043
3044/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3045/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3046/// when they refer multiple MIOperands inside a single one.
3047bool ARMAsmParser::
3048cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3049                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3050  // Create a writeback register dummy placeholder.
3051  Inst.addOperand(MCOperand::CreateImm(0));
3052  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3053  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3054  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3055  return true;
3056}
3057
3058/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3059/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3060/// when they refer multiple MIOperands inside a single one.
3061bool ARMAsmParser::
3062cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3063                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3064  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3065
3066  // Create a writeback register dummy placeholder.
3067  Inst.addOperand(MCOperand::CreateImm(0));
3068
3069  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3070  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3071  return true;
3072}
3073
3074/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3075/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3076/// when they refer multiple MIOperands inside a single one.
3077bool ARMAsmParser::
3078cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3079                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3080  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3081
3082  // Create a writeback register dummy placeholder.
3083  Inst.addOperand(MCOperand::CreateImm(0));
3084
3085  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3086  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3087  return true;
3088}
3089
3090
3091/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3092/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3093/// when they refer multiple MIOperands inside a single one.
3094bool ARMAsmParser::
3095cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3096                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3097  // Create a writeback register dummy placeholder.
3098  Inst.addOperand(MCOperand::CreateImm(0));
3099  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3100  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3101  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3102  return true;
3103}
3104
3105/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3106/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3107/// when they refer multiple MIOperands inside a single one.
3108bool ARMAsmParser::
3109cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3110                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3111  // Create a writeback register dummy placeholder.
3112  Inst.addOperand(MCOperand::CreateImm(0));
3113  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3114  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3115  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3116  return true;
3117}
3118
3119/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3120/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3121/// when they refer multiple MIOperands inside a single one.
3122bool ARMAsmParser::
3123cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3124                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3125  // Create a writeback register dummy placeholder.
3126  Inst.addOperand(MCOperand::CreateImm(0));
3127  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3128  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3129  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3130  return true;
3131}
3132
3133/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
3134/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3135/// when they refer multiple MIOperands inside a single one.
3136bool ARMAsmParser::
3137cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3138                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3139  // Rt
3140  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3141  // Create a writeback register dummy placeholder.
3142  Inst.addOperand(MCOperand::CreateImm(0));
3143  // addr
3144  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3145  // offset
3146  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3147  // pred
3148  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3149  return true;
3150}
3151
3152/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
3153/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3154/// when they refer multiple MIOperands inside a single one.
3155bool ARMAsmParser::
3156cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3157                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3158  // Rt
3159  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3160  // Create a writeback register dummy placeholder.
3161  Inst.addOperand(MCOperand::CreateImm(0));
3162  // addr
3163  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3164  // offset
3165  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3166  // pred
3167  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3168  return true;
3169}
3170
3171/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
3172/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3173/// when they refer multiple MIOperands inside a single one.
3174bool ARMAsmParser::
3175cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3176                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3177  // Create a writeback register dummy placeholder.
3178  Inst.addOperand(MCOperand::CreateImm(0));
3179  // Rt
3180  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3181  // addr
3182  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3183  // offset
3184  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3185  // pred
3186  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3187  return true;
3188}
3189
3190/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
3191/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3192/// when they refer multiple MIOperands inside a single one.
3193bool ARMAsmParser::
3194cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3195                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3196  // Create a writeback register dummy placeholder.
3197  Inst.addOperand(MCOperand::CreateImm(0));
3198  // Rt
3199  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3200  // addr
3201  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3202  // offset
3203  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3204  // pred
3205  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3206  return true;
3207}
3208
3209/// cvtLdrdPre - Convert parsed operands to MCInst.
3210/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3211/// when they refer multiple MIOperands inside a single one.
3212bool ARMAsmParser::
3213cvtLdrdPre(MCInst &Inst, unsigned Opcode,
3214           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3215  // Rt, Rt2
3216  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3217  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3218  // Create a writeback register dummy placeholder.
3219  Inst.addOperand(MCOperand::CreateImm(0));
3220  // addr
3221  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3222  // pred
3223  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3224  return true;
3225}
3226
3227/// cvtStrdPre - Convert parsed operands to MCInst.
3228/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3229/// when they refer multiple MIOperands inside a single one.
3230bool ARMAsmParser::
3231cvtStrdPre(MCInst &Inst, unsigned Opcode,
3232           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3233  // Create a writeback register dummy placeholder.
3234  Inst.addOperand(MCOperand::CreateImm(0));
3235  // Rt, Rt2
3236  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3237  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3238  // addr
3239  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3240  // pred
3241  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3242  return true;
3243}
3244
3245/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3246/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3247/// when they refer multiple MIOperands inside a single one.
3248bool ARMAsmParser::
3249cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3250                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3251  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3252  // Create a writeback register dummy placeholder.
3253  Inst.addOperand(MCOperand::CreateImm(0));
3254  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3255  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3256  return true;
3257}
3258
3259/// cvtThumbMultiple- Convert parsed operands to MCInst.
3260/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3261/// when they refer multiple MIOperands inside a single one.
3262bool ARMAsmParser::
3263cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
3264           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3265  // The second source operand must be the same register as the destination
3266  // operand.
3267  if (Operands.size() == 6 &&
3268      (((ARMOperand*)Operands[3])->getReg() !=
3269       ((ARMOperand*)Operands[5])->getReg()) &&
3270      (((ARMOperand*)Operands[3])->getReg() !=
3271       ((ARMOperand*)Operands[4])->getReg())) {
3272    Error(Operands[3]->getStartLoc(),
3273          "destination register must match source register");
3274    return false;
3275  }
3276  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3277  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
3278  ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
3279  // If we have a three-operand form, use that, else the second source operand
3280  // is just the destination operand again.
3281  if (Operands.size() == 6)
3282    ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3283  else
3284    Inst.addOperand(Inst.getOperand(0));
3285  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
3286
3287  return true;
3288}
3289
3290/// Parse an ARM memory expression, return false if successful else return true
3291/// or an error.  The first token must be a '[' when called.
3292bool ARMAsmParser::
3293parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3294  SMLoc S, E;
3295  assert(Parser.getTok().is(AsmToken::LBrac) &&
3296         "Token is not a Left Bracket");
3297  S = Parser.getTok().getLoc();
3298  Parser.Lex(); // Eat left bracket token.
3299
3300  const AsmToken &BaseRegTok = Parser.getTok();
3301  int BaseRegNum = tryParseRegister();
3302  if (BaseRegNum == -1)
3303    return Error(BaseRegTok.getLoc(), "register expected");
3304
3305  // The next token must either be a comma or a closing bracket.
3306  const AsmToken &Tok = Parser.getTok();
3307  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
3308    return Error(Tok.getLoc(), "malformed memory operand");
3309
3310  if (Tok.is(AsmToken::RBrac)) {
3311    E = Tok.getLoc();
3312    Parser.Lex(); // Eat right bracket token.
3313
3314    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
3315                                             0, 0, false, S, E));
3316
3317    // If there's a pre-indexing writeback marker, '!', just add it as a token
3318    // operand. It's rather odd, but syntactically valid.
3319    if (Parser.getTok().is(AsmToken::Exclaim)) {
3320      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3321      Parser.Lex(); // Eat the '!'.
3322    }
3323
3324    return false;
3325  }
3326
3327  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
3328  Parser.Lex(); // Eat the comma.
3329
3330  // If we have a ':', it's an alignment specifier.
3331  if (Parser.getTok().is(AsmToken::Colon)) {
3332    Parser.Lex(); // Eat the ':'.
3333    E = Parser.getTok().getLoc();
3334
3335    const MCExpr *Expr;
3336    if (getParser().ParseExpression(Expr))
3337     return true;
3338
3339    // The expression has to be a constant. Memory references with relocations
3340    // don't come through here, as they use the <label> forms of the relevant
3341    // instructions.
3342    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3343    if (!CE)
3344      return Error (E, "constant expression expected");
3345
3346    unsigned Align = 0;
3347    switch (CE->getValue()) {
3348    default:
3349      return Error(E, "alignment specifier must be 64, 128, or 256 bits");
3350    case 64:  Align = 8; break;
3351    case 128: Align = 16; break;
3352    case 256: Align = 32; break;
3353    }
3354
3355    // Now we should have the closing ']'
3356    E = Parser.getTok().getLoc();
3357    if (Parser.getTok().isNot(AsmToken::RBrac))
3358      return Error(E, "']' expected");
3359    Parser.Lex(); // Eat right bracket token.
3360
3361    // Don't worry about range checking the value here. That's handled by
3362    // the is*() predicates.
3363    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
3364                                             ARM_AM::no_shift, 0, Align,
3365                                             false, S, E));
3366
3367    // If there's a pre-indexing writeback marker, '!', just add it as a token
3368    // operand.
3369    if (Parser.getTok().is(AsmToken::Exclaim)) {
3370      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3371      Parser.Lex(); // Eat the '!'.
3372    }
3373
3374    return false;
3375  }
3376
3377  // If we have a '#', it's an immediate offset, else assume it's a register
3378  // offset.
3379  if (Parser.getTok().is(AsmToken::Hash)) {
3380    Parser.Lex(); // Eat the '#'.
3381    E = Parser.getTok().getLoc();
3382
3383    bool isNegative = getParser().getTok().is(AsmToken::Minus);
3384    const MCExpr *Offset;
3385    if (getParser().ParseExpression(Offset))
3386     return true;
3387
3388    // The expression has to be a constant. Memory references with relocations
3389    // don't come through here, as they use the <label> forms of the relevant
3390    // instructions.
3391    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3392    if (!CE)
3393      return Error (E, "constant expression expected");
3394
3395    // If the constant was #-0, represent it as INT32_MIN.
3396    int32_t Val = CE->getValue();
3397    if (isNegative && Val == 0)
3398      CE = MCConstantExpr::Create(INT32_MIN, getContext());
3399
3400    // Now we should have the closing ']'
3401    E = Parser.getTok().getLoc();
3402    if (Parser.getTok().isNot(AsmToken::RBrac))
3403      return Error(E, "']' expected");
3404    Parser.Lex(); // Eat right bracket token.
3405
3406    // Don't worry about range checking the value here. That's handled by
3407    // the is*() predicates.
3408    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
3409                                             ARM_AM::no_shift, 0, 0,
3410                                             false, S, E));
3411
3412    // If there's a pre-indexing writeback marker, '!', just add it as a token
3413    // operand.
3414    if (Parser.getTok().is(AsmToken::Exclaim)) {
3415      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3416      Parser.Lex(); // Eat the '!'.
3417    }
3418
3419    return false;
3420  }
3421
3422  // The register offset is optionally preceded by a '+' or '-'
3423  bool isNegative = false;
3424  if (Parser.getTok().is(AsmToken::Minus)) {
3425    isNegative = true;
3426    Parser.Lex(); // Eat the '-'.
3427  } else if (Parser.getTok().is(AsmToken::Plus)) {
3428    // Nothing to do.
3429    Parser.Lex(); // Eat the '+'.
3430  }
3431
3432  E = Parser.getTok().getLoc();
3433  int OffsetRegNum = tryParseRegister();
3434  if (OffsetRegNum == -1)
3435    return Error(E, "register expected");
3436
3437  // If there's a shift operator, handle it.
3438  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
3439  unsigned ShiftImm = 0;
3440  if (Parser.getTok().is(AsmToken::Comma)) {
3441    Parser.Lex(); // Eat the ','.
3442    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
3443      return true;
3444  }
3445
3446  // Now we should have the closing ']'
3447  E = Parser.getTok().getLoc();
3448  if (Parser.getTok().isNot(AsmToken::RBrac))
3449    return Error(E, "']' expected");
3450  Parser.Lex(); // Eat right bracket token.
3451
3452  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
3453                                           ShiftType, ShiftImm, 0, isNegative,
3454                                           S, E));
3455
3456  // If there's a pre-indexing writeback marker, '!', just add it as a token
3457  // operand.
3458  if (Parser.getTok().is(AsmToken::Exclaim)) {
3459    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3460    Parser.Lex(); // Eat the '!'.
3461  }
3462
3463  return false;
3464}
3465
3466/// parseMemRegOffsetShift - one of these two:
3467///   ( lsl | lsr | asr | ror ) , # shift_amount
3468///   rrx
3469/// return true if it parses a shift otherwise it returns false.
3470bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
3471                                          unsigned &Amount) {
3472  SMLoc Loc = Parser.getTok().getLoc();
3473  const AsmToken &Tok = Parser.getTok();
3474  if (Tok.isNot(AsmToken::Identifier))
3475    return true;
3476  StringRef ShiftName = Tok.getString();
3477  if (ShiftName == "lsl" || ShiftName == "LSL")
3478    St = ARM_AM::lsl;
3479  else if (ShiftName == "lsr" || ShiftName == "LSR")
3480    St = ARM_AM::lsr;
3481  else if (ShiftName == "asr" || ShiftName == "ASR")
3482    St = ARM_AM::asr;
3483  else if (ShiftName == "ror" || ShiftName == "ROR")
3484    St = ARM_AM::ror;
3485  else if (ShiftName == "rrx" || ShiftName == "RRX")
3486    St = ARM_AM::rrx;
3487  else
3488    return Error(Loc, "illegal shift operator");
3489  Parser.Lex(); // Eat shift type token.
3490
3491  // rrx stands alone.
3492  Amount = 0;
3493  if (St != ARM_AM::rrx) {
3494    Loc = Parser.getTok().getLoc();
3495    // A '#' and a shift amount.
3496    const AsmToken &HashTok = Parser.getTok();
3497    if (HashTok.isNot(AsmToken::Hash))
3498      return Error(HashTok.getLoc(), "'#' expected");
3499    Parser.Lex(); // Eat hash token.
3500
3501    const MCExpr *Expr;
3502    if (getParser().ParseExpression(Expr))
3503      return true;
3504    // Range check the immediate.
3505    // lsl, ror: 0 <= imm <= 31
3506    // lsr, asr: 0 <= imm <= 32
3507    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3508    if (!CE)
3509      return Error(Loc, "shift amount must be an immediate");
3510    int64_t Imm = CE->getValue();
3511    if (Imm < 0 ||
3512        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
3513        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
3514      return Error(Loc, "immediate shift value out of range");
3515    Amount = Imm;
3516  }
3517
3518  return false;
3519}
3520
3521/// parseFPImm - A floating point immediate expression operand.
3522ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3523parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3524  SMLoc S = Parser.getTok().getLoc();
3525
3526  if (Parser.getTok().isNot(AsmToken::Hash))
3527    return MatchOperand_NoMatch;
3528
3529  // Disambiguate the VMOV forms that can accept an FP immediate.
3530  // vmov.f32 <sreg>, #imm
3531  // vmov.f64 <dreg>, #imm
3532  // vmov.f32 <dreg>, #imm  @ vector f32x2
3533  // vmov.f32 <qreg>, #imm  @ vector f32x4
3534  //
3535  // There are also the NEON VMOV instructions which expect an
3536  // integer constant. Make sure we don't try to parse an FPImm
3537  // for these:
3538  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
3539  ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
3540  if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
3541                           TyOp->getToken() != ".f64"))
3542    return MatchOperand_NoMatch;
3543
3544  Parser.Lex(); // Eat the '#'.
3545
3546  // Handle negation, as that still comes through as a separate token.
3547  bool isNegative = false;
3548  if (Parser.getTok().is(AsmToken::Minus)) {
3549    isNegative = true;
3550    Parser.Lex();
3551  }
3552  const AsmToken &Tok = Parser.getTok();
3553  if (Tok.is(AsmToken::Real)) {
3554    APFloat RealVal(APFloat::IEEEdouble, Tok.getString());
3555    uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
3556    // If we had a '-' in front, toggle the sign bit.
3557    IntVal ^= (uint64_t)isNegative << 63;
3558    int Val = ARM_AM::getFP64Imm(APInt(64, IntVal));
3559    Parser.Lex(); // Eat the token.
3560    if (Val == -1) {
3561      TokError("floating point value out of range");
3562      return MatchOperand_ParseFail;
3563    }
3564    Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
3565    return MatchOperand_Success;
3566  }
3567  if (Tok.is(AsmToken::Integer)) {
3568    int64_t Val = Tok.getIntVal();
3569    Parser.Lex(); // Eat the token.
3570    if (Val > 255 || Val < 0) {
3571      TokError("encoded floating point value out of range");
3572      return MatchOperand_ParseFail;
3573    }
3574    Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
3575    return MatchOperand_Success;
3576  }
3577
3578  TokError("invalid floating point immediate");
3579  return MatchOperand_ParseFail;
3580}
3581/// Parse a arm instruction operand.  For now this parses the operand regardless
3582/// of the mnemonic.
3583bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3584                                StringRef Mnemonic) {
3585  SMLoc S, E;
3586
3587  // Check if the current operand has a custom associated parser, if so, try to
3588  // custom parse the operand, or fallback to the general approach.
3589  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
3590  if (ResTy == MatchOperand_Success)
3591    return false;
3592  // If there wasn't a custom match, try the generic matcher below. Otherwise,
3593  // there was a match, but an error occurred, in which case, just return that
3594  // the operand parsing failed.
3595  if (ResTy == MatchOperand_ParseFail)
3596    return true;
3597
3598  switch (getLexer().getKind()) {
3599  default:
3600    Error(Parser.getTok().getLoc(), "unexpected token in operand");
3601    return true;
3602  case AsmToken::Identifier: {
3603    // If this is VMRS, check for the apsr_nzcv operand.
3604    if (!tryParseRegisterWithWriteBack(Operands))
3605      return false;
3606    int Res = tryParseShiftRegister(Operands);
3607    if (Res == 0) // success
3608      return false;
3609    else if (Res == -1) // irrecoverable error
3610      return true;
3611    if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") {
3612      S = Parser.getTok().getLoc();
3613      Parser.Lex();
3614      Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S));
3615      return false;
3616    }
3617
3618    // Fall though for the Identifier case that is not a register or a
3619    // special name.
3620  }
3621  case AsmToken::Integer: // things like 1f and 2b as a branch targets
3622  case AsmToken::Dot: {   // . as a branch target
3623    // This was not a register so parse other operands that start with an
3624    // identifier (like labels) as expressions and create them as immediates.
3625    const MCExpr *IdVal;
3626    S = Parser.getTok().getLoc();
3627    if (getParser().ParseExpression(IdVal))
3628      return true;
3629    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3630    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
3631    return false;
3632  }
3633  case AsmToken::LBrac:
3634    return parseMemory(Operands);
3635  case AsmToken::LCurly:
3636    return parseRegisterList(Operands);
3637  case AsmToken::Hash: {
3638    // #42 -> immediate.
3639    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
3640    S = Parser.getTok().getLoc();
3641    Parser.Lex();
3642    bool isNegative = Parser.getTok().is(AsmToken::Minus);
3643    const MCExpr *ImmVal;
3644    if (getParser().ParseExpression(ImmVal))
3645      return true;
3646    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
3647    if (!CE) {
3648      Error(S, "constant expression expected");
3649      return MatchOperand_ParseFail;
3650    }
3651    int32_t Val = CE->getValue();
3652    if (isNegative && Val == 0)
3653      ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
3654    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3655    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
3656    return false;
3657  }
3658  case AsmToken::Colon: {
3659    // ":lower16:" and ":upper16:" expression prefixes
3660    // FIXME: Check it's an expression prefix,
3661    // e.g. (FOO - :lower16:BAR) isn't legal.
3662    ARMMCExpr::VariantKind RefKind;
3663    if (parsePrefix(RefKind))
3664      return true;
3665
3666    const MCExpr *SubExprVal;
3667    if (getParser().ParseExpression(SubExprVal))
3668      return true;
3669
3670    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
3671                                                   getContext());
3672    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3673    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
3674    return false;
3675  }
3676  }
3677}
3678
3679// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
3680//  :lower16: and :upper16:.
3681bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
3682  RefKind = ARMMCExpr::VK_ARM_None;
3683
3684  // :lower16: and :upper16: modifiers
3685  assert(getLexer().is(AsmToken::Colon) && "expected a :");
3686  Parser.Lex(); // Eat ':'
3687
3688  if (getLexer().isNot(AsmToken::Identifier)) {
3689    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
3690    return true;
3691  }
3692
3693  StringRef IDVal = Parser.getTok().getIdentifier();
3694  if (IDVal == "lower16") {
3695    RefKind = ARMMCExpr::VK_ARM_LO16;
3696  } else if (IDVal == "upper16") {
3697    RefKind = ARMMCExpr::VK_ARM_HI16;
3698  } else {
3699    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
3700    return true;
3701  }
3702  Parser.Lex();
3703
3704  if (getLexer().isNot(AsmToken::Colon)) {
3705    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
3706    return true;
3707  }
3708  Parser.Lex(); // Eat the last ':'
3709  return false;
3710}
3711
3712/// \brief Given a mnemonic, split out possible predication code and carry
3713/// setting letters to form a canonical mnemonic and flags.
3714//
3715// FIXME: Would be nice to autogen this.
3716// FIXME: This is a bit of a maze of special cases.
3717StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
3718                                      unsigned &PredicationCode,
3719                                      bool &CarrySetting,
3720                                      unsigned &ProcessorIMod,
3721                                      StringRef &ITMask) {
3722  PredicationCode = ARMCC::AL;
3723  CarrySetting = false;
3724  ProcessorIMod = 0;
3725
3726  // Ignore some mnemonics we know aren't predicated forms.
3727  //
3728  // FIXME: Would be nice to autogen this.
3729  if ((Mnemonic == "movs" && isThumb()) ||
3730      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
3731      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
3732      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
3733      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
3734      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
3735      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
3736      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
3737    return Mnemonic;
3738
3739  // First, split out any predication code. Ignore mnemonics we know aren't
3740  // predicated but do have a carry-set and so weren't caught above.
3741  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
3742      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
3743      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
3744      Mnemonic != "sbcs" && Mnemonic != "rscs") {
3745    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
3746      .Case("eq", ARMCC::EQ)
3747      .Case("ne", ARMCC::NE)
3748      .Case("hs", ARMCC::HS)
3749      .Case("cs", ARMCC::HS)
3750      .Case("lo", ARMCC::LO)
3751      .Case("cc", ARMCC::LO)
3752      .Case("mi", ARMCC::MI)
3753      .Case("pl", ARMCC::PL)
3754      .Case("vs", ARMCC::VS)
3755      .Case("vc", ARMCC::VC)
3756      .Case("hi", ARMCC::HI)
3757      .Case("ls", ARMCC::LS)
3758      .Case("ge", ARMCC::GE)
3759      .Case("lt", ARMCC::LT)
3760      .Case("gt", ARMCC::GT)
3761      .Case("le", ARMCC::LE)
3762      .Case("al", ARMCC::AL)
3763      .Default(~0U);
3764    if (CC != ~0U) {
3765      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
3766      PredicationCode = CC;
3767    }
3768  }
3769
3770  // Next, determine if we have a carry setting bit. We explicitly ignore all
3771  // the instructions we know end in 's'.
3772  if (Mnemonic.endswith("s") &&
3773      !(Mnemonic == "cps" || Mnemonic == "mls" ||
3774        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
3775        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
3776        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
3777        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
3778        (Mnemonic == "movs" && isThumb()))) {
3779    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
3780    CarrySetting = true;
3781  }
3782
3783  // The "cps" instruction can have a interrupt mode operand which is glued into
3784  // the mnemonic. Check if this is the case, split it and parse the imod op
3785  if (Mnemonic.startswith("cps")) {
3786    // Split out any imod code.
3787    unsigned IMod =
3788      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
3789      .Case("ie", ARM_PROC::IE)
3790      .Case("id", ARM_PROC::ID)
3791      .Default(~0U);
3792    if (IMod != ~0U) {
3793      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
3794      ProcessorIMod = IMod;
3795    }
3796  }
3797
3798  // The "it" instruction has the condition mask on the end of the mnemonic.
3799  if (Mnemonic.startswith("it")) {
3800    ITMask = Mnemonic.slice(2, Mnemonic.size());
3801    Mnemonic = Mnemonic.slice(0, 2);
3802  }
3803
3804  return Mnemonic;
3805}
3806
3807/// \brief Given a canonical mnemonic, determine if the instruction ever allows
3808/// inclusion of carry set or predication code operands.
3809//
3810// FIXME: It would be nice to autogen this.
3811void ARMAsmParser::
3812getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
3813                      bool &CanAcceptPredicationCode) {
3814  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
3815      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
3816      Mnemonic == "add" || Mnemonic == "adc" ||
3817      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
3818      Mnemonic == "orr" || Mnemonic == "mvn" ||
3819      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
3820      Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
3821      (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
3822                      Mnemonic == "mla" || Mnemonic == "smlal" ||
3823                      Mnemonic == "umlal" || Mnemonic == "umull"))) {
3824    CanAcceptCarrySet = true;
3825  } else
3826    CanAcceptCarrySet = false;
3827
3828  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
3829      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
3830      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
3831      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
3832      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
3833      (Mnemonic == "clrex" && !isThumb()) ||
3834      (Mnemonic == "nop" && isThumbOne()) ||
3835      ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
3836        Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
3837        Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
3838      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
3839       !isThumb()) ||
3840      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
3841    CanAcceptPredicationCode = false;
3842  } else
3843    CanAcceptPredicationCode = true;
3844
3845  if (isThumb()) {
3846    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
3847        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
3848      CanAcceptPredicationCode = false;
3849  }
3850}
3851
3852bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
3853                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3854  // FIXME: This is all horribly hacky. We really need a better way to deal
3855  // with optional operands like this in the matcher table.
3856
3857  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
3858  // another does not. Specifically, the MOVW instruction does not. So we
3859  // special case it here and remove the defaulted (non-setting) cc_out
3860  // operand if that's the instruction we're trying to match.
3861  //
3862  // We do this as post-processing of the explicit operands rather than just
3863  // conditionally adding the cc_out in the first place because we need
3864  // to check the type of the parsed immediate operand.
3865  if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
3866      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
3867      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
3868      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3869    return true;
3870
3871  // Register-register 'add' for thumb does not have a cc_out operand
3872  // when there are only two register operands.
3873  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
3874      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3875      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3876      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3877    return true;
3878  // Register-register 'add' for thumb does not have a cc_out operand
3879  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
3880  // have to check the immediate range here since Thumb2 has a variant
3881  // that can handle a different range and has a cc_out operand.
3882  if (((isThumb() && Mnemonic == "add") ||
3883       (isThumbTwo() && Mnemonic == "sub")) &&
3884      Operands.size() == 6 &&
3885      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3886      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3887      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
3888      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
3889      (static_cast<ARMOperand*>(Operands[5])->isReg() ||
3890       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
3891    return true;
3892  // For Thumb2, add/sub immediate does not have a cc_out operand for the
3893  // imm0_4095 variant. That's the least-preferred variant when
3894  // selecting via the generic "add" mnemonic, so to know that we
3895  // should remove the cc_out operand, we have to explicitly check that
3896  // it's not one of the other variants. Ugh.
3897  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
3898      Operands.size() == 6 &&
3899      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3900      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3901      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3902    // Nest conditions rather than one big 'if' statement for readability.
3903    //
3904    // If either register is a high reg, it's either one of the SP
3905    // variants (handled above) or a 32-bit encoding, so we just
3906    // check against T3.
3907    if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
3908         !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
3909        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
3910      return false;
3911    // If both registers are low, we're in an IT block, and the immediate is
3912    // in range, we should use encoding T1 instead, which has a cc_out.
3913    if (inITBlock() &&
3914        isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
3915        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
3916        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
3917      return false;
3918
3919    // Otherwise, we use encoding T4, which does not have a cc_out
3920    // operand.
3921    return true;
3922  }
3923
3924  // The thumb2 multiply instruction doesn't have a CCOut register, so
3925  // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
3926  // use the 16-bit encoding or not.
3927  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
3928      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
3929      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3930      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3931      static_cast<ARMOperand*>(Operands[5])->isReg() &&
3932      // If the registers aren't low regs, the destination reg isn't the
3933      // same as one of the source regs, or the cc_out operand is zero
3934      // outside of an IT block, we have to use the 32-bit encoding, so
3935      // remove the cc_out operand.
3936      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
3937       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
3938       !inITBlock() ||
3939       (static_cast<ARMOperand*>(Operands[3])->getReg() !=
3940        static_cast<ARMOperand*>(Operands[5])->getReg() &&
3941        static_cast<ARMOperand*>(Operands[3])->getReg() !=
3942        static_cast<ARMOperand*>(Operands[4])->getReg())))
3943    return true;
3944
3945
3946
3947  // Register-register 'add/sub' for thumb does not have a cc_out operand
3948  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
3949  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
3950  // right, this will result in better diagnostics (which operand is off)
3951  // anyway.
3952  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
3953      (Operands.size() == 5 || Operands.size() == 6) &&
3954      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3955      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
3956      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3957    return true;
3958
3959  return false;
3960}
3961
3962/// Parse an arm instruction mnemonic followed by its operands.
3963bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
3964                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3965  // Create the leading tokens for the mnemonic, split by '.' characters.
3966  size_t Start = 0, Next = Name.find('.');
3967  StringRef Mnemonic = Name.slice(Start, Next);
3968
3969  // Split out the predication code and carry setting flag from the mnemonic.
3970  unsigned PredicationCode;
3971  unsigned ProcessorIMod;
3972  bool CarrySetting;
3973  StringRef ITMask;
3974  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
3975                           ProcessorIMod, ITMask);
3976
3977  // In Thumb1, only the branch (B) instruction can be predicated.
3978  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
3979    Parser.EatToEndOfStatement();
3980    return Error(NameLoc, "conditional execution not supported in Thumb1");
3981  }
3982
3983  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
3984
3985  // Handle the IT instruction ITMask. Convert it to a bitmask. This
3986  // is the mask as it will be for the IT encoding if the conditional
3987  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
3988  // where the conditional bit0 is zero, the instruction post-processing
3989  // will adjust the mask accordingly.
3990  if (Mnemonic == "it") {
3991    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
3992    if (ITMask.size() > 3) {
3993      Parser.EatToEndOfStatement();
3994      return Error(Loc, "too many conditions on IT instruction");
3995    }
3996    unsigned Mask = 8;
3997    for (unsigned i = ITMask.size(); i != 0; --i) {
3998      char pos = ITMask[i - 1];
3999      if (pos != 't' && pos != 'e') {
4000        Parser.EatToEndOfStatement();
4001        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
4002      }
4003      Mask >>= 1;
4004      if (ITMask[i - 1] == 't')
4005        Mask |= 8;
4006    }
4007    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
4008  }
4009
4010  // FIXME: This is all a pretty gross hack. We should automatically handle
4011  // optional operands like this via tblgen.
4012
4013  // Next, add the CCOut and ConditionCode operands, if needed.
4014  //
4015  // For mnemonics which can ever incorporate a carry setting bit or predication
4016  // code, our matching model involves us always generating CCOut and
4017  // ConditionCode operands to match the mnemonic "as written" and then we let
4018  // the matcher deal with finding the right instruction or generating an
4019  // appropriate error.
4020  bool CanAcceptCarrySet, CanAcceptPredicationCode;
4021  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
4022
4023  // If we had a carry-set on an instruction that can't do that, issue an
4024  // error.
4025  if (!CanAcceptCarrySet && CarrySetting) {
4026    Parser.EatToEndOfStatement();
4027    return Error(NameLoc, "instruction '" + Mnemonic +
4028                 "' can not set flags, but 's' suffix specified");
4029  }
4030  // If we had a predication code on an instruction that can't do that, issue an
4031  // error.
4032  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
4033    Parser.EatToEndOfStatement();
4034    return Error(NameLoc, "instruction '" + Mnemonic +
4035                 "' is not predicable, but condition code specified");
4036  }
4037
4038  // Add the carry setting operand, if necessary.
4039  if (CanAcceptCarrySet) {
4040    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
4041    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
4042                                               Loc));
4043  }
4044
4045  // Add the predication code operand, if necessary.
4046  if (CanAcceptPredicationCode) {
4047    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
4048                                      CarrySetting);
4049    Operands.push_back(ARMOperand::CreateCondCode(
4050                         ARMCC::CondCodes(PredicationCode), Loc));
4051  }
4052
4053  // Add the processor imod operand, if necessary.
4054  if (ProcessorIMod) {
4055    Operands.push_back(ARMOperand::CreateImm(
4056          MCConstantExpr::Create(ProcessorIMod, getContext()),
4057                                 NameLoc, NameLoc));
4058  }
4059
4060  // Add the remaining tokens in the mnemonic.
4061  while (Next != StringRef::npos) {
4062    Start = Next;
4063    Next = Name.find('.', Start + 1);
4064    StringRef ExtraToken = Name.slice(Start, Next);
4065
4066    // For now, we're only parsing Thumb1 (for the most part), so
4067    // just ignore ".n" qualifiers. We'll use them to restrict
4068    // matching when we do Thumb2.
4069    if (ExtraToken != ".n") {
4070      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
4071      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
4072    }
4073  }
4074
4075  // Read the remaining operands.
4076  if (getLexer().isNot(AsmToken::EndOfStatement)) {
4077    // Read the first operand.
4078    if (parseOperand(Operands, Mnemonic)) {
4079      Parser.EatToEndOfStatement();
4080      return true;
4081    }
4082
4083    while (getLexer().is(AsmToken::Comma)) {
4084      Parser.Lex();  // Eat the comma.
4085
4086      // Parse and remember the operand.
4087      if (parseOperand(Operands, Mnemonic)) {
4088        Parser.EatToEndOfStatement();
4089        return true;
4090      }
4091    }
4092  }
4093
4094  if (getLexer().isNot(AsmToken::EndOfStatement)) {
4095    SMLoc Loc = getLexer().getLoc();
4096    Parser.EatToEndOfStatement();
4097    return Error(Loc, "unexpected token in argument list");
4098  }
4099
4100  Parser.Lex(); // Consume the EndOfStatement
4101
4102  // Some instructions, mostly Thumb, have forms for the same mnemonic that
4103  // do and don't have a cc_out optional-def operand. With some spot-checks
4104  // of the operand list, we can figure out which variant we're trying to
4105  // parse and adjust accordingly before actually matching. We shouldn't ever
4106  // try to remove a cc_out operand that was explicitly set on the the
4107  // mnemonic, of course (CarrySetting == true). Reason number #317 the
4108  // table driven matcher doesn't fit well with the ARM instruction set.
4109  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
4110    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4111    Operands.erase(Operands.begin() + 1);
4112    delete Op;
4113  }
4114
4115  // ARM mode 'blx' need special handling, as the register operand version
4116  // is predicable, but the label operand version is not. So, we can't rely
4117  // on the Mnemonic based checking to correctly figure out when to put
4118  // a k_CondCode operand in the list. If we're trying to match the label
4119  // version, remove the k_CondCode operand here.
4120  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
4121      static_cast<ARMOperand*>(Operands[2])->isImm()) {
4122    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4123    Operands.erase(Operands.begin() + 1);
4124    delete Op;
4125  }
4126
4127  // The vector-compare-to-zero instructions have a literal token "#0" at
4128  // the end that comes to here as an immediate operand. Convert it to a
4129  // token to play nicely with the matcher.
4130  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
4131      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
4132      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4133    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4134    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4135    if (CE && CE->getValue() == 0) {
4136      Operands.erase(Operands.begin() + 5);
4137      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4138      delete Op;
4139    }
4140  }
4141  // VCMP{E} does the same thing, but with a different operand count.
4142  if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
4143      static_cast<ARMOperand*>(Operands[4])->isImm()) {
4144    ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
4145    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4146    if (CE && CE->getValue() == 0) {
4147      Operands.erase(Operands.begin() + 4);
4148      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4149      delete Op;
4150    }
4151  }
4152  // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
4153  // end. Convert it to a token here.
4154  if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
4155      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4156    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4157    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4158    if (CE && CE->getValue() == 0) {
4159      Operands.erase(Operands.begin() + 5);
4160      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4161      delete Op;
4162    }
4163  }
4164
4165  return false;
4166}
4167
4168// Validate context-sensitive operand constraints.
4169
4170// return 'true' if register list contains non-low GPR registers,
4171// 'false' otherwise. If Reg is in the register list or is HiReg, set
4172// 'containsReg' to true.
4173static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
4174                                 unsigned HiReg, bool &containsReg) {
4175  containsReg = false;
4176  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4177    unsigned OpReg = Inst.getOperand(i).getReg();
4178    if (OpReg == Reg)
4179      containsReg = true;
4180    // Anything other than a low register isn't legal here.
4181    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
4182      return true;
4183  }
4184  return false;
4185}
4186
4187// Check if the specified regisgter is in the register list of the inst,
4188// starting at the indicated operand number.
4189static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
4190  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4191    unsigned OpReg = Inst.getOperand(i).getReg();
4192    if (OpReg == Reg)
4193      return true;
4194  }
4195  return false;
4196}
4197
4198// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
4199// the ARMInsts array) instead. Getting that here requires awkward
4200// API changes, though. Better way?
4201namespace llvm {
4202extern MCInstrDesc ARMInsts[];
4203}
4204static MCInstrDesc &getInstDesc(unsigned Opcode) {
4205  return ARMInsts[Opcode];
4206}
4207
4208// FIXME: We would really like to be able to tablegen'erate this.
4209bool ARMAsmParser::
4210validateInstruction(MCInst &Inst,
4211                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4212  MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
4213  SMLoc Loc = Operands[0]->getStartLoc();
4214  // Check the IT block state first.
4215  // NOTE: In Thumb mode, the BKPT instruction has the interesting property of
4216  // being allowed in IT blocks, but not being predicable.  It just always
4217  // executes.
4218  if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
4219    unsigned bit = 1;
4220    if (ITState.FirstCond)
4221      ITState.FirstCond = false;
4222    else
4223      bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
4224    // The instruction must be predicable.
4225    if (!MCID.isPredicable())
4226      return Error(Loc, "instructions in IT block must be predicable");
4227    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
4228    unsigned ITCond = bit ? ITState.Cond :
4229      ARMCC::getOppositeCondition(ITState.Cond);
4230    if (Cond != ITCond) {
4231      // Find the condition code Operand to get its SMLoc information.
4232      SMLoc CondLoc;
4233      for (unsigned i = 1; i < Operands.size(); ++i)
4234        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
4235          CondLoc = Operands[i]->getStartLoc();
4236      return Error(CondLoc, "incorrect condition in IT block; got '" +
4237                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
4238                   "', but expected '" +
4239                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
4240    }
4241  // Check for non-'al' condition codes outside of the IT block.
4242  } else if (isThumbTwo() && MCID.isPredicable() &&
4243             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
4244             ARMCC::AL && Inst.getOpcode() != ARM::tB &&
4245             Inst.getOpcode() != ARM::t2B)
4246    return Error(Loc, "predicated instructions must be in IT block");
4247
4248  switch (Inst.getOpcode()) {
4249  case ARM::LDRD:
4250  case ARM::LDRD_PRE:
4251  case ARM::LDRD_POST:
4252  case ARM::LDREXD: {
4253    // Rt2 must be Rt + 1.
4254    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4255    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4256    if (Rt2 != Rt + 1)
4257      return Error(Operands[3]->getStartLoc(),
4258                   "destination operands must be sequential");
4259    return false;
4260  }
4261  case ARM::STRD: {
4262    // Rt2 must be Rt + 1.
4263    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4264    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4265    if (Rt2 != Rt + 1)
4266      return Error(Operands[3]->getStartLoc(),
4267                   "source operands must be sequential");
4268    return false;
4269  }
4270  case ARM::STRD_PRE:
4271  case ARM::STRD_POST:
4272  case ARM::STREXD: {
4273    // Rt2 must be Rt + 1.
4274    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4275    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
4276    if (Rt2 != Rt + 1)
4277      return Error(Operands[3]->getStartLoc(),
4278                   "source operands must be sequential");
4279    return false;
4280  }
4281  case ARM::SBFX:
4282  case ARM::UBFX: {
4283    // width must be in range [1, 32-lsb]
4284    unsigned lsb = Inst.getOperand(2).getImm();
4285    unsigned widthm1 = Inst.getOperand(3).getImm();
4286    if (widthm1 >= 32 - lsb)
4287      return Error(Operands[5]->getStartLoc(),
4288                   "bitfield width must be in range [1,32-lsb]");
4289    return false;
4290  }
4291  case ARM::tLDMIA: {
4292    // If we're parsing Thumb2, the .w variant is available and handles
4293    // most cases that are normally illegal for a Thumb1 LDM
4294    // instruction. We'll make the transformation in processInstruction()
4295    // if necessary.
4296    //
4297    // Thumb LDM instructions are writeback iff the base register is not
4298    // in the register list.
4299    unsigned Rn = Inst.getOperand(0).getReg();
4300    bool hasWritebackToken =
4301      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
4302       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
4303    bool listContainsBase;
4304    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
4305      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
4306                   "registers must be in range r0-r7");
4307    // If we should have writeback, then there should be a '!' token.
4308    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
4309      return Error(Operands[2]->getStartLoc(),
4310                   "writeback operator '!' expected");
4311    // If we should not have writeback, there must not be a '!'. This is
4312    // true even for the 32-bit wide encodings.
4313    if (listContainsBase && hasWritebackToken)
4314      return Error(Operands[3]->getStartLoc(),
4315                   "writeback operator '!' not allowed when base register "
4316                   "in register list");
4317
4318    break;
4319  }
4320  case ARM::t2LDMIA_UPD: {
4321    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
4322      return Error(Operands[4]->getStartLoc(),
4323                   "writeback operator '!' not allowed when base register "
4324                   "in register list");
4325    break;
4326  }
4327  case ARM::tPOP: {
4328    bool listContainsBase;
4329    if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
4330      return Error(Operands[2]->getStartLoc(),
4331                   "registers must be in range r0-r7 or pc");
4332    break;
4333  }
4334  case ARM::tPUSH: {
4335    bool listContainsBase;
4336    if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
4337      return Error(Operands[2]->getStartLoc(),
4338                   "registers must be in range r0-r7 or lr");
4339    break;
4340  }
4341  case ARM::tSTMIA_UPD: {
4342    bool listContainsBase;
4343    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
4344      return Error(Operands[4]->getStartLoc(),
4345                   "registers must be in range r0-r7");
4346    break;
4347  }
4348  }
4349
4350  return false;
4351}
4352
4353void ARMAsmParser::
4354processInstruction(MCInst &Inst,
4355                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4356  switch (Inst.getOpcode()) {
4357  case ARM::LDMIA_UPD:
4358    // If this is a load of a single register via a 'pop', then we should use
4359    // a post-indexed LDR instruction instead, per the ARM ARM.
4360    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
4361        Inst.getNumOperands() == 5) {
4362      MCInst TmpInst;
4363      TmpInst.setOpcode(ARM::LDR_POST_IMM);
4364      TmpInst.addOperand(Inst.getOperand(4)); // Rt
4365      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4366      TmpInst.addOperand(Inst.getOperand(1)); // Rn
4367      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
4368      TmpInst.addOperand(MCOperand::CreateImm(4));
4369      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4370      TmpInst.addOperand(Inst.getOperand(3));
4371      Inst = TmpInst;
4372    }
4373    break;
4374  case ARM::STMDB_UPD:
4375    // If this is a store of a single register via a 'push', then we should use
4376    // a pre-indexed STR instruction instead, per the ARM ARM.
4377    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
4378        Inst.getNumOperands() == 5) {
4379      MCInst TmpInst;
4380      TmpInst.setOpcode(ARM::STR_PRE_IMM);
4381      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4382      TmpInst.addOperand(Inst.getOperand(4)); // Rt
4383      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
4384      TmpInst.addOperand(MCOperand::CreateImm(-4));
4385      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4386      TmpInst.addOperand(Inst.getOperand(3));
4387      Inst = TmpInst;
4388    }
4389    break;
4390  case ARM::tADDi8:
4391    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
4392    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
4393    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
4394    // to encoding T1 if <Rd> is omitted."
4395    if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
4396      Inst.setOpcode(ARM::tADDi3);
4397    break;
4398  case ARM::tSUBi8:
4399    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
4400    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
4401    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
4402    // to encoding T1 if <Rd> is omitted."
4403    if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
4404      Inst.setOpcode(ARM::tSUBi3);
4405    break;
4406  case ARM::tB:
4407    // A Thumb conditional branch outside of an IT block is a tBcc.
4408    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
4409      Inst.setOpcode(ARM::tBcc);
4410    break;
4411  case ARM::t2B:
4412    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
4413    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
4414      Inst.setOpcode(ARM::t2Bcc);
4415    break;
4416  case ARM::t2Bcc:
4417    // If the conditional is AL or we're in an IT block, we really want t2B.
4418    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock())
4419      Inst.setOpcode(ARM::t2B);
4420    break;
4421  case ARM::tBcc:
4422    // If the conditional is AL, we really want tB.
4423    if (Inst.getOperand(1).getImm() == ARMCC::AL)
4424      Inst.setOpcode(ARM::tB);
4425    break;
4426  case ARM::tLDMIA: {
4427    // If the register list contains any high registers, or if the writeback
4428    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
4429    // instead if we're in Thumb2. Otherwise, this should have generated
4430    // an error in validateInstruction().
4431    unsigned Rn = Inst.getOperand(0).getReg();
4432    bool hasWritebackToken =
4433      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
4434       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
4435    bool listContainsBase;
4436    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
4437        (!listContainsBase && !hasWritebackToken) ||
4438        (listContainsBase && hasWritebackToken)) {
4439      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
4440      assert (isThumbTwo());
4441      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
4442      // If we're switching to the updating version, we need to insert
4443      // the writeback tied operand.
4444      if (hasWritebackToken)
4445        Inst.insert(Inst.begin(),
4446                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
4447    }
4448    break;
4449  }
4450  case ARM::tSTMIA_UPD: {
4451    // If the register list contains any high registers, we need to use
4452    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
4453    // should have generated an error in validateInstruction().
4454    unsigned Rn = Inst.getOperand(0).getReg();
4455    bool listContainsBase;
4456    if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
4457      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
4458      assert (isThumbTwo());
4459      Inst.setOpcode(ARM::t2STMIA_UPD);
4460    }
4461    break;
4462  }
4463  case ARM::t2MOVi: {
4464    // If we can use the 16-bit encoding and the user didn't explicitly
4465    // request the 32-bit variant, transform it here.
4466    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4467        Inst.getOperand(1).getImm() <= 255 &&
4468        ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
4469         Inst.getOperand(4).getReg() == ARM::CPSR) ||
4470        (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
4471        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4472         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4473      // The operands aren't in the same order for tMOVi8...
4474      MCInst TmpInst;
4475      TmpInst.setOpcode(ARM::tMOVi8);
4476      TmpInst.addOperand(Inst.getOperand(0));
4477      TmpInst.addOperand(Inst.getOperand(4));
4478      TmpInst.addOperand(Inst.getOperand(1));
4479      TmpInst.addOperand(Inst.getOperand(2));
4480      TmpInst.addOperand(Inst.getOperand(3));
4481      Inst = TmpInst;
4482    }
4483    break;
4484  }
4485  case ARM::t2MOVr: {
4486    // If we can use the 16-bit encoding and the user didn't explicitly
4487    // request the 32-bit variant, transform it here.
4488    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4489        isARMLowRegister(Inst.getOperand(1).getReg()) &&
4490        Inst.getOperand(2).getImm() == ARMCC::AL &&
4491        Inst.getOperand(4).getReg() == ARM::CPSR &&
4492        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4493         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4494      // The operands aren't the same for tMOV[S]r... (no cc_out)
4495      MCInst TmpInst;
4496      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
4497      TmpInst.addOperand(Inst.getOperand(0));
4498      TmpInst.addOperand(Inst.getOperand(1));
4499      TmpInst.addOperand(Inst.getOperand(2));
4500      TmpInst.addOperand(Inst.getOperand(3));
4501      Inst = TmpInst;
4502    }
4503    break;
4504  }
4505  case ARM::t2SXTH:
4506  case ARM::t2SXTB:
4507  case ARM::t2UXTH:
4508  case ARM::t2UXTB: {
4509    // If we can use the 16-bit encoding and the user didn't explicitly
4510    // request the 32-bit variant, transform it here.
4511    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4512        isARMLowRegister(Inst.getOperand(1).getReg()) &&
4513        Inst.getOperand(2).getImm() == 0 &&
4514        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4515         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4516      unsigned NewOpc;
4517      switch (Inst.getOpcode()) {
4518      default: llvm_unreachable("Illegal opcode!");
4519      case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
4520      case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
4521      case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
4522      case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
4523      }
4524      // The operands aren't the same for thumb1 (no rotate operand).
4525      MCInst TmpInst;
4526      TmpInst.setOpcode(NewOpc);
4527      TmpInst.addOperand(Inst.getOperand(0));
4528      TmpInst.addOperand(Inst.getOperand(1));
4529      TmpInst.addOperand(Inst.getOperand(3));
4530      TmpInst.addOperand(Inst.getOperand(4));
4531      Inst = TmpInst;
4532    }
4533    break;
4534  }
4535  case ARM::t2IT: {
4536    // The mask bits for all but the first condition are represented as
4537    // the low bit of the condition code value implies 't'. We currently
4538    // always have 1 implies 't', so XOR toggle the bits if the low bit
4539    // of the condition code is zero. The encoding also expects the low
4540    // bit of the condition to be encoded as bit 4 of the mask operand,
4541    // so mask that in if needed
4542    MCOperand &MO = Inst.getOperand(1);
4543    unsigned Mask = MO.getImm();
4544    unsigned OrigMask = Mask;
4545    unsigned TZ = CountTrailingZeros_32(Mask);
4546    if ((Inst.getOperand(0).getImm() & 1) == 0) {
4547      assert(Mask && TZ <= 3 && "illegal IT mask value!");
4548      for (unsigned i = 3; i != TZ; --i)
4549        Mask ^= 1 << i;
4550    } else
4551      Mask |= 0x10;
4552    MO.setImm(Mask);
4553
4554    // Set up the IT block state according to the IT instruction we just
4555    // matched.
4556    assert(!inITBlock() && "nested IT blocks?!");
4557    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
4558    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
4559    ITState.CurPosition = 0;
4560    ITState.FirstCond = true;
4561    break;
4562  }
4563  }
4564}
4565
4566unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
4567  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
4568  // suffix depending on whether they're in an IT block or not.
4569  unsigned Opc = Inst.getOpcode();
4570  MCInstrDesc &MCID = getInstDesc(Opc);
4571  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
4572    assert(MCID.hasOptionalDef() &&
4573           "optionally flag setting instruction missing optional def operand");
4574    assert(MCID.NumOperands == Inst.getNumOperands() &&
4575           "operand count mismatch!");
4576    // Find the optional-def operand (cc_out).
4577    unsigned OpNo;
4578    for (OpNo = 0;
4579         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
4580         ++OpNo)
4581      ;
4582    // If we're parsing Thumb1, reject it completely.
4583    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
4584      return Match_MnemonicFail;
4585    // If we're parsing Thumb2, which form is legal depends on whether we're
4586    // in an IT block.
4587    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
4588        !inITBlock())
4589      return Match_RequiresITBlock;
4590    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
4591        inITBlock())
4592      return Match_RequiresNotITBlock;
4593  }
4594  // Some high-register supporting Thumb1 encodings only allow both registers
4595  // to be from r0-r7 when in Thumb2.
4596  else if (Opc == ARM::tADDhirr && isThumbOne() &&
4597           isARMLowRegister(Inst.getOperand(1).getReg()) &&
4598           isARMLowRegister(Inst.getOperand(2).getReg()))
4599    return Match_RequiresThumb2;
4600  // Others only require ARMv6 or later.
4601  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
4602           isARMLowRegister(Inst.getOperand(0).getReg()) &&
4603           isARMLowRegister(Inst.getOperand(1).getReg()))
4604    return Match_RequiresV6;
4605  return Match_Success;
4606}
4607
4608bool ARMAsmParser::
4609MatchAndEmitInstruction(SMLoc IDLoc,
4610                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4611                        MCStreamer &Out) {
4612  MCInst Inst;
4613  unsigned ErrorInfo;
4614  unsigned MatchResult;
4615  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
4616  switch (MatchResult) {
4617  default: break;
4618  case Match_Success:
4619    // Context sensitive operand constraints aren't handled by the matcher,
4620    // so check them here.
4621    if (validateInstruction(Inst, Operands)) {
4622      // Still progress the IT block, otherwise one wrong condition causes
4623      // nasty cascading errors.
4624      forwardITPosition();
4625      return true;
4626    }
4627
4628    // Some instructions need post-processing to, for example, tweak which
4629    // encoding is selected.
4630    processInstruction(Inst, Operands);
4631
4632    // Only move forward at the very end so that everything in validate
4633    // and process gets a consistent answer about whether we're in an IT
4634    // block.
4635    forwardITPosition();
4636
4637    Out.EmitInstruction(Inst);
4638    return false;
4639  case Match_MissingFeature:
4640    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
4641    return true;
4642  case Match_InvalidOperand: {
4643    SMLoc ErrorLoc = IDLoc;
4644    if (ErrorInfo != ~0U) {
4645      if (ErrorInfo >= Operands.size())
4646        return Error(IDLoc, "too few operands for instruction");
4647
4648      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
4649      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
4650    }
4651
4652    return Error(ErrorLoc, "invalid operand for instruction");
4653  }
4654  case Match_MnemonicFail:
4655    return Error(IDLoc, "invalid instruction");
4656  case Match_ConversionFail:
4657    // The converter function will have already emited a diagnostic.
4658    return true;
4659  case Match_RequiresNotITBlock:
4660    return Error(IDLoc, "flag setting instruction only valid outside IT block");
4661  case Match_RequiresITBlock:
4662    return Error(IDLoc, "instruction only valid inside IT block");
4663  case Match_RequiresV6:
4664    return Error(IDLoc, "instruction variant requires ARMv6 or later");
4665  case Match_RequiresThumb2:
4666    return Error(IDLoc, "instruction variant requires Thumb2");
4667  }
4668
4669  llvm_unreachable("Implement any new match types added!");
4670  return true;
4671}
4672
4673/// parseDirective parses the arm specific directives
4674bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
4675  StringRef IDVal = DirectiveID.getIdentifier();
4676  if (IDVal == ".word")
4677    return parseDirectiveWord(4, DirectiveID.getLoc());
4678  else if (IDVal == ".thumb")
4679    return parseDirectiveThumb(DirectiveID.getLoc());
4680  else if (IDVal == ".thumb_func")
4681    return parseDirectiveThumbFunc(DirectiveID.getLoc());
4682  else if (IDVal == ".code")
4683    return parseDirectiveCode(DirectiveID.getLoc());
4684  else if (IDVal == ".syntax")
4685    return parseDirectiveSyntax(DirectiveID.getLoc());
4686  return true;
4687}
4688
4689/// parseDirectiveWord
4690///  ::= .word [ expression (, expression)* ]
4691bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
4692  if (getLexer().isNot(AsmToken::EndOfStatement)) {
4693    for (;;) {
4694      const MCExpr *Value;
4695      if (getParser().ParseExpression(Value))
4696        return true;
4697
4698      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
4699
4700      if (getLexer().is(AsmToken::EndOfStatement))
4701        break;
4702
4703      // FIXME: Improve diagnostic.
4704      if (getLexer().isNot(AsmToken::Comma))
4705        return Error(L, "unexpected token in directive");
4706      Parser.Lex();
4707    }
4708  }
4709
4710  Parser.Lex();
4711  return false;
4712}
4713
4714/// parseDirectiveThumb
4715///  ::= .thumb
4716bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
4717  if (getLexer().isNot(AsmToken::EndOfStatement))
4718    return Error(L, "unexpected token in directive");
4719  Parser.Lex();
4720
4721  // TODO: set thumb mode
4722  // TODO: tell the MC streamer the mode
4723  // getParser().getStreamer().Emit???();
4724  return false;
4725}
4726
4727/// parseDirectiveThumbFunc
4728///  ::= .thumbfunc symbol_name
4729bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
4730  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
4731  bool isMachO = MAI.hasSubsectionsViaSymbols();
4732  StringRef Name;
4733
4734  // Darwin asm has function name after .thumb_func direction
4735  // ELF doesn't
4736  if (isMachO) {
4737    const AsmToken &Tok = Parser.getTok();
4738    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
4739      return Error(L, "unexpected token in .thumb_func directive");
4740    Name = Tok.getString();
4741    Parser.Lex(); // Consume the identifier token.
4742  }
4743
4744  if (getLexer().isNot(AsmToken::EndOfStatement))
4745    return Error(L, "unexpected token in directive");
4746  Parser.Lex();
4747
4748  // FIXME: assuming function name will be the line following .thumb_func
4749  if (!isMachO) {
4750    Name = Parser.getTok().getString();
4751  }
4752
4753  // Mark symbol as a thumb symbol.
4754  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
4755  getParser().getStreamer().EmitThumbFunc(Func);
4756  return false;
4757}
4758
4759/// parseDirectiveSyntax
4760///  ::= .syntax unified | divided
4761bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
4762  const AsmToken &Tok = Parser.getTok();
4763  if (Tok.isNot(AsmToken::Identifier))
4764    return Error(L, "unexpected token in .syntax directive");
4765  StringRef Mode = Tok.getString();
4766  if (Mode == "unified" || Mode == "UNIFIED")
4767    Parser.Lex();
4768  else if (Mode == "divided" || Mode == "DIVIDED")
4769    return Error(L, "'.syntax divided' arm asssembly not supported");
4770  else
4771    return Error(L, "unrecognized syntax mode in .syntax directive");
4772
4773  if (getLexer().isNot(AsmToken::EndOfStatement))
4774    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4775  Parser.Lex();
4776
4777  // TODO tell the MC streamer the mode
4778  // getParser().getStreamer().Emit???();
4779  return false;
4780}
4781
4782/// parseDirectiveCode
4783///  ::= .code 16 | 32
4784bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
4785  const AsmToken &Tok = Parser.getTok();
4786  if (Tok.isNot(AsmToken::Integer))
4787    return Error(L, "unexpected token in .code directive");
4788  int64_t Val = Parser.getTok().getIntVal();
4789  if (Val == 16)
4790    Parser.Lex();
4791  else if (Val == 32)
4792    Parser.Lex();
4793  else
4794    return Error(L, "invalid operand to .code directive");
4795
4796  if (getLexer().isNot(AsmToken::EndOfStatement))
4797    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4798  Parser.Lex();
4799
4800  if (Val == 16) {
4801    if (!isThumb())
4802      SwitchMode();
4803    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
4804  } else {
4805    if (isThumb())
4806      SwitchMode();
4807    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
4808  }
4809
4810  return false;
4811}
4812
4813extern "C" void LLVMInitializeARMAsmLexer();
4814
4815/// Force static initialization.
4816extern "C" void LLVMInitializeARMAsmParser() {
4817  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
4818  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
4819  LLVMInitializeARMAsmLexer();
4820}
4821
4822#define GET_REGISTER_MATCHER
4823#define GET_MATCHER_IMPLEMENTATION
4824#include "ARMGenAsmMatcher.inc"
4825