ARMAsmParser.cpp revision 2c3f70e5d4b4f179f21ed1b2ba14674f9d65c9b0 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/MCTargetAsmParser.h"
24#include "llvm/Target/TargetRegistry.h"
25#include "llvm/Support/SourceMgr.h"
26#include "llvm/Support/raw_ostream.h"
27#include "llvm/ADT/OwningPtr.h"
28#include "llvm/ADT/STLExtras.h"
29#include "llvm/ADT/SmallVector.h"
30#include "llvm/ADT/StringExtras.h"
31#include "llvm/ADT/StringSwitch.h"
32#include "llvm/ADT/Twine.h"
33
34using namespace llvm;
35
36namespace {
37
38class ARMOperand;
39
40class ARMAsmParser : public MCTargetAsmParser {
41  MCSubtargetInfo &STI;
42  MCAsmParser &Parser;
43
44  MCAsmParser &getParser() const { return Parser; }
45  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
46
47  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
48  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
49
50  int tryParseRegister();
51  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
52  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
53  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
54  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
55  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
56  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
57  const MCExpr *applyPrefixToExpr(const MCExpr *E,
58                                  MCSymbolRefExpr::VariantKind Variant);
59
60
61  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
62                              unsigned &ShiftAmount);
63  bool parseDirectiveWord(unsigned Size, SMLoc L);
64  bool parseDirectiveThumb(SMLoc L);
65  bool parseDirectiveThumbFunc(SMLoc L);
66  bool parseDirectiveCode(SMLoc L);
67  bool parseDirectiveSyntax(SMLoc L);
68
69  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
70                          bool &CarrySetting, unsigned &ProcessorIMod);
71  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
72                             bool &CanAcceptPredicationCode);
73
74  bool isThumb() const {
75    // FIXME: Can tablegen auto-generate this?
76    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
77  }
78  bool isThumbOne() const {
79    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
80  }
81  bool isThumbTwo() const {
82    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
83  }
84  bool hasV6Ops() const {
85    return STI.getFeatureBits() & ARM::HasV6Ops;
86  }
87  void SwitchMode() {
88    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
89    setAvailableFeatures(FB);
90  }
91
92  /// @name Auto-generated Match Functions
93  /// {
94
95#define GET_ASSEMBLER_HEADER
96#include "ARMGenAsmMatcher.inc"
97
98  /// }
99
100  OperandMatchResultTy parseCoprocNumOperand(
101    SmallVectorImpl<MCParsedAsmOperand*>&);
102  OperandMatchResultTy parseCoprocRegOperand(
103    SmallVectorImpl<MCParsedAsmOperand*>&);
104  OperandMatchResultTy parseMemBarrierOptOperand(
105    SmallVectorImpl<MCParsedAsmOperand*>&);
106  OperandMatchResultTy parseProcIFlagsOperand(
107    SmallVectorImpl<MCParsedAsmOperand*>&);
108  OperandMatchResultTy parseMSRMaskOperand(
109    SmallVectorImpl<MCParsedAsmOperand*>&);
110  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
111                                   StringRef Op, int Low, int High);
112  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
113    return parsePKHImm(O, "lsl", 0, 31);
114  }
115  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
116    return parsePKHImm(O, "asr", 1, 32);
117  }
118  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
119  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
120  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
121  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
122  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
123  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
124
125  // Asm Match Converter Methods
126  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
127                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
128  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
129                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
130  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
131                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
132  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
133                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
134  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
135                             const SmallVectorImpl<MCParsedAsmOperand*> &);
136  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
137                             const SmallVectorImpl<MCParsedAsmOperand*> &);
138  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
139                             const SmallVectorImpl<MCParsedAsmOperand*> &);
140  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
141                             const SmallVectorImpl<MCParsedAsmOperand*> &);
142  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
143                  const SmallVectorImpl<MCParsedAsmOperand*> &);
144  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
145                  const SmallVectorImpl<MCParsedAsmOperand*> &);
146  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
147                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
148  bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
149                        const SmallVectorImpl<MCParsedAsmOperand*> &);
150
151  bool validateInstruction(MCInst &Inst,
152                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
153  void processInstruction(MCInst &Inst,
154                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
155  bool shouldOmitCCOutOperand(StringRef Mnemonic,
156                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
157
158public:
159  enum ARMMatchResultTy {
160    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
161    Match_RequiresV6,
162    Match_RequiresThumb2
163  };
164
165  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
166    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
167    MCAsmParserExtension::Initialize(_Parser);
168
169    // Initialize the set of available features.
170    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
171  }
172
173  // Implementation of the MCTargetAsmParser interface:
174  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
175  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
176                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
177  bool ParseDirective(AsmToken DirectiveID);
178
179  unsigned checkTargetMatchPredicate(MCInst &Inst);
180
181  bool MatchAndEmitInstruction(SMLoc IDLoc,
182                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
183                               MCStreamer &Out);
184};
185} // end anonymous namespace
186
187namespace {
188
189/// ARMOperand - Instances of this class represent a parsed ARM machine
190/// instruction.
191class ARMOperand : public MCParsedAsmOperand {
192  enum KindTy {
193    CondCode,
194    CCOut,
195    CoprocNum,
196    CoprocReg,
197    Immediate,
198    MemBarrierOpt,
199    Memory,
200    PostIndexRegister,
201    MSRMask,
202    ProcIFlags,
203    Register,
204    RegisterList,
205    DPRRegisterList,
206    SPRRegisterList,
207    ShiftedRegister,
208    ShiftedImmediate,
209    ShifterImmediate,
210    RotateImmediate,
211    BitfieldDescriptor,
212    Token
213  } Kind;
214
215  SMLoc StartLoc, EndLoc;
216  SmallVector<unsigned, 8> Registers;
217
218  union {
219    struct {
220      ARMCC::CondCodes Val;
221    } CC;
222
223    struct {
224      ARM_MB::MemBOpt Val;
225    } MBOpt;
226
227    struct {
228      unsigned Val;
229    } Cop;
230
231    struct {
232      ARM_PROC::IFlags Val;
233    } IFlags;
234
235    struct {
236      unsigned Val;
237    } MMask;
238
239    struct {
240      const char *Data;
241      unsigned Length;
242    } Tok;
243
244    struct {
245      unsigned RegNum;
246    } Reg;
247
248    struct {
249      const MCExpr *Val;
250    } Imm;
251
252    /// Combined record for all forms of ARM address expressions.
253    struct {
254      unsigned BaseRegNum;
255      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
256      // was specified.
257      const MCConstantExpr *OffsetImm;  // Offset immediate value
258      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
259      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
260      unsigned ShiftImm;      // shift for OffsetReg.
261      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
262    } Mem;
263
264    struct {
265      unsigned RegNum;
266      bool isAdd;
267      ARM_AM::ShiftOpc ShiftTy;
268      unsigned ShiftImm;
269    } PostIdxReg;
270
271    struct {
272      bool isASR;
273      unsigned Imm;
274    } ShifterImm;
275    struct {
276      ARM_AM::ShiftOpc ShiftTy;
277      unsigned SrcReg;
278      unsigned ShiftReg;
279      unsigned ShiftImm;
280    } RegShiftedReg;
281    struct {
282      ARM_AM::ShiftOpc ShiftTy;
283      unsigned SrcReg;
284      unsigned ShiftImm;
285    } RegShiftedImm;
286    struct {
287      unsigned Imm;
288    } RotImm;
289    struct {
290      unsigned LSB;
291      unsigned Width;
292    } Bitfield;
293  };
294
295  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
296public:
297  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
298    Kind = o.Kind;
299    StartLoc = o.StartLoc;
300    EndLoc = o.EndLoc;
301    switch (Kind) {
302    case CondCode:
303      CC = o.CC;
304      break;
305    case Token:
306      Tok = o.Tok;
307      break;
308    case CCOut:
309    case Register:
310      Reg = o.Reg;
311      break;
312    case RegisterList:
313    case DPRRegisterList:
314    case SPRRegisterList:
315      Registers = o.Registers;
316      break;
317    case CoprocNum:
318    case CoprocReg:
319      Cop = o.Cop;
320      break;
321    case Immediate:
322      Imm = o.Imm;
323      break;
324    case MemBarrierOpt:
325      MBOpt = o.MBOpt;
326      break;
327    case Memory:
328      Mem = o.Mem;
329      break;
330    case PostIndexRegister:
331      PostIdxReg = o.PostIdxReg;
332      break;
333    case MSRMask:
334      MMask = o.MMask;
335      break;
336    case ProcIFlags:
337      IFlags = o.IFlags;
338      break;
339    case ShifterImmediate:
340      ShifterImm = o.ShifterImm;
341      break;
342    case ShiftedRegister:
343      RegShiftedReg = o.RegShiftedReg;
344      break;
345    case ShiftedImmediate:
346      RegShiftedImm = o.RegShiftedImm;
347      break;
348    case RotateImmediate:
349      RotImm = o.RotImm;
350      break;
351    case BitfieldDescriptor:
352      Bitfield = o.Bitfield;
353      break;
354    }
355  }
356
357  /// getStartLoc - Get the location of the first token of this operand.
358  SMLoc getStartLoc() const { return StartLoc; }
359  /// getEndLoc - Get the location of the last token of this operand.
360  SMLoc getEndLoc() const { return EndLoc; }
361
362  ARMCC::CondCodes getCondCode() const {
363    assert(Kind == CondCode && "Invalid access!");
364    return CC.Val;
365  }
366
367  unsigned getCoproc() const {
368    assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
369    return Cop.Val;
370  }
371
372  StringRef getToken() const {
373    assert(Kind == Token && "Invalid access!");
374    return StringRef(Tok.Data, Tok.Length);
375  }
376
377  unsigned getReg() const {
378    assert((Kind == Register || Kind == CCOut) && "Invalid access!");
379    return Reg.RegNum;
380  }
381
382  const SmallVectorImpl<unsigned> &getRegList() const {
383    assert((Kind == RegisterList || Kind == DPRRegisterList ||
384            Kind == SPRRegisterList) && "Invalid access!");
385    return Registers;
386  }
387
388  const MCExpr *getImm() const {
389    assert(Kind == Immediate && "Invalid access!");
390    return Imm.Val;
391  }
392
393  ARM_MB::MemBOpt getMemBarrierOpt() const {
394    assert(Kind == MemBarrierOpt && "Invalid access!");
395    return MBOpt.Val;
396  }
397
398  ARM_PROC::IFlags getProcIFlags() const {
399    assert(Kind == ProcIFlags && "Invalid access!");
400    return IFlags.Val;
401  }
402
403  unsigned getMSRMask() const {
404    assert(Kind == MSRMask && "Invalid access!");
405    return MMask.Val;
406  }
407
408  bool isCoprocNum() const { return Kind == CoprocNum; }
409  bool isCoprocReg() const { return Kind == CoprocReg; }
410  bool isCondCode() const { return Kind == CondCode; }
411  bool isCCOut() const { return Kind == CCOut; }
412  bool isImm() const { return Kind == Immediate; }
413  bool isImm0_255() const {
414    if (Kind != Immediate)
415      return false;
416    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
417    if (!CE) return false;
418    int64_t Value = CE->getValue();
419    return Value >= 0 && Value < 256;
420  }
421  bool isImm0_7() const {
422    if (Kind != Immediate)
423      return false;
424    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
425    if (!CE) return false;
426    int64_t Value = CE->getValue();
427    return Value >= 0 && Value < 8;
428  }
429  bool isImm0_15() const {
430    if (Kind != Immediate)
431      return false;
432    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
433    if (!CE) return false;
434    int64_t Value = CE->getValue();
435    return Value >= 0 && Value < 16;
436  }
437  bool isImm0_31() const {
438    if (Kind != Immediate)
439      return false;
440    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
441    if (!CE) return false;
442    int64_t Value = CE->getValue();
443    return Value >= 0 && Value < 32;
444  }
445  bool isImm1_16() const {
446    if (Kind != Immediate)
447      return false;
448    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
449    if (!CE) return false;
450    int64_t Value = CE->getValue();
451    return Value > 0 && Value < 17;
452  }
453  bool isImm1_32() const {
454    if (Kind != Immediate)
455      return false;
456    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
457    if (!CE) return false;
458    int64_t Value = CE->getValue();
459    return Value > 0 && Value < 33;
460  }
461  bool isImm0_65535() const {
462    if (Kind != Immediate)
463      return false;
464    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
465    if (!CE) return false;
466    int64_t Value = CE->getValue();
467    return Value >= 0 && Value < 65536;
468  }
469  bool isImm0_65535Expr() const {
470    if (Kind != Immediate)
471      return false;
472    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
473    // If it's not a constant expression, it'll generate a fixup and be
474    // handled later.
475    if (!CE) return true;
476    int64_t Value = CE->getValue();
477    return Value >= 0 && Value < 65536;
478  }
479  bool isImm24bit() const {
480    if (Kind != Immediate)
481      return false;
482    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
483    if (!CE) return false;
484    int64_t Value = CE->getValue();
485    return Value >= 0 && Value <= 0xffffff;
486  }
487  bool isImmThumbSR() const {
488    if (Kind != Immediate)
489      return false;
490    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
491    if (!CE) return false;
492    int64_t Value = CE->getValue();
493    return Value > 0 && Value < 33;
494  }
495  bool isPKHLSLImm() const {
496    if (Kind != Immediate)
497      return false;
498    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
499    if (!CE) return false;
500    int64_t Value = CE->getValue();
501    return Value >= 0 && Value < 32;
502  }
503  bool isPKHASRImm() const {
504    if (Kind != Immediate)
505      return false;
506    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
507    if (!CE) return false;
508    int64_t Value = CE->getValue();
509    return Value > 0 && Value <= 32;
510  }
511  bool isARMSOImm() const {
512    if (Kind != Immediate)
513      return false;
514    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
515    if (!CE) return false;
516    int64_t Value = CE->getValue();
517    return ARM_AM::getSOImmVal(Value) != -1;
518  }
519  bool isT2SOImm() const {
520    if (Kind != Immediate)
521      return false;
522    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
523    if (!CE) return false;
524    int64_t Value = CE->getValue();
525    return ARM_AM::getT2SOImmVal(Value) != -1;
526  }
527  bool isSetEndImm() const {
528    if (Kind != Immediate)
529      return false;
530    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
531    if (!CE) return false;
532    int64_t Value = CE->getValue();
533    return Value == 1 || Value == 0;
534  }
535  bool isReg() const { return Kind == Register; }
536  bool isRegList() const { return Kind == RegisterList; }
537  bool isDPRRegList() const { return Kind == DPRRegisterList; }
538  bool isSPRRegList() const { return Kind == SPRRegisterList; }
539  bool isToken() const { return Kind == Token; }
540  bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
541  bool isMemory() const { return Kind == Memory; }
542  bool isShifterImm() const { return Kind == ShifterImmediate; }
543  bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
544  bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
545  bool isRotImm() const { return Kind == RotateImmediate; }
546  bool isBitfield() const { return Kind == BitfieldDescriptor; }
547  bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
548  bool isPostIdxReg() const {
549    return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
550  }
551  bool isMemNoOffset() const {
552    if (Kind != Memory)
553      return false;
554    // No offset of any kind.
555    return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
556  }
557  bool isAddrMode2() const {
558    if (Kind != Memory)
559      return false;
560    // Check for register offset.
561    if (Mem.OffsetRegNum) return true;
562    // Immediate offset in range [-4095, 4095].
563    if (!Mem.OffsetImm) return true;
564    int64_t Val = Mem.OffsetImm->getValue();
565    return Val > -4096 && Val < 4096;
566  }
567  bool isAM2OffsetImm() const {
568    if (Kind != Immediate)
569      return false;
570    // Immediate offset in range [-4095, 4095].
571    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
572    if (!CE) return false;
573    int64_t Val = CE->getValue();
574    return Val > -4096 && Val < 4096;
575  }
576  bool isAddrMode3() const {
577    if (Kind != Memory)
578      return false;
579    // No shifts are legal for AM3.
580    if (Mem.ShiftType != ARM_AM::no_shift) return false;
581    // Check for register offset.
582    if (Mem.OffsetRegNum) return true;
583    // Immediate offset in range [-255, 255].
584    if (!Mem.OffsetImm) return true;
585    int64_t Val = Mem.OffsetImm->getValue();
586    return Val > -256 && Val < 256;
587  }
588  bool isAM3Offset() const {
589    if (Kind != Immediate && Kind != PostIndexRegister)
590      return false;
591    if (Kind == PostIndexRegister)
592      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
593    // Immediate offset in range [-255, 255].
594    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
595    if (!CE) return false;
596    int64_t Val = CE->getValue();
597    // Special case, #-0 is INT32_MIN.
598    return (Val > -256 && Val < 256) || Val == INT32_MIN;
599  }
600  bool isAddrMode5() const {
601    if (Kind != Memory)
602      return false;
603    // Check for register offset.
604    if (Mem.OffsetRegNum) return false;
605    // Immediate offset in range [-1020, 1020] and a multiple of 4.
606    if (!Mem.OffsetImm) return true;
607    int64_t Val = Mem.OffsetImm->getValue();
608    return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0);
609  }
610  bool isMemRegOffset() const {
611    if (Kind != Memory || !Mem.OffsetRegNum)
612      return false;
613    return true;
614  }
615  bool isMemThumbRR() const {
616    // Thumb reg+reg addressing is simple. Just two registers, a base and
617    // an offset. No shifts, negations or any other complicating factors.
618    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
619        Mem.ShiftType != ARM_AM::no_shift)
620      return false;
621    return isARMLowRegister(Mem.BaseRegNum) &&
622      (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
623  }
624  bool isMemThumbRIs4() const {
625    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
626        !isARMLowRegister(Mem.BaseRegNum))
627      return false;
628    // Immediate offset, multiple of 4 in range [0, 124].
629    if (!Mem.OffsetImm) return true;
630    int64_t Val = Mem.OffsetImm->getValue();
631    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
632  }
633  bool isMemThumbRIs2() const {
634    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
635        !isARMLowRegister(Mem.BaseRegNum))
636      return false;
637    // Immediate offset, multiple of 4 in range [0, 62].
638    if (!Mem.OffsetImm) return true;
639    int64_t Val = Mem.OffsetImm->getValue();
640    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
641  }
642  bool isMemThumbRIs1() const {
643    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
644        !isARMLowRegister(Mem.BaseRegNum))
645      return false;
646    // Immediate offset in range [0, 31].
647    if (!Mem.OffsetImm) return true;
648    int64_t Val = Mem.OffsetImm->getValue();
649    return Val >= 0 && Val <= 31;
650  }
651  bool isMemThumbSPI() const {
652    if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
653      return false;
654    // Immediate offset, multiple of 4 in range [0, 1020].
655    if (!Mem.OffsetImm) return true;
656    int64_t Val = Mem.OffsetImm->getValue();
657    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
658  }
659  bool isMemImm8Offset() const {
660    if (Kind != Memory || Mem.OffsetRegNum != 0)
661      return false;
662    // Immediate offset in range [-255, 255].
663    if (!Mem.OffsetImm) return true;
664    int64_t Val = Mem.OffsetImm->getValue();
665    return Val > -256 && Val < 256;
666  }
667  bool isMemImm12Offset() const {
668    // If we have an immediate that's not a constant, treat it as a label
669    // reference needing a fixup. If it is a constant, it's something else
670    // and we reject it.
671    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
672      return true;
673
674    if (Kind != Memory || Mem.OffsetRegNum != 0)
675      return false;
676    // Immediate offset in range [-4095, 4095].
677    if (!Mem.OffsetImm) return true;
678    int64_t Val = Mem.OffsetImm->getValue();
679    return Val > -4096 && Val < 4096;
680  }
681  bool isPostIdxImm8() const {
682    if (Kind != Immediate)
683      return false;
684    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
685    if (!CE) return false;
686    int64_t Val = CE->getValue();
687    return Val > -256 && Val < 256;
688  }
689
690  bool isMSRMask() const { return Kind == MSRMask; }
691  bool isProcIFlags() const { return Kind == ProcIFlags; }
692
693  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
694    // Add as immediates when possible.  Null MCExpr = 0.
695    if (Expr == 0)
696      Inst.addOperand(MCOperand::CreateImm(0));
697    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
698      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
699    else
700      Inst.addOperand(MCOperand::CreateExpr(Expr));
701  }
702
703  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
704    assert(N == 2 && "Invalid number of operands!");
705    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
706    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
707    Inst.addOperand(MCOperand::CreateReg(RegNum));
708  }
709
710  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
711    assert(N == 1 && "Invalid number of operands!");
712    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
713  }
714
715  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
716    assert(N == 1 && "Invalid number of operands!");
717    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
718  }
719
720  void addCCOutOperands(MCInst &Inst, unsigned N) const {
721    assert(N == 1 && "Invalid number of operands!");
722    Inst.addOperand(MCOperand::CreateReg(getReg()));
723  }
724
725  void addRegOperands(MCInst &Inst, unsigned N) const {
726    assert(N == 1 && "Invalid number of operands!");
727    Inst.addOperand(MCOperand::CreateReg(getReg()));
728  }
729
730  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
731    assert(N == 3 && "Invalid number of operands!");
732    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
733    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
734    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
735    Inst.addOperand(MCOperand::CreateImm(
736      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
737  }
738
739  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
740    assert(N == 2 && "Invalid number of operands!");
741    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
742    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
743    Inst.addOperand(MCOperand::CreateImm(
744      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
745  }
746
747
748  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
749    assert(N == 1 && "Invalid number of operands!");
750    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
751                                         ShifterImm.Imm));
752  }
753
754  void addRegListOperands(MCInst &Inst, unsigned N) const {
755    assert(N == 1 && "Invalid number of operands!");
756    const SmallVectorImpl<unsigned> &RegList = getRegList();
757    for (SmallVectorImpl<unsigned>::const_iterator
758           I = RegList.begin(), E = RegList.end(); I != E; ++I)
759      Inst.addOperand(MCOperand::CreateReg(*I));
760  }
761
762  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
763    addRegListOperands(Inst, N);
764  }
765
766  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
767    addRegListOperands(Inst, N);
768  }
769
770  void addRotImmOperands(MCInst &Inst, unsigned N) const {
771    assert(N == 1 && "Invalid number of operands!");
772    // Encoded as val>>3. The printer handles display as 8, 16, 24.
773    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
774  }
775
776  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
777    assert(N == 1 && "Invalid number of operands!");
778    // Munge the lsb/width into a bitfield mask.
779    unsigned lsb = Bitfield.LSB;
780    unsigned width = Bitfield.Width;
781    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
782    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
783                      (32 - (lsb + width)));
784    Inst.addOperand(MCOperand::CreateImm(Mask));
785  }
786
787  void addImmOperands(MCInst &Inst, unsigned N) const {
788    assert(N == 1 && "Invalid number of operands!");
789    addExpr(Inst, getImm());
790  }
791
792  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
793    assert(N == 1 && "Invalid number of operands!");
794    addExpr(Inst, getImm());
795  }
796
797  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
798    assert(N == 1 && "Invalid number of operands!");
799    addExpr(Inst, getImm());
800  }
801
802  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
803    assert(N == 1 && "Invalid number of operands!");
804    addExpr(Inst, getImm());
805  }
806
807  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
808    assert(N == 1 && "Invalid number of operands!");
809    addExpr(Inst, getImm());
810  }
811
812  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
813    assert(N == 1 && "Invalid number of operands!");
814    // The constant encodes as the immediate-1, and we store in the instruction
815    // the bits as encoded, so subtract off one here.
816    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
817    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
818  }
819
820  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
821    assert(N == 1 && "Invalid number of operands!");
822    // The constant encodes as the immediate-1, and we store in the instruction
823    // the bits as encoded, so subtract off one here.
824    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
825    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
826  }
827
828  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
829    assert(N == 1 && "Invalid number of operands!");
830    addExpr(Inst, getImm());
831  }
832
833  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
834    assert(N == 1 && "Invalid number of operands!");
835    addExpr(Inst, getImm());
836  }
837
838  void addImm24bitOperands(MCInst &Inst, unsigned N) const {
839    assert(N == 1 && "Invalid number of operands!");
840    addExpr(Inst, getImm());
841  }
842
843  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
844    assert(N == 1 && "Invalid number of operands!");
845    // The constant encodes as the immediate, except for 32, which encodes as
846    // zero.
847    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
848    unsigned Imm = CE->getValue();
849    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
850  }
851
852  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
853    assert(N == 1 && "Invalid number of operands!");
854    addExpr(Inst, getImm());
855  }
856
857  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
858    assert(N == 1 && "Invalid number of operands!");
859    // An ASR value of 32 encodes as 0, so that's how we want to add it to
860    // the instruction as well.
861    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
862    int Val = CE->getValue();
863    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
864  }
865
866  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
867    assert(N == 1 && "Invalid number of operands!");
868    addExpr(Inst, getImm());
869  }
870
871  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
872    assert(N == 1 && "Invalid number of operands!");
873    addExpr(Inst, getImm());
874  }
875
876  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
877    assert(N == 1 && "Invalid number of operands!");
878    addExpr(Inst, getImm());
879  }
880
881  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
882    assert(N == 1 && "Invalid number of operands!");
883    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
884  }
885
886  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
887    assert(N == 1 && "Invalid number of operands!");
888    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
889  }
890
891  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
892    assert(N == 3 && "Invalid number of operands!");
893    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
894    if (!Mem.OffsetRegNum) {
895      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
896      // Special case for #-0
897      if (Val == INT32_MIN) Val = 0;
898      if (Val < 0) Val = -Val;
899      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
900    } else {
901      // For register offset, we encode the shift type and negation flag
902      // here.
903      Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
904                              Mem.ShiftImm, Mem.ShiftType);
905    }
906    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
907    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
908    Inst.addOperand(MCOperand::CreateImm(Val));
909  }
910
911  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
912    assert(N == 2 && "Invalid number of operands!");
913    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
914    assert(CE && "non-constant AM2OffsetImm operand!");
915    int32_t Val = CE->getValue();
916    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
917    // Special case for #-0
918    if (Val == INT32_MIN) Val = 0;
919    if (Val < 0) Val = -Val;
920    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
921    Inst.addOperand(MCOperand::CreateReg(0));
922    Inst.addOperand(MCOperand::CreateImm(Val));
923  }
924
925  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
926    assert(N == 3 && "Invalid number of operands!");
927    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
928    if (!Mem.OffsetRegNum) {
929      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
930      // Special case for #-0
931      if (Val == INT32_MIN) Val = 0;
932      if (Val < 0) Val = -Val;
933      Val = ARM_AM::getAM3Opc(AddSub, Val);
934    } else {
935      // For register offset, we encode the shift type and negation flag
936      // here.
937      Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
938    }
939    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
940    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
941    Inst.addOperand(MCOperand::CreateImm(Val));
942  }
943
944  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
945    assert(N == 2 && "Invalid number of operands!");
946    if (Kind == PostIndexRegister) {
947      int32_t Val =
948        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
949      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
950      Inst.addOperand(MCOperand::CreateImm(Val));
951      return;
952    }
953
954    // Constant offset.
955    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
956    int32_t Val = CE->getValue();
957    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
958    // Special case for #-0
959    if (Val == INT32_MIN) Val = 0;
960    if (Val < 0) Val = -Val;
961    Val = ARM_AM::getAM3Opc(AddSub, Val);
962    Inst.addOperand(MCOperand::CreateReg(0));
963    Inst.addOperand(MCOperand::CreateImm(Val));
964  }
965
966  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
967    assert(N == 2 && "Invalid number of operands!");
968    // The lower two bits are always zero and as such are not encoded.
969    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
970    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
971    // Special case for #-0
972    if (Val == INT32_MIN) Val = 0;
973    if (Val < 0) Val = -Val;
974    Val = ARM_AM::getAM5Opc(AddSub, Val);
975    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
976    Inst.addOperand(MCOperand::CreateImm(Val));
977  }
978
979  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
980    assert(N == 2 && "Invalid number of operands!");
981    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
982    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
983    Inst.addOperand(MCOperand::CreateImm(Val));
984  }
985
986  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
987    assert(N == 2 && "Invalid number of operands!");
988    // If this is an immediate, it's a label reference.
989    if (Kind == Immediate) {
990      addExpr(Inst, getImm());
991      Inst.addOperand(MCOperand::CreateImm(0));
992      return;
993    }
994
995    // Otherwise, it's a normal memory reg+offset.
996    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
997    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
998    Inst.addOperand(MCOperand::CreateImm(Val));
999  }
1000
1001  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1002    assert(N == 3 && "Invalid number of operands!");
1003    unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1004                                     Mem.ShiftImm, Mem.ShiftType);
1005    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1006    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1007    Inst.addOperand(MCOperand::CreateImm(Val));
1008  }
1009
1010  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1011    assert(N == 2 && "Invalid number of operands!");
1012    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1013    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1014  }
1015
1016  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1017    assert(N == 2 && "Invalid number of operands!");
1018    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1019    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1020    Inst.addOperand(MCOperand::CreateImm(Val));
1021  }
1022
1023  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1024    assert(N == 2 && "Invalid number of operands!");
1025    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1026    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1027    Inst.addOperand(MCOperand::CreateImm(Val));
1028  }
1029
1030  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1031    assert(N == 2 && "Invalid number of operands!");
1032    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1033    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1034    Inst.addOperand(MCOperand::CreateImm(Val));
1035  }
1036
1037  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1038    assert(N == 2 && "Invalid number of operands!");
1039    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1040    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1041    Inst.addOperand(MCOperand::CreateImm(Val));
1042  }
1043
1044  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1045    assert(N == 1 && "Invalid number of operands!");
1046    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1047    assert(CE && "non-constant post-idx-imm8 operand!");
1048    int Imm = CE->getValue();
1049    bool isAdd = Imm >= 0;
1050    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1051    Inst.addOperand(MCOperand::CreateImm(Imm));
1052  }
1053
1054  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1055    assert(N == 2 && "Invalid number of operands!");
1056    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1057    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1058  }
1059
1060  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1061    assert(N == 2 && "Invalid number of operands!");
1062    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1063    // The sign, shift type, and shift amount are encoded in a single operand
1064    // using the AM2 encoding helpers.
1065    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1066    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1067                                     PostIdxReg.ShiftTy);
1068    Inst.addOperand(MCOperand::CreateImm(Imm));
1069  }
1070
1071  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1072    assert(N == 1 && "Invalid number of operands!");
1073    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1074  }
1075
1076  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1077    assert(N == 1 && "Invalid number of operands!");
1078    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1079  }
1080
1081  virtual void print(raw_ostream &OS) const;
1082
1083  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1084    ARMOperand *Op = new ARMOperand(CondCode);
1085    Op->CC.Val = CC;
1086    Op->StartLoc = S;
1087    Op->EndLoc = S;
1088    return Op;
1089  }
1090
1091  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1092    ARMOperand *Op = new ARMOperand(CoprocNum);
1093    Op->Cop.Val = CopVal;
1094    Op->StartLoc = S;
1095    Op->EndLoc = S;
1096    return Op;
1097  }
1098
1099  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1100    ARMOperand *Op = new ARMOperand(CoprocReg);
1101    Op->Cop.Val = CopVal;
1102    Op->StartLoc = S;
1103    Op->EndLoc = S;
1104    return Op;
1105  }
1106
1107  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1108    ARMOperand *Op = new ARMOperand(CCOut);
1109    Op->Reg.RegNum = RegNum;
1110    Op->StartLoc = S;
1111    Op->EndLoc = S;
1112    return Op;
1113  }
1114
1115  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1116    ARMOperand *Op = new ARMOperand(Token);
1117    Op->Tok.Data = Str.data();
1118    Op->Tok.Length = Str.size();
1119    Op->StartLoc = S;
1120    Op->EndLoc = S;
1121    return Op;
1122  }
1123
1124  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1125    ARMOperand *Op = new ARMOperand(Register);
1126    Op->Reg.RegNum = RegNum;
1127    Op->StartLoc = S;
1128    Op->EndLoc = E;
1129    return Op;
1130  }
1131
1132  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1133                                           unsigned SrcReg,
1134                                           unsigned ShiftReg,
1135                                           unsigned ShiftImm,
1136                                           SMLoc S, SMLoc E) {
1137    ARMOperand *Op = new ARMOperand(ShiftedRegister);
1138    Op->RegShiftedReg.ShiftTy = ShTy;
1139    Op->RegShiftedReg.SrcReg = SrcReg;
1140    Op->RegShiftedReg.ShiftReg = ShiftReg;
1141    Op->RegShiftedReg.ShiftImm = ShiftImm;
1142    Op->StartLoc = S;
1143    Op->EndLoc = E;
1144    return Op;
1145  }
1146
1147  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1148                                            unsigned SrcReg,
1149                                            unsigned ShiftImm,
1150                                            SMLoc S, SMLoc E) {
1151    ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1152    Op->RegShiftedImm.ShiftTy = ShTy;
1153    Op->RegShiftedImm.SrcReg = SrcReg;
1154    Op->RegShiftedImm.ShiftImm = ShiftImm;
1155    Op->StartLoc = S;
1156    Op->EndLoc = E;
1157    return Op;
1158  }
1159
1160  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1161                                   SMLoc S, SMLoc E) {
1162    ARMOperand *Op = new ARMOperand(ShifterImmediate);
1163    Op->ShifterImm.isASR = isASR;
1164    Op->ShifterImm.Imm = Imm;
1165    Op->StartLoc = S;
1166    Op->EndLoc = E;
1167    return Op;
1168  }
1169
1170  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1171    ARMOperand *Op = new ARMOperand(RotateImmediate);
1172    Op->RotImm.Imm = Imm;
1173    Op->StartLoc = S;
1174    Op->EndLoc = E;
1175    return Op;
1176  }
1177
1178  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1179                                    SMLoc S, SMLoc E) {
1180    ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1181    Op->Bitfield.LSB = LSB;
1182    Op->Bitfield.Width = Width;
1183    Op->StartLoc = S;
1184    Op->EndLoc = E;
1185    return Op;
1186  }
1187
1188  static ARMOperand *
1189  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1190                SMLoc StartLoc, SMLoc EndLoc) {
1191    KindTy Kind = RegisterList;
1192
1193    if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1194        contains(Regs.front().first))
1195      Kind = DPRRegisterList;
1196    else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1197             contains(Regs.front().first))
1198      Kind = SPRRegisterList;
1199
1200    ARMOperand *Op = new ARMOperand(Kind);
1201    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1202           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1203      Op->Registers.push_back(I->first);
1204    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1205    Op->StartLoc = StartLoc;
1206    Op->EndLoc = EndLoc;
1207    return Op;
1208  }
1209
1210  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1211    ARMOperand *Op = new ARMOperand(Immediate);
1212    Op->Imm.Val = Val;
1213    Op->StartLoc = S;
1214    Op->EndLoc = E;
1215    return Op;
1216  }
1217
1218  static ARMOperand *CreateMem(unsigned BaseRegNum,
1219                               const MCConstantExpr *OffsetImm,
1220                               unsigned OffsetRegNum,
1221                               ARM_AM::ShiftOpc ShiftType,
1222                               unsigned ShiftImm,
1223                               bool isNegative,
1224                               SMLoc S, SMLoc E) {
1225    ARMOperand *Op = new ARMOperand(Memory);
1226    Op->Mem.BaseRegNum = BaseRegNum;
1227    Op->Mem.OffsetImm = OffsetImm;
1228    Op->Mem.OffsetRegNum = OffsetRegNum;
1229    Op->Mem.ShiftType = ShiftType;
1230    Op->Mem.ShiftImm = ShiftImm;
1231    Op->Mem.isNegative = isNegative;
1232    Op->StartLoc = S;
1233    Op->EndLoc = E;
1234    return Op;
1235  }
1236
1237  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1238                                      ARM_AM::ShiftOpc ShiftTy,
1239                                      unsigned ShiftImm,
1240                                      SMLoc S, SMLoc E) {
1241    ARMOperand *Op = new ARMOperand(PostIndexRegister);
1242    Op->PostIdxReg.RegNum = RegNum;
1243    Op->PostIdxReg.isAdd = isAdd;
1244    Op->PostIdxReg.ShiftTy = ShiftTy;
1245    Op->PostIdxReg.ShiftImm = ShiftImm;
1246    Op->StartLoc = S;
1247    Op->EndLoc = E;
1248    return Op;
1249  }
1250
1251  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1252    ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1253    Op->MBOpt.Val = Opt;
1254    Op->StartLoc = S;
1255    Op->EndLoc = S;
1256    return Op;
1257  }
1258
1259  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1260    ARMOperand *Op = new ARMOperand(ProcIFlags);
1261    Op->IFlags.Val = IFlags;
1262    Op->StartLoc = S;
1263    Op->EndLoc = S;
1264    return Op;
1265  }
1266
1267  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1268    ARMOperand *Op = new ARMOperand(MSRMask);
1269    Op->MMask.Val = MMask;
1270    Op->StartLoc = S;
1271    Op->EndLoc = S;
1272    return Op;
1273  }
1274};
1275
1276} // end anonymous namespace.
1277
1278void ARMOperand::print(raw_ostream &OS) const {
1279  switch (Kind) {
1280  case CondCode:
1281    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1282    break;
1283  case CCOut:
1284    OS << "<ccout " << getReg() << ">";
1285    break;
1286  case CoprocNum:
1287    OS << "<coprocessor number: " << getCoproc() << ">";
1288    break;
1289  case CoprocReg:
1290    OS << "<coprocessor register: " << getCoproc() << ">";
1291    break;
1292  case MSRMask:
1293    OS << "<mask: " << getMSRMask() << ">";
1294    break;
1295  case Immediate:
1296    getImm()->print(OS);
1297    break;
1298  case MemBarrierOpt:
1299    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1300    break;
1301  case Memory:
1302    OS << "<memory "
1303       << " base:" << Mem.BaseRegNum;
1304    OS << ">";
1305    break;
1306  case PostIndexRegister:
1307    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1308       << PostIdxReg.RegNum;
1309    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1310      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1311         << PostIdxReg.ShiftImm;
1312    OS << ">";
1313    break;
1314  case ProcIFlags: {
1315    OS << "<ARM_PROC::";
1316    unsigned IFlags = getProcIFlags();
1317    for (int i=2; i >= 0; --i)
1318      if (IFlags & (1 << i))
1319        OS << ARM_PROC::IFlagsToString(1 << i);
1320    OS << ">";
1321    break;
1322  }
1323  case Register:
1324    OS << "<register " << getReg() << ">";
1325    break;
1326  case ShifterImmediate:
1327    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1328       << " #" << ShifterImm.Imm << ">";
1329    break;
1330  case ShiftedRegister:
1331    OS << "<so_reg_reg "
1332       << RegShiftedReg.SrcReg
1333       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1334       << ", " << RegShiftedReg.ShiftReg << ", "
1335       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1336       << ">";
1337    break;
1338  case ShiftedImmediate:
1339    OS << "<so_reg_imm "
1340       << RegShiftedImm.SrcReg
1341       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1342       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1343       << ">";
1344    break;
1345  case RotateImmediate:
1346    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1347    break;
1348  case BitfieldDescriptor:
1349    OS << "<bitfield " << "lsb: " << Bitfield.LSB
1350       << ", width: " << Bitfield.Width << ">";
1351    break;
1352  case RegisterList:
1353  case DPRRegisterList:
1354  case SPRRegisterList: {
1355    OS << "<register_list ";
1356
1357    const SmallVectorImpl<unsigned> &RegList = getRegList();
1358    for (SmallVectorImpl<unsigned>::const_iterator
1359           I = RegList.begin(), E = RegList.end(); I != E; ) {
1360      OS << *I;
1361      if (++I < E) OS << ", ";
1362    }
1363
1364    OS << ">";
1365    break;
1366  }
1367  case Token:
1368    OS << "'" << getToken() << "'";
1369    break;
1370  }
1371}
1372
1373/// @name Auto-generated Match Functions
1374/// {
1375
1376static unsigned MatchRegisterName(StringRef Name);
1377
1378/// }
1379
1380bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1381                                 SMLoc &StartLoc, SMLoc &EndLoc) {
1382  RegNo = tryParseRegister();
1383
1384  return (RegNo == (unsigned)-1);
1385}
1386
1387/// Try to parse a register name.  The token must be an Identifier when called,
1388/// and if it is a register name the token is eaten and the register number is
1389/// returned.  Otherwise return -1.
1390///
1391int ARMAsmParser::tryParseRegister() {
1392  const AsmToken &Tok = Parser.getTok();
1393  if (Tok.isNot(AsmToken::Identifier)) return -1;
1394
1395  // FIXME: Validate register for the current architecture; we have to do
1396  // validation later, so maybe there is no need for this here.
1397  std::string upperCase = Tok.getString().str();
1398  std::string lowerCase = LowercaseString(upperCase);
1399  unsigned RegNum = MatchRegisterName(lowerCase);
1400  if (!RegNum) {
1401    RegNum = StringSwitch<unsigned>(lowerCase)
1402      .Case("r13", ARM::SP)
1403      .Case("r14", ARM::LR)
1404      .Case("r15", ARM::PC)
1405      .Case("ip", ARM::R12)
1406      .Default(0);
1407  }
1408  if (!RegNum) return -1;
1409
1410  Parser.Lex(); // Eat identifier token.
1411  return RegNum;
1412}
1413
1414// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
1415// If a recoverable error occurs, return 1. If an irrecoverable error
1416// occurs, return -1. An irrecoverable error is one where tokens have been
1417// consumed in the process of trying to parse the shifter (i.e., when it is
1418// indeed a shifter operand, but malformed).
1419int ARMAsmParser::tryParseShiftRegister(
1420                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1421  SMLoc S = Parser.getTok().getLoc();
1422  const AsmToken &Tok = Parser.getTok();
1423  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1424
1425  std::string upperCase = Tok.getString().str();
1426  std::string lowerCase = LowercaseString(upperCase);
1427  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1428      .Case("lsl", ARM_AM::lsl)
1429      .Case("lsr", ARM_AM::lsr)
1430      .Case("asr", ARM_AM::asr)
1431      .Case("ror", ARM_AM::ror)
1432      .Case("rrx", ARM_AM::rrx)
1433      .Default(ARM_AM::no_shift);
1434
1435  if (ShiftTy == ARM_AM::no_shift)
1436    return 1;
1437
1438  Parser.Lex(); // Eat the operator.
1439
1440  // The source register for the shift has already been added to the
1441  // operand list, so we need to pop it off and combine it into the shifted
1442  // register operand instead.
1443  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1444  if (!PrevOp->isReg())
1445    return Error(PrevOp->getStartLoc(), "shift must be of a register");
1446  int SrcReg = PrevOp->getReg();
1447  int64_t Imm = 0;
1448  int ShiftReg = 0;
1449  if (ShiftTy == ARM_AM::rrx) {
1450    // RRX Doesn't have an explicit shift amount. The encoder expects
1451    // the shift register to be the same as the source register. Seems odd,
1452    // but OK.
1453    ShiftReg = SrcReg;
1454  } else {
1455    // Figure out if this is shifted by a constant or a register (for non-RRX).
1456    if (Parser.getTok().is(AsmToken::Hash)) {
1457      Parser.Lex(); // Eat hash.
1458      SMLoc ImmLoc = Parser.getTok().getLoc();
1459      const MCExpr *ShiftExpr = 0;
1460      if (getParser().ParseExpression(ShiftExpr)) {
1461        Error(ImmLoc, "invalid immediate shift value");
1462        return -1;
1463      }
1464      // The expression must be evaluatable as an immediate.
1465      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1466      if (!CE) {
1467        Error(ImmLoc, "invalid immediate shift value");
1468        return -1;
1469      }
1470      // Range check the immediate.
1471      // lsl, ror: 0 <= imm <= 31
1472      // lsr, asr: 0 <= imm <= 32
1473      Imm = CE->getValue();
1474      if (Imm < 0 ||
1475          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1476          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1477        Error(ImmLoc, "immediate shift value out of range");
1478        return -1;
1479      }
1480    } else if (Parser.getTok().is(AsmToken::Identifier)) {
1481      ShiftReg = tryParseRegister();
1482      SMLoc L = Parser.getTok().getLoc();
1483      if (ShiftReg == -1) {
1484        Error (L, "expected immediate or register in shift operand");
1485        return -1;
1486      }
1487    } else {
1488      Error (Parser.getTok().getLoc(),
1489                    "expected immediate or register in shift operand");
1490      return -1;
1491    }
1492  }
1493
1494  if (ShiftReg && ShiftTy != ARM_AM::rrx)
1495    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1496                                                         ShiftReg, Imm,
1497                                               S, Parser.getTok().getLoc()));
1498  else
1499    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1500                                               S, Parser.getTok().getLoc()));
1501
1502  return 0;
1503}
1504
1505
1506/// Try to parse a register name.  The token must be an Identifier when called.
1507/// If it's a register, an AsmOperand is created. Another AsmOperand is created
1508/// if there is a "writeback". 'true' if it's not a register.
1509///
1510/// TODO this is likely to change to allow different register types and or to
1511/// parse for a specific register type.
1512bool ARMAsmParser::
1513tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1514  SMLoc S = Parser.getTok().getLoc();
1515  int RegNo = tryParseRegister();
1516  if (RegNo == -1)
1517    return true;
1518
1519  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1520
1521  const AsmToken &ExclaimTok = Parser.getTok();
1522  if (ExclaimTok.is(AsmToken::Exclaim)) {
1523    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1524                                               ExclaimTok.getLoc()));
1525    Parser.Lex(); // Eat exclaim token
1526  }
1527
1528  return false;
1529}
1530
1531/// MatchCoprocessorOperandName - Try to parse an coprocessor related
1532/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1533/// "c5", ...
1534static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1535  // Use the same layout as the tablegen'erated register name matcher. Ugly,
1536  // but efficient.
1537  switch (Name.size()) {
1538  default: break;
1539  case 2:
1540    if (Name[0] != CoprocOp)
1541      return -1;
1542    switch (Name[1]) {
1543    default:  return -1;
1544    case '0': return 0;
1545    case '1': return 1;
1546    case '2': return 2;
1547    case '3': return 3;
1548    case '4': return 4;
1549    case '5': return 5;
1550    case '6': return 6;
1551    case '7': return 7;
1552    case '8': return 8;
1553    case '9': return 9;
1554    }
1555    break;
1556  case 3:
1557    if (Name[0] != CoprocOp || Name[1] != '1')
1558      return -1;
1559    switch (Name[2]) {
1560    default:  return -1;
1561    case '0': return 10;
1562    case '1': return 11;
1563    case '2': return 12;
1564    case '3': return 13;
1565    case '4': return 14;
1566    case '5': return 15;
1567    }
1568    break;
1569  }
1570
1571  return -1;
1572}
1573
1574/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1575/// token must be an Identifier when called, and if it is a coprocessor
1576/// number, the token is eaten and the operand is added to the operand list.
1577ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1578parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1579  SMLoc S = Parser.getTok().getLoc();
1580  const AsmToken &Tok = Parser.getTok();
1581  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1582
1583  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1584  if (Num == -1)
1585    return MatchOperand_NoMatch;
1586
1587  Parser.Lex(); // Eat identifier token.
1588  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1589  return MatchOperand_Success;
1590}
1591
1592/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1593/// token must be an Identifier when called, and if it is a coprocessor
1594/// number, the token is eaten and the operand is added to the operand list.
1595ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1596parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1597  SMLoc S = Parser.getTok().getLoc();
1598  const AsmToken &Tok = Parser.getTok();
1599  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1600
1601  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1602  if (Reg == -1)
1603    return MatchOperand_NoMatch;
1604
1605  Parser.Lex(); // Eat identifier token.
1606  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1607  return MatchOperand_Success;
1608}
1609
1610/// Parse a register list, return it if successful else return null.  The first
1611/// token must be a '{' when called.
1612bool ARMAsmParser::
1613parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1614  assert(Parser.getTok().is(AsmToken::LCurly) &&
1615         "Token is not a Left Curly Brace");
1616  SMLoc S = Parser.getTok().getLoc();
1617
1618  // Read the rest of the registers in the list.
1619  unsigned PrevRegNum = 0;
1620  SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1621
1622  do {
1623    bool IsRange = Parser.getTok().is(AsmToken::Minus);
1624    Parser.Lex(); // Eat non-identifier token.
1625
1626    const AsmToken &RegTok = Parser.getTok();
1627    SMLoc RegLoc = RegTok.getLoc();
1628    if (RegTok.isNot(AsmToken::Identifier)) {
1629      Error(RegLoc, "register expected");
1630      return true;
1631    }
1632
1633    int RegNum = tryParseRegister();
1634    if (RegNum == -1) {
1635      Error(RegLoc, "register expected");
1636      return true;
1637    }
1638
1639    if (IsRange) {
1640      int Reg = PrevRegNum;
1641      do {
1642        ++Reg;
1643        Registers.push_back(std::make_pair(Reg, RegLoc));
1644      } while (Reg != RegNum);
1645    } else {
1646      Registers.push_back(std::make_pair(RegNum, RegLoc));
1647    }
1648
1649    PrevRegNum = RegNum;
1650  } while (Parser.getTok().is(AsmToken::Comma) ||
1651           Parser.getTok().is(AsmToken::Minus));
1652
1653  // Process the right curly brace of the list.
1654  const AsmToken &RCurlyTok = Parser.getTok();
1655  if (RCurlyTok.isNot(AsmToken::RCurly)) {
1656    Error(RCurlyTok.getLoc(), "'}' expected");
1657    return true;
1658  }
1659
1660  SMLoc E = RCurlyTok.getLoc();
1661  Parser.Lex(); // Eat right curly brace token.
1662
1663  // Verify the register list.
1664  SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1665    RI = Registers.begin(), RE = Registers.end();
1666
1667  unsigned HighRegNum = getARMRegisterNumbering(RI->first);
1668  bool EmittedWarning = false;
1669
1670  DenseMap<unsigned, bool> RegMap;
1671  RegMap[HighRegNum] = true;
1672
1673  for (++RI; RI != RE; ++RI) {
1674    const std::pair<unsigned, SMLoc> &RegInfo = *RI;
1675    unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1676
1677    if (RegMap[Reg]) {
1678      Error(RegInfo.second, "register duplicated in register list");
1679      return true;
1680    }
1681
1682    if (!EmittedWarning && Reg < HighRegNum)
1683      Warning(RegInfo.second,
1684              "register not in ascending order in register list");
1685
1686    RegMap[Reg] = true;
1687    HighRegNum = std::max(Reg, HighRegNum);
1688  }
1689
1690  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1691  return false;
1692}
1693
1694/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1695ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1696parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1697  SMLoc S = Parser.getTok().getLoc();
1698  const AsmToken &Tok = Parser.getTok();
1699  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1700  StringRef OptStr = Tok.getString();
1701
1702  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1703    .Case("sy",    ARM_MB::SY)
1704    .Case("st",    ARM_MB::ST)
1705    .Case("sh",    ARM_MB::ISH)
1706    .Case("ish",   ARM_MB::ISH)
1707    .Case("shst",  ARM_MB::ISHST)
1708    .Case("ishst", ARM_MB::ISHST)
1709    .Case("nsh",   ARM_MB::NSH)
1710    .Case("un",    ARM_MB::NSH)
1711    .Case("nshst", ARM_MB::NSHST)
1712    .Case("unst",  ARM_MB::NSHST)
1713    .Case("osh",   ARM_MB::OSH)
1714    .Case("oshst", ARM_MB::OSHST)
1715    .Default(~0U);
1716
1717  if (Opt == ~0U)
1718    return MatchOperand_NoMatch;
1719
1720  Parser.Lex(); // Eat identifier token.
1721  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1722  return MatchOperand_Success;
1723}
1724
1725/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1726ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1727parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1728  SMLoc S = Parser.getTok().getLoc();
1729  const AsmToken &Tok = Parser.getTok();
1730  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1731  StringRef IFlagsStr = Tok.getString();
1732
1733  unsigned IFlags = 0;
1734  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1735    unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1736    .Case("a", ARM_PROC::A)
1737    .Case("i", ARM_PROC::I)
1738    .Case("f", ARM_PROC::F)
1739    .Default(~0U);
1740
1741    // If some specific iflag is already set, it means that some letter is
1742    // present more than once, this is not acceptable.
1743    if (Flag == ~0U || (IFlags & Flag))
1744      return MatchOperand_NoMatch;
1745
1746    IFlags |= Flag;
1747  }
1748
1749  Parser.Lex(); // Eat identifier token.
1750  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1751  return MatchOperand_Success;
1752}
1753
1754/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1755ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1756parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1757  SMLoc S = Parser.getTok().getLoc();
1758  const AsmToken &Tok = Parser.getTok();
1759  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1760  StringRef Mask = Tok.getString();
1761
1762  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1763  size_t Start = 0, Next = Mask.find('_');
1764  StringRef Flags = "";
1765  std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1766  if (Next != StringRef::npos)
1767    Flags = Mask.slice(Next+1, Mask.size());
1768
1769  // FlagsVal contains the complete mask:
1770  // 3-0: Mask
1771  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1772  unsigned FlagsVal = 0;
1773
1774  if (SpecReg == "apsr") {
1775    FlagsVal = StringSwitch<unsigned>(Flags)
1776    .Case("nzcvq",  0x8) // same as CPSR_f
1777    .Case("g",      0x4) // same as CPSR_s
1778    .Case("nzcvqg", 0xc) // same as CPSR_fs
1779    .Default(~0U);
1780
1781    if (FlagsVal == ~0U) {
1782      if (!Flags.empty())
1783        return MatchOperand_NoMatch;
1784      else
1785        FlagsVal = 0; // No flag
1786    }
1787  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1788    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1789      Flags = "fc";
1790    for (int i = 0, e = Flags.size(); i != e; ++i) {
1791      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1792      .Case("c", 1)
1793      .Case("x", 2)
1794      .Case("s", 4)
1795      .Case("f", 8)
1796      .Default(~0U);
1797
1798      // If some specific flag is already set, it means that some letter is
1799      // present more than once, this is not acceptable.
1800      if (FlagsVal == ~0U || (FlagsVal & Flag))
1801        return MatchOperand_NoMatch;
1802      FlagsVal |= Flag;
1803    }
1804  } else // No match for special register.
1805    return MatchOperand_NoMatch;
1806
1807  // Special register without flags are equivalent to "fc" flags.
1808  if (!FlagsVal)
1809    FlagsVal = 0x9;
1810
1811  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1812  if (SpecReg == "spsr")
1813    FlagsVal |= 16;
1814
1815  Parser.Lex(); // Eat identifier token.
1816  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1817  return MatchOperand_Success;
1818}
1819
1820ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1821parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1822            int Low, int High) {
1823  const AsmToken &Tok = Parser.getTok();
1824  if (Tok.isNot(AsmToken::Identifier)) {
1825    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1826    return MatchOperand_ParseFail;
1827  }
1828  StringRef ShiftName = Tok.getString();
1829  std::string LowerOp = LowercaseString(Op);
1830  std::string UpperOp = UppercaseString(Op);
1831  if (ShiftName != LowerOp && ShiftName != UpperOp) {
1832    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1833    return MatchOperand_ParseFail;
1834  }
1835  Parser.Lex(); // Eat shift type token.
1836
1837  // There must be a '#' and a shift amount.
1838  if (Parser.getTok().isNot(AsmToken::Hash)) {
1839    Error(Parser.getTok().getLoc(), "'#' expected");
1840    return MatchOperand_ParseFail;
1841  }
1842  Parser.Lex(); // Eat hash token.
1843
1844  const MCExpr *ShiftAmount;
1845  SMLoc Loc = Parser.getTok().getLoc();
1846  if (getParser().ParseExpression(ShiftAmount)) {
1847    Error(Loc, "illegal expression");
1848    return MatchOperand_ParseFail;
1849  }
1850  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1851  if (!CE) {
1852    Error(Loc, "constant expression expected");
1853    return MatchOperand_ParseFail;
1854  }
1855  int Val = CE->getValue();
1856  if (Val < Low || Val > High) {
1857    Error(Loc, "immediate value out of range");
1858    return MatchOperand_ParseFail;
1859  }
1860
1861  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1862
1863  return MatchOperand_Success;
1864}
1865
1866ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1867parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1868  const AsmToken &Tok = Parser.getTok();
1869  SMLoc S = Tok.getLoc();
1870  if (Tok.isNot(AsmToken::Identifier)) {
1871    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1872    return MatchOperand_ParseFail;
1873  }
1874  int Val = StringSwitch<int>(Tok.getString())
1875    .Case("be", 1)
1876    .Case("le", 0)
1877    .Default(-1);
1878  Parser.Lex(); // Eat the token.
1879
1880  if (Val == -1) {
1881    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1882    return MatchOperand_ParseFail;
1883  }
1884  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1885                                                                  getContext()),
1886                                           S, Parser.getTok().getLoc()));
1887  return MatchOperand_Success;
1888}
1889
1890/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
1891/// instructions. Legal values are:
1892///     lsl #n  'n' in [0,31]
1893///     asr #n  'n' in [1,32]
1894///             n == 32 encoded as n == 0.
1895ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1896parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1897  const AsmToken &Tok = Parser.getTok();
1898  SMLoc S = Tok.getLoc();
1899  if (Tok.isNot(AsmToken::Identifier)) {
1900    Error(S, "shift operator 'asr' or 'lsl' expected");
1901    return MatchOperand_ParseFail;
1902  }
1903  StringRef ShiftName = Tok.getString();
1904  bool isASR;
1905  if (ShiftName == "lsl" || ShiftName == "LSL")
1906    isASR = false;
1907  else if (ShiftName == "asr" || ShiftName == "ASR")
1908    isASR = true;
1909  else {
1910    Error(S, "shift operator 'asr' or 'lsl' expected");
1911    return MatchOperand_ParseFail;
1912  }
1913  Parser.Lex(); // Eat the operator.
1914
1915  // A '#' and a shift amount.
1916  if (Parser.getTok().isNot(AsmToken::Hash)) {
1917    Error(Parser.getTok().getLoc(), "'#' expected");
1918    return MatchOperand_ParseFail;
1919  }
1920  Parser.Lex(); // Eat hash token.
1921
1922  const MCExpr *ShiftAmount;
1923  SMLoc E = Parser.getTok().getLoc();
1924  if (getParser().ParseExpression(ShiftAmount)) {
1925    Error(E, "malformed shift expression");
1926    return MatchOperand_ParseFail;
1927  }
1928  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1929  if (!CE) {
1930    Error(E, "shift amount must be an immediate");
1931    return MatchOperand_ParseFail;
1932  }
1933
1934  int64_t Val = CE->getValue();
1935  if (isASR) {
1936    // Shift amount must be in [1,32]
1937    if (Val < 1 || Val > 32) {
1938      Error(E, "'asr' shift amount must be in range [1,32]");
1939      return MatchOperand_ParseFail;
1940    }
1941    // asr #32 encoded as asr #0.
1942    if (Val == 32) Val = 0;
1943  } else {
1944    // Shift amount must be in [1,32]
1945    if (Val < 0 || Val > 31) {
1946      Error(E, "'lsr' shift amount must be in range [0,31]");
1947      return MatchOperand_ParseFail;
1948    }
1949  }
1950
1951  E = Parser.getTok().getLoc();
1952  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
1953
1954  return MatchOperand_Success;
1955}
1956
1957/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
1958/// of instructions. Legal values are:
1959///     ror #n  'n' in {0, 8, 16, 24}
1960ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1961parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1962  const AsmToken &Tok = Parser.getTok();
1963  SMLoc S = Tok.getLoc();
1964  if (Tok.isNot(AsmToken::Identifier)) {
1965    Error(S, "rotate operator 'ror' expected");
1966    return MatchOperand_ParseFail;
1967  }
1968  StringRef ShiftName = Tok.getString();
1969  if (ShiftName != "ror" && ShiftName != "ROR") {
1970    Error(S, "rotate operator 'ror' expected");
1971    return MatchOperand_ParseFail;
1972  }
1973  Parser.Lex(); // Eat the operator.
1974
1975  // A '#' and a rotate amount.
1976  if (Parser.getTok().isNot(AsmToken::Hash)) {
1977    Error(Parser.getTok().getLoc(), "'#' expected");
1978    return MatchOperand_ParseFail;
1979  }
1980  Parser.Lex(); // Eat hash token.
1981
1982  const MCExpr *ShiftAmount;
1983  SMLoc E = Parser.getTok().getLoc();
1984  if (getParser().ParseExpression(ShiftAmount)) {
1985    Error(E, "malformed rotate expression");
1986    return MatchOperand_ParseFail;
1987  }
1988  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1989  if (!CE) {
1990    Error(E, "rotate amount must be an immediate");
1991    return MatchOperand_ParseFail;
1992  }
1993
1994  int64_t Val = CE->getValue();
1995  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
1996  // normally, zero is represented in asm by omitting the rotate operand
1997  // entirely.
1998  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
1999    Error(E, "'ror' rotate amount must be 8, 16, or 24");
2000    return MatchOperand_ParseFail;
2001  }
2002
2003  E = Parser.getTok().getLoc();
2004  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2005
2006  return MatchOperand_Success;
2007}
2008
2009ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2010parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2011  SMLoc S = Parser.getTok().getLoc();
2012  // The bitfield descriptor is really two operands, the LSB and the width.
2013  if (Parser.getTok().isNot(AsmToken::Hash)) {
2014    Error(Parser.getTok().getLoc(), "'#' expected");
2015    return MatchOperand_ParseFail;
2016  }
2017  Parser.Lex(); // Eat hash token.
2018
2019  const MCExpr *LSBExpr;
2020  SMLoc E = Parser.getTok().getLoc();
2021  if (getParser().ParseExpression(LSBExpr)) {
2022    Error(E, "malformed immediate expression");
2023    return MatchOperand_ParseFail;
2024  }
2025  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2026  if (!CE) {
2027    Error(E, "'lsb' operand must be an immediate");
2028    return MatchOperand_ParseFail;
2029  }
2030
2031  int64_t LSB = CE->getValue();
2032  // The LSB must be in the range [0,31]
2033  if (LSB < 0 || LSB > 31) {
2034    Error(E, "'lsb' operand must be in the range [0,31]");
2035    return MatchOperand_ParseFail;
2036  }
2037  E = Parser.getTok().getLoc();
2038
2039  // Expect another immediate operand.
2040  if (Parser.getTok().isNot(AsmToken::Comma)) {
2041    Error(Parser.getTok().getLoc(), "too few operands");
2042    return MatchOperand_ParseFail;
2043  }
2044  Parser.Lex(); // Eat hash token.
2045  if (Parser.getTok().isNot(AsmToken::Hash)) {
2046    Error(Parser.getTok().getLoc(), "'#' expected");
2047    return MatchOperand_ParseFail;
2048  }
2049  Parser.Lex(); // Eat hash token.
2050
2051  const MCExpr *WidthExpr;
2052  if (getParser().ParseExpression(WidthExpr)) {
2053    Error(E, "malformed immediate expression");
2054    return MatchOperand_ParseFail;
2055  }
2056  CE = dyn_cast<MCConstantExpr>(WidthExpr);
2057  if (!CE) {
2058    Error(E, "'width' operand must be an immediate");
2059    return MatchOperand_ParseFail;
2060  }
2061
2062  int64_t Width = CE->getValue();
2063  // The LSB must be in the range [1,32-lsb]
2064  if (Width < 1 || Width > 32 - LSB) {
2065    Error(E, "'width' operand must be in the range [1,32-lsb]");
2066    return MatchOperand_ParseFail;
2067  }
2068  E = Parser.getTok().getLoc();
2069
2070  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2071
2072  return MatchOperand_Success;
2073}
2074
2075ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2076parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2077  // Check for a post-index addressing register operand. Specifically:
2078  // postidx_reg := '+' register {, shift}
2079  //              | '-' register {, shift}
2080  //              | register {, shift}
2081
2082  // This method must return MatchOperand_NoMatch without consuming any tokens
2083  // in the case where there is no match, as other alternatives take other
2084  // parse methods.
2085  AsmToken Tok = Parser.getTok();
2086  SMLoc S = Tok.getLoc();
2087  bool haveEaten = false;
2088  bool isAdd = true;
2089  int Reg = -1;
2090  if (Tok.is(AsmToken::Plus)) {
2091    Parser.Lex(); // Eat the '+' token.
2092    haveEaten = true;
2093  } else if (Tok.is(AsmToken::Minus)) {
2094    Parser.Lex(); // Eat the '-' token.
2095    isAdd = false;
2096    haveEaten = true;
2097  }
2098  if (Parser.getTok().is(AsmToken::Identifier))
2099    Reg = tryParseRegister();
2100  if (Reg == -1) {
2101    if (!haveEaten)
2102      return MatchOperand_NoMatch;
2103    Error(Parser.getTok().getLoc(), "register expected");
2104    return MatchOperand_ParseFail;
2105  }
2106  SMLoc E = Parser.getTok().getLoc();
2107
2108  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2109  unsigned ShiftImm = 0;
2110  if (Parser.getTok().is(AsmToken::Comma)) {
2111    Parser.Lex(); // Eat the ','.
2112    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2113      return MatchOperand_ParseFail;
2114  }
2115
2116  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2117                                                  ShiftImm, S, E));
2118
2119  return MatchOperand_Success;
2120}
2121
2122ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2123parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2124  // Check for a post-index addressing register operand. Specifically:
2125  // am3offset := '+' register
2126  //              | '-' register
2127  //              | register
2128  //              | # imm
2129  //              | # + imm
2130  //              | # - imm
2131
2132  // This method must return MatchOperand_NoMatch without consuming any tokens
2133  // in the case where there is no match, as other alternatives take other
2134  // parse methods.
2135  AsmToken Tok = Parser.getTok();
2136  SMLoc S = Tok.getLoc();
2137
2138  // Do immediates first, as we always parse those if we have a '#'.
2139  if (Parser.getTok().is(AsmToken::Hash)) {
2140    Parser.Lex(); // Eat the '#'.
2141    // Explicitly look for a '-', as we need to encode negative zero
2142    // differently.
2143    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2144    const MCExpr *Offset;
2145    if (getParser().ParseExpression(Offset))
2146      return MatchOperand_ParseFail;
2147    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2148    if (!CE) {
2149      Error(S, "constant expression expected");
2150      return MatchOperand_ParseFail;
2151    }
2152    SMLoc E = Tok.getLoc();
2153    // Negative zero is encoded as the flag value INT32_MIN.
2154    int32_t Val = CE->getValue();
2155    if (isNegative && Val == 0)
2156      Val = INT32_MIN;
2157
2158    Operands.push_back(
2159      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2160
2161    return MatchOperand_Success;
2162  }
2163
2164
2165  bool haveEaten = false;
2166  bool isAdd = true;
2167  int Reg = -1;
2168  if (Tok.is(AsmToken::Plus)) {
2169    Parser.Lex(); // Eat the '+' token.
2170    haveEaten = true;
2171  } else if (Tok.is(AsmToken::Minus)) {
2172    Parser.Lex(); // Eat the '-' token.
2173    isAdd = false;
2174    haveEaten = true;
2175  }
2176  if (Parser.getTok().is(AsmToken::Identifier))
2177    Reg = tryParseRegister();
2178  if (Reg == -1) {
2179    if (!haveEaten)
2180      return MatchOperand_NoMatch;
2181    Error(Parser.getTok().getLoc(), "register expected");
2182    return MatchOperand_ParseFail;
2183  }
2184  SMLoc E = Parser.getTok().getLoc();
2185
2186  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2187                                                  0, S, E));
2188
2189  return MatchOperand_Success;
2190}
2191
2192/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2193/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2194/// when they refer multiple MIOperands inside a single one.
2195bool ARMAsmParser::
2196cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2197                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2198  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2199
2200  // Create a writeback register dummy placeholder.
2201  Inst.addOperand(MCOperand::CreateImm(0));
2202
2203  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2204  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2205  return true;
2206}
2207
2208/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2209/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2210/// when they refer multiple MIOperands inside a single one.
2211bool ARMAsmParser::
2212cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2213                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2214  // Create a writeback register dummy placeholder.
2215  Inst.addOperand(MCOperand::CreateImm(0));
2216  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2217  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2218  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2219  return true;
2220}
2221
2222/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2223/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2224/// when they refer multiple MIOperands inside a single one.
2225bool ARMAsmParser::
2226cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2227                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2228  // Create a writeback register dummy placeholder.
2229  Inst.addOperand(MCOperand::CreateImm(0));
2230  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2231  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2232  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2233  return true;
2234}
2235
2236/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2237/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2238/// when they refer multiple MIOperands inside a single one.
2239bool ARMAsmParser::
2240cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2241                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2242  // Create a writeback register dummy placeholder.
2243  Inst.addOperand(MCOperand::CreateImm(0));
2244  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2245  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2246  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2247  return true;
2248}
2249
2250/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2251/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2252/// when they refer multiple MIOperands inside a single one.
2253bool ARMAsmParser::
2254cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2255                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2256  // Rt
2257  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2258  // Create a writeback register dummy placeholder.
2259  Inst.addOperand(MCOperand::CreateImm(0));
2260  // addr
2261  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2262  // offset
2263  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2264  // pred
2265  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2266  return true;
2267}
2268
2269/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2270/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2271/// when they refer multiple MIOperands inside a single one.
2272bool ARMAsmParser::
2273cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2274                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2275  // Rt
2276  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2277  // Create a writeback register dummy placeholder.
2278  Inst.addOperand(MCOperand::CreateImm(0));
2279  // addr
2280  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2281  // offset
2282  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2283  // pred
2284  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2285  return true;
2286}
2287
2288/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2289/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2290/// when they refer multiple MIOperands inside a single one.
2291bool ARMAsmParser::
2292cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2293                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2294  // Create a writeback register dummy placeholder.
2295  Inst.addOperand(MCOperand::CreateImm(0));
2296  // Rt
2297  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2298  // addr
2299  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2300  // offset
2301  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2302  // pred
2303  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2304  return true;
2305}
2306
2307/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2308/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2309/// when they refer multiple MIOperands inside a single one.
2310bool ARMAsmParser::
2311cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2312                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2313  // Create a writeback register dummy placeholder.
2314  Inst.addOperand(MCOperand::CreateImm(0));
2315  // Rt
2316  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2317  // addr
2318  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2319  // offset
2320  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2321  // pred
2322  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2323  return true;
2324}
2325
2326/// cvtLdrdPre - Convert parsed operands to MCInst.
2327/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2328/// when they refer multiple MIOperands inside a single one.
2329bool ARMAsmParser::
2330cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2331           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2332  // Rt, Rt2
2333  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2334  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2335  // Create a writeback register dummy placeholder.
2336  Inst.addOperand(MCOperand::CreateImm(0));
2337  // addr
2338  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2339  // pred
2340  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2341  return true;
2342}
2343
2344/// cvtStrdPre - Convert parsed operands to MCInst.
2345/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2346/// when they refer multiple MIOperands inside a single one.
2347bool ARMAsmParser::
2348cvtStrdPre(MCInst &Inst, unsigned Opcode,
2349           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2350  // Create a writeback register dummy placeholder.
2351  Inst.addOperand(MCOperand::CreateImm(0));
2352  // Rt, Rt2
2353  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2354  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2355  // addr
2356  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2357  // pred
2358  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2359  return true;
2360}
2361
2362/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2363/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2364/// when they refer multiple MIOperands inside a single one.
2365bool ARMAsmParser::
2366cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2367                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2368  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2369  // Create a writeback register dummy placeholder.
2370  Inst.addOperand(MCOperand::CreateImm(0));
2371  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2372  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2373  return true;
2374}
2375
2376/// cvtThumbMultiple- Convert parsed operands to MCInst.
2377/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2378/// when they refer multiple MIOperands inside a single one.
2379bool ARMAsmParser::
2380cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
2381           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2382  // The second source operand must be the same register as the destination
2383  // operand.
2384  if (Operands.size() == 6 &&
2385      (((ARMOperand*)Operands[3])->getReg() !=
2386       ((ARMOperand*)Operands[5])->getReg()) &&
2387      (((ARMOperand*)Operands[3])->getReg() !=
2388       ((ARMOperand*)Operands[4])->getReg())) {
2389    Error(Operands[3]->getStartLoc(),
2390          "destination register must match source register");
2391    return false;
2392  }
2393  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2394  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
2395  ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
2396  // If we have a three-operand form, use that, else the second source operand
2397  // is just the destination operand again.
2398  if (Operands.size() == 6)
2399    ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
2400  else
2401    Inst.addOperand(Inst.getOperand(0));
2402  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
2403
2404  return true;
2405}
2406
2407/// Parse an ARM memory expression, return false if successful else return true
2408/// or an error.  The first token must be a '[' when called.
2409bool ARMAsmParser::
2410parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2411  SMLoc S, E;
2412  assert(Parser.getTok().is(AsmToken::LBrac) &&
2413         "Token is not a Left Bracket");
2414  S = Parser.getTok().getLoc();
2415  Parser.Lex(); // Eat left bracket token.
2416
2417  const AsmToken &BaseRegTok = Parser.getTok();
2418  int BaseRegNum = tryParseRegister();
2419  if (BaseRegNum == -1)
2420    return Error(BaseRegTok.getLoc(), "register expected");
2421
2422  // The next token must either be a comma or a closing bracket.
2423  const AsmToken &Tok = Parser.getTok();
2424  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2425    return Error(Tok.getLoc(), "malformed memory operand");
2426
2427  if (Tok.is(AsmToken::RBrac)) {
2428    E = Tok.getLoc();
2429    Parser.Lex(); // Eat right bracket token.
2430
2431    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2432                                             0, false, S, E));
2433
2434    return false;
2435  }
2436
2437  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2438  Parser.Lex(); // Eat the comma.
2439
2440  // If we have a '#' it's an immediate offset, else assume it's a register
2441  // offset.
2442  if (Parser.getTok().is(AsmToken::Hash)) {
2443    Parser.Lex(); // Eat the '#'.
2444    E = Parser.getTok().getLoc();
2445
2446    // FIXME: Special case #-0 so we can correctly set the U bit.
2447
2448    const MCExpr *Offset;
2449    if (getParser().ParseExpression(Offset))
2450     return true;
2451
2452    // The expression has to be a constant. Memory references with relocations
2453    // don't come through here, as they use the <label> forms of the relevant
2454    // instructions.
2455    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2456    if (!CE)
2457      return Error (E, "constant expression expected");
2458
2459    // Now we should have the closing ']'
2460    E = Parser.getTok().getLoc();
2461    if (Parser.getTok().isNot(AsmToken::RBrac))
2462      return Error(E, "']' expected");
2463    Parser.Lex(); // Eat right bracket token.
2464
2465    // Don't worry about range checking the value here. That's handled by
2466    // the is*() predicates.
2467    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2468                                             ARM_AM::no_shift, 0, false, S,E));
2469
2470    // If there's a pre-indexing writeback marker, '!', just add it as a token
2471    // operand.
2472    if (Parser.getTok().is(AsmToken::Exclaim)) {
2473      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2474      Parser.Lex(); // Eat the '!'.
2475    }
2476
2477    return false;
2478  }
2479
2480  // The register offset is optionally preceded by a '+' or '-'
2481  bool isNegative = false;
2482  if (Parser.getTok().is(AsmToken::Minus)) {
2483    isNegative = true;
2484    Parser.Lex(); // Eat the '-'.
2485  } else if (Parser.getTok().is(AsmToken::Plus)) {
2486    // Nothing to do.
2487    Parser.Lex(); // Eat the '+'.
2488  }
2489
2490  E = Parser.getTok().getLoc();
2491  int OffsetRegNum = tryParseRegister();
2492  if (OffsetRegNum == -1)
2493    return Error(E, "register expected");
2494
2495  // If there's a shift operator, handle it.
2496  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2497  unsigned ShiftImm = 0;
2498  if (Parser.getTok().is(AsmToken::Comma)) {
2499    Parser.Lex(); // Eat the ','.
2500    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2501      return true;
2502  }
2503
2504  // Now we should have the closing ']'
2505  E = Parser.getTok().getLoc();
2506  if (Parser.getTok().isNot(AsmToken::RBrac))
2507    return Error(E, "']' expected");
2508  Parser.Lex(); // Eat right bracket token.
2509
2510  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2511                                           ShiftType, ShiftImm, isNegative,
2512                                           S, E));
2513
2514  // If there's a pre-indexing writeback marker, '!', just add it as a token
2515  // operand.
2516  if (Parser.getTok().is(AsmToken::Exclaim)) {
2517    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2518    Parser.Lex(); // Eat the '!'.
2519  }
2520
2521  return false;
2522}
2523
2524/// parseMemRegOffsetShift - one of these two:
2525///   ( lsl | lsr | asr | ror ) , # shift_amount
2526///   rrx
2527/// return true if it parses a shift otherwise it returns false.
2528bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2529                                          unsigned &Amount) {
2530  SMLoc Loc = Parser.getTok().getLoc();
2531  const AsmToken &Tok = Parser.getTok();
2532  if (Tok.isNot(AsmToken::Identifier))
2533    return true;
2534  StringRef ShiftName = Tok.getString();
2535  if (ShiftName == "lsl" || ShiftName == "LSL")
2536    St = ARM_AM::lsl;
2537  else if (ShiftName == "lsr" || ShiftName == "LSR")
2538    St = ARM_AM::lsr;
2539  else if (ShiftName == "asr" || ShiftName == "ASR")
2540    St = ARM_AM::asr;
2541  else if (ShiftName == "ror" || ShiftName == "ROR")
2542    St = ARM_AM::ror;
2543  else if (ShiftName == "rrx" || ShiftName == "RRX")
2544    St = ARM_AM::rrx;
2545  else
2546    return Error(Loc, "illegal shift operator");
2547  Parser.Lex(); // Eat shift type token.
2548
2549  // rrx stands alone.
2550  Amount = 0;
2551  if (St != ARM_AM::rrx) {
2552    Loc = Parser.getTok().getLoc();
2553    // A '#' and a shift amount.
2554    const AsmToken &HashTok = Parser.getTok();
2555    if (HashTok.isNot(AsmToken::Hash))
2556      return Error(HashTok.getLoc(), "'#' expected");
2557    Parser.Lex(); // Eat hash token.
2558
2559    const MCExpr *Expr;
2560    if (getParser().ParseExpression(Expr))
2561      return true;
2562    // Range check the immediate.
2563    // lsl, ror: 0 <= imm <= 31
2564    // lsr, asr: 0 <= imm <= 32
2565    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2566    if (!CE)
2567      return Error(Loc, "shift amount must be an immediate");
2568    int64_t Imm = CE->getValue();
2569    if (Imm < 0 ||
2570        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2571        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2572      return Error(Loc, "immediate shift value out of range");
2573    Amount = Imm;
2574  }
2575
2576  return false;
2577}
2578
2579/// Parse a arm instruction operand.  For now this parses the operand regardless
2580/// of the mnemonic.
2581bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2582                                StringRef Mnemonic) {
2583  SMLoc S, E;
2584
2585  // Check if the current operand has a custom associated parser, if so, try to
2586  // custom parse the operand, or fallback to the general approach.
2587  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2588  if (ResTy == MatchOperand_Success)
2589    return false;
2590  // If there wasn't a custom match, try the generic matcher below. Otherwise,
2591  // there was a match, but an error occurred, in which case, just return that
2592  // the operand parsing failed.
2593  if (ResTy == MatchOperand_ParseFail)
2594    return true;
2595
2596  switch (getLexer().getKind()) {
2597  default:
2598    Error(Parser.getTok().getLoc(), "unexpected token in operand");
2599    return true;
2600  case AsmToken::Identifier: {
2601    if (!tryParseRegisterWithWriteBack(Operands))
2602      return false;
2603    int Res = tryParseShiftRegister(Operands);
2604    if (Res == 0) // success
2605      return false;
2606    else if (Res == -1) // irrecoverable error
2607      return true;
2608
2609    // Fall though for the Identifier case that is not a register or a
2610    // special name.
2611  }
2612  case AsmToken::Integer: // things like 1f and 2b as a branch targets
2613  case AsmToken::Dot: {   // . as a branch target
2614    // This was not a register so parse other operands that start with an
2615    // identifier (like labels) as expressions and create them as immediates.
2616    const MCExpr *IdVal;
2617    S = Parser.getTok().getLoc();
2618    if (getParser().ParseExpression(IdVal))
2619      return true;
2620    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2621    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2622    return false;
2623  }
2624  case AsmToken::LBrac:
2625    return parseMemory(Operands);
2626  case AsmToken::LCurly:
2627    return parseRegisterList(Operands);
2628  case AsmToken::Hash:
2629    // #42 -> immediate.
2630    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2631    S = Parser.getTok().getLoc();
2632    Parser.Lex();
2633    const MCExpr *ImmVal;
2634    if (getParser().ParseExpression(ImmVal))
2635      return true;
2636    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2637    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2638    return false;
2639  case AsmToken::Colon: {
2640    // ":lower16:" and ":upper16:" expression prefixes
2641    // FIXME: Check it's an expression prefix,
2642    // e.g. (FOO - :lower16:BAR) isn't legal.
2643    ARMMCExpr::VariantKind RefKind;
2644    if (parsePrefix(RefKind))
2645      return true;
2646
2647    const MCExpr *SubExprVal;
2648    if (getParser().ParseExpression(SubExprVal))
2649      return true;
2650
2651    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2652                                                   getContext());
2653    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2654    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2655    return false;
2656  }
2657  }
2658}
2659
2660// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2661//  :lower16: and :upper16:.
2662bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2663  RefKind = ARMMCExpr::VK_ARM_None;
2664
2665  // :lower16: and :upper16: modifiers
2666  assert(getLexer().is(AsmToken::Colon) && "expected a :");
2667  Parser.Lex(); // Eat ':'
2668
2669  if (getLexer().isNot(AsmToken::Identifier)) {
2670    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2671    return true;
2672  }
2673
2674  StringRef IDVal = Parser.getTok().getIdentifier();
2675  if (IDVal == "lower16") {
2676    RefKind = ARMMCExpr::VK_ARM_LO16;
2677  } else if (IDVal == "upper16") {
2678    RefKind = ARMMCExpr::VK_ARM_HI16;
2679  } else {
2680    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2681    return true;
2682  }
2683  Parser.Lex();
2684
2685  if (getLexer().isNot(AsmToken::Colon)) {
2686    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2687    return true;
2688  }
2689  Parser.Lex(); // Eat the last ':'
2690  return false;
2691}
2692
2693const MCExpr *
2694ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2695                                MCSymbolRefExpr::VariantKind Variant) {
2696  // Recurse over the given expression, rebuilding it to apply the given variant
2697  // to the leftmost symbol.
2698  if (Variant == MCSymbolRefExpr::VK_None)
2699    return E;
2700
2701  switch (E->getKind()) {
2702  case MCExpr::Target:
2703    llvm_unreachable("Can't handle target expr yet");
2704  case MCExpr::Constant:
2705    llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2706
2707  case MCExpr::SymbolRef: {
2708    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2709
2710    if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2711      return 0;
2712
2713    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2714  }
2715
2716  case MCExpr::Unary:
2717    llvm_unreachable("Can't handle unary expressions yet");
2718
2719  case MCExpr::Binary: {
2720    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2721    const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2722    const MCExpr *RHS = BE->getRHS();
2723    if (!LHS)
2724      return 0;
2725
2726    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2727  }
2728  }
2729
2730  assert(0 && "Invalid expression kind!");
2731  return 0;
2732}
2733
2734/// \brief Given a mnemonic, split out possible predication code and carry
2735/// setting letters to form a canonical mnemonic and flags.
2736//
2737// FIXME: Would be nice to autogen this.
2738StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2739                                      unsigned &PredicationCode,
2740                                      bool &CarrySetting,
2741                                      unsigned &ProcessorIMod) {
2742  PredicationCode = ARMCC::AL;
2743  CarrySetting = false;
2744  ProcessorIMod = 0;
2745
2746  // Ignore some mnemonics we know aren't predicated forms.
2747  //
2748  // FIXME: Would be nice to autogen this.
2749  if ((Mnemonic == "movs" && isThumb()) ||
2750      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
2751      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
2752      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
2753      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
2754      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
2755      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
2756      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2757    return Mnemonic;
2758
2759  // First, split out any predication code. Ignore mnemonics we know aren't
2760  // predicated but do have a carry-set and so weren't caught above.
2761  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2762      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2763      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls") {
2764    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2765      .Case("eq", ARMCC::EQ)
2766      .Case("ne", ARMCC::NE)
2767      .Case("hs", ARMCC::HS)
2768      .Case("cs", ARMCC::HS)
2769      .Case("lo", ARMCC::LO)
2770      .Case("cc", ARMCC::LO)
2771      .Case("mi", ARMCC::MI)
2772      .Case("pl", ARMCC::PL)
2773      .Case("vs", ARMCC::VS)
2774      .Case("vc", ARMCC::VC)
2775      .Case("hi", ARMCC::HI)
2776      .Case("ls", ARMCC::LS)
2777      .Case("ge", ARMCC::GE)
2778      .Case("lt", ARMCC::LT)
2779      .Case("gt", ARMCC::GT)
2780      .Case("le", ARMCC::LE)
2781      .Case("al", ARMCC::AL)
2782      .Default(~0U);
2783    if (CC != ~0U) {
2784      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2785      PredicationCode = CC;
2786    }
2787  }
2788
2789  // Next, determine if we have a carry setting bit. We explicitly ignore all
2790  // the instructions we know end in 's'.
2791  if (Mnemonic.endswith("s") &&
2792      !(Mnemonic == "cps" || Mnemonic == "mls" ||
2793        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2794        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2795        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2796        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
2797        (Mnemonic == "movs" && isThumb()))) {
2798    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2799    CarrySetting = true;
2800  }
2801
2802  // The "cps" instruction can have a interrupt mode operand which is glued into
2803  // the mnemonic. Check if this is the case, split it and parse the imod op
2804  if (Mnemonic.startswith("cps")) {
2805    // Split out any imod code.
2806    unsigned IMod =
2807      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2808      .Case("ie", ARM_PROC::IE)
2809      .Case("id", ARM_PROC::ID)
2810      .Default(~0U);
2811    if (IMod != ~0U) {
2812      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2813      ProcessorIMod = IMod;
2814    }
2815  }
2816
2817  return Mnemonic;
2818}
2819
2820/// \brief Given a canonical mnemonic, determine if the instruction ever allows
2821/// inclusion of carry set or predication code operands.
2822//
2823// FIXME: It would be nice to autogen this.
2824void ARMAsmParser::
2825getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2826                      bool &CanAcceptPredicationCode) {
2827  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2828      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2829      Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2830      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2831      Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2832      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2833      Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2834      Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" ||
2835      // FIXME: We need a better way. This really confused Thumb2
2836      // parsing for 'mov'.
2837      (Mnemonic == "mov" && !isThumbOne())) {
2838    CanAcceptCarrySet = true;
2839  } else {
2840    CanAcceptCarrySet = false;
2841  }
2842
2843  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2844      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2845      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2846      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2847      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2848      Mnemonic == "setend" ||
2849      ((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) ||
2850      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs"))
2851        && !isThumb()) ||
2852      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2853    CanAcceptPredicationCode = false;
2854  } else {
2855    CanAcceptPredicationCode = true;
2856  }
2857
2858  if (isThumb())
2859    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2860        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2861      CanAcceptPredicationCode = false;
2862}
2863
2864bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
2865                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2866
2867  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2868  // another does not. Specifically, the MOVW instruction does not. So we
2869  // special case it here and remove the defaulted (non-setting) cc_out
2870  // operand if that's the instruction we're trying to match.
2871  //
2872  // We do this as post-processing of the explicit operands rather than just
2873  // conditionally adding the cc_out in the first place because we need
2874  // to check the type of the parsed immediate operand.
2875  if (Mnemonic == "mov" && Operands.size() > 4 &&
2876      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
2877      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
2878      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2879    return true;
2880
2881  // Register-register 'add' for thumb does not have a cc_out operand
2882  // when there are only two register operands.
2883  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
2884      static_cast<ARMOperand*>(Operands[3])->isReg() &&
2885      static_cast<ARMOperand*>(Operands[4])->isReg() &&
2886      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2887    return true;
2888
2889  return false;
2890}
2891
2892/// Parse an arm instruction mnemonic followed by its operands.
2893bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2894                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2895  // Create the leading tokens for the mnemonic, split by '.' characters.
2896  size_t Start = 0, Next = Name.find('.');
2897  StringRef Mnemonic = Name.slice(Start, Next);
2898
2899  // Split out the predication code and carry setting flag from the mnemonic.
2900  unsigned PredicationCode;
2901  unsigned ProcessorIMod;
2902  bool CarrySetting;
2903  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
2904                           ProcessorIMod);
2905
2906  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
2907
2908  // FIXME: This is all a pretty gross hack. We should automatically handle
2909  // optional operands like this via tblgen.
2910
2911  // Next, add the CCOut and ConditionCode operands, if needed.
2912  //
2913  // For mnemonics which can ever incorporate a carry setting bit or predication
2914  // code, our matching model involves us always generating CCOut and
2915  // ConditionCode operands to match the mnemonic "as written" and then we let
2916  // the matcher deal with finding the right instruction or generating an
2917  // appropriate error.
2918  bool CanAcceptCarrySet, CanAcceptPredicationCode;
2919  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
2920
2921  // If we had a carry-set on an instruction that can't do that, issue an
2922  // error.
2923  if (!CanAcceptCarrySet && CarrySetting) {
2924    Parser.EatToEndOfStatement();
2925    return Error(NameLoc, "instruction '" + Mnemonic +
2926                 "' can not set flags, but 's' suffix specified");
2927  }
2928  // If we had a predication code on an instruction that can't do that, issue an
2929  // error.
2930  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
2931    Parser.EatToEndOfStatement();
2932    return Error(NameLoc, "instruction '" + Mnemonic +
2933                 "' is not predicable, but condition code specified");
2934  }
2935
2936  // Add the carry setting operand, if necessary.
2937  //
2938  // FIXME: It would be awesome if we could somehow invent a location such that
2939  // match errors on this operand would print a nice diagnostic about how the
2940  // 's' character in the mnemonic resulted in a CCOut operand.
2941  if (CanAcceptCarrySet)
2942    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
2943                                               NameLoc));
2944
2945  // Add the predication code operand, if necessary.
2946  if (CanAcceptPredicationCode) {
2947    Operands.push_back(ARMOperand::CreateCondCode(
2948                         ARMCC::CondCodes(PredicationCode), NameLoc));
2949  }
2950
2951  // Add the processor imod operand, if necessary.
2952  if (ProcessorIMod) {
2953    Operands.push_back(ARMOperand::CreateImm(
2954          MCConstantExpr::Create(ProcessorIMod, getContext()),
2955                                 NameLoc, NameLoc));
2956  } else {
2957    // This mnemonic can't ever accept a imod, but the user wrote
2958    // one (or misspelled another mnemonic).
2959
2960    // FIXME: Issue a nice error.
2961  }
2962
2963  // Add the remaining tokens in the mnemonic.
2964  while (Next != StringRef::npos) {
2965    Start = Next;
2966    Next = Name.find('.', Start + 1);
2967    StringRef ExtraToken = Name.slice(Start, Next);
2968
2969    Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
2970  }
2971
2972  // Read the remaining operands.
2973  if (getLexer().isNot(AsmToken::EndOfStatement)) {
2974    // Read the first operand.
2975    if (parseOperand(Operands, Mnemonic)) {
2976      Parser.EatToEndOfStatement();
2977      return true;
2978    }
2979
2980    while (getLexer().is(AsmToken::Comma)) {
2981      Parser.Lex();  // Eat the comma.
2982
2983      // Parse and remember the operand.
2984      if (parseOperand(Operands, Mnemonic)) {
2985        Parser.EatToEndOfStatement();
2986        return true;
2987      }
2988    }
2989  }
2990
2991  if (getLexer().isNot(AsmToken::EndOfStatement)) {
2992    Parser.EatToEndOfStatement();
2993    return TokError("unexpected token in argument list");
2994  }
2995
2996  Parser.Lex(); // Consume the EndOfStatement
2997
2998  // Some instructions, mostly Thumb, have forms for the same mnemonic that
2999  // do and don't have a cc_out optional-def operand. With some spot-checks
3000  // of the operand list, we can figure out which variant we're trying to
3001  // parse and adjust accordingly before actually matching. Reason number
3002  // #317 the table driven matcher doesn't fit well with the ARM instruction
3003  // set.
3004  if (shouldOmitCCOutOperand(Mnemonic, Operands)) {
3005    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3006    Operands.erase(Operands.begin() + 1);
3007    delete Op;
3008  }
3009
3010  // ARM mode 'blx' need special handling, as the register operand version
3011  // is predicable, but the label operand version is not. So, we can't rely
3012  // on the Mnemonic based checking to correctly figure out when to put
3013  // a CondCode operand in the list. If we're trying to match the label
3014  // version, remove the CondCode operand here.
3015  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
3016      static_cast<ARMOperand*>(Operands[2])->isImm()) {
3017    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3018    Operands.erase(Operands.begin() + 1);
3019    delete Op;
3020  }
3021
3022  // The vector-compare-to-zero instructions have a literal token "#0" at
3023  // the end that comes to here as an immediate operand. Convert it to a
3024  // token to play nicely with the matcher.
3025  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
3026      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
3027      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3028    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3029    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3030    if (CE && CE->getValue() == 0) {
3031      Operands.erase(Operands.begin() + 5);
3032      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3033      delete Op;
3034    }
3035  }
3036  return false;
3037}
3038
3039// Validate context-sensitive operand constraints.
3040// FIXME: We would really like to be able to tablegen'erate this.
3041bool ARMAsmParser::
3042validateInstruction(MCInst &Inst,
3043                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3044  switch (Inst.getOpcode()) {
3045  case ARM::LDRD:
3046  case ARM::LDRD_PRE:
3047  case ARM::LDRD_POST:
3048  case ARM::LDREXD: {
3049    // Rt2 must be Rt + 1.
3050    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3051    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3052    if (Rt2 != Rt + 1)
3053      return Error(Operands[3]->getStartLoc(),
3054                   "destination operands must be sequential");
3055    return false;
3056  }
3057  case ARM::STRD: {
3058    // Rt2 must be Rt + 1.
3059    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3060    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3061    if (Rt2 != Rt + 1)
3062      return Error(Operands[3]->getStartLoc(),
3063                   "source operands must be sequential");
3064    return false;
3065  }
3066  case ARM::STRD_PRE:
3067  case ARM::STRD_POST:
3068  case ARM::STREXD: {
3069    // Rt2 must be Rt + 1.
3070    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3071    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3072    if (Rt2 != Rt + 1)
3073      return Error(Operands[3]->getStartLoc(),
3074                   "source operands must be sequential");
3075    return false;
3076  }
3077  case ARM::SBFX:
3078  case ARM::UBFX: {
3079    // width must be in range [1, 32-lsb]
3080    unsigned lsb = Inst.getOperand(2).getImm();
3081    unsigned widthm1 = Inst.getOperand(3).getImm();
3082    if (widthm1 >= 32 - lsb)
3083      return Error(Operands[5]->getStartLoc(),
3084                   "bitfield width must be in range [1,32-lsb]");
3085    return false;
3086  }
3087  case ARM::tLDMIA: {
3088    // Thumb LDM instructions are writeback iff the base register is not
3089    // in the register list.
3090    unsigned Rn = Inst.getOperand(0).getReg();
3091    bool doesWriteback = true;
3092    for (unsigned i = 3; i < Inst.getNumOperands(); ++i) {
3093      unsigned Reg = Inst.getOperand(i).getReg();
3094      if (Reg == Rn)
3095        doesWriteback = false;
3096      // Anything other than a low register isn't legal here.
3097      if (!isARMLowRegister(Reg))
3098        return Error(Operands[4]->getStartLoc(),
3099                     "registers must be in range r0-r7");
3100    }
3101    // If we should have writeback, then there should be a '!' token.
3102    if (doesWriteback &&
3103        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
3104         static_cast<ARMOperand*>(Operands[3])->getToken() != "!"))
3105      return Error(Operands[2]->getStartLoc(),
3106                   "writeback operator '!' expected");
3107
3108    break;
3109  }
3110  }
3111
3112  return false;
3113}
3114
3115void ARMAsmParser::
3116processInstruction(MCInst &Inst,
3117                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3118  switch (Inst.getOpcode()) {
3119  case ARM::LDMIA_UPD:
3120    // If this is a load of a single register via a 'pop', then we should use
3121    // a post-indexed LDR instruction instead, per the ARM ARM.
3122    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3123        Inst.getNumOperands() == 5) {
3124      MCInst TmpInst;
3125      TmpInst.setOpcode(ARM::LDR_POST_IMM);
3126      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3127      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3128      TmpInst.addOperand(Inst.getOperand(1)); // Rn
3129      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
3130      TmpInst.addOperand(MCOperand::CreateImm(4));
3131      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3132      TmpInst.addOperand(Inst.getOperand(3));
3133      Inst = TmpInst;
3134    }
3135    break;
3136  case ARM::STMDB_UPD:
3137    // If this is a store of a single register via a 'push', then we should use
3138    // a pre-indexed STR instruction instead, per the ARM ARM.
3139    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3140        Inst.getNumOperands() == 5) {
3141      MCInst TmpInst;
3142      TmpInst.setOpcode(ARM::STR_PRE_IMM);
3143      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3144      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3145      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3146      TmpInst.addOperand(MCOperand::CreateImm(-4));
3147      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3148      TmpInst.addOperand(Inst.getOperand(3));
3149      Inst = TmpInst;
3150    }
3151    break;
3152  case ARM::tADDi8:
3153    // If the immediate is in the range 0-7, we really wanted tADDi3.
3154    if (Inst.getOperand(3).getImm() < 8)
3155      Inst.setOpcode(ARM::tADDi3);
3156    break;
3157  case ARM::tBcc:
3158    // If the conditional is AL, we really want tB.
3159    if (Inst.getOperand(1).getImm() == ARMCC::AL)
3160      Inst.setOpcode(ARM::tB);
3161    break;
3162  }
3163}
3164
3165// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3166// the ARMInsts array) instead. Getting that here requires awkward
3167// API changes, though. Better way?
3168namespace llvm {
3169extern MCInstrDesc ARMInsts[];
3170}
3171static MCInstrDesc &getInstDesc(unsigned Opcode) {
3172  return ARMInsts[Opcode];
3173}
3174
3175unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3176  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3177  // suffix depending on whether they're in an IT block or not.
3178  unsigned Opc = Inst.getOpcode();
3179  MCInstrDesc &MCID = getInstDesc(Opc);
3180  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3181    assert(MCID.hasOptionalDef() &&
3182           "optionally flag setting instruction missing optional def operand");
3183    assert(MCID.NumOperands == Inst.getNumOperands() &&
3184           "operand count mismatch!");
3185    // Find the optional-def operand (cc_out).
3186    unsigned OpNo;
3187    for (OpNo = 0;
3188         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3189         ++OpNo)
3190      ;
3191    // If we're parsing Thumb1, reject it completely.
3192    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3193      return Match_MnemonicFail;
3194    // If we're parsing Thumb2, which form is legal depends on whether we're
3195    // in an IT block.
3196    // FIXME: We don't yet do IT blocks, so just always consider it to be
3197    // that we aren't in one until we do.
3198    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3199      return Match_RequiresITBlock;
3200  }
3201  // Some high-register supporting Thumb1 encodings only allow both registers
3202  // to be from r0-r7 when in Thumb2.
3203  else if (Opc == ARM::tADDhirr && isThumbOne() &&
3204           isARMLowRegister(Inst.getOperand(1).getReg()) &&
3205           isARMLowRegister(Inst.getOperand(2).getReg()))
3206    return Match_RequiresThumb2;
3207  // Others only require ARMv6 or later.
3208  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
3209           isARMLowRegister(Inst.getOperand(0).getReg()) &&
3210           isARMLowRegister(Inst.getOperand(1).getReg()))
3211    return Match_RequiresV6;
3212  return Match_Success;
3213}
3214
3215bool ARMAsmParser::
3216MatchAndEmitInstruction(SMLoc IDLoc,
3217                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3218                        MCStreamer &Out) {
3219  MCInst Inst;
3220  unsigned ErrorInfo;
3221  unsigned MatchResult;
3222  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3223  switch (MatchResult) {
3224  default: break;
3225  case Match_Success:
3226    // Context sensitive operand constraints aren't handled by the matcher,
3227    // so check them here.
3228    if (validateInstruction(Inst, Operands))
3229      return true;
3230
3231    // Some instructions need post-processing to, for example, tweak which
3232    // encoding is selected.
3233    processInstruction(Inst, Operands);
3234
3235    Out.EmitInstruction(Inst);
3236    return false;
3237  case Match_MissingFeature:
3238    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3239    return true;
3240  case Match_InvalidOperand: {
3241    SMLoc ErrorLoc = IDLoc;
3242    if (ErrorInfo != ~0U) {
3243      if (ErrorInfo >= Operands.size())
3244        return Error(IDLoc, "too few operands for instruction");
3245
3246      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3247      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3248    }
3249
3250    return Error(ErrorLoc, "invalid operand for instruction");
3251  }
3252  case Match_MnemonicFail:
3253    return Error(IDLoc, "invalid instruction");
3254  case Match_ConversionFail:
3255    // The converter function will have already emited a diagnostic.
3256    return true;
3257  case Match_RequiresITBlock:
3258    return Error(IDLoc, "instruction only valid inside IT block");
3259  case Match_RequiresV6:
3260    return Error(IDLoc, "instruction variant requires ARMv6 or later");
3261  case Match_RequiresThumb2:
3262    return Error(IDLoc, "instruction variant requires Thumb2");
3263  }
3264
3265  llvm_unreachable("Implement any new match types added!");
3266  return true;
3267}
3268
3269/// parseDirective parses the arm specific directives
3270bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3271  StringRef IDVal = DirectiveID.getIdentifier();
3272  if (IDVal == ".word")
3273    return parseDirectiveWord(4, DirectiveID.getLoc());
3274  else if (IDVal == ".thumb")
3275    return parseDirectiveThumb(DirectiveID.getLoc());
3276  else if (IDVal == ".thumb_func")
3277    return parseDirectiveThumbFunc(DirectiveID.getLoc());
3278  else if (IDVal == ".code")
3279    return parseDirectiveCode(DirectiveID.getLoc());
3280  else if (IDVal == ".syntax")
3281    return parseDirectiveSyntax(DirectiveID.getLoc());
3282  return true;
3283}
3284
3285/// parseDirectiveWord
3286///  ::= .word [ expression (, expression)* ]
3287bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3288  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3289    for (;;) {
3290      const MCExpr *Value;
3291      if (getParser().ParseExpression(Value))
3292        return true;
3293
3294      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3295
3296      if (getLexer().is(AsmToken::EndOfStatement))
3297        break;
3298
3299      // FIXME: Improve diagnostic.
3300      if (getLexer().isNot(AsmToken::Comma))
3301        return Error(L, "unexpected token in directive");
3302      Parser.Lex();
3303    }
3304  }
3305
3306  Parser.Lex();
3307  return false;
3308}
3309
3310/// parseDirectiveThumb
3311///  ::= .thumb
3312bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3313  if (getLexer().isNot(AsmToken::EndOfStatement))
3314    return Error(L, "unexpected token in directive");
3315  Parser.Lex();
3316
3317  // TODO: set thumb mode
3318  // TODO: tell the MC streamer the mode
3319  // getParser().getStreamer().Emit???();
3320  return false;
3321}
3322
3323/// parseDirectiveThumbFunc
3324///  ::= .thumbfunc symbol_name
3325bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3326  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3327  bool isMachO = MAI.hasSubsectionsViaSymbols();
3328  StringRef Name;
3329
3330  // Darwin asm has function name after .thumb_func direction
3331  // ELF doesn't
3332  if (isMachO) {
3333    const AsmToken &Tok = Parser.getTok();
3334    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3335      return Error(L, "unexpected token in .thumb_func directive");
3336    Name = Tok.getString();
3337    Parser.Lex(); // Consume the identifier token.
3338  }
3339
3340  if (getLexer().isNot(AsmToken::EndOfStatement))
3341    return Error(L, "unexpected token in directive");
3342  Parser.Lex();
3343
3344  // FIXME: assuming function name will be the line following .thumb_func
3345  if (!isMachO) {
3346    Name = Parser.getTok().getString();
3347  }
3348
3349  // Mark symbol as a thumb symbol.
3350  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3351  getParser().getStreamer().EmitThumbFunc(Func);
3352  return false;
3353}
3354
3355/// parseDirectiveSyntax
3356///  ::= .syntax unified | divided
3357bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3358  const AsmToken &Tok = Parser.getTok();
3359  if (Tok.isNot(AsmToken::Identifier))
3360    return Error(L, "unexpected token in .syntax directive");
3361  StringRef Mode = Tok.getString();
3362  if (Mode == "unified" || Mode == "UNIFIED")
3363    Parser.Lex();
3364  else if (Mode == "divided" || Mode == "DIVIDED")
3365    return Error(L, "'.syntax divided' arm asssembly not supported");
3366  else
3367    return Error(L, "unrecognized syntax mode in .syntax directive");
3368
3369  if (getLexer().isNot(AsmToken::EndOfStatement))
3370    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3371  Parser.Lex();
3372
3373  // TODO tell the MC streamer the mode
3374  // getParser().getStreamer().Emit???();
3375  return false;
3376}
3377
3378/// parseDirectiveCode
3379///  ::= .code 16 | 32
3380bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3381  const AsmToken &Tok = Parser.getTok();
3382  if (Tok.isNot(AsmToken::Integer))
3383    return Error(L, "unexpected token in .code directive");
3384  int64_t Val = Parser.getTok().getIntVal();
3385  if (Val == 16)
3386    Parser.Lex();
3387  else if (Val == 32)
3388    Parser.Lex();
3389  else
3390    return Error(L, "invalid operand to .code directive");
3391
3392  if (getLexer().isNot(AsmToken::EndOfStatement))
3393    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3394  Parser.Lex();
3395
3396  if (Val == 16) {
3397    if (!isThumb()) {
3398      SwitchMode();
3399      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3400    }
3401  } else {
3402    if (isThumb()) {
3403      SwitchMode();
3404      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3405    }
3406  }
3407
3408  return false;
3409}
3410
3411extern "C" void LLVMInitializeARMAsmLexer();
3412
3413/// Force static initialization.
3414extern "C" void LLVMInitializeARMAsmParser() {
3415  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3416  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3417  LLVMInitializeARMAsmLexer();
3418}
3419
3420#define GET_REGISTER_MATCHER
3421#define GET_MATCHER_IMPLEMENTATION
3422#include "ARMGenAsmMatcher.inc"
3423