ARMAsmParser.cpp revision 3483acabf012b847b13b969ebd9ce5c4d16d9eb7 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "ARM.h"
11#include "ARMSubtarget.h"
12#include "llvm/MC/MCParser/MCAsmLexer.h"
13#include "llvm/MC/MCParser/MCAsmParser.h"
14#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
15#include "llvm/MC/MCStreamer.h"
16#include "llvm/MC/MCExpr.h"
17#include "llvm/MC/MCInst.h"
18#include "llvm/Target/TargetRegistry.h"
19#include "llvm/Target/TargetAsmParser.h"
20#include "llvm/Support/Compiler.h"
21#include "llvm/Support/SourceMgr.h"
22#include "llvm/ADT/OwningPtr.h"
23#include "llvm/ADT/SmallVector.h"
24#include "llvm/ADT/Twine.h"
25using namespace llvm;
26
27namespace {
28struct ARMOperand;
29
30// The shift types for register controlled shifts in arm memory addressing
31enum ShiftType {
32  Lsl,
33  Lsr,
34  Asr,
35  Ror,
36  Rrx
37};
38
39class ARMAsmParser : public TargetAsmParser {
40  MCAsmParser &Parser;
41  TargetMachine &TM;
42
43private:
44  MCAsmParser &getParser() const { return Parser; }
45
46  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
47
48  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
49
50  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
51
52  bool MaybeParseRegister(OwningPtr<ARMOperand> &Op, bool ParseWriteBack);
53
54  bool ParseRegisterList(OwningPtr<ARMOperand> &Op);
55
56  bool ParseMemory(OwningPtr<ARMOperand> &Op);
57
58  bool ParseMemoryOffsetReg(bool &Negative,
59                            bool &OffsetRegShifted,
60                            enum ShiftType &ShiftType,
61                            const MCExpr *&ShiftAmount,
62                            const MCExpr *&Offset,
63                            bool &OffsetIsReg,
64                            int &OffsetRegNum,
65                            SMLoc &E);
66
67  bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
68
69  bool ParseOperand(OwningPtr<ARMOperand> &Op);
70
71  bool ParseDirectiveWord(unsigned Size, SMLoc L);
72
73  bool ParseDirectiveThumb(SMLoc L);
74
75  bool ParseDirectiveThumbFunc(SMLoc L);
76
77  bool ParseDirectiveCode(SMLoc L);
78
79  bool ParseDirectiveSyntax(SMLoc L);
80
81  /// @name Auto-generated Match Functions
82  /// {
83
84  unsigned ComputeAvailableFeatures(const ARMSubtarget *Subtarget) const;
85
86  bool MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
87                        MCInst &Inst);
88
89  /// }
90
91
92public:
93  ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
94    : TargetAsmParser(T), Parser(_Parser), TM(_TM) {}
95
96  virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
97                                SmallVectorImpl<MCParsedAsmOperand*> &Operands);
98
99  virtual bool ParseDirective(AsmToken DirectiveID);
100};
101
102/// ARMOperand - Instances of this class represent a parsed ARM machine
103/// instruction.
104struct ARMOperand : public MCParsedAsmOperand {
105private:
106  ARMOperand() {}
107public:
108  enum KindTy {
109    Token,
110    Register,
111    Immediate,
112    Memory
113  } Kind;
114
115  SMLoc StartLoc, EndLoc;
116
117  union {
118    struct {
119      const char *Data;
120      unsigned Length;
121    } Tok;
122
123    struct {
124      unsigned RegNum;
125      bool Writeback;
126    } Reg;
127
128    struct {
129      const MCExpr *Val;
130    } Imm;
131
132    // This is for all forms of ARM address expressions
133    struct {
134      unsigned BaseRegNum;
135      unsigned OffsetRegNum; // used when OffsetIsReg is true
136      const MCExpr *Offset; // used when OffsetIsReg is false
137      const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
138      enum ShiftType ShiftType;  // used when OffsetRegShifted is true
139      unsigned
140        OffsetRegShifted : 1, // only used when OffsetIsReg is true
141        Preindexed : 1,
142        Postindexed : 1,
143        OffsetIsReg : 1,
144        Negative : 1, // only used when OffsetIsReg is true
145        Writeback : 1;
146    } Mem;
147
148  };
149
150  ARMOperand(KindTy K, SMLoc S, SMLoc E)
151    : Kind(K), StartLoc(S), EndLoc(E) {}
152
153  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
154    Kind = o.Kind;
155    StartLoc = o.StartLoc;
156    EndLoc = o.EndLoc;
157    switch (Kind) {
158    case Token:
159    Tok = o.Tok;
160      break;
161    case Register:
162      Reg = o.Reg;
163      break;
164    case Immediate:
165      Imm = o.Imm;
166      break;
167    case Memory:
168      Mem = o.Mem;
169      break;
170    }
171  }
172
173  /// getStartLoc - Get the location of the first token of this operand.
174  SMLoc getStartLoc() const { return StartLoc; }
175  /// getEndLoc - Get the location of the last token of this operand.
176  SMLoc getEndLoc() const { return EndLoc; }
177
178  StringRef getToken() const {
179    assert(Kind == Token && "Invalid access!");
180    return StringRef(Tok.Data, Tok.Length);
181  }
182
183  unsigned getReg() const {
184    assert(Kind == Register && "Invalid access!");
185    return Reg.RegNum;
186  }
187
188  const MCExpr *getImm() const {
189    assert(Kind == Immediate && "Invalid access!");
190    return Imm.Val;
191  }
192
193  bool isImm() const { return Kind == Immediate; }
194
195  bool isReg() const { return Kind == Register; }
196
197  bool isToken() const {return Kind == Token; }
198
199  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
200    // Add as immediates when possible.
201    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
202      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
203    else
204      Inst.addOperand(MCOperand::CreateExpr(Expr));
205  }
206
207  void addRegOperands(MCInst &Inst, unsigned N) const {
208    assert(N == 1 && "Invalid number of operands!");
209    Inst.addOperand(MCOperand::CreateReg(getReg()));
210  }
211
212  void addImmOperands(MCInst &Inst, unsigned N) const {
213    assert(N == 1 && "Invalid number of operands!");
214    addExpr(Inst, getImm());
215  }
216
217  static void CreateToken(OwningPtr<ARMOperand> &Op, StringRef Str,
218                          SMLoc S) {
219    Op.reset(new ARMOperand);
220    Op->Kind = Token;
221    Op->Tok.Data = Str.data();
222    Op->Tok.Length = Str.size();
223    Op->StartLoc = S;
224    Op->EndLoc = S;
225  }
226
227  static void CreateReg(OwningPtr<ARMOperand> &Op, unsigned RegNum,
228                        bool Writeback, SMLoc S, SMLoc E) {
229    Op.reset(new ARMOperand);
230    Op->Kind = Register;
231    Op->Reg.RegNum = RegNum;
232    Op->Reg.Writeback = Writeback;
233
234    Op->StartLoc = S;
235    Op->EndLoc = E;
236  }
237
238  static void CreateImm(OwningPtr<ARMOperand> &Op, const MCExpr *Val,
239                        SMLoc S, SMLoc E) {
240    Op.reset(new ARMOperand);
241    Op->Kind = Immediate;
242    Op->Imm.Val = Val;
243
244    Op->StartLoc = S;
245    Op->EndLoc = E;
246  }
247
248  static void CreateMem(OwningPtr<ARMOperand> &Op,
249                        unsigned BaseRegNum, bool OffsetIsReg,
250                        const MCExpr *Offset, unsigned OffsetRegNum,
251                        bool OffsetRegShifted, enum ShiftType ShiftType,
252                        const MCExpr *ShiftAmount, bool Preindexed,
253                        bool Postindexed, bool Negative, bool Writeback,
254                        SMLoc S, SMLoc E) {
255    Op.reset(new ARMOperand);
256    Op->Kind = Memory;
257    Op->Mem.BaseRegNum = BaseRegNum;
258    Op->Mem.OffsetIsReg = OffsetIsReg;
259    Op->Mem.Offset = Offset;
260    Op->Mem.OffsetRegNum = OffsetRegNum;
261    Op->Mem.OffsetRegShifted = OffsetRegShifted;
262    Op->Mem.ShiftType = ShiftType;
263    Op->Mem.ShiftAmount = ShiftAmount;
264    Op->Mem.Preindexed = Preindexed;
265    Op->Mem.Postindexed = Postindexed;
266    Op->Mem.Negative = Negative;
267    Op->Mem.Writeback = Writeback;
268
269    Op->StartLoc = S;
270    Op->EndLoc = E;
271  }
272};
273
274} // end anonymous namespace.
275
276
277/// @name Auto-generated Match Functions
278/// {
279
280static unsigned MatchRegisterName(StringRef Name);
281
282/// }
283
284/// Try to parse a register name.  The token must be an Identifier when called,
285/// and if it is a register name a Reg operand is created, the token is eaten
286/// and false is returned.  Else true is returned and no token is eaten.
287/// TODO this is likely to change to allow different register types and or to
288/// parse for a specific register type.
289bool ARMAsmParser::MaybeParseRegister
290  (OwningPtr<ARMOperand> &Op, bool ParseWriteBack) {
291  SMLoc S, E;
292  const AsmToken &Tok = Parser.getTok();
293  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
294
295  // FIXME: Validate register for the current architecture; we have to do
296  // validation later, so maybe there is no need for this here.
297  int RegNum;
298
299  RegNum = MatchRegisterName(Tok.getString());
300  if (RegNum == -1)
301    return true;
302
303  S = Tok.getLoc();
304
305  Parser.Lex(); // Eat identifier token.
306
307  E = Parser.getTok().getLoc();
308
309  bool Writeback = false;
310  if (ParseWriteBack) {
311    const AsmToken &ExclaimTok = Parser.getTok();
312    if (ExclaimTok.is(AsmToken::Exclaim)) {
313      E = ExclaimTok.getLoc();
314      Writeback = true;
315      Parser.Lex(); // Eat exclaim token
316    }
317  }
318
319  ARMOperand::CreateReg(Op, RegNum, Writeback, S, E);
320
321  return false;
322}
323
324/// Parse a register list, return false if successful else return true or an
325/// error.  The first token must be a '{' when called.
326bool ARMAsmParser::ParseRegisterList(OwningPtr<ARMOperand> &Op) {
327  SMLoc S, E;
328  assert(Parser.getTok().is(AsmToken::LCurly) &&
329         "Token is not an Left Curly Brace");
330  S = Parser.getTok().getLoc();
331  Parser.Lex(); // Eat left curly brace token.
332
333  const AsmToken &RegTok = Parser.getTok();
334  SMLoc RegLoc = RegTok.getLoc();
335  if (RegTok.isNot(AsmToken::Identifier))
336    return Error(RegLoc, "register expected");
337  int RegNum = MatchRegisterName(RegTok.getString());
338  if (RegNum == -1)
339    return Error(RegLoc, "register expected");
340  Parser.Lex(); // Eat identifier token.
341  unsigned RegList = 1 << RegNum;
342
343  int HighRegNum = RegNum;
344  // TODO ranges like "{Rn-Rm}"
345  while (Parser.getTok().is(AsmToken::Comma)) {
346    Parser.Lex(); // Eat comma token.
347
348    const AsmToken &RegTok = Parser.getTok();
349    SMLoc RegLoc = RegTok.getLoc();
350    if (RegTok.isNot(AsmToken::Identifier))
351      return Error(RegLoc, "register expected");
352    int RegNum = MatchRegisterName(RegTok.getString());
353    if (RegNum == -1)
354      return Error(RegLoc, "register expected");
355
356    if (RegList & (1 << RegNum))
357      Warning(RegLoc, "register duplicated in register list");
358    else if (RegNum <= HighRegNum)
359      Warning(RegLoc, "register not in ascending order in register list");
360    RegList |= 1 << RegNum;
361    HighRegNum = RegNum;
362
363    Parser.Lex(); // Eat identifier token.
364  }
365  const AsmToken &RCurlyTok = Parser.getTok();
366  if (RCurlyTok.isNot(AsmToken::RCurly))
367    return Error(RCurlyTok.getLoc(), "'}' expected");
368  E = RCurlyTok.getLoc();
369  Parser.Lex(); // Eat left curly brace token.
370
371  return false;
372}
373
374/// Parse an arm memory expression, return false if successful else return true
375/// or an error.  The first token must be a '[' when called.
376/// TODO Only preindexing and postindexing addressing are started, unindexed
377/// with option, etc are still to do.
378bool ARMAsmParser::ParseMemory(OwningPtr<ARMOperand> &Op) {
379  SMLoc S, E;
380  assert(Parser.getTok().is(AsmToken::LBrac) &&
381         "Token is not an Left Bracket");
382  S = Parser.getTok().getLoc();
383  Parser.Lex(); // Eat left bracket token.
384
385  const AsmToken &BaseRegTok = Parser.getTok();
386  if (BaseRegTok.isNot(AsmToken::Identifier))
387    return Error(BaseRegTok.getLoc(), "register expected");
388  if (MaybeParseRegister(Op, false))
389    return Error(BaseRegTok.getLoc(), "register expected");
390  int BaseRegNum = Op->getReg();
391
392  bool Preindexed = false;
393  bool Postindexed = false;
394  bool OffsetIsReg = false;
395  bool Negative = false;
396  bool Writeback = false;
397
398  // First look for preindexed address forms, that is after the "[Rn" we now
399  // have to see if the next token is a comma.
400  const AsmToken &Tok = Parser.getTok();
401  if (Tok.is(AsmToken::Comma)) {
402    Preindexed = true;
403    Parser.Lex(); // Eat comma token.
404    int OffsetRegNum;
405    bool OffsetRegShifted;
406    enum ShiftType ShiftType;
407    const MCExpr *ShiftAmount;
408    const MCExpr *Offset;
409    if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
410                            Offset, OffsetIsReg, OffsetRegNum, E))
411      return true;
412    const AsmToken &RBracTok = Parser.getTok();
413    if (RBracTok.isNot(AsmToken::RBrac))
414      return Error(RBracTok.getLoc(), "']' expected");
415    E = RBracTok.getLoc();
416    Parser.Lex(); // Eat right bracket token.
417
418    const AsmToken &ExclaimTok = Parser.getTok();
419    if (ExclaimTok.is(AsmToken::Exclaim)) {
420      E = ExclaimTok.getLoc();
421      Writeback = true;
422      Parser.Lex(); // Eat exclaim token
423    }
424    ARMOperand::CreateMem(Op, BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
425                          OffsetRegShifted, ShiftType, ShiftAmount,
426                          Preindexed, Postindexed, Negative, Writeback, S, E);
427    return false;
428  }
429  // The "[Rn" we have so far was not followed by a comma.
430  else if (Tok.is(AsmToken::RBrac)) {
431    // This is a post indexing addressing forms, that is a ']' follows after
432    // the "[Rn".
433    Postindexed = true;
434    Writeback = true;
435    E = Tok.getLoc();
436    Parser.Lex(); // Eat right bracket token.
437
438    int OffsetRegNum = 0;
439    bool OffsetRegShifted = false;
440    enum ShiftType ShiftType;
441    const MCExpr *ShiftAmount;
442    const MCExpr *Offset;
443
444    const AsmToken &NextTok = Parser.getTok();
445    if (NextTok.isNot(AsmToken::EndOfStatement)) {
446      if (NextTok.isNot(AsmToken::Comma))
447        return Error(NextTok.getLoc(), "',' expected");
448      Parser.Lex(); // Eat comma token.
449      if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
450                              ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
451                              E))
452        return true;
453    }
454
455    ARMOperand::CreateMem(Op, BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
456                          OffsetRegShifted, ShiftType, ShiftAmount,
457                          Preindexed, Postindexed, Negative, Writeback, S, E);
458    return false;
459  }
460
461  return true;
462}
463
464/// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
465/// we will parse the following (were +/- means that a plus or minus is
466/// optional):
467///   +/-Rm
468///   +/-Rm, shift
469///   #offset
470/// we return false on success or an error otherwise.
471bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
472                                        bool &OffsetRegShifted,
473                                        enum ShiftType &ShiftType,
474                                        const MCExpr *&ShiftAmount,
475                                        const MCExpr *&Offset,
476                                        bool &OffsetIsReg,
477                                        int &OffsetRegNum,
478                                        SMLoc &E) {
479  OwningPtr<ARMOperand> Op;
480  Negative = false;
481  OffsetRegShifted = false;
482  OffsetIsReg = false;
483  OffsetRegNum = -1;
484  const AsmToken &NextTok = Parser.getTok();
485  E = NextTok.getLoc();
486  if (NextTok.is(AsmToken::Plus))
487    Parser.Lex(); // Eat plus token.
488  else if (NextTok.is(AsmToken::Minus)) {
489    Negative = true;
490    Parser.Lex(); // Eat minus token
491  }
492  // See if there is a register following the "[Rn," or "[Rn]," we have so far.
493  const AsmToken &OffsetRegTok = Parser.getTok();
494  if (OffsetRegTok.is(AsmToken::Identifier)) {
495    OffsetIsReg = !MaybeParseRegister(Op, false);
496    if (OffsetIsReg) {
497      E = Op->getEndLoc();
498      OffsetRegNum = Op->getReg();
499    }
500  }
501  // If we parsed a register as the offset then their can be a shift after that
502  if (OffsetRegNum != -1) {
503    // Look for a comma then a shift
504    const AsmToken &Tok = Parser.getTok();
505    if (Tok.is(AsmToken::Comma)) {
506      Parser.Lex(); // Eat comma token.
507
508      const AsmToken &Tok = Parser.getTok();
509      if (ParseShift(ShiftType, ShiftAmount, E))
510        return Error(Tok.getLoc(), "shift expected");
511      OffsetRegShifted = true;
512    }
513  }
514  else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
515    // Look for #offset following the "[Rn," or "[Rn],"
516    const AsmToken &HashTok = Parser.getTok();
517    if (HashTok.isNot(AsmToken::Hash))
518      return Error(HashTok.getLoc(), "'#' expected");
519
520    Parser.Lex(); // Eat hash token.
521
522    if (getParser().ParseExpression(Offset))
523     return true;
524    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
525  }
526  return false;
527}
528
529/// ParseShift as one of these two:
530///   ( lsl | lsr | asr | ror ) , # shift_amount
531///   rrx
532/// and returns true if it parses a shift otherwise it returns false.
533bool ARMAsmParser::ParseShift(ShiftType &St,
534                              const MCExpr *&ShiftAmount,
535                              SMLoc &E) {
536  const AsmToken &Tok = Parser.getTok();
537  if (Tok.isNot(AsmToken::Identifier))
538    return true;
539  StringRef ShiftName = Tok.getString();
540  if (ShiftName == "lsl" || ShiftName == "LSL")
541    St = Lsl;
542  else if (ShiftName == "lsr" || ShiftName == "LSR")
543    St = Lsr;
544  else if (ShiftName == "asr" || ShiftName == "ASR")
545    St = Asr;
546  else if (ShiftName == "ror" || ShiftName == "ROR")
547    St = Ror;
548  else if (ShiftName == "rrx" || ShiftName == "RRX")
549    St = Rrx;
550  else
551    return true;
552  Parser.Lex(); // Eat shift type token.
553
554  // Rrx stands alone.
555  if (St == Rrx)
556    return false;
557
558  // Otherwise, there must be a '#' and a shift amount.
559  const AsmToken &HashTok = Parser.getTok();
560  if (HashTok.isNot(AsmToken::Hash))
561    return Error(HashTok.getLoc(), "'#' expected");
562  Parser.Lex(); // Eat hash token.
563
564  if (getParser().ParseExpression(ShiftAmount))
565    return true;
566
567  return false;
568}
569
570/// Parse a arm instruction operand.  For now this parses the operand regardless
571/// of the mnemonic.
572bool ARMAsmParser::ParseOperand(OwningPtr<ARMOperand> &Op) {
573  SMLoc S, E;
574
575  switch (getLexer().getKind()) {
576  case AsmToken::Identifier:
577    if (!MaybeParseRegister(Op, true))
578      return false;
579    // This was not a register so parse other operands that start with an
580    // identifier (like labels) as expressions and create them as immediates.
581    const MCExpr *IdVal;
582    S = Parser.getTok().getLoc();
583    if (getParser().ParseExpression(IdVal))
584      return true;
585    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
586    ARMOperand::CreateImm(Op, IdVal, S, E);
587    return false;
588  case AsmToken::LBrac:
589    return ParseMemory(Op);
590  case AsmToken::LCurly:
591    return ParseRegisterList(Op);
592  case AsmToken::Hash:
593    // #42 -> immediate.
594    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
595    S = Parser.getTok().getLoc();
596    Parser.Lex();
597    const MCExpr *ImmVal;
598    if (getParser().ParseExpression(ImmVal))
599      return true;
600    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
601    ARMOperand::CreateImm(Op, ImmVal, S, E);
602    return false;
603  default:
604    return Error(Parser.getTok().getLoc(), "unexpected token in operand");
605  }
606}
607
608/// Parse an arm instruction mnemonic followed by its operands.
609bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
610                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
611  OwningPtr<ARMOperand> Op;
612  ARMOperand::CreateToken(Op, Name, NameLoc);
613
614  Operands.push_back(Op.take());
615
616  if (getLexer().isNot(AsmToken::EndOfStatement)) {
617
618    // Read the first operand.
619    OwningPtr<ARMOperand> Op;
620    if (ParseOperand(Op)) return true;
621    Operands.push_back(Op.take());
622
623    while (getLexer().is(AsmToken::Comma)) {
624      Parser.Lex();  // Eat the comma.
625
626      // Parse and remember the operand.
627      if (ParseOperand(Op)) return true;
628      Operands.push_back(Op.take());
629    }
630  }
631  return false;
632}
633
634/// ParseDirective parses the arm specific directives
635bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
636  StringRef IDVal = DirectiveID.getIdentifier();
637  if (IDVal == ".word")
638    return ParseDirectiveWord(4, DirectiveID.getLoc());
639  else if (IDVal == ".thumb")
640    return ParseDirectiveThumb(DirectiveID.getLoc());
641  else if (IDVal == ".thumb_func")
642    return ParseDirectiveThumbFunc(DirectiveID.getLoc());
643  else if (IDVal == ".code")
644    return ParseDirectiveCode(DirectiveID.getLoc());
645  else if (IDVal == ".syntax")
646    return ParseDirectiveSyntax(DirectiveID.getLoc());
647  return true;
648}
649
650/// ParseDirectiveWord
651///  ::= .word [ expression (, expression)* ]
652bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
653  if (getLexer().isNot(AsmToken::EndOfStatement)) {
654    for (;;) {
655      const MCExpr *Value;
656      if (getParser().ParseExpression(Value))
657        return true;
658
659      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
660
661      if (getLexer().is(AsmToken::EndOfStatement))
662        break;
663
664      // FIXME: Improve diagnostic.
665      if (getLexer().isNot(AsmToken::Comma))
666        return Error(L, "unexpected token in directive");
667      Parser.Lex();
668    }
669  }
670
671  Parser.Lex();
672  return false;
673}
674
675/// ParseDirectiveThumb
676///  ::= .thumb
677bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
678  if (getLexer().isNot(AsmToken::EndOfStatement))
679    return Error(L, "unexpected token in directive");
680  Parser.Lex();
681
682  // TODO: set thumb mode
683  // TODO: tell the MC streamer the mode
684  // getParser().getStreamer().Emit???();
685  return false;
686}
687
688/// ParseDirectiveThumbFunc
689///  ::= .thumbfunc symbol_name
690bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
691  const AsmToken &Tok = Parser.getTok();
692  if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
693    return Error(L, "unexpected token in .syntax directive");
694  StringRef ATTRIBUTE_UNUSED SymbolName = Parser.getTok().getIdentifier();
695  Parser.Lex(); // Consume the identifier token.
696
697  if (getLexer().isNot(AsmToken::EndOfStatement))
698    return Error(L, "unexpected token in directive");
699  Parser.Lex();
700
701  // TODO: mark symbol as a thumb symbol
702  // getParser().getStreamer().Emit???();
703  return false;
704}
705
706/// ParseDirectiveSyntax
707///  ::= .syntax unified | divided
708bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
709  const AsmToken &Tok = Parser.getTok();
710  if (Tok.isNot(AsmToken::Identifier))
711    return Error(L, "unexpected token in .syntax directive");
712  StringRef Mode = Tok.getString();
713  if (Mode == "unified" || Mode == "UNIFIED")
714    Parser.Lex();
715  else if (Mode == "divided" || Mode == "DIVIDED")
716    Parser.Lex();
717  else
718    return Error(L, "unrecognized syntax mode in .syntax directive");
719
720  if (getLexer().isNot(AsmToken::EndOfStatement))
721    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
722  Parser.Lex();
723
724  // TODO tell the MC streamer the mode
725  // getParser().getStreamer().Emit???();
726  return false;
727}
728
729/// ParseDirectiveCode
730///  ::= .code 16 | 32
731bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
732  const AsmToken &Tok = Parser.getTok();
733  if (Tok.isNot(AsmToken::Integer))
734    return Error(L, "unexpected token in .code directive");
735  int64_t Val = Parser.getTok().getIntVal();
736  if (Val == 16)
737    Parser.Lex();
738  else if (Val == 32)
739    Parser.Lex();
740  else
741    return Error(L, "invalid operand to .code directive");
742
743  if (getLexer().isNot(AsmToken::EndOfStatement))
744    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
745  Parser.Lex();
746
747  // TODO tell the MC streamer the mode
748  // getParser().getStreamer().Emit???();
749  return false;
750}
751
752extern "C" void LLVMInitializeARMAsmLexer();
753
754/// Force static initialization.
755extern "C" void LLVMInitializeARMAsmParser() {
756  RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
757  RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
758  LLVMInitializeARMAsmLexer();
759}
760
761#include "ARMGenAsmMatcher.inc"
762