ARMAsmParser.cpp revision 429af6fa4124d8b6dd310069e0a44dcacb35fc8a 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/MCTargetAsmParser.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/SourceMgr.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/ADT/BitVector.h"
30#include "llvm/ADT/OwningPtr.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/StringSwitch.h"
34#include "llvm/ADT/Twine.h"
35
36using namespace llvm;
37
38namespace {
39
40class ARMOperand;
41
42enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
43
44class ARMAsmParser : public MCTargetAsmParser {
45  MCSubtargetInfo &STI;
46  MCAsmParser &Parser;
47  const MCRegisterInfo *MRI;
48
49  // Map of register aliases registers via the .req directive.
50  StringMap<unsigned> RegisterReqs;
51
52  struct {
53    ARMCC::CondCodes Cond;    // Condition for IT block.
54    unsigned Mask:4;          // Condition mask for instructions.
55                              // Starting at first 1 (from lsb).
56                              //   '1'  condition as indicated in IT.
57                              //   '0'  inverse of condition (else).
58                              // Count of instructions in IT block is
59                              // 4 - trailingzeroes(mask)
60
61    bool FirstCond;           // Explicit flag for when we're parsing the
62                              // First instruction in the IT block. It's
63                              // implied in the mask, so needs special
64                              // handling.
65
66    unsigned CurPosition;     // Current position in parsing of IT
67                              // block. In range [0,3]. Initialized
68                              // according to count of instructions in block.
69                              // ~0U if no active IT block.
70  } ITState;
71  bool inITBlock() { return ITState.CurPosition != ~0U;}
72  void forwardITPosition() {
73    if (!inITBlock()) return;
74    // Move to the next instruction in the IT block, if there is one. If not,
75    // mark the block as done.
76    unsigned TZ = CountTrailingZeros_32(ITState.Mask);
77    if (++ITState.CurPosition == 5 - TZ)
78      ITState.CurPosition = ~0U; // Done with the IT block after this.
79  }
80
81
82  MCAsmParser &getParser() const { return Parser; }
83  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
84
85  bool Warning(SMLoc L, const Twine &Msg,
86               ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
87    return Parser.Warning(L, Msg, Ranges);
88  }
89  bool Error(SMLoc L, const Twine &Msg,
90             ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
91    return Parser.Error(L, Msg, Ranges);
92  }
93
94  int tryParseRegister();
95  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
96  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
97  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
98  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
99  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
100  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
101  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
102                              unsigned &ShiftAmount);
103  bool parseDirectiveWord(unsigned Size, SMLoc L);
104  bool parseDirectiveThumb(SMLoc L);
105  bool parseDirectiveARM(SMLoc L);
106  bool parseDirectiveThumbFunc(SMLoc L);
107  bool parseDirectiveCode(SMLoc L);
108  bool parseDirectiveSyntax(SMLoc L);
109  bool parseDirectiveReq(StringRef Name, SMLoc L);
110  bool parseDirectiveUnreq(SMLoc L);
111  bool parseDirectiveArch(SMLoc L);
112  bool parseDirectiveEabiAttr(SMLoc L);
113
114  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
115                          bool &CarrySetting, unsigned &ProcessorIMod,
116                          StringRef &ITMask);
117  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
118                             bool &CanAcceptPredicationCode);
119
120  bool isThumb() const {
121    // FIXME: Can tablegen auto-generate this?
122    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
123  }
124  bool isThumbOne() const {
125    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
126  }
127  bool isThumbTwo() const {
128    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
129  }
130  bool hasV6Ops() const {
131    return STI.getFeatureBits() & ARM::HasV6Ops;
132  }
133  bool hasV7Ops() const {
134    return STI.getFeatureBits() & ARM::HasV7Ops;
135  }
136  void SwitchMode() {
137    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
138    setAvailableFeatures(FB);
139  }
140  bool isMClass() const {
141    return STI.getFeatureBits() & ARM::FeatureMClass;
142  }
143
144  /// @name Auto-generated Match Functions
145  /// {
146
147#define GET_ASSEMBLER_HEADER
148#include "ARMGenAsmMatcher.inc"
149
150  /// }
151
152  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
153  OperandMatchResultTy parseCoprocNumOperand(
154    SmallVectorImpl<MCParsedAsmOperand*>&);
155  OperandMatchResultTy parseCoprocRegOperand(
156    SmallVectorImpl<MCParsedAsmOperand*>&);
157  OperandMatchResultTy parseCoprocOptionOperand(
158    SmallVectorImpl<MCParsedAsmOperand*>&);
159  OperandMatchResultTy parseMemBarrierOptOperand(
160    SmallVectorImpl<MCParsedAsmOperand*>&);
161  OperandMatchResultTy parseProcIFlagsOperand(
162    SmallVectorImpl<MCParsedAsmOperand*>&);
163  OperandMatchResultTy parseMSRMaskOperand(
164    SmallVectorImpl<MCParsedAsmOperand*>&);
165  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
166                                   StringRef Op, int Low, int High);
167  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
168    return parsePKHImm(O, "lsl", 0, 31);
169  }
170  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
171    return parsePKHImm(O, "asr", 1, 32);
172  }
173  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
174  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
175  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
176  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
177  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
178  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
179  OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
180  OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
181  OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index);
182
183  // Asm Match Converter Methods
184  void cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
185                    const SmallVectorImpl<MCParsedAsmOperand*> &);
186  void cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
187                    const SmallVectorImpl<MCParsedAsmOperand*> &);
188  void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
189                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
190  void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
191                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
192  void cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
193                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
194  void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
195                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
196  void cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
197                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
198  void cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
199                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
200  void cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
201                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
202  void cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
203                             const SmallVectorImpl<MCParsedAsmOperand*> &);
204  void cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
205                             const SmallVectorImpl<MCParsedAsmOperand*> &);
206  void cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
207                             const SmallVectorImpl<MCParsedAsmOperand*> &);
208  void cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
209                             const SmallVectorImpl<MCParsedAsmOperand*> &);
210  void cvtLdrdPre(MCInst &Inst, unsigned Opcode,
211                  const SmallVectorImpl<MCParsedAsmOperand*> &);
212  void cvtStrdPre(MCInst &Inst, unsigned Opcode,
213                  const SmallVectorImpl<MCParsedAsmOperand*> &);
214  void cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
215                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
216  void cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
217                        const SmallVectorImpl<MCParsedAsmOperand*> &);
218  void cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
219                     const SmallVectorImpl<MCParsedAsmOperand*> &);
220  void cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
221                        const SmallVectorImpl<MCParsedAsmOperand*> &);
222  void cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
223                     const SmallVectorImpl<MCParsedAsmOperand*> &);
224  void cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
225                        const SmallVectorImpl<MCParsedAsmOperand*> &);
226
227  bool validateInstruction(MCInst &Inst,
228                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
229  bool processInstruction(MCInst &Inst,
230                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
231  bool shouldOmitCCOutOperand(StringRef Mnemonic,
232                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
233
234public:
235  enum ARMMatchResultTy {
236    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
237    Match_RequiresNotITBlock,
238    Match_RequiresV6,
239    Match_RequiresThumb2,
240#define GET_OPERAND_DIAGNOSTIC_TYPES
241#include "ARMGenAsmMatcher.inc"
242
243  };
244
245  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
246    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
247    MCAsmParserExtension::Initialize(_Parser);
248
249    // Cache the MCRegisterInfo.
250    MRI = &getContext().getRegisterInfo();
251
252    // Initialize the set of available features.
253    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
254
255    // Not in an ITBlock to start with.
256    ITState.CurPosition = ~0U;
257  }
258
259  // Implementation of the MCTargetAsmParser interface:
260  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
261  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
262                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
263  bool ParseDirective(AsmToken DirectiveID);
264
265  unsigned checkTargetMatchPredicate(MCInst &Inst);
266
267  bool MatchAndEmitInstruction(SMLoc IDLoc,
268                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
269                               MCStreamer &Out);
270};
271} // end anonymous namespace
272
273namespace {
274
275/// ARMOperand - Instances of this class represent a parsed ARM machine
276/// instruction.
277class ARMOperand : public MCParsedAsmOperand {
278  enum KindTy {
279    k_CondCode,
280    k_CCOut,
281    k_ITCondMask,
282    k_CoprocNum,
283    k_CoprocReg,
284    k_CoprocOption,
285    k_Immediate,
286    k_MemBarrierOpt,
287    k_Memory,
288    k_PostIndexRegister,
289    k_MSRMask,
290    k_ProcIFlags,
291    k_VectorIndex,
292    k_Register,
293    k_RegisterList,
294    k_DPRRegisterList,
295    k_SPRRegisterList,
296    k_VectorList,
297    k_VectorListAllLanes,
298    k_VectorListIndexed,
299    k_ShiftedRegister,
300    k_ShiftedImmediate,
301    k_ShifterImmediate,
302    k_RotateImmediate,
303    k_BitfieldDescriptor,
304    k_Token
305  } Kind;
306
307  SMLoc StartLoc, EndLoc;
308  SmallVector<unsigned, 8> Registers;
309
310  union {
311    struct {
312      ARMCC::CondCodes Val;
313    } CC;
314
315    struct {
316      unsigned Val;
317    } Cop;
318
319    struct {
320      unsigned Val;
321    } CoprocOption;
322
323    struct {
324      unsigned Mask:4;
325    } ITMask;
326
327    struct {
328      ARM_MB::MemBOpt Val;
329    } MBOpt;
330
331    struct {
332      ARM_PROC::IFlags Val;
333    } IFlags;
334
335    struct {
336      unsigned Val;
337    } MMask;
338
339    struct {
340      const char *Data;
341      unsigned Length;
342    } Tok;
343
344    struct {
345      unsigned RegNum;
346    } Reg;
347
348    // A vector register list is a sequential list of 1 to 4 registers.
349    struct {
350      unsigned RegNum;
351      unsigned Count;
352      unsigned LaneIndex;
353      bool isDoubleSpaced;
354    } VectorList;
355
356    struct {
357      unsigned Val;
358    } VectorIndex;
359
360    struct {
361      const MCExpr *Val;
362    } Imm;
363
364    /// Combined record for all forms of ARM address expressions.
365    struct {
366      unsigned BaseRegNum;
367      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
368      // was specified.
369      const MCConstantExpr *OffsetImm;  // Offset immediate value
370      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
371      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
372      unsigned ShiftImm;        // shift for OffsetReg.
373      unsigned Alignment;       // 0 = no alignment specified
374                                // n = alignment in bytes (2, 4, 8, 16, or 32)
375      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
376    } Memory;
377
378    struct {
379      unsigned RegNum;
380      bool isAdd;
381      ARM_AM::ShiftOpc ShiftTy;
382      unsigned ShiftImm;
383    } PostIdxReg;
384
385    struct {
386      bool isASR;
387      unsigned Imm;
388    } ShifterImm;
389    struct {
390      ARM_AM::ShiftOpc ShiftTy;
391      unsigned SrcReg;
392      unsigned ShiftReg;
393      unsigned ShiftImm;
394    } RegShiftedReg;
395    struct {
396      ARM_AM::ShiftOpc ShiftTy;
397      unsigned SrcReg;
398      unsigned ShiftImm;
399    } RegShiftedImm;
400    struct {
401      unsigned Imm;
402    } RotImm;
403    struct {
404      unsigned LSB;
405      unsigned Width;
406    } Bitfield;
407  };
408
409  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
410public:
411  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
412    Kind = o.Kind;
413    StartLoc = o.StartLoc;
414    EndLoc = o.EndLoc;
415    switch (Kind) {
416    case k_CondCode:
417      CC = o.CC;
418      break;
419    case k_ITCondMask:
420      ITMask = o.ITMask;
421      break;
422    case k_Token:
423      Tok = o.Tok;
424      break;
425    case k_CCOut:
426    case k_Register:
427      Reg = o.Reg;
428      break;
429    case k_RegisterList:
430    case k_DPRRegisterList:
431    case k_SPRRegisterList:
432      Registers = o.Registers;
433      break;
434    case k_VectorList:
435    case k_VectorListAllLanes:
436    case k_VectorListIndexed:
437      VectorList = o.VectorList;
438      break;
439    case k_CoprocNum:
440    case k_CoprocReg:
441      Cop = o.Cop;
442      break;
443    case k_CoprocOption:
444      CoprocOption = o.CoprocOption;
445      break;
446    case k_Immediate:
447      Imm = o.Imm;
448      break;
449    case k_MemBarrierOpt:
450      MBOpt = o.MBOpt;
451      break;
452    case k_Memory:
453      Memory = o.Memory;
454      break;
455    case k_PostIndexRegister:
456      PostIdxReg = o.PostIdxReg;
457      break;
458    case k_MSRMask:
459      MMask = o.MMask;
460      break;
461    case k_ProcIFlags:
462      IFlags = o.IFlags;
463      break;
464    case k_ShifterImmediate:
465      ShifterImm = o.ShifterImm;
466      break;
467    case k_ShiftedRegister:
468      RegShiftedReg = o.RegShiftedReg;
469      break;
470    case k_ShiftedImmediate:
471      RegShiftedImm = o.RegShiftedImm;
472      break;
473    case k_RotateImmediate:
474      RotImm = o.RotImm;
475      break;
476    case k_BitfieldDescriptor:
477      Bitfield = o.Bitfield;
478      break;
479    case k_VectorIndex:
480      VectorIndex = o.VectorIndex;
481      break;
482    }
483  }
484
485  /// getStartLoc - Get the location of the first token of this operand.
486  SMLoc getStartLoc() const { return StartLoc; }
487  /// getEndLoc - Get the location of the last token of this operand.
488  SMLoc getEndLoc() const { return EndLoc; }
489
490  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
491
492  ARMCC::CondCodes getCondCode() const {
493    assert(Kind == k_CondCode && "Invalid access!");
494    return CC.Val;
495  }
496
497  unsigned getCoproc() const {
498    assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
499    return Cop.Val;
500  }
501
502  StringRef getToken() const {
503    assert(Kind == k_Token && "Invalid access!");
504    return StringRef(Tok.Data, Tok.Length);
505  }
506
507  unsigned getReg() const {
508    assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
509    return Reg.RegNum;
510  }
511
512  const SmallVectorImpl<unsigned> &getRegList() const {
513    assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
514            Kind == k_SPRRegisterList) && "Invalid access!");
515    return Registers;
516  }
517
518  const MCExpr *getImm() const {
519    assert(isImm() && "Invalid access!");
520    return Imm.Val;
521  }
522
523  unsigned getVectorIndex() const {
524    assert(Kind == k_VectorIndex && "Invalid access!");
525    return VectorIndex.Val;
526  }
527
528  ARM_MB::MemBOpt getMemBarrierOpt() const {
529    assert(Kind == k_MemBarrierOpt && "Invalid access!");
530    return MBOpt.Val;
531  }
532
533  ARM_PROC::IFlags getProcIFlags() const {
534    assert(Kind == k_ProcIFlags && "Invalid access!");
535    return IFlags.Val;
536  }
537
538  unsigned getMSRMask() const {
539    assert(Kind == k_MSRMask && "Invalid access!");
540    return MMask.Val;
541  }
542
543  bool isCoprocNum() const { return Kind == k_CoprocNum; }
544  bool isCoprocReg() const { return Kind == k_CoprocReg; }
545  bool isCoprocOption() const { return Kind == k_CoprocOption; }
546  bool isCondCode() const { return Kind == k_CondCode; }
547  bool isCCOut() const { return Kind == k_CCOut; }
548  bool isITMask() const { return Kind == k_ITCondMask; }
549  bool isITCondCode() const { return Kind == k_CondCode; }
550  bool isImm() const { return Kind == k_Immediate; }
551  bool isFPImm() const {
552    if (!isImm()) return false;
553    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
554    if (!CE) return false;
555    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
556    return Val != -1;
557  }
558  bool isFBits16() const {
559    if (!isImm()) return false;
560    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
561    if (!CE) return false;
562    int64_t Value = CE->getValue();
563    return Value >= 0 && Value <= 16;
564  }
565  bool isFBits32() const {
566    if (!isImm()) return false;
567    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
568    if (!CE) return false;
569    int64_t Value = CE->getValue();
570    return Value >= 1 && Value <= 32;
571  }
572  bool isImm8s4() const {
573    if (!isImm()) return false;
574    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
575    if (!CE) return false;
576    int64_t Value = CE->getValue();
577    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
578  }
579  bool isImm0_1020s4() const {
580    if (!isImm()) return false;
581    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
582    if (!CE) return false;
583    int64_t Value = CE->getValue();
584    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
585  }
586  bool isImm0_508s4() const {
587    if (!isImm()) return false;
588    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
589    if (!CE) return false;
590    int64_t Value = CE->getValue();
591    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
592  }
593  bool isImm0_508s4Neg() const {
594    if (!isImm()) return false;
595    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
596    if (!CE) return false;
597    int64_t Value = -CE->getValue();
598    // explicitly exclude zero. we want that to use the normal 0_508 version.
599    return ((Value & 3) == 0) && Value > 0 && Value <= 508;
600  }
601  bool isImm0_255() const {
602    if (!isImm()) return false;
603    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
604    if (!CE) return false;
605    int64_t Value = CE->getValue();
606    return Value >= 0 && Value < 256;
607  }
608  bool isImm0_4095() const {
609    if (!isImm()) return false;
610    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
611    if (!CE) return false;
612    int64_t Value = CE->getValue();
613    return Value >= 0 && Value < 4096;
614  }
615  bool isImm0_4095Neg() const {
616    if (!isImm()) return false;
617    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
618    if (!CE) return false;
619    int64_t Value = -CE->getValue();
620    return Value > 0 && Value < 4096;
621  }
622  bool isImm0_1() const {
623    if (!isImm()) return false;
624    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
625    if (!CE) return false;
626    int64_t Value = CE->getValue();
627    return Value >= 0 && Value < 2;
628  }
629  bool isImm0_3() const {
630    if (!isImm()) return false;
631    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
632    if (!CE) return false;
633    int64_t Value = CE->getValue();
634    return Value >= 0 && Value < 4;
635  }
636  bool isImm0_7() const {
637    if (!isImm()) return false;
638    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
639    if (!CE) return false;
640    int64_t Value = CE->getValue();
641    return Value >= 0 && Value < 8;
642  }
643  bool isImm0_15() const {
644    if (!isImm()) return false;
645    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
646    if (!CE) return false;
647    int64_t Value = CE->getValue();
648    return Value >= 0 && Value < 16;
649  }
650  bool isImm0_31() const {
651    if (!isImm()) return false;
652    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
653    if (!CE) return false;
654    int64_t Value = CE->getValue();
655    return Value >= 0 && Value < 32;
656  }
657  bool isImm0_63() const {
658    if (!isImm()) return false;
659    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
660    if (!CE) return false;
661    int64_t Value = CE->getValue();
662    return Value >= 0 && Value < 64;
663  }
664  bool isImm8() const {
665    if (!isImm()) return false;
666    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
667    if (!CE) return false;
668    int64_t Value = CE->getValue();
669    return Value == 8;
670  }
671  bool isImm16() const {
672    if (!isImm()) return false;
673    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
674    if (!CE) return false;
675    int64_t Value = CE->getValue();
676    return Value == 16;
677  }
678  bool isImm32() const {
679    if (!isImm()) return false;
680    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
681    if (!CE) return false;
682    int64_t Value = CE->getValue();
683    return Value == 32;
684  }
685  bool isShrImm8() const {
686    if (!isImm()) return false;
687    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
688    if (!CE) return false;
689    int64_t Value = CE->getValue();
690    return Value > 0 && Value <= 8;
691  }
692  bool isShrImm16() const {
693    if (!isImm()) return false;
694    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
695    if (!CE) return false;
696    int64_t Value = CE->getValue();
697    return Value > 0 && Value <= 16;
698  }
699  bool isShrImm32() const {
700    if (!isImm()) return false;
701    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
702    if (!CE) return false;
703    int64_t Value = CE->getValue();
704    return Value > 0 && Value <= 32;
705  }
706  bool isShrImm64() const {
707    if (!isImm()) return false;
708    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
709    if (!CE) return false;
710    int64_t Value = CE->getValue();
711    return Value > 0 && Value <= 64;
712  }
713  bool isImm1_7() const {
714    if (!isImm()) return false;
715    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
716    if (!CE) return false;
717    int64_t Value = CE->getValue();
718    return Value > 0 && Value < 8;
719  }
720  bool isImm1_15() const {
721    if (!isImm()) return false;
722    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
723    if (!CE) return false;
724    int64_t Value = CE->getValue();
725    return Value > 0 && Value < 16;
726  }
727  bool isImm1_31() const {
728    if (!isImm()) return false;
729    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
730    if (!CE) return false;
731    int64_t Value = CE->getValue();
732    return Value > 0 && Value < 32;
733  }
734  bool isImm1_16() const {
735    if (!isImm()) return false;
736    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
737    if (!CE) return false;
738    int64_t Value = CE->getValue();
739    return Value > 0 && Value < 17;
740  }
741  bool isImm1_32() const {
742    if (!isImm()) return false;
743    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
744    if (!CE) return false;
745    int64_t Value = CE->getValue();
746    return Value > 0 && Value < 33;
747  }
748  bool isImm0_32() const {
749    if (!isImm()) return false;
750    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
751    if (!CE) return false;
752    int64_t Value = CE->getValue();
753    return Value >= 0 && Value < 33;
754  }
755  bool isImm0_65535() const {
756    if (!isImm()) return false;
757    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
758    if (!CE) return false;
759    int64_t Value = CE->getValue();
760    return Value >= 0 && Value < 65536;
761  }
762  bool isImm0_65535Expr() const {
763    if (!isImm()) return false;
764    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
765    // If it's not a constant expression, it'll generate a fixup and be
766    // handled later.
767    if (!CE) return true;
768    int64_t Value = CE->getValue();
769    return Value >= 0 && Value < 65536;
770  }
771  bool isImm24bit() const {
772    if (!isImm()) return false;
773    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
774    if (!CE) return false;
775    int64_t Value = CE->getValue();
776    return Value >= 0 && Value <= 0xffffff;
777  }
778  bool isImmThumbSR() const {
779    if (!isImm()) return false;
780    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
781    if (!CE) return false;
782    int64_t Value = CE->getValue();
783    return Value > 0 && Value < 33;
784  }
785  bool isPKHLSLImm() const {
786    if (!isImm()) return false;
787    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
788    if (!CE) return false;
789    int64_t Value = CE->getValue();
790    return Value >= 0 && Value < 32;
791  }
792  bool isPKHASRImm() const {
793    if (!isImm()) return false;
794    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
795    if (!CE) return false;
796    int64_t Value = CE->getValue();
797    return Value > 0 && Value <= 32;
798  }
799  bool isAdrLabel() const {
800    // If we have an immediate that's not a constant, treat it as a label
801    // reference needing a fixup. If it is a constant, but it can't fit
802    // into shift immediate encoding, we reject it.
803    if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
804    else return (isARMSOImm() || isARMSOImmNeg());
805  }
806  bool isARMSOImm() const {
807    if (!isImm()) return false;
808    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
809    if (!CE) return false;
810    int64_t Value = CE->getValue();
811    return ARM_AM::getSOImmVal(Value) != -1;
812  }
813  bool isARMSOImmNot() const {
814    if (!isImm()) return false;
815    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
816    if (!CE) return false;
817    int64_t Value = CE->getValue();
818    return ARM_AM::getSOImmVal(~Value) != -1;
819  }
820  bool isARMSOImmNeg() const {
821    if (!isImm()) return false;
822    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
823    if (!CE) return false;
824    int64_t Value = CE->getValue();
825    // Only use this when not representable as a plain so_imm.
826    return ARM_AM::getSOImmVal(Value) == -1 &&
827      ARM_AM::getSOImmVal(-Value) != -1;
828  }
829  bool isT2SOImm() const {
830    if (!isImm()) return false;
831    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
832    if (!CE) return false;
833    int64_t Value = CE->getValue();
834    return ARM_AM::getT2SOImmVal(Value) != -1;
835  }
836  bool isT2SOImmNot() const {
837    if (!isImm()) return false;
838    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
839    if (!CE) return false;
840    int64_t Value = CE->getValue();
841    return ARM_AM::getT2SOImmVal(~Value) != -1;
842  }
843  bool isT2SOImmNeg() const {
844    if (!isImm()) return false;
845    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
846    if (!CE) return false;
847    int64_t Value = CE->getValue();
848    // Only use this when not representable as a plain so_imm.
849    return ARM_AM::getT2SOImmVal(Value) == -1 &&
850      ARM_AM::getT2SOImmVal(-Value) != -1;
851  }
852  bool isSetEndImm() const {
853    if (!isImm()) return false;
854    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
855    if (!CE) return false;
856    int64_t Value = CE->getValue();
857    return Value == 1 || Value == 0;
858  }
859  bool isReg() const { return Kind == k_Register; }
860  bool isRegList() const { return Kind == k_RegisterList; }
861  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
862  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
863  bool isToken() const { return Kind == k_Token; }
864  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
865  bool isMemory() const { return Kind == k_Memory; }
866  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
867  bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
868  bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
869  bool isRotImm() const { return Kind == k_RotateImmediate; }
870  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
871  bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
872  bool isPostIdxReg() const {
873    return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
874  }
875  bool isMemNoOffset(bool alignOK = false) const {
876    if (!isMemory())
877      return false;
878    // No offset of any kind.
879    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
880     (alignOK || Memory.Alignment == 0);
881  }
882  bool isMemPCRelImm12() const {
883    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
884      return false;
885    // Base register must be PC.
886    if (Memory.BaseRegNum != ARM::PC)
887      return false;
888    // Immediate offset in range [-4095, 4095].
889    if (!Memory.OffsetImm) return true;
890    int64_t Val = Memory.OffsetImm->getValue();
891    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
892  }
893  bool isAlignedMemory() const {
894    return isMemNoOffset(true);
895  }
896  bool isAddrMode2() const {
897    if (!isMemory() || Memory.Alignment != 0) return false;
898    // Check for register offset.
899    if (Memory.OffsetRegNum) return true;
900    // Immediate offset in range [-4095, 4095].
901    if (!Memory.OffsetImm) return true;
902    int64_t Val = Memory.OffsetImm->getValue();
903    return Val > -4096 && Val < 4096;
904  }
905  bool isAM2OffsetImm() const {
906    if (!isImm()) return false;
907    // Immediate offset in range [-4095, 4095].
908    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
909    if (!CE) return false;
910    int64_t Val = CE->getValue();
911    return Val > -4096 && Val < 4096;
912  }
913  bool isAddrMode3() const {
914    // If we have an immediate that's not a constant, treat it as a label
915    // reference needing a fixup. If it is a constant, it's something else
916    // and we reject it.
917    if (isImm() && !isa<MCConstantExpr>(getImm()))
918      return true;
919    if (!isMemory() || Memory.Alignment != 0) return false;
920    // No shifts are legal for AM3.
921    if (Memory.ShiftType != ARM_AM::no_shift) return false;
922    // Check for register offset.
923    if (Memory.OffsetRegNum) return true;
924    // Immediate offset in range [-255, 255].
925    if (!Memory.OffsetImm) return true;
926    int64_t Val = Memory.OffsetImm->getValue();
927    // The #-0 offset is encoded as INT32_MIN, and we have to check
928    // for this too.
929    return (Val > -256 && Val < 256) || Val == INT32_MIN;
930  }
931  bool isAM3Offset() const {
932    if (Kind != k_Immediate && Kind != k_PostIndexRegister)
933      return false;
934    if (Kind == k_PostIndexRegister)
935      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
936    // Immediate offset in range [-255, 255].
937    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
938    if (!CE) return false;
939    int64_t Val = CE->getValue();
940    // Special case, #-0 is INT32_MIN.
941    return (Val > -256 && Val < 256) || Val == INT32_MIN;
942  }
943  bool isAddrMode5() const {
944    // If we have an immediate that's not a constant, treat it as a label
945    // reference needing a fixup. If it is a constant, it's something else
946    // and we reject it.
947    if (isImm() && !isa<MCConstantExpr>(getImm()))
948      return true;
949    if (!isMemory() || Memory.Alignment != 0) return false;
950    // Check for register offset.
951    if (Memory.OffsetRegNum) return false;
952    // Immediate offset in range [-1020, 1020] and a multiple of 4.
953    if (!Memory.OffsetImm) return true;
954    int64_t Val = Memory.OffsetImm->getValue();
955    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
956      Val == INT32_MIN;
957  }
958  bool isMemTBB() const {
959    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
960        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
961      return false;
962    return true;
963  }
964  bool isMemTBH() const {
965    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
966        Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
967        Memory.Alignment != 0 )
968      return false;
969    return true;
970  }
971  bool isMemRegOffset() const {
972    if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
973      return false;
974    return true;
975  }
976  bool isT2MemRegOffset() const {
977    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
978        Memory.Alignment != 0)
979      return false;
980    // Only lsl #{0, 1, 2, 3} allowed.
981    if (Memory.ShiftType == ARM_AM::no_shift)
982      return true;
983    if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
984      return false;
985    return true;
986  }
987  bool isMemThumbRR() const {
988    // Thumb reg+reg addressing is simple. Just two registers, a base and
989    // an offset. No shifts, negations or any other complicating factors.
990    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
991        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
992      return false;
993    return isARMLowRegister(Memory.BaseRegNum) &&
994      (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
995  }
996  bool isMemThumbRIs4() const {
997    if (!isMemory() || Memory.OffsetRegNum != 0 ||
998        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
999      return false;
1000    // Immediate offset, multiple of 4 in range [0, 124].
1001    if (!Memory.OffsetImm) return true;
1002    int64_t Val = Memory.OffsetImm->getValue();
1003    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1004  }
1005  bool isMemThumbRIs2() const {
1006    if (!isMemory() || Memory.OffsetRegNum != 0 ||
1007        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1008      return false;
1009    // Immediate offset, multiple of 4 in range [0, 62].
1010    if (!Memory.OffsetImm) return true;
1011    int64_t Val = Memory.OffsetImm->getValue();
1012    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1013  }
1014  bool isMemThumbRIs1() const {
1015    if (!isMemory() || Memory.OffsetRegNum != 0 ||
1016        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1017      return false;
1018    // Immediate offset in range [0, 31].
1019    if (!Memory.OffsetImm) return true;
1020    int64_t Val = Memory.OffsetImm->getValue();
1021    return Val >= 0 && Val <= 31;
1022  }
1023  bool isMemThumbSPI() const {
1024    if (!isMemory() || Memory.OffsetRegNum != 0 ||
1025        Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1026      return false;
1027    // Immediate offset, multiple of 4 in range [0, 1020].
1028    if (!Memory.OffsetImm) return true;
1029    int64_t Val = Memory.OffsetImm->getValue();
1030    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1031  }
1032  bool isMemImm8s4Offset() const {
1033    // If we have an immediate that's not a constant, treat it as a label
1034    // reference needing a fixup. If it is a constant, it's something else
1035    // and we reject it.
1036    if (isImm() && !isa<MCConstantExpr>(getImm()))
1037      return true;
1038    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1039      return false;
1040    // Immediate offset a multiple of 4 in range [-1020, 1020].
1041    if (!Memory.OffsetImm) return true;
1042    int64_t Val = Memory.OffsetImm->getValue();
1043    // Special case, #-0 is INT32_MIN.
1044    return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1045  }
1046  bool isMemImm0_1020s4Offset() const {
1047    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1048      return false;
1049    // Immediate offset a multiple of 4 in range [0, 1020].
1050    if (!Memory.OffsetImm) return true;
1051    int64_t Val = Memory.OffsetImm->getValue();
1052    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1053  }
1054  bool isMemImm8Offset() const {
1055    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1056      return false;
1057    // Base reg of PC isn't allowed for these encodings.
1058    if (Memory.BaseRegNum == ARM::PC) return false;
1059    // Immediate offset in range [-255, 255].
1060    if (!Memory.OffsetImm) return true;
1061    int64_t Val = Memory.OffsetImm->getValue();
1062    return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1063  }
1064  bool isMemPosImm8Offset() const {
1065    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1066      return false;
1067    // Immediate offset in range [0, 255].
1068    if (!Memory.OffsetImm) return true;
1069    int64_t Val = Memory.OffsetImm->getValue();
1070    return Val >= 0 && Val < 256;
1071  }
1072  bool isMemNegImm8Offset() const {
1073    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1074      return false;
1075    // Base reg of PC isn't allowed for these encodings.
1076    if (Memory.BaseRegNum == ARM::PC) return false;
1077    // Immediate offset in range [-255, -1].
1078    if (!Memory.OffsetImm) return false;
1079    int64_t Val = Memory.OffsetImm->getValue();
1080    return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1081  }
1082  bool isMemUImm12Offset() const {
1083    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1084      return false;
1085    // Immediate offset in range [0, 4095].
1086    if (!Memory.OffsetImm) return true;
1087    int64_t Val = Memory.OffsetImm->getValue();
1088    return (Val >= 0 && Val < 4096);
1089  }
1090  bool isMemImm12Offset() const {
1091    // If we have an immediate that's not a constant, treat it as a label
1092    // reference needing a fixup. If it is a constant, it's something else
1093    // and we reject it.
1094    if (isImm() && !isa<MCConstantExpr>(getImm()))
1095      return true;
1096
1097    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1098      return false;
1099    // Immediate offset in range [-4095, 4095].
1100    if (!Memory.OffsetImm) return true;
1101    int64_t Val = Memory.OffsetImm->getValue();
1102    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1103  }
1104  bool isPostIdxImm8() const {
1105    if (!isImm()) return false;
1106    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1107    if (!CE) return false;
1108    int64_t Val = CE->getValue();
1109    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1110  }
1111  bool isPostIdxImm8s4() const {
1112    if (!isImm()) return false;
1113    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1114    if (!CE) return false;
1115    int64_t Val = CE->getValue();
1116    return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1117      (Val == INT32_MIN);
1118  }
1119
1120  bool isMSRMask() const { return Kind == k_MSRMask; }
1121  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1122
1123  // NEON operands.
1124  bool isSingleSpacedVectorList() const {
1125    return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1126  }
1127  bool isDoubleSpacedVectorList() const {
1128    return Kind == k_VectorList && VectorList.isDoubleSpaced;
1129  }
1130  bool isVecListOneD() const {
1131    if (!isSingleSpacedVectorList()) return false;
1132    return VectorList.Count == 1;
1133  }
1134
1135  bool isVecListDPair() const {
1136    if (!isSingleSpacedVectorList()) return false;
1137    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1138              .contains(VectorList.RegNum));
1139  }
1140
1141  bool isVecListThreeD() const {
1142    if (!isSingleSpacedVectorList()) return false;
1143    return VectorList.Count == 3;
1144  }
1145
1146  bool isVecListFourD() const {
1147    if (!isSingleSpacedVectorList()) return false;
1148    return VectorList.Count == 4;
1149  }
1150
1151  bool isVecListDPairSpaced() const {
1152    if (isSingleSpacedVectorList()) return false;
1153    return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1154              .contains(VectorList.RegNum));
1155  }
1156
1157  bool isVecListThreeQ() const {
1158    if (!isDoubleSpacedVectorList()) return false;
1159    return VectorList.Count == 3;
1160  }
1161
1162  bool isVecListFourQ() const {
1163    if (!isDoubleSpacedVectorList()) return false;
1164    return VectorList.Count == 4;
1165  }
1166
1167  bool isSingleSpacedVectorAllLanes() const {
1168    return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1169  }
1170  bool isDoubleSpacedVectorAllLanes() const {
1171    return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1172  }
1173  bool isVecListOneDAllLanes() const {
1174    if (!isSingleSpacedVectorAllLanes()) return false;
1175    return VectorList.Count == 1;
1176  }
1177
1178  bool isVecListDPairAllLanes() const {
1179    if (!isSingleSpacedVectorAllLanes()) return false;
1180    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1181              .contains(VectorList.RegNum));
1182  }
1183
1184  bool isVecListDPairSpacedAllLanes() const {
1185    if (!isDoubleSpacedVectorAllLanes()) return false;
1186    return VectorList.Count == 2;
1187  }
1188
1189  bool isVecListThreeDAllLanes() const {
1190    if (!isSingleSpacedVectorAllLanes()) return false;
1191    return VectorList.Count == 3;
1192  }
1193
1194  bool isVecListThreeQAllLanes() const {
1195    if (!isDoubleSpacedVectorAllLanes()) return false;
1196    return VectorList.Count == 3;
1197  }
1198
1199  bool isVecListFourDAllLanes() const {
1200    if (!isSingleSpacedVectorAllLanes()) return false;
1201    return VectorList.Count == 4;
1202  }
1203
1204  bool isVecListFourQAllLanes() const {
1205    if (!isDoubleSpacedVectorAllLanes()) return false;
1206    return VectorList.Count == 4;
1207  }
1208
1209  bool isSingleSpacedVectorIndexed() const {
1210    return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1211  }
1212  bool isDoubleSpacedVectorIndexed() const {
1213    return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1214  }
1215  bool isVecListOneDByteIndexed() const {
1216    if (!isSingleSpacedVectorIndexed()) return false;
1217    return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1218  }
1219
1220  bool isVecListOneDHWordIndexed() const {
1221    if (!isSingleSpacedVectorIndexed()) return false;
1222    return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1223  }
1224
1225  bool isVecListOneDWordIndexed() const {
1226    if (!isSingleSpacedVectorIndexed()) return false;
1227    return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1228  }
1229
1230  bool isVecListTwoDByteIndexed() const {
1231    if (!isSingleSpacedVectorIndexed()) return false;
1232    return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1233  }
1234
1235  bool isVecListTwoDHWordIndexed() const {
1236    if (!isSingleSpacedVectorIndexed()) return false;
1237    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1238  }
1239
1240  bool isVecListTwoQWordIndexed() const {
1241    if (!isDoubleSpacedVectorIndexed()) return false;
1242    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1243  }
1244
1245  bool isVecListTwoQHWordIndexed() const {
1246    if (!isDoubleSpacedVectorIndexed()) return false;
1247    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1248  }
1249
1250  bool isVecListTwoDWordIndexed() const {
1251    if (!isSingleSpacedVectorIndexed()) return false;
1252    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1253  }
1254
1255  bool isVecListThreeDByteIndexed() const {
1256    if (!isSingleSpacedVectorIndexed()) return false;
1257    return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1258  }
1259
1260  bool isVecListThreeDHWordIndexed() const {
1261    if (!isSingleSpacedVectorIndexed()) return false;
1262    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1263  }
1264
1265  bool isVecListThreeQWordIndexed() const {
1266    if (!isDoubleSpacedVectorIndexed()) return false;
1267    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1268  }
1269
1270  bool isVecListThreeQHWordIndexed() const {
1271    if (!isDoubleSpacedVectorIndexed()) return false;
1272    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1273  }
1274
1275  bool isVecListThreeDWordIndexed() const {
1276    if (!isSingleSpacedVectorIndexed()) return false;
1277    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1278  }
1279
1280  bool isVecListFourDByteIndexed() const {
1281    if (!isSingleSpacedVectorIndexed()) return false;
1282    return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1283  }
1284
1285  bool isVecListFourDHWordIndexed() const {
1286    if (!isSingleSpacedVectorIndexed()) return false;
1287    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1288  }
1289
1290  bool isVecListFourQWordIndexed() const {
1291    if (!isDoubleSpacedVectorIndexed()) return false;
1292    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1293  }
1294
1295  bool isVecListFourQHWordIndexed() const {
1296    if (!isDoubleSpacedVectorIndexed()) return false;
1297    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1298  }
1299
1300  bool isVecListFourDWordIndexed() const {
1301    if (!isSingleSpacedVectorIndexed()) return false;
1302    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1303  }
1304
1305  bool isVectorIndex8() const {
1306    if (Kind != k_VectorIndex) return false;
1307    return VectorIndex.Val < 8;
1308  }
1309  bool isVectorIndex16() const {
1310    if (Kind != k_VectorIndex) return false;
1311    return VectorIndex.Val < 4;
1312  }
1313  bool isVectorIndex32() const {
1314    if (Kind != k_VectorIndex) return false;
1315    return VectorIndex.Val < 2;
1316  }
1317
1318  bool isNEONi8splat() const {
1319    if (!isImm()) return false;
1320    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1321    // Must be a constant.
1322    if (!CE) return false;
1323    int64_t Value = CE->getValue();
1324    // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1325    // value.
1326    return Value >= 0 && Value < 256;
1327  }
1328
1329  bool isNEONi16splat() const {
1330    if (!isImm()) return false;
1331    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1332    // Must be a constant.
1333    if (!CE) return false;
1334    int64_t Value = CE->getValue();
1335    // i16 value in the range [0,255] or [0x0100, 0xff00]
1336    return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1337  }
1338
1339  bool isNEONi32splat() const {
1340    if (!isImm()) return false;
1341    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1342    // Must be a constant.
1343    if (!CE) return false;
1344    int64_t Value = CE->getValue();
1345    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1346    return (Value >= 0 && Value < 256) ||
1347      (Value >= 0x0100 && Value <= 0xff00) ||
1348      (Value >= 0x010000 && Value <= 0xff0000) ||
1349      (Value >= 0x01000000 && Value <= 0xff000000);
1350  }
1351
1352  bool isNEONi32vmov() const {
1353    if (!isImm()) return false;
1354    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1355    // Must be a constant.
1356    if (!CE) return false;
1357    int64_t Value = CE->getValue();
1358    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1359    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1360    return (Value >= 0 && Value < 256) ||
1361      (Value >= 0x0100 && Value <= 0xff00) ||
1362      (Value >= 0x010000 && Value <= 0xff0000) ||
1363      (Value >= 0x01000000 && Value <= 0xff000000) ||
1364      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1365      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1366  }
1367  bool isNEONi32vmovNeg() const {
1368    if (!isImm()) return false;
1369    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1370    // Must be a constant.
1371    if (!CE) return false;
1372    int64_t Value = ~CE->getValue();
1373    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1374    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1375    return (Value >= 0 && Value < 256) ||
1376      (Value >= 0x0100 && Value <= 0xff00) ||
1377      (Value >= 0x010000 && Value <= 0xff0000) ||
1378      (Value >= 0x01000000 && Value <= 0xff000000) ||
1379      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1380      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1381  }
1382
1383  bool isNEONi64splat() const {
1384    if (!isImm()) return false;
1385    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1386    // Must be a constant.
1387    if (!CE) return false;
1388    uint64_t Value = CE->getValue();
1389    // i64 value with each byte being either 0 or 0xff.
1390    for (unsigned i = 0; i < 8; ++i)
1391      if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1392    return true;
1393  }
1394
1395  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1396    // Add as immediates when possible.  Null MCExpr = 0.
1397    if (Expr == 0)
1398      Inst.addOperand(MCOperand::CreateImm(0));
1399    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1400      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1401    else
1402      Inst.addOperand(MCOperand::CreateExpr(Expr));
1403  }
1404
1405  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1406    assert(N == 2 && "Invalid number of operands!");
1407    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1408    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1409    Inst.addOperand(MCOperand::CreateReg(RegNum));
1410  }
1411
1412  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1413    assert(N == 1 && "Invalid number of operands!");
1414    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1415  }
1416
1417  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1418    assert(N == 1 && "Invalid number of operands!");
1419    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1420  }
1421
1422  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1423    assert(N == 1 && "Invalid number of operands!");
1424    Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1425  }
1426
1427  void addITMaskOperands(MCInst &Inst, unsigned N) const {
1428    assert(N == 1 && "Invalid number of operands!");
1429    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1430  }
1431
1432  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1433    assert(N == 1 && "Invalid number of operands!");
1434    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1435  }
1436
1437  void addCCOutOperands(MCInst &Inst, unsigned N) const {
1438    assert(N == 1 && "Invalid number of operands!");
1439    Inst.addOperand(MCOperand::CreateReg(getReg()));
1440  }
1441
1442  void addRegOperands(MCInst &Inst, unsigned N) const {
1443    assert(N == 1 && "Invalid number of operands!");
1444    Inst.addOperand(MCOperand::CreateReg(getReg()));
1445  }
1446
1447  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1448    assert(N == 3 && "Invalid number of operands!");
1449    assert(isRegShiftedReg() &&
1450           "addRegShiftedRegOperands() on non RegShiftedReg!");
1451    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1452    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1453    Inst.addOperand(MCOperand::CreateImm(
1454      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1455  }
1456
1457  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1458    assert(N == 2 && "Invalid number of operands!");
1459    assert(isRegShiftedImm() &&
1460           "addRegShiftedImmOperands() on non RegShiftedImm!");
1461    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1462    // Shift of #32 is encoded as 0 where permitted
1463    unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1464    Inst.addOperand(MCOperand::CreateImm(
1465      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1466  }
1467
1468  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1469    assert(N == 1 && "Invalid number of operands!");
1470    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1471                                         ShifterImm.Imm));
1472  }
1473
1474  void addRegListOperands(MCInst &Inst, unsigned N) const {
1475    assert(N == 1 && "Invalid number of operands!");
1476    const SmallVectorImpl<unsigned> &RegList = getRegList();
1477    for (SmallVectorImpl<unsigned>::const_iterator
1478           I = RegList.begin(), E = RegList.end(); I != E; ++I)
1479      Inst.addOperand(MCOperand::CreateReg(*I));
1480  }
1481
1482  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1483    addRegListOperands(Inst, N);
1484  }
1485
1486  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1487    addRegListOperands(Inst, N);
1488  }
1489
1490  void addRotImmOperands(MCInst &Inst, unsigned N) const {
1491    assert(N == 1 && "Invalid number of operands!");
1492    // Encoded as val>>3. The printer handles display as 8, 16, 24.
1493    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1494  }
1495
1496  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1497    assert(N == 1 && "Invalid number of operands!");
1498    // Munge the lsb/width into a bitfield mask.
1499    unsigned lsb = Bitfield.LSB;
1500    unsigned width = Bitfield.Width;
1501    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1502    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1503                      (32 - (lsb + width)));
1504    Inst.addOperand(MCOperand::CreateImm(Mask));
1505  }
1506
1507  void addImmOperands(MCInst &Inst, unsigned N) const {
1508    assert(N == 1 && "Invalid number of operands!");
1509    addExpr(Inst, getImm());
1510  }
1511
1512  void addFBits16Operands(MCInst &Inst, unsigned N) const {
1513    assert(N == 1 && "Invalid number of operands!");
1514    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1515    Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1516  }
1517
1518  void addFBits32Operands(MCInst &Inst, unsigned N) const {
1519    assert(N == 1 && "Invalid number of operands!");
1520    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1521    Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1522  }
1523
1524  void addFPImmOperands(MCInst &Inst, unsigned N) const {
1525    assert(N == 1 && "Invalid number of operands!");
1526    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1527    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1528    Inst.addOperand(MCOperand::CreateImm(Val));
1529  }
1530
1531  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1532    assert(N == 1 && "Invalid number of operands!");
1533    // FIXME: We really want to scale the value here, but the LDRD/STRD
1534    // instruction don't encode operands that way yet.
1535    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1536    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1537  }
1538
1539  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1540    assert(N == 1 && "Invalid number of operands!");
1541    // The immediate is scaled by four in the encoding and is stored
1542    // in the MCInst as such. Lop off the low two bits here.
1543    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1544    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1545  }
1546
1547  void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1548    assert(N == 1 && "Invalid number of operands!");
1549    // The immediate is scaled by four in the encoding and is stored
1550    // in the MCInst as such. Lop off the low two bits here.
1551    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1552    Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1553  }
1554
1555  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1556    assert(N == 1 && "Invalid number of operands!");
1557    // The immediate is scaled by four in the encoding and is stored
1558    // in the MCInst as such. Lop off the low two bits here.
1559    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1560    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1561  }
1562
1563  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1564    assert(N == 1 && "Invalid number of operands!");
1565    // The constant encodes as the immediate-1, and we store in the instruction
1566    // the bits as encoded, so subtract off one here.
1567    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1568    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1569  }
1570
1571  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1572    assert(N == 1 && "Invalid number of operands!");
1573    // The constant encodes as the immediate-1, and we store in the instruction
1574    // the bits as encoded, so subtract off one here.
1575    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1576    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1577  }
1578
1579  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1580    assert(N == 1 && "Invalid number of operands!");
1581    // The constant encodes as the immediate, except for 32, which encodes as
1582    // zero.
1583    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1584    unsigned Imm = CE->getValue();
1585    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1586  }
1587
1588  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1589    assert(N == 1 && "Invalid number of operands!");
1590    // An ASR value of 32 encodes as 0, so that's how we want to add it to
1591    // the instruction as well.
1592    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1593    int Val = CE->getValue();
1594    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1595  }
1596
1597  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1598    assert(N == 1 && "Invalid number of operands!");
1599    // The operand is actually a t2_so_imm, but we have its bitwise
1600    // negation in the assembly source, so twiddle it here.
1601    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1602    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1603  }
1604
1605  void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1606    assert(N == 1 && "Invalid number of operands!");
1607    // The operand is actually a t2_so_imm, but we have its
1608    // negation in the assembly source, so twiddle it here.
1609    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1610    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1611  }
1612
1613  void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1614    assert(N == 1 && "Invalid number of operands!");
1615    // The operand is actually an imm0_4095, but we have its
1616    // negation in the assembly source, so twiddle it here.
1617    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1618    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1619  }
1620
1621  void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1622    assert(N == 1 && "Invalid number of operands!");
1623    // The operand is actually a so_imm, but we have its bitwise
1624    // negation in the assembly source, so twiddle it here.
1625    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1626    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1627  }
1628
1629  void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1630    assert(N == 1 && "Invalid number of operands!");
1631    // The operand is actually a so_imm, but we have its
1632    // negation in the assembly source, so twiddle it here.
1633    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1634    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1635  }
1636
1637  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1638    assert(N == 1 && "Invalid number of operands!");
1639    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1640  }
1641
1642  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1643    assert(N == 1 && "Invalid number of operands!");
1644    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1645  }
1646
1647  void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1648    assert(N == 1 && "Invalid number of operands!");
1649    int32_t Imm = Memory.OffsetImm->getValue();
1650    // FIXME: Handle #-0
1651    if (Imm == INT32_MIN) Imm = 0;
1652    Inst.addOperand(MCOperand::CreateImm(Imm));
1653  }
1654
1655  void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1656    assert(N == 1 && "Invalid number of operands!");
1657    assert(isImm() && "Not an immediate!");
1658
1659    // If we have an immediate that's not a constant, treat it as a label
1660    // reference needing a fixup.
1661    if (!isa<MCConstantExpr>(getImm())) {
1662      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1663      return;
1664    }
1665
1666    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1667    int Val = CE->getValue();
1668    Inst.addOperand(MCOperand::CreateImm(Val));
1669  }
1670
1671  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1672    assert(N == 2 && "Invalid number of operands!");
1673    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1674    Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1675  }
1676
1677  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1678    assert(N == 3 && "Invalid number of operands!");
1679    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1680    if (!Memory.OffsetRegNum) {
1681      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1682      // Special case for #-0
1683      if (Val == INT32_MIN) Val = 0;
1684      if (Val < 0) Val = -Val;
1685      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1686    } else {
1687      // For register offset, we encode the shift type and negation flag
1688      // here.
1689      Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1690                              Memory.ShiftImm, Memory.ShiftType);
1691    }
1692    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1693    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1694    Inst.addOperand(MCOperand::CreateImm(Val));
1695  }
1696
1697  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1698    assert(N == 2 && "Invalid number of operands!");
1699    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1700    assert(CE && "non-constant AM2OffsetImm operand!");
1701    int32_t Val = CE->getValue();
1702    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1703    // Special case for #-0
1704    if (Val == INT32_MIN) Val = 0;
1705    if (Val < 0) Val = -Val;
1706    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1707    Inst.addOperand(MCOperand::CreateReg(0));
1708    Inst.addOperand(MCOperand::CreateImm(Val));
1709  }
1710
1711  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1712    assert(N == 3 && "Invalid number of operands!");
1713    // If we have an immediate that's not a constant, treat it as a label
1714    // reference needing a fixup. If it is a constant, it's something else
1715    // and we reject it.
1716    if (isImm()) {
1717      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1718      Inst.addOperand(MCOperand::CreateReg(0));
1719      Inst.addOperand(MCOperand::CreateImm(0));
1720      return;
1721    }
1722
1723    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1724    if (!Memory.OffsetRegNum) {
1725      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1726      // Special case for #-0
1727      if (Val == INT32_MIN) Val = 0;
1728      if (Val < 0) Val = -Val;
1729      Val = ARM_AM::getAM3Opc(AddSub, Val);
1730    } else {
1731      // For register offset, we encode the shift type and negation flag
1732      // here.
1733      Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1734    }
1735    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1736    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1737    Inst.addOperand(MCOperand::CreateImm(Val));
1738  }
1739
1740  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1741    assert(N == 2 && "Invalid number of operands!");
1742    if (Kind == k_PostIndexRegister) {
1743      int32_t Val =
1744        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1745      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1746      Inst.addOperand(MCOperand::CreateImm(Val));
1747      return;
1748    }
1749
1750    // Constant offset.
1751    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1752    int32_t Val = CE->getValue();
1753    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1754    // Special case for #-0
1755    if (Val == INT32_MIN) Val = 0;
1756    if (Val < 0) Val = -Val;
1757    Val = ARM_AM::getAM3Opc(AddSub, Val);
1758    Inst.addOperand(MCOperand::CreateReg(0));
1759    Inst.addOperand(MCOperand::CreateImm(Val));
1760  }
1761
1762  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1763    assert(N == 2 && "Invalid number of operands!");
1764    // If we have an immediate that's not a constant, treat it as a label
1765    // reference needing a fixup. If it is a constant, it's something else
1766    // and we reject it.
1767    if (isImm()) {
1768      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1769      Inst.addOperand(MCOperand::CreateImm(0));
1770      return;
1771    }
1772
1773    // The lower two bits are always zero and as such are not encoded.
1774    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1775    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1776    // Special case for #-0
1777    if (Val == INT32_MIN) Val = 0;
1778    if (Val < 0) Val = -Val;
1779    Val = ARM_AM::getAM5Opc(AddSub, Val);
1780    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1781    Inst.addOperand(MCOperand::CreateImm(Val));
1782  }
1783
1784  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1785    assert(N == 2 && "Invalid number of operands!");
1786    // If we have an immediate that's not a constant, treat it as a label
1787    // reference needing a fixup. If it is a constant, it's something else
1788    // and we reject it.
1789    if (isImm()) {
1790      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1791      Inst.addOperand(MCOperand::CreateImm(0));
1792      return;
1793    }
1794
1795    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1796    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1797    Inst.addOperand(MCOperand::CreateImm(Val));
1798  }
1799
1800  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1801    assert(N == 2 && "Invalid number of operands!");
1802    // The lower two bits are always zero and as such are not encoded.
1803    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1804    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1805    Inst.addOperand(MCOperand::CreateImm(Val));
1806  }
1807
1808  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1809    assert(N == 2 && "Invalid number of operands!");
1810    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1811    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1812    Inst.addOperand(MCOperand::CreateImm(Val));
1813  }
1814
1815  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1816    addMemImm8OffsetOperands(Inst, N);
1817  }
1818
1819  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1820    addMemImm8OffsetOperands(Inst, N);
1821  }
1822
1823  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1824    assert(N == 2 && "Invalid number of operands!");
1825    // If this is an immediate, it's a label reference.
1826    if (isImm()) {
1827      addExpr(Inst, getImm());
1828      Inst.addOperand(MCOperand::CreateImm(0));
1829      return;
1830    }
1831
1832    // Otherwise, it's a normal memory reg+offset.
1833    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1834    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1835    Inst.addOperand(MCOperand::CreateImm(Val));
1836  }
1837
1838  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1839    assert(N == 2 && "Invalid number of operands!");
1840    // If this is an immediate, it's a label reference.
1841    if (isImm()) {
1842      addExpr(Inst, getImm());
1843      Inst.addOperand(MCOperand::CreateImm(0));
1844      return;
1845    }
1846
1847    // Otherwise, it's a normal memory reg+offset.
1848    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1849    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1850    Inst.addOperand(MCOperand::CreateImm(Val));
1851  }
1852
1853  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1854    assert(N == 2 && "Invalid number of operands!");
1855    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1856    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1857  }
1858
1859  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1860    assert(N == 2 && "Invalid number of operands!");
1861    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1862    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1863  }
1864
1865  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1866    assert(N == 3 && "Invalid number of operands!");
1867    unsigned Val =
1868      ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1869                        Memory.ShiftImm, Memory.ShiftType);
1870    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1871    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1872    Inst.addOperand(MCOperand::CreateImm(Val));
1873  }
1874
1875  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1876    assert(N == 3 && "Invalid number of operands!");
1877    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1878    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1879    Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1880  }
1881
1882  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1883    assert(N == 2 && "Invalid number of operands!");
1884    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1885    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1886  }
1887
1888  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1889    assert(N == 2 && "Invalid number of operands!");
1890    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1891    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1892    Inst.addOperand(MCOperand::CreateImm(Val));
1893  }
1894
1895  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1896    assert(N == 2 && "Invalid number of operands!");
1897    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1898    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1899    Inst.addOperand(MCOperand::CreateImm(Val));
1900  }
1901
1902  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1903    assert(N == 2 && "Invalid number of operands!");
1904    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1905    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1906    Inst.addOperand(MCOperand::CreateImm(Val));
1907  }
1908
1909  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1910    assert(N == 2 && "Invalid number of operands!");
1911    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1912    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1913    Inst.addOperand(MCOperand::CreateImm(Val));
1914  }
1915
1916  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1917    assert(N == 1 && "Invalid number of operands!");
1918    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1919    assert(CE && "non-constant post-idx-imm8 operand!");
1920    int Imm = CE->getValue();
1921    bool isAdd = Imm >= 0;
1922    if (Imm == INT32_MIN) Imm = 0;
1923    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1924    Inst.addOperand(MCOperand::CreateImm(Imm));
1925  }
1926
1927  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1928    assert(N == 1 && "Invalid number of operands!");
1929    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1930    assert(CE && "non-constant post-idx-imm8s4 operand!");
1931    int Imm = CE->getValue();
1932    bool isAdd = Imm >= 0;
1933    if (Imm == INT32_MIN) Imm = 0;
1934    // Immediate is scaled by 4.
1935    Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1936    Inst.addOperand(MCOperand::CreateImm(Imm));
1937  }
1938
1939  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1940    assert(N == 2 && "Invalid number of operands!");
1941    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1942    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1943  }
1944
1945  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1946    assert(N == 2 && "Invalid number of operands!");
1947    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1948    // The sign, shift type, and shift amount are encoded in a single operand
1949    // using the AM2 encoding helpers.
1950    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1951    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1952                                     PostIdxReg.ShiftTy);
1953    Inst.addOperand(MCOperand::CreateImm(Imm));
1954  }
1955
1956  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1957    assert(N == 1 && "Invalid number of operands!");
1958    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1959  }
1960
1961  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1962    assert(N == 1 && "Invalid number of operands!");
1963    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1964  }
1965
1966  void addVecListOperands(MCInst &Inst, unsigned N) const {
1967    assert(N == 1 && "Invalid number of operands!");
1968    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1969  }
1970
1971  void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
1972    assert(N == 2 && "Invalid number of operands!");
1973    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1974    Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
1975  }
1976
1977  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1978    assert(N == 1 && "Invalid number of operands!");
1979    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1980  }
1981
1982  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1983    assert(N == 1 && "Invalid number of operands!");
1984    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1985  }
1986
1987  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1988    assert(N == 1 && "Invalid number of operands!");
1989    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1990  }
1991
1992  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1993    assert(N == 1 && "Invalid number of operands!");
1994    // The immediate encodes the type of constant as well as the value.
1995    // Mask in that this is an i8 splat.
1996    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1997    Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1998  }
1999
2000  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2001    assert(N == 1 && "Invalid number of operands!");
2002    // The immediate encodes the type of constant as well as the value.
2003    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2004    unsigned Value = CE->getValue();
2005    if (Value >= 256)
2006      Value = (Value >> 8) | 0xa00;
2007    else
2008      Value |= 0x800;
2009    Inst.addOperand(MCOperand::CreateImm(Value));
2010  }
2011
2012  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2013    assert(N == 1 && "Invalid number of operands!");
2014    // The immediate encodes the type of constant as well as the value.
2015    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2016    unsigned Value = CE->getValue();
2017    if (Value >= 256 && Value <= 0xff00)
2018      Value = (Value >> 8) | 0x200;
2019    else if (Value > 0xffff && Value <= 0xff0000)
2020      Value = (Value >> 16) | 0x400;
2021    else if (Value > 0xffffff)
2022      Value = (Value >> 24) | 0x600;
2023    Inst.addOperand(MCOperand::CreateImm(Value));
2024  }
2025
2026  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2027    assert(N == 1 && "Invalid number of operands!");
2028    // The immediate encodes the type of constant as well as the value.
2029    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2030    unsigned Value = CE->getValue();
2031    if (Value >= 256 && Value <= 0xffff)
2032      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2033    else if (Value > 0xffff && Value <= 0xffffff)
2034      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2035    else if (Value > 0xffffff)
2036      Value = (Value >> 24) | 0x600;
2037    Inst.addOperand(MCOperand::CreateImm(Value));
2038  }
2039
2040  void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2041    assert(N == 1 && "Invalid number of operands!");
2042    // The immediate encodes the type of constant as well as the value.
2043    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2044    unsigned Value = ~CE->getValue();
2045    if (Value >= 256 && Value <= 0xffff)
2046      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2047    else if (Value > 0xffff && Value <= 0xffffff)
2048      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2049    else if (Value > 0xffffff)
2050      Value = (Value >> 24) | 0x600;
2051    Inst.addOperand(MCOperand::CreateImm(Value));
2052  }
2053
2054  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2055    assert(N == 1 && "Invalid number of operands!");
2056    // The immediate encodes the type of constant as well as the value.
2057    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2058    uint64_t Value = CE->getValue();
2059    unsigned Imm = 0;
2060    for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2061      Imm |= (Value & 1) << i;
2062    }
2063    Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2064  }
2065
2066  virtual void print(raw_ostream &OS) const;
2067
2068  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2069    ARMOperand *Op = new ARMOperand(k_ITCondMask);
2070    Op->ITMask.Mask = Mask;
2071    Op->StartLoc = S;
2072    Op->EndLoc = S;
2073    return Op;
2074  }
2075
2076  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2077    ARMOperand *Op = new ARMOperand(k_CondCode);
2078    Op->CC.Val = CC;
2079    Op->StartLoc = S;
2080    Op->EndLoc = S;
2081    return Op;
2082  }
2083
2084  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2085    ARMOperand *Op = new ARMOperand(k_CoprocNum);
2086    Op->Cop.Val = CopVal;
2087    Op->StartLoc = S;
2088    Op->EndLoc = S;
2089    return Op;
2090  }
2091
2092  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2093    ARMOperand *Op = new ARMOperand(k_CoprocReg);
2094    Op->Cop.Val = CopVal;
2095    Op->StartLoc = S;
2096    Op->EndLoc = S;
2097    return Op;
2098  }
2099
2100  static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2101    ARMOperand *Op = new ARMOperand(k_CoprocOption);
2102    Op->Cop.Val = Val;
2103    Op->StartLoc = S;
2104    Op->EndLoc = E;
2105    return Op;
2106  }
2107
2108  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2109    ARMOperand *Op = new ARMOperand(k_CCOut);
2110    Op->Reg.RegNum = RegNum;
2111    Op->StartLoc = S;
2112    Op->EndLoc = S;
2113    return Op;
2114  }
2115
2116  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2117    ARMOperand *Op = new ARMOperand(k_Token);
2118    Op->Tok.Data = Str.data();
2119    Op->Tok.Length = Str.size();
2120    Op->StartLoc = S;
2121    Op->EndLoc = S;
2122    return Op;
2123  }
2124
2125  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2126    ARMOperand *Op = new ARMOperand(k_Register);
2127    Op->Reg.RegNum = RegNum;
2128    Op->StartLoc = S;
2129    Op->EndLoc = E;
2130    return Op;
2131  }
2132
2133  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2134                                           unsigned SrcReg,
2135                                           unsigned ShiftReg,
2136                                           unsigned ShiftImm,
2137                                           SMLoc S, SMLoc E) {
2138    ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2139    Op->RegShiftedReg.ShiftTy = ShTy;
2140    Op->RegShiftedReg.SrcReg = SrcReg;
2141    Op->RegShiftedReg.ShiftReg = ShiftReg;
2142    Op->RegShiftedReg.ShiftImm = ShiftImm;
2143    Op->StartLoc = S;
2144    Op->EndLoc = E;
2145    return Op;
2146  }
2147
2148  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2149                                            unsigned SrcReg,
2150                                            unsigned ShiftImm,
2151                                            SMLoc S, SMLoc E) {
2152    ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2153    Op->RegShiftedImm.ShiftTy = ShTy;
2154    Op->RegShiftedImm.SrcReg = SrcReg;
2155    Op->RegShiftedImm.ShiftImm = ShiftImm;
2156    Op->StartLoc = S;
2157    Op->EndLoc = E;
2158    return Op;
2159  }
2160
2161  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2162                                   SMLoc S, SMLoc E) {
2163    ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2164    Op->ShifterImm.isASR = isASR;
2165    Op->ShifterImm.Imm = Imm;
2166    Op->StartLoc = S;
2167    Op->EndLoc = E;
2168    return Op;
2169  }
2170
2171  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2172    ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2173    Op->RotImm.Imm = Imm;
2174    Op->StartLoc = S;
2175    Op->EndLoc = E;
2176    return Op;
2177  }
2178
2179  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2180                                    SMLoc S, SMLoc E) {
2181    ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2182    Op->Bitfield.LSB = LSB;
2183    Op->Bitfield.Width = Width;
2184    Op->StartLoc = S;
2185    Op->EndLoc = E;
2186    return Op;
2187  }
2188
2189  static ARMOperand *
2190  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
2191                SMLoc StartLoc, SMLoc EndLoc) {
2192    KindTy Kind = k_RegisterList;
2193
2194    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
2195      Kind = k_DPRRegisterList;
2196    else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2197             contains(Regs.front().first))
2198      Kind = k_SPRRegisterList;
2199
2200    ARMOperand *Op = new ARMOperand(Kind);
2201    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
2202           I = Regs.begin(), E = Regs.end(); I != E; ++I)
2203      Op->Registers.push_back(I->first);
2204    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
2205    Op->StartLoc = StartLoc;
2206    Op->EndLoc = EndLoc;
2207    return Op;
2208  }
2209
2210  static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2211                                      bool isDoubleSpaced, SMLoc S, SMLoc E) {
2212    ARMOperand *Op = new ARMOperand(k_VectorList);
2213    Op->VectorList.RegNum = RegNum;
2214    Op->VectorList.Count = Count;
2215    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2216    Op->StartLoc = S;
2217    Op->EndLoc = E;
2218    return Op;
2219  }
2220
2221  static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2222                                              bool isDoubleSpaced,
2223                                              SMLoc S, SMLoc E) {
2224    ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2225    Op->VectorList.RegNum = RegNum;
2226    Op->VectorList.Count = Count;
2227    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2228    Op->StartLoc = S;
2229    Op->EndLoc = E;
2230    return Op;
2231  }
2232
2233  static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2234                                             unsigned Index,
2235                                             bool isDoubleSpaced,
2236                                             SMLoc S, SMLoc E) {
2237    ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2238    Op->VectorList.RegNum = RegNum;
2239    Op->VectorList.Count = Count;
2240    Op->VectorList.LaneIndex = Index;
2241    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2242    Op->StartLoc = S;
2243    Op->EndLoc = E;
2244    return Op;
2245  }
2246
2247  static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2248                                       MCContext &Ctx) {
2249    ARMOperand *Op = new ARMOperand(k_VectorIndex);
2250    Op->VectorIndex.Val = Idx;
2251    Op->StartLoc = S;
2252    Op->EndLoc = E;
2253    return Op;
2254  }
2255
2256  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2257    ARMOperand *Op = new ARMOperand(k_Immediate);
2258    Op->Imm.Val = Val;
2259    Op->StartLoc = S;
2260    Op->EndLoc = E;
2261    return Op;
2262  }
2263
2264  static ARMOperand *CreateMem(unsigned BaseRegNum,
2265                               const MCConstantExpr *OffsetImm,
2266                               unsigned OffsetRegNum,
2267                               ARM_AM::ShiftOpc ShiftType,
2268                               unsigned ShiftImm,
2269                               unsigned Alignment,
2270                               bool isNegative,
2271                               SMLoc S, SMLoc E) {
2272    ARMOperand *Op = new ARMOperand(k_Memory);
2273    Op->Memory.BaseRegNum = BaseRegNum;
2274    Op->Memory.OffsetImm = OffsetImm;
2275    Op->Memory.OffsetRegNum = OffsetRegNum;
2276    Op->Memory.ShiftType = ShiftType;
2277    Op->Memory.ShiftImm = ShiftImm;
2278    Op->Memory.Alignment = Alignment;
2279    Op->Memory.isNegative = isNegative;
2280    Op->StartLoc = S;
2281    Op->EndLoc = E;
2282    return Op;
2283  }
2284
2285  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2286                                      ARM_AM::ShiftOpc ShiftTy,
2287                                      unsigned ShiftImm,
2288                                      SMLoc S, SMLoc E) {
2289    ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2290    Op->PostIdxReg.RegNum = RegNum;
2291    Op->PostIdxReg.isAdd = isAdd;
2292    Op->PostIdxReg.ShiftTy = ShiftTy;
2293    Op->PostIdxReg.ShiftImm = ShiftImm;
2294    Op->StartLoc = S;
2295    Op->EndLoc = E;
2296    return Op;
2297  }
2298
2299  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2300    ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2301    Op->MBOpt.Val = Opt;
2302    Op->StartLoc = S;
2303    Op->EndLoc = S;
2304    return Op;
2305  }
2306
2307  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2308    ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2309    Op->IFlags.Val = IFlags;
2310    Op->StartLoc = S;
2311    Op->EndLoc = S;
2312    return Op;
2313  }
2314
2315  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2316    ARMOperand *Op = new ARMOperand(k_MSRMask);
2317    Op->MMask.Val = MMask;
2318    Op->StartLoc = S;
2319    Op->EndLoc = S;
2320    return Op;
2321  }
2322};
2323
2324} // end anonymous namespace.
2325
2326void ARMOperand::print(raw_ostream &OS) const {
2327  switch (Kind) {
2328  case k_CondCode:
2329    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2330    break;
2331  case k_CCOut:
2332    OS << "<ccout " << getReg() << ">";
2333    break;
2334  case k_ITCondMask: {
2335    static const char *const MaskStr[] = {
2336      "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2337      "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2338    };
2339    assert((ITMask.Mask & 0xf) == ITMask.Mask);
2340    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2341    break;
2342  }
2343  case k_CoprocNum:
2344    OS << "<coprocessor number: " << getCoproc() << ">";
2345    break;
2346  case k_CoprocReg:
2347    OS << "<coprocessor register: " << getCoproc() << ">";
2348    break;
2349  case k_CoprocOption:
2350    OS << "<coprocessor option: " << CoprocOption.Val << ">";
2351    break;
2352  case k_MSRMask:
2353    OS << "<mask: " << getMSRMask() << ">";
2354    break;
2355  case k_Immediate:
2356    getImm()->print(OS);
2357    break;
2358  case k_MemBarrierOpt:
2359    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2360    break;
2361  case k_Memory:
2362    OS << "<memory "
2363       << " base:" << Memory.BaseRegNum;
2364    OS << ">";
2365    break;
2366  case k_PostIndexRegister:
2367    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2368       << PostIdxReg.RegNum;
2369    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2370      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2371         << PostIdxReg.ShiftImm;
2372    OS << ">";
2373    break;
2374  case k_ProcIFlags: {
2375    OS << "<ARM_PROC::";
2376    unsigned IFlags = getProcIFlags();
2377    for (int i=2; i >= 0; --i)
2378      if (IFlags & (1 << i))
2379        OS << ARM_PROC::IFlagsToString(1 << i);
2380    OS << ">";
2381    break;
2382  }
2383  case k_Register:
2384    OS << "<register " << getReg() << ">";
2385    break;
2386  case k_ShifterImmediate:
2387    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2388       << " #" << ShifterImm.Imm << ">";
2389    break;
2390  case k_ShiftedRegister:
2391    OS << "<so_reg_reg "
2392       << RegShiftedReg.SrcReg << " "
2393       << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2394       << " " << RegShiftedReg.ShiftReg << ">";
2395    break;
2396  case k_ShiftedImmediate:
2397    OS << "<so_reg_imm "
2398       << RegShiftedImm.SrcReg << " "
2399       << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2400       << " #" << RegShiftedImm.ShiftImm << ">";
2401    break;
2402  case k_RotateImmediate:
2403    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2404    break;
2405  case k_BitfieldDescriptor:
2406    OS << "<bitfield " << "lsb: " << Bitfield.LSB
2407       << ", width: " << Bitfield.Width << ">";
2408    break;
2409  case k_RegisterList:
2410  case k_DPRRegisterList:
2411  case k_SPRRegisterList: {
2412    OS << "<register_list ";
2413
2414    const SmallVectorImpl<unsigned> &RegList = getRegList();
2415    for (SmallVectorImpl<unsigned>::const_iterator
2416           I = RegList.begin(), E = RegList.end(); I != E; ) {
2417      OS << *I;
2418      if (++I < E) OS << ", ";
2419    }
2420
2421    OS << ">";
2422    break;
2423  }
2424  case k_VectorList:
2425    OS << "<vector_list " << VectorList.Count << " * "
2426       << VectorList.RegNum << ">";
2427    break;
2428  case k_VectorListAllLanes:
2429    OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2430       << VectorList.RegNum << ">";
2431    break;
2432  case k_VectorListIndexed:
2433    OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2434       << VectorList.Count << " * " << VectorList.RegNum << ">";
2435    break;
2436  case k_Token:
2437    OS << "'" << getToken() << "'";
2438    break;
2439  case k_VectorIndex:
2440    OS << "<vectorindex " << getVectorIndex() << ">";
2441    break;
2442  }
2443}
2444
2445/// @name Auto-generated Match Functions
2446/// {
2447
2448static unsigned MatchRegisterName(StringRef Name);
2449
2450/// }
2451
2452bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2453                                 SMLoc &StartLoc, SMLoc &EndLoc) {
2454  StartLoc = Parser.getTok().getLoc();
2455  RegNo = tryParseRegister();
2456  EndLoc = Parser.getTok().getLoc();
2457
2458  return (RegNo == (unsigned)-1);
2459}
2460
2461/// Try to parse a register name.  The token must be an Identifier when called,
2462/// and if it is a register name the token is eaten and the register number is
2463/// returned.  Otherwise return -1.
2464///
2465int ARMAsmParser::tryParseRegister() {
2466  const AsmToken &Tok = Parser.getTok();
2467  if (Tok.isNot(AsmToken::Identifier)) return -1;
2468
2469  std::string lowerCase = Tok.getString().lower();
2470  unsigned RegNum = MatchRegisterName(lowerCase);
2471  if (!RegNum) {
2472    RegNum = StringSwitch<unsigned>(lowerCase)
2473      .Case("r13", ARM::SP)
2474      .Case("r14", ARM::LR)
2475      .Case("r15", ARM::PC)
2476      .Case("ip", ARM::R12)
2477      // Additional register name aliases for 'gas' compatibility.
2478      .Case("a1", ARM::R0)
2479      .Case("a2", ARM::R1)
2480      .Case("a3", ARM::R2)
2481      .Case("a4", ARM::R3)
2482      .Case("v1", ARM::R4)
2483      .Case("v2", ARM::R5)
2484      .Case("v3", ARM::R6)
2485      .Case("v4", ARM::R7)
2486      .Case("v5", ARM::R8)
2487      .Case("v6", ARM::R9)
2488      .Case("v7", ARM::R10)
2489      .Case("v8", ARM::R11)
2490      .Case("sb", ARM::R9)
2491      .Case("sl", ARM::R10)
2492      .Case("fp", ARM::R11)
2493      .Default(0);
2494  }
2495  if (!RegNum) {
2496    // Check for aliases registered via .req. Canonicalize to lower case.
2497    // That's more consistent since register names are case insensitive, and
2498    // it's how the original entry was passed in from MC/MCParser/AsmParser.
2499    StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2500    // If no match, return failure.
2501    if (Entry == RegisterReqs.end())
2502      return -1;
2503    Parser.Lex(); // Eat identifier token.
2504    return Entry->getValue();
2505  }
2506
2507  Parser.Lex(); // Eat identifier token.
2508
2509  return RegNum;
2510}
2511
2512// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2513// If a recoverable error occurs, return 1. If an irrecoverable error
2514// occurs, return -1. An irrecoverable error is one where tokens have been
2515// consumed in the process of trying to parse the shifter (i.e., when it is
2516// indeed a shifter operand, but malformed).
2517int ARMAsmParser::tryParseShiftRegister(
2518                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2519  SMLoc S = Parser.getTok().getLoc();
2520  const AsmToken &Tok = Parser.getTok();
2521  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2522
2523  std::string lowerCase = Tok.getString().lower();
2524  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2525      .Case("asl", ARM_AM::lsl)
2526      .Case("lsl", ARM_AM::lsl)
2527      .Case("lsr", ARM_AM::lsr)
2528      .Case("asr", ARM_AM::asr)
2529      .Case("ror", ARM_AM::ror)
2530      .Case("rrx", ARM_AM::rrx)
2531      .Default(ARM_AM::no_shift);
2532
2533  if (ShiftTy == ARM_AM::no_shift)
2534    return 1;
2535
2536  Parser.Lex(); // Eat the operator.
2537
2538  // The source register for the shift has already been added to the
2539  // operand list, so we need to pop it off and combine it into the shifted
2540  // register operand instead.
2541  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2542  if (!PrevOp->isReg())
2543    return Error(PrevOp->getStartLoc(), "shift must be of a register");
2544  int SrcReg = PrevOp->getReg();
2545  int64_t Imm = 0;
2546  int ShiftReg = 0;
2547  if (ShiftTy == ARM_AM::rrx) {
2548    // RRX Doesn't have an explicit shift amount. The encoder expects
2549    // the shift register to be the same as the source register. Seems odd,
2550    // but OK.
2551    ShiftReg = SrcReg;
2552  } else {
2553    // Figure out if this is shifted by a constant or a register (for non-RRX).
2554    if (Parser.getTok().is(AsmToken::Hash) ||
2555        Parser.getTok().is(AsmToken::Dollar)) {
2556      Parser.Lex(); // Eat hash.
2557      SMLoc ImmLoc = Parser.getTok().getLoc();
2558      const MCExpr *ShiftExpr = 0;
2559      if (getParser().ParseExpression(ShiftExpr)) {
2560        Error(ImmLoc, "invalid immediate shift value");
2561        return -1;
2562      }
2563      // The expression must be evaluatable as an immediate.
2564      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2565      if (!CE) {
2566        Error(ImmLoc, "invalid immediate shift value");
2567        return -1;
2568      }
2569      // Range check the immediate.
2570      // lsl, ror: 0 <= imm <= 31
2571      // lsr, asr: 0 <= imm <= 32
2572      Imm = CE->getValue();
2573      if (Imm < 0 ||
2574          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2575          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2576        Error(ImmLoc, "immediate shift value out of range");
2577        return -1;
2578      }
2579      // shift by zero is a nop. Always send it through as lsl.
2580      // ('as' compatibility)
2581      if (Imm == 0)
2582        ShiftTy = ARM_AM::lsl;
2583    } else if (Parser.getTok().is(AsmToken::Identifier)) {
2584      ShiftReg = tryParseRegister();
2585      SMLoc L = Parser.getTok().getLoc();
2586      if (ShiftReg == -1) {
2587        Error (L, "expected immediate or register in shift operand");
2588        return -1;
2589      }
2590    } else {
2591      Error (Parser.getTok().getLoc(),
2592                    "expected immediate or register in shift operand");
2593      return -1;
2594    }
2595  }
2596
2597  if (ShiftReg && ShiftTy != ARM_AM::rrx)
2598    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2599                                                         ShiftReg, Imm,
2600                                               S, Parser.getTok().getLoc()));
2601  else
2602    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2603                                               S, Parser.getTok().getLoc()));
2604
2605  return 0;
2606}
2607
2608
2609/// Try to parse a register name.  The token must be an Identifier when called.
2610/// If it's a register, an AsmOperand is created. Another AsmOperand is created
2611/// if there is a "writeback". 'true' if it's not a register.
2612///
2613/// TODO this is likely to change to allow different register types and or to
2614/// parse for a specific register type.
2615bool ARMAsmParser::
2616tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2617  SMLoc S = Parser.getTok().getLoc();
2618  int RegNo = tryParseRegister();
2619  if (RegNo == -1)
2620    return true;
2621
2622  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2623
2624  const AsmToken &ExclaimTok = Parser.getTok();
2625  if (ExclaimTok.is(AsmToken::Exclaim)) {
2626    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2627                                               ExclaimTok.getLoc()));
2628    Parser.Lex(); // Eat exclaim token
2629    return false;
2630  }
2631
2632  // Also check for an index operand. This is only legal for vector registers,
2633  // but that'll get caught OK in operand matching, so we don't need to
2634  // explicitly filter everything else out here.
2635  if (Parser.getTok().is(AsmToken::LBrac)) {
2636    SMLoc SIdx = Parser.getTok().getLoc();
2637    Parser.Lex(); // Eat left bracket token.
2638
2639    const MCExpr *ImmVal;
2640    if (getParser().ParseExpression(ImmVal))
2641      return true;
2642    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2643    if (!MCE)
2644      return TokError("immediate value expected for vector index");
2645
2646    SMLoc E = Parser.getTok().getLoc();
2647    if (Parser.getTok().isNot(AsmToken::RBrac))
2648      return Error(E, "']' expected");
2649
2650    Parser.Lex(); // Eat right bracket token.
2651
2652    Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2653                                                     SIdx, E,
2654                                                     getContext()));
2655  }
2656
2657  return false;
2658}
2659
2660/// MatchCoprocessorOperandName - Try to parse an coprocessor related
2661/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2662/// "c5", ...
2663static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2664  // Use the same layout as the tablegen'erated register name matcher. Ugly,
2665  // but efficient.
2666  switch (Name.size()) {
2667  default: return -1;
2668  case 2:
2669    if (Name[0] != CoprocOp)
2670      return -1;
2671    switch (Name[1]) {
2672    default:  return -1;
2673    case '0': return 0;
2674    case '1': return 1;
2675    case '2': return 2;
2676    case '3': return 3;
2677    case '4': return 4;
2678    case '5': return 5;
2679    case '6': return 6;
2680    case '7': return 7;
2681    case '8': return 8;
2682    case '9': return 9;
2683    }
2684  case 3:
2685    if (Name[0] != CoprocOp || Name[1] != '1')
2686      return -1;
2687    switch (Name[2]) {
2688    default:  return -1;
2689    case '0': return 10;
2690    case '1': return 11;
2691    case '2': return 12;
2692    case '3': return 13;
2693    case '4': return 14;
2694    case '5': return 15;
2695    }
2696  }
2697}
2698
2699/// parseITCondCode - Try to parse a condition code for an IT instruction.
2700ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2701parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2702  SMLoc S = Parser.getTok().getLoc();
2703  const AsmToken &Tok = Parser.getTok();
2704  if (!Tok.is(AsmToken::Identifier))
2705    return MatchOperand_NoMatch;
2706  unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2707    .Case("eq", ARMCC::EQ)
2708    .Case("ne", ARMCC::NE)
2709    .Case("hs", ARMCC::HS)
2710    .Case("cs", ARMCC::HS)
2711    .Case("lo", ARMCC::LO)
2712    .Case("cc", ARMCC::LO)
2713    .Case("mi", ARMCC::MI)
2714    .Case("pl", ARMCC::PL)
2715    .Case("vs", ARMCC::VS)
2716    .Case("vc", ARMCC::VC)
2717    .Case("hi", ARMCC::HI)
2718    .Case("ls", ARMCC::LS)
2719    .Case("ge", ARMCC::GE)
2720    .Case("lt", ARMCC::LT)
2721    .Case("gt", ARMCC::GT)
2722    .Case("le", ARMCC::LE)
2723    .Case("al", ARMCC::AL)
2724    .Default(~0U);
2725  if (CC == ~0U)
2726    return MatchOperand_NoMatch;
2727  Parser.Lex(); // Eat the token.
2728
2729  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2730
2731  return MatchOperand_Success;
2732}
2733
2734/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2735/// token must be an Identifier when called, and if it is a coprocessor
2736/// number, the token is eaten and the operand is added to the operand list.
2737ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2738parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2739  SMLoc S = Parser.getTok().getLoc();
2740  const AsmToken &Tok = Parser.getTok();
2741  if (Tok.isNot(AsmToken::Identifier))
2742    return MatchOperand_NoMatch;
2743
2744  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2745  if (Num == -1)
2746    return MatchOperand_NoMatch;
2747
2748  Parser.Lex(); // Eat identifier token.
2749  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2750  return MatchOperand_Success;
2751}
2752
2753/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2754/// token must be an Identifier when called, and if it is a coprocessor
2755/// number, the token is eaten and the operand is added to the operand list.
2756ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2757parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2758  SMLoc S = Parser.getTok().getLoc();
2759  const AsmToken &Tok = Parser.getTok();
2760  if (Tok.isNot(AsmToken::Identifier))
2761    return MatchOperand_NoMatch;
2762
2763  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2764  if (Reg == -1)
2765    return MatchOperand_NoMatch;
2766
2767  Parser.Lex(); // Eat identifier token.
2768  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2769  return MatchOperand_Success;
2770}
2771
2772/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2773/// coproc_option : '{' imm0_255 '}'
2774ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2775parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2776  SMLoc S = Parser.getTok().getLoc();
2777
2778  // If this isn't a '{', this isn't a coprocessor immediate operand.
2779  if (Parser.getTok().isNot(AsmToken::LCurly))
2780    return MatchOperand_NoMatch;
2781  Parser.Lex(); // Eat the '{'
2782
2783  const MCExpr *Expr;
2784  SMLoc Loc = Parser.getTok().getLoc();
2785  if (getParser().ParseExpression(Expr)) {
2786    Error(Loc, "illegal expression");
2787    return MatchOperand_ParseFail;
2788  }
2789  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2790  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2791    Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2792    return MatchOperand_ParseFail;
2793  }
2794  int Val = CE->getValue();
2795
2796  // Check for and consume the closing '}'
2797  if (Parser.getTok().isNot(AsmToken::RCurly))
2798    return MatchOperand_ParseFail;
2799  SMLoc E = Parser.getTok().getLoc();
2800  Parser.Lex(); // Eat the '}'
2801
2802  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2803  return MatchOperand_Success;
2804}
2805
2806// For register list parsing, we need to map from raw GPR register numbering
2807// to the enumeration values. The enumeration values aren't sorted by
2808// register number due to our using "sp", "lr" and "pc" as canonical names.
2809static unsigned getNextRegister(unsigned Reg) {
2810  // If this is a GPR, we need to do it manually, otherwise we can rely
2811  // on the sort ordering of the enumeration since the other reg-classes
2812  // are sane.
2813  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2814    return Reg + 1;
2815  switch(Reg) {
2816  default: llvm_unreachable("Invalid GPR number!");
2817  case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
2818  case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
2819  case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
2820  case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
2821  case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
2822  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2823  case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
2824  case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
2825  }
2826}
2827
2828// Return the low-subreg of a given Q register.
2829static unsigned getDRegFromQReg(unsigned QReg) {
2830  switch (QReg) {
2831  default: llvm_unreachable("expected a Q register!");
2832  case ARM::Q0:  return ARM::D0;
2833  case ARM::Q1:  return ARM::D2;
2834  case ARM::Q2:  return ARM::D4;
2835  case ARM::Q3:  return ARM::D6;
2836  case ARM::Q4:  return ARM::D8;
2837  case ARM::Q5:  return ARM::D10;
2838  case ARM::Q6:  return ARM::D12;
2839  case ARM::Q7:  return ARM::D14;
2840  case ARM::Q8:  return ARM::D16;
2841  case ARM::Q9:  return ARM::D18;
2842  case ARM::Q10: return ARM::D20;
2843  case ARM::Q11: return ARM::D22;
2844  case ARM::Q12: return ARM::D24;
2845  case ARM::Q13: return ARM::D26;
2846  case ARM::Q14: return ARM::D28;
2847  case ARM::Q15: return ARM::D30;
2848  }
2849}
2850
2851/// Parse a register list.
2852bool ARMAsmParser::
2853parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2854  assert(Parser.getTok().is(AsmToken::LCurly) &&
2855         "Token is not a Left Curly Brace");
2856  SMLoc S = Parser.getTok().getLoc();
2857  Parser.Lex(); // Eat '{' token.
2858  SMLoc RegLoc = Parser.getTok().getLoc();
2859
2860  // Check the first register in the list to see what register class
2861  // this is a list of.
2862  int Reg = tryParseRegister();
2863  if (Reg == -1)
2864    return Error(RegLoc, "register expected");
2865
2866  // The reglist instructions have at most 16 registers, so reserve
2867  // space for that many.
2868  SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2869
2870  // Allow Q regs and just interpret them as the two D sub-registers.
2871  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2872    Reg = getDRegFromQReg(Reg);
2873    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2874    ++Reg;
2875  }
2876  const MCRegisterClass *RC;
2877  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2878    RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2879  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2880    RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2881  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2882    RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2883  else
2884    return Error(RegLoc, "invalid register in register list");
2885
2886  // Store the register.
2887  Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2888
2889  // This starts immediately after the first register token in the list,
2890  // so we can see either a comma or a minus (range separator) as a legal
2891  // next token.
2892  while (Parser.getTok().is(AsmToken::Comma) ||
2893         Parser.getTok().is(AsmToken::Minus)) {
2894    if (Parser.getTok().is(AsmToken::Minus)) {
2895      Parser.Lex(); // Eat the minus.
2896      SMLoc EndLoc = Parser.getTok().getLoc();
2897      int EndReg = tryParseRegister();
2898      if (EndReg == -1)
2899        return Error(EndLoc, "register expected");
2900      // Allow Q regs and just interpret them as the two D sub-registers.
2901      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2902        EndReg = getDRegFromQReg(EndReg) + 1;
2903      // If the register is the same as the start reg, there's nothing
2904      // more to do.
2905      if (Reg == EndReg)
2906        continue;
2907      // The register must be in the same register class as the first.
2908      if (!RC->contains(EndReg))
2909        return Error(EndLoc, "invalid register in register list");
2910      // Ranges must go from low to high.
2911      if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
2912        return Error(EndLoc, "bad range in register list");
2913
2914      // Add all the registers in the range to the register list.
2915      while (Reg != EndReg) {
2916        Reg = getNextRegister(Reg);
2917        Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2918      }
2919      continue;
2920    }
2921    Parser.Lex(); // Eat the comma.
2922    RegLoc = Parser.getTok().getLoc();
2923    int OldReg = Reg;
2924    const AsmToken RegTok = Parser.getTok();
2925    Reg = tryParseRegister();
2926    if (Reg == -1)
2927      return Error(RegLoc, "register expected");
2928    // Allow Q regs and just interpret them as the two D sub-registers.
2929    bool isQReg = false;
2930    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2931      Reg = getDRegFromQReg(Reg);
2932      isQReg = true;
2933    }
2934    // The register must be in the same register class as the first.
2935    if (!RC->contains(Reg))
2936      return Error(RegLoc, "invalid register in register list");
2937    // List must be monotonically increasing.
2938    if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
2939      if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2940        Warning(RegLoc, "register list not in ascending order");
2941      else
2942        return Error(RegLoc, "register list not in ascending order");
2943    }
2944    if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
2945      Warning(RegLoc, "duplicated register (" + RegTok.getString() +
2946              ") in register list");
2947      continue;
2948    }
2949    // VFP register lists must also be contiguous.
2950    // It's OK to use the enumeration values directly here rather, as the
2951    // VFP register classes have the enum sorted properly.
2952    if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2953        Reg != OldReg + 1)
2954      return Error(RegLoc, "non-contiguous register range");
2955    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2956    if (isQReg)
2957      Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2958  }
2959
2960  SMLoc E = Parser.getTok().getLoc();
2961  if (Parser.getTok().isNot(AsmToken::RCurly))
2962    return Error(E, "'}' expected");
2963  Parser.Lex(); // Eat '}' token.
2964
2965  // Push the register list operand.
2966  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2967
2968  // The ARM system instruction variants for LDM/STM have a '^' token here.
2969  if (Parser.getTok().is(AsmToken::Caret)) {
2970    Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
2971    Parser.Lex(); // Eat '^' token.
2972  }
2973
2974  return false;
2975}
2976
2977// Helper function to parse the lane index for vector lists.
2978ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2979parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) {
2980  Index = 0; // Always return a defined index value.
2981  if (Parser.getTok().is(AsmToken::LBrac)) {
2982    Parser.Lex(); // Eat the '['.
2983    if (Parser.getTok().is(AsmToken::RBrac)) {
2984      // "Dn[]" is the 'all lanes' syntax.
2985      LaneKind = AllLanes;
2986      Parser.Lex(); // Eat the ']'.
2987      return MatchOperand_Success;
2988    }
2989
2990    // There's an optional '#' token here. Normally there wouldn't be, but
2991    // inline assemble puts one in, and it's friendly to accept that.
2992    if (Parser.getTok().is(AsmToken::Hash))
2993      Parser.Lex(); // Eat the '#'
2994
2995    const MCExpr *LaneIndex;
2996    SMLoc Loc = Parser.getTok().getLoc();
2997    if (getParser().ParseExpression(LaneIndex)) {
2998      Error(Loc, "illegal expression");
2999      return MatchOperand_ParseFail;
3000    }
3001    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3002    if (!CE) {
3003      Error(Loc, "lane index must be empty or an integer");
3004      return MatchOperand_ParseFail;
3005    }
3006    if (Parser.getTok().isNot(AsmToken::RBrac)) {
3007      Error(Parser.getTok().getLoc(), "']' expected");
3008      return MatchOperand_ParseFail;
3009    }
3010    Parser.Lex(); // Eat the ']'.
3011    int64_t Val = CE->getValue();
3012
3013    // FIXME: Make this range check context sensitive for .8, .16, .32.
3014    if (Val < 0 || Val > 7) {
3015      Error(Parser.getTok().getLoc(), "lane index out of range");
3016      return MatchOperand_ParseFail;
3017    }
3018    Index = Val;
3019    LaneKind = IndexedLane;
3020    return MatchOperand_Success;
3021  }
3022  LaneKind = NoLanes;
3023  return MatchOperand_Success;
3024}
3025
3026// parse a vector register list
3027ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3028parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3029  VectorLaneTy LaneKind;
3030  unsigned LaneIndex;
3031  SMLoc S = Parser.getTok().getLoc();
3032  // As an extension (to match gas), support a plain D register or Q register
3033  // (without encosing curly braces) as a single or double entry list,
3034  // respectively.
3035  if (Parser.getTok().is(AsmToken::Identifier)) {
3036    int Reg = tryParseRegister();
3037    if (Reg == -1)
3038      return MatchOperand_NoMatch;
3039    SMLoc E = Parser.getTok().getLoc();
3040    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3041      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
3042      if (Res != MatchOperand_Success)
3043        return Res;
3044      switch (LaneKind) {
3045      case NoLanes:
3046        E = Parser.getTok().getLoc();
3047        Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3048        break;
3049      case AllLanes:
3050        E = Parser.getTok().getLoc();
3051        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3052                                                                S, E));
3053        break;
3054      case IndexedLane:
3055        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3056                                                               LaneIndex,
3057                                                               false, S, E));
3058        break;
3059      }
3060      return MatchOperand_Success;
3061    }
3062    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3063      Reg = getDRegFromQReg(Reg);
3064      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
3065      if (Res != MatchOperand_Success)
3066        return Res;
3067      switch (LaneKind) {
3068      case NoLanes:
3069        E = Parser.getTok().getLoc();
3070        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3071                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3072        Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3073        break;
3074      case AllLanes:
3075        E = Parser.getTok().getLoc();
3076        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3077                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3078        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3079                                                                S, E));
3080        break;
3081      case IndexedLane:
3082        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3083                                                               LaneIndex,
3084                                                               false, S, E));
3085        break;
3086      }
3087      return MatchOperand_Success;
3088    }
3089    Error(S, "vector register expected");
3090    return MatchOperand_ParseFail;
3091  }
3092
3093  if (Parser.getTok().isNot(AsmToken::LCurly))
3094    return MatchOperand_NoMatch;
3095
3096  Parser.Lex(); // Eat '{' token.
3097  SMLoc RegLoc = Parser.getTok().getLoc();
3098
3099  int Reg = tryParseRegister();
3100  if (Reg == -1) {
3101    Error(RegLoc, "register expected");
3102    return MatchOperand_ParseFail;
3103  }
3104  unsigned Count = 1;
3105  int Spacing = 0;
3106  unsigned FirstReg = Reg;
3107  // The list is of D registers, but we also allow Q regs and just interpret
3108  // them as the two D sub-registers.
3109  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3110    FirstReg = Reg = getDRegFromQReg(Reg);
3111    Spacing = 1; // double-spacing requires explicit D registers, otherwise
3112                 // it's ambiguous with four-register single spaced.
3113    ++Reg;
3114    ++Count;
3115  }
3116  if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success)
3117    return MatchOperand_ParseFail;
3118
3119  while (Parser.getTok().is(AsmToken::Comma) ||
3120         Parser.getTok().is(AsmToken::Minus)) {
3121    if (Parser.getTok().is(AsmToken::Minus)) {
3122      if (!Spacing)
3123        Spacing = 1; // Register range implies a single spaced list.
3124      else if (Spacing == 2) {
3125        Error(Parser.getTok().getLoc(),
3126              "sequential registers in double spaced list");
3127        return MatchOperand_ParseFail;
3128      }
3129      Parser.Lex(); // Eat the minus.
3130      SMLoc EndLoc = Parser.getTok().getLoc();
3131      int EndReg = tryParseRegister();
3132      if (EndReg == -1) {
3133        Error(EndLoc, "register expected");
3134        return MatchOperand_ParseFail;
3135      }
3136      // Allow Q regs and just interpret them as the two D sub-registers.
3137      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3138        EndReg = getDRegFromQReg(EndReg) + 1;
3139      // If the register is the same as the start reg, there's nothing
3140      // more to do.
3141      if (Reg == EndReg)
3142        continue;
3143      // The register must be in the same register class as the first.
3144      if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3145        Error(EndLoc, "invalid register in register list");
3146        return MatchOperand_ParseFail;
3147      }
3148      // Ranges must go from low to high.
3149      if (Reg > EndReg) {
3150        Error(EndLoc, "bad range in register list");
3151        return MatchOperand_ParseFail;
3152      }
3153      // Parse the lane specifier if present.
3154      VectorLaneTy NextLaneKind;
3155      unsigned NextLaneIndex;
3156      if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3157        return MatchOperand_ParseFail;
3158      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3159        Error(EndLoc, "mismatched lane index in register list");
3160        return MatchOperand_ParseFail;
3161      }
3162      EndLoc = Parser.getTok().getLoc();
3163
3164      // Add all the registers in the range to the register list.
3165      Count += EndReg - Reg;
3166      Reg = EndReg;
3167      continue;
3168    }
3169    Parser.Lex(); // Eat the comma.
3170    RegLoc = Parser.getTok().getLoc();
3171    int OldReg = Reg;
3172    Reg = tryParseRegister();
3173    if (Reg == -1) {
3174      Error(RegLoc, "register expected");
3175      return MatchOperand_ParseFail;
3176    }
3177    // vector register lists must be contiguous.
3178    // It's OK to use the enumeration values directly here rather, as the
3179    // VFP register classes have the enum sorted properly.
3180    //
3181    // The list is of D registers, but we also allow Q regs and just interpret
3182    // them as the two D sub-registers.
3183    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3184      if (!Spacing)
3185        Spacing = 1; // Register range implies a single spaced list.
3186      else if (Spacing == 2) {
3187        Error(RegLoc,
3188              "invalid register in double-spaced list (must be 'D' register')");
3189        return MatchOperand_ParseFail;
3190      }
3191      Reg = getDRegFromQReg(Reg);
3192      if (Reg != OldReg + 1) {
3193        Error(RegLoc, "non-contiguous register range");
3194        return MatchOperand_ParseFail;
3195      }
3196      ++Reg;
3197      Count += 2;
3198      // Parse the lane specifier if present.
3199      VectorLaneTy NextLaneKind;
3200      unsigned NextLaneIndex;
3201      SMLoc EndLoc = Parser.getTok().getLoc();
3202      if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3203        return MatchOperand_ParseFail;
3204      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3205        Error(EndLoc, "mismatched lane index in register list");
3206        return MatchOperand_ParseFail;
3207      }
3208      continue;
3209    }
3210    // Normal D register.
3211    // Figure out the register spacing (single or double) of the list if
3212    // we don't know it already.
3213    if (!Spacing)
3214      Spacing = 1 + (Reg == OldReg + 2);
3215
3216    // Just check that it's contiguous and keep going.
3217    if (Reg != OldReg + Spacing) {
3218      Error(RegLoc, "non-contiguous register range");
3219      return MatchOperand_ParseFail;
3220    }
3221    ++Count;
3222    // Parse the lane specifier if present.
3223    VectorLaneTy NextLaneKind;
3224    unsigned NextLaneIndex;
3225    SMLoc EndLoc = Parser.getTok().getLoc();
3226    if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3227      return MatchOperand_ParseFail;
3228    if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3229      Error(EndLoc, "mismatched lane index in register list");
3230      return MatchOperand_ParseFail;
3231    }
3232  }
3233
3234  SMLoc E = Parser.getTok().getLoc();
3235  if (Parser.getTok().isNot(AsmToken::RCurly)) {
3236    Error(E, "'}' expected");
3237    return MatchOperand_ParseFail;
3238  }
3239  Parser.Lex(); // Eat '}' token.
3240
3241  switch (LaneKind) {
3242  case NoLanes:
3243    // Two-register operands have been converted to the
3244    // composite register classes.
3245    if (Count == 2) {
3246      const MCRegisterClass *RC = (Spacing == 1) ?
3247        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3248        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3249      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3250    }
3251
3252    Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3253                                                    (Spacing == 2), S, E));
3254    break;
3255  case AllLanes:
3256    // Two-register operands have been converted to the
3257    // composite register classes.
3258    if (Count == 2) {
3259      const MCRegisterClass *RC = (Spacing == 1) ?
3260        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3261        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3262      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3263    }
3264    Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3265                                                            (Spacing == 2),
3266                                                            S, E));
3267    break;
3268  case IndexedLane:
3269    Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3270                                                           LaneIndex,
3271                                                           (Spacing == 2),
3272                                                           S, E));
3273    break;
3274  }
3275  return MatchOperand_Success;
3276}
3277
3278/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3279ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3280parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3281  SMLoc S = Parser.getTok().getLoc();
3282  const AsmToken &Tok = Parser.getTok();
3283  unsigned Opt;
3284
3285  if (Tok.is(AsmToken::Identifier)) {
3286    StringRef OptStr = Tok.getString();
3287
3288    Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3289      .Case("sy",    ARM_MB::SY)
3290      .Case("st",    ARM_MB::ST)
3291      .Case("sh",    ARM_MB::ISH)
3292      .Case("ish",   ARM_MB::ISH)
3293      .Case("shst",  ARM_MB::ISHST)
3294      .Case("ishst", ARM_MB::ISHST)
3295      .Case("nsh",   ARM_MB::NSH)
3296      .Case("un",    ARM_MB::NSH)
3297      .Case("nshst", ARM_MB::NSHST)
3298      .Case("unst",  ARM_MB::NSHST)
3299      .Case("osh",   ARM_MB::OSH)
3300      .Case("oshst", ARM_MB::OSHST)
3301      .Default(~0U);
3302
3303    if (Opt == ~0U)
3304      return MatchOperand_NoMatch;
3305
3306    Parser.Lex(); // Eat identifier token.
3307  } else if (Tok.is(AsmToken::Hash) ||
3308             Tok.is(AsmToken::Dollar) ||
3309             Tok.is(AsmToken::Integer)) {
3310    if (Parser.getTok().isNot(AsmToken::Integer))
3311      Parser.Lex(); // Eat the '#'.
3312    SMLoc Loc = Parser.getTok().getLoc();
3313
3314    const MCExpr *MemBarrierID;
3315    if (getParser().ParseExpression(MemBarrierID)) {
3316      Error(Loc, "illegal expression");
3317      return MatchOperand_ParseFail;
3318    }
3319
3320    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3321    if (!CE) {
3322      Error(Loc, "constant expression expected");
3323      return MatchOperand_ParseFail;
3324    }
3325
3326    int Val = CE->getValue();
3327    if (Val & ~0xf) {
3328      Error(Loc, "immediate value out of range");
3329      return MatchOperand_ParseFail;
3330    }
3331
3332    Opt = ARM_MB::RESERVED_0 + Val;
3333  } else
3334    return MatchOperand_ParseFail;
3335
3336  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3337  return MatchOperand_Success;
3338}
3339
3340/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3341ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3342parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3343  SMLoc S = Parser.getTok().getLoc();
3344  const AsmToken &Tok = Parser.getTok();
3345  if (!Tok.is(AsmToken::Identifier))
3346    return MatchOperand_NoMatch;
3347  StringRef IFlagsStr = Tok.getString();
3348
3349  // An iflags string of "none" is interpreted to mean that none of the AIF
3350  // bits are set.  Not a terribly useful instruction, but a valid encoding.
3351  unsigned IFlags = 0;
3352  if (IFlagsStr != "none") {
3353        for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3354      unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3355        .Case("a", ARM_PROC::A)
3356        .Case("i", ARM_PROC::I)
3357        .Case("f", ARM_PROC::F)
3358        .Default(~0U);
3359
3360      // If some specific iflag is already set, it means that some letter is
3361      // present more than once, this is not acceptable.
3362      if (Flag == ~0U || (IFlags & Flag))
3363        return MatchOperand_NoMatch;
3364
3365      IFlags |= Flag;
3366    }
3367  }
3368
3369  Parser.Lex(); // Eat identifier token.
3370  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3371  return MatchOperand_Success;
3372}
3373
3374/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3375ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3376parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3377  SMLoc S = Parser.getTok().getLoc();
3378  const AsmToken &Tok = Parser.getTok();
3379  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3380  StringRef Mask = Tok.getString();
3381
3382  if (isMClass()) {
3383    // See ARMv6-M 10.1.1
3384    std::string Name = Mask.lower();
3385    unsigned FlagsVal = StringSwitch<unsigned>(Name)
3386      // Note: in the documentation:
3387      //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3388      //  for MSR APSR_nzcvq.
3389      // but we do make it an alias here.  This is so to get the "mask encoding"
3390      // bits correct on MSR APSR writes.
3391      //
3392      // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3393      // should really only be allowed when writing a special register.  Note
3394      // they get dropped in the MRS instruction reading a special register as
3395      // the SYSm field is only 8 bits.
3396      //
3397      // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3398      // includes the DSP extension but that is not checked.
3399      .Case("apsr", 0x800)
3400      .Case("apsr_nzcvq", 0x800)
3401      .Case("apsr_g", 0x400)
3402      .Case("apsr_nzcvqg", 0xc00)
3403      .Case("iapsr", 0x801)
3404      .Case("iapsr_nzcvq", 0x801)
3405      .Case("iapsr_g", 0x401)
3406      .Case("iapsr_nzcvqg", 0xc01)
3407      .Case("eapsr", 0x802)
3408      .Case("eapsr_nzcvq", 0x802)
3409      .Case("eapsr_g", 0x402)
3410      .Case("eapsr_nzcvqg", 0xc02)
3411      .Case("xpsr", 0x803)
3412      .Case("xpsr_nzcvq", 0x803)
3413      .Case("xpsr_g", 0x403)
3414      .Case("xpsr_nzcvqg", 0xc03)
3415      .Case("ipsr", 0x805)
3416      .Case("epsr", 0x806)
3417      .Case("iepsr", 0x807)
3418      .Case("msp", 0x808)
3419      .Case("psp", 0x809)
3420      .Case("primask", 0x810)
3421      .Case("basepri", 0x811)
3422      .Case("basepri_max", 0x812)
3423      .Case("faultmask", 0x813)
3424      .Case("control", 0x814)
3425      .Default(~0U);
3426
3427    if (FlagsVal == ~0U)
3428      return MatchOperand_NoMatch;
3429
3430    if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3431      // basepri, basepri_max and faultmask only valid for V7m.
3432      return MatchOperand_NoMatch;
3433
3434    Parser.Lex(); // Eat identifier token.
3435    Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3436    return MatchOperand_Success;
3437  }
3438
3439  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3440  size_t Start = 0, Next = Mask.find('_');
3441  StringRef Flags = "";
3442  std::string SpecReg = Mask.slice(Start, Next).lower();
3443  if (Next != StringRef::npos)
3444    Flags = Mask.slice(Next+1, Mask.size());
3445
3446  // FlagsVal contains the complete mask:
3447  // 3-0: Mask
3448  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3449  unsigned FlagsVal = 0;
3450
3451  if (SpecReg == "apsr") {
3452    FlagsVal = StringSwitch<unsigned>(Flags)
3453    .Case("nzcvq",  0x8) // same as CPSR_f
3454    .Case("g",      0x4) // same as CPSR_s
3455    .Case("nzcvqg", 0xc) // same as CPSR_fs
3456    .Default(~0U);
3457
3458    if (FlagsVal == ~0U) {
3459      if (!Flags.empty())
3460        return MatchOperand_NoMatch;
3461      else
3462        FlagsVal = 8; // No flag
3463    }
3464  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3465    // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3466    if (Flags == "all" || Flags == "")
3467      Flags = "fc";
3468    for (int i = 0, e = Flags.size(); i != e; ++i) {
3469      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3470      .Case("c", 1)
3471      .Case("x", 2)
3472      .Case("s", 4)
3473      .Case("f", 8)
3474      .Default(~0U);
3475
3476      // If some specific flag is already set, it means that some letter is
3477      // present more than once, this is not acceptable.
3478      if (FlagsVal == ~0U || (FlagsVal & Flag))
3479        return MatchOperand_NoMatch;
3480      FlagsVal |= Flag;
3481    }
3482  } else // No match for special register.
3483    return MatchOperand_NoMatch;
3484
3485  // Special register without flags is NOT equivalent to "fc" flags.
3486  // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
3487  // two lines would enable gas compatibility at the expense of breaking
3488  // round-tripping.
3489  //
3490  // if (!FlagsVal)
3491  //  FlagsVal = 0x9;
3492
3493  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3494  if (SpecReg == "spsr")
3495    FlagsVal |= 16;
3496
3497  Parser.Lex(); // Eat identifier token.
3498  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3499  return MatchOperand_Success;
3500}
3501
3502ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3503parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3504            int Low, int High) {
3505  const AsmToken &Tok = Parser.getTok();
3506  if (Tok.isNot(AsmToken::Identifier)) {
3507    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3508    return MatchOperand_ParseFail;
3509  }
3510  StringRef ShiftName = Tok.getString();
3511  std::string LowerOp = Op.lower();
3512  std::string UpperOp = Op.upper();
3513  if (ShiftName != LowerOp && ShiftName != UpperOp) {
3514    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3515    return MatchOperand_ParseFail;
3516  }
3517  Parser.Lex(); // Eat shift type token.
3518
3519  // There must be a '#' and a shift amount.
3520  if (Parser.getTok().isNot(AsmToken::Hash) &&
3521      Parser.getTok().isNot(AsmToken::Dollar)) {
3522    Error(Parser.getTok().getLoc(), "'#' expected");
3523    return MatchOperand_ParseFail;
3524  }
3525  Parser.Lex(); // Eat hash token.
3526
3527  const MCExpr *ShiftAmount;
3528  SMLoc Loc = Parser.getTok().getLoc();
3529  if (getParser().ParseExpression(ShiftAmount)) {
3530    Error(Loc, "illegal expression");
3531    return MatchOperand_ParseFail;
3532  }
3533  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3534  if (!CE) {
3535    Error(Loc, "constant expression expected");
3536    return MatchOperand_ParseFail;
3537  }
3538  int Val = CE->getValue();
3539  if (Val < Low || Val > High) {
3540    Error(Loc, "immediate value out of range");
3541    return MatchOperand_ParseFail;
3542  }
3543
3544  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
3545
3546  return MatchOperand_Success;
3547}
3548
3549ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3550parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3551  const AsmToken &Tok = Parser.getTok();
3552  SMLoc S = Tok.getLoc();
3553  if (Tok.isNot(AsmToken::Identifier)) {
3554    Error(Tok.getLoc(), "'be' or 'le' operand expected");
3555    return MatchOperand_ParseFail;
3556  }
3557  int Val = StringSwitch<int>(Tok.getString())
3558    .Case("be", 1)
3559    .Case("le", 0)
3560    .Default(-1);
3561  Parser.Lex(); // Eat the token.
3562
3563  if (Val == -1) {
3564    Error(Tok.getLoc(), "'be' or 'le' operand expected");
3565    return MatchOperand_ParseFail;
3566  }
3567  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3568                                                                  getContext()),
3569                                           S, Parser.getTok().getLoc()));
3570  return MatchOperand_Success;
3571}
3572
3573/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3574/// instructions. Legal values are:
3575///     lsl #n  'n' in [0,31]
3576///     asr #n  'n' in [1,32]
3577///             n == 32 encoded as n == 0.
3578ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3579parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3580  const AsmToken &Tok = Parser.getTok();
3581  SMLoc S = Tok.getLoc();
3582  if (Tok.isNot(AsmToken::Identifier)) {
3583    Error(S, "shift operator 'asr' or 'lsl' expected");
3584    return MatchOperand_ParseFail;
3585  }
3586  StringRef ShiftName = Tok.getString();
3587  bool isASR;
3588  if (ShiftName == "lsl" || ShiftName == "LSL")
3589    isASR = false;
3590  else if (ShiftName == "asr" || ShiftName == "ASR")
3591    isASR = true;
3592  else {
3593    Error(S, "shift operator 'asr' or 'lsl' expected");
3594    return MatchOperand_ParseFail;
3595  }
3596  Parser.Lex(); // Eat the operator.
3597
3598  // A '#' and a shift amount.
3599  if (Parser.getTok().isNot(AsmToken::Hash) &&
3600      Parser.getTok().isNot(AsmToken::Dollar)) {
3601    Error(Parser.getTok().getLoc(), "'#' expected");
3602    return MatchOperand_ParseFail;
3603  }
3604  Parser.Lex(); // Eat hash token.
3605
3606  const MCExpr *ShiftAmount;
3607  SMLoc E = Parser.getTok().getLoc();
3608  if (getParser().ParseExpression(ShiftAmount)) {
3609    Error(E, "malformed shift expression");
3610    return MatchOperand_ParseFail;
3611  }
3612  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3613  if (!CE) {
3614    Error(E, "shift amount must be an immediate");
3615    return MatchOperand_ParseFail;
3616  }
3617
3618  int64_t Val = CE->getValue();
3619  if (isASR) {
3620    // Shift amount must be in [1,32]
3621    if (Val < 1 || Val > 32) {
3622      Error(E, "'asr' shift amount must be in range [1,32]");
3623      return MatchOperand_ParseFail;
3624    }
3625    // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3626    if (isThumb() && Val == 32) {
3627      Error(E, "'asr #32' shift amount not allowed in Thumb mode");
3628      return MatchOperand_ParseFail;
3629    }
3630    if (Val == 32) Val = 0;
3631  } else {
3632    // Shift amount must be in [1,32]
3633    if (Val < 0 || Val > 31) {
3634      Error(E, "'lsr' shift amount must be in range [0,31]");
3635      return MatchOperand_ParseFail;
3636    }
3637  }
3638
3639  E = Parser.getTok().getLoc();
3640  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
3641
3642  return MatchOperand_Success;
3643}
3644
3645/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3646/// of instructions. Legal values are:
3647///     ror #n  'n' in {0, 8, 16, 24}
3648ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3649parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3650  const AsmToken &Tok = Parser.getTok();
3651  SMLoc S = Tok.getLoc();
3652  if (Tok.isNot(AsmToken::Identifier))
3653    return MatchOperand_NoMatch;
3654  StringRef ShiftName = Tok.getString();
3655  if (ShiftName != "ror" && ShiftName != "ROR")
3656    return MatchOperand_NoMatch;
3657  Parser.Lex(); // Eat the operator.
3658
3659  // A '#' and a rotate amount.
3660  if (Parser.getTok().isNot(AsmToken::Hash) &&
3661      Parser.getTok().isNot(AsmToken::Dollar)) {
3662    Error(Parser.getTok().getLoc(), "'#' expected");
3663    return MatchOperand_ParseFail;
3664  }
3665  Parser.Lex(); // Eat hash token.
3666
3667  const MCExpr *ShiftAmount;
3668  SMLoc E = Parser.getTok().getLoc();
3669  if (getParser().ParseExpression(ShiftAmount)) {
3670    Error(E, "malformed rotate expression");
3671    return MatchOperand_ParseFail;
3672  }
3673  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3674  if (!CE) {
3675    Error(E, "rotate amount must be an immediate");
3676    return MatchOperand_ParseFail;
3677  }
3678
3679  int64_t Val = CE->getValue();
3680  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3681  // normally, zero is represented in asm by omitting the rotate operand
3682  // entirely.
3683  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3684    Error(E, "'ror' rotate amount must be 8, 16, or 24");
3685    return MatchOperand_ParseFail;
3686  }
3687
3688  E = Parser.getTok().getLoc();
3689  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
3690
3691  return MatchOperand_Success;
3692}
3693
3694ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3695parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3696  SMLoc S = Parser.getTok().getLoc();
3697  // The bitfield descriptor is really two operands, the LSB and the width.
3698  if (Parser.getTok().isNot(AsmToken::Hash) &&
3699      Parser.getTok().isNot(AsmToken::Dollar)) {
3700    Error(Parser.getTok().getLoc(), "'#' expected");
3701    return MatchOperand_ParseFail;
3702  }
3703  Parser.Lex(); // Eat hash token.
3704
3705  const MCExpr *LSBExpr;
3706  SMLoc E = Parser.getTok().getLoc();
3707  if (getParser().ParseExpression(LSBExpr)) {
3708    Error(E, "malformed immediate expression");
3709    return MatchOperand_ParseFail;
3710  }
3711  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3712  if (!CE) {
3713    Error(E, "'lsb' operand must be an immediate");
3714    return MatchOperand_ParseFail;
3715  }
3716
3717  int64_t LSB = CE->getValue();
3718  // The LSB must be in the range [0,31]
3719  if (LSB < 0 || LSB > 31) {
3720    Error(E, "'lsb' operand must be in the range [0,31]");
3721    return MatchOperand_ParseFail;
3722  }
3723  E = Parser.getTok().getLoc();
3724
3725  // Expect another immediate operand.
3726  if (Parser.getTok().isNot(AsmToken::Comma)) {
3727    Error(Parser.getTok().getLoc(), "too few operands");
3728    return MatchOperand_ParseFail;
3729  }
3730  Parser.Lex(); // Eat hash token.
3731  if (Parser.getTok().isNot(AsmToken::Hash) &&
3732      Parser.getTok().isNot(AsmToken::Dollar)) {
3733    Error(Parser.getTok().getLoc(), "'#' expected");
3734    return MatchOperand_ParseFail;
3735  }
3736  Parser.Lex(); // Eat hash token.
3737
3738  const MCExpr *WidthExpr;
3739  if (getParser().ParseExpression(WidthExpr)) {
3740    Error(E, "malformed immediate expression");
3741    return MatchOperand_ParseFail;
3742  }
3743  CE = dyn_cast<MCConstantExpr>(WidthExpr);
3744  if (!CE) {
3745    Error(E, "'width' operand must be an immediate");
3746    return MatchOperand_ParseFail;
3747  }
3748
3749  int64_t Width = CE->getValue();
3750  // The LSB must be in the range [1,32-lsb]
3751  if (Width < 1 || Width > 32 - LSB) {
3752    Error(E, "'width' operand must be in the range [1,32-lsb]");
3753    return MatchOperand_ParseFail;
3754  }
3755  E = Parser.getTok().getLoc();
3756
3757  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
3758
3759  return MatchOperand_Success;
3760}
3761
3762ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3763parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3764  // Check for a post-index addressing register operand. Specifically:
3765  // postidx_reg := '+' register {, shift}
3766  //              | '-' register {, shift}
3767  //              | register {, shift}
3768
3769  // This method must return MatchOperand_NoMatch without consuming any tokens
3770  // in the case where there is no match, as other alternatives take other
3771  // parse methods.
3772  AsmToken Tok = Parser.getTok();
3773  SMLoc S = Tok.getLoc();
3774  bool haveEaten = false;
3775  bool isAdd = true;
3776  int Reg = -1;
3777  if (Tok.is(AsmToken::Plus)) {
3778    Parser.Lex(); // Eat the '+' token.
3779    haveEaten = true;
3780  } else if (Tok.is(AsmToken::Minus)) {
3781    Parser.Lex(); // Eat the '-' token.
3782    isAdd = false;
3783    haveEaten = true;
3784  }
3785  if (Parser.getTok().is(AsmToken::Identifier))
3786    Reg = tryParseRegister();
3787  if (Reg == -1) {
3788    if (!haveEaten)
3789      return MatchOperand_NoMatch;
3790    Error(Parser.getTok().getLoc(), "register expected");
3791    return MatchOperand_ParseFail;
3792  }
3793  SMLoc E = Parser.getTok().getLoc();
3794
3795  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3796  unsigned ShiftImm = 0;
3797  if (Parser.getTok().is(AsmToken::Comma)) {
3798    Parser.Lex(); // Eat the ','.
3799    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3800      return MatchOperand_ParseFail;
3801  }
3802
3803  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3804                                                  ShiftImm, S, E));
3805
3806  return MatchOperand_Success;
3807}
3808
3809ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3810parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3811  // Check for a post-index addressing register operand. Specifically:
3812  // am3offset := '+' register
3813  //              | '-' register
3814  //              | register
3815  //              | # imm
3816  //              | # + imm
3817  //              | # - imm
3818
3819  // This method must return MatchOperand_NoMatch without consuming any tokens
3820  // in the case where there is no match, as other alternatives take other
3821  // parse methods.
3822  AsmToken Tok = Parser.getTok();
3823  SMLoc S = Tok.getLoc();
3824
3825  // Do immediates first, as we always parse those if we have a '#'.
3826  if (Parser.getTok().is(AsmToken::Hash) ||
3827      Parser.getTok().is(AsmToken::Dollar)) {
3828    Parser.Lex(); // Eat the '#'.
3829    // Explicitly look for a '-', as we need to encode negative zero
3830    // differently.
3831    bool isNegative = Parser.getTok().is(AsmToken::Minus);
3832    const MCExpr *Offset;
3833    if (getParser().ParseExpression(Offset))
3834      return MatchOperand_ParseFail;
3835    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3836    if (!CE) {
3837      Error(S, "constant expression expected");
3838      return MatchOperand_ParseFail;
3839    }
3840    SMLoc E = Tok.getLoc();
3841    // Negative zero is encoded as the flag value INT32_MIN.
3842    int32_t Val = CE->getValue();
3843    if (isNegative && Val == 0)
3844      Val = INT32_MIN;
3845
3846    Operands.push_back(
3847      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3848
3849    return MatchOperand_Success;
3850  }
3851
3852
3853  bool haveEaten = false;
3854  bool isAdd = true;
3855  int Reg = -1;
3856  if (Tok.is(AsmToken::Plus)) {
3857    Parser.Lex(); // Eat the '+' token.
3858    haveEaten = true;
3859  } else if (Tok.is(AsmToken::Minus)) {
3860    Parser.Lex(); // Eat the '-' token.
3861    isAdd = false;
3862    haveEaten = true;
3863  }
3864  if (Parser.getTok().is(AsmToken::Identifier))
3865    Reg = tryParseRegister();
3866  if (Reg == -1) {
3867    if (!haveEaten)
3868      return MatchOperand_NoMatch;
3869    Error(Parser.getTok().getLoc(), "register expected");
3870    return MatchOperand_ParseFail;
3871  }
3872  SMLoc E = Parser.getTok().getLoc();
3873
3874  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3875                                                  0, S, E));
3876
3877  return MatchOperand_Success;
3878}
3879
3880/// cvtT2LdrdPre - Convert parsed operands to MCInst.
3881/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3882/// when they refer multiple MIOperands inside a single one.
3883void ARMAsmParser::
3884cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3885             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3886  // Rt, Rt2
3887  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3888  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3889  // Create a writeback register dummy placeholder.
3890  Inst.addOperand(MCOperand::CreateReg(0));
3891  // addr
3892  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3893  // pred
3894  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3895}
3896
3897/// cvtT2StrdPre - Convert parsed operands to MCInst.
3898/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3899/// when they refer multiple MIOperands inside a single one.
3900void ARMAsmParser::
3901cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3902             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3903  // Create a writeback register dummy placeholder.
3904  Inst.addOperand(MCOperand::CreateReg(0));
3905  // Rt, Rt2
3906  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3907  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3908  // addr
3909  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3910  // pred
3911  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3912}
3913
3914/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3915/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3916/// when they refer multiple MIOperands inside a single one.
3917void ARMAsmParser::
3918cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3919                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3920  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3921
3922  // Create a writeback register dummy placeholder.
3923  Inst.addOperand(MCOperand::CreateImm(0));
3924
3925  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3926  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3927}
3928
3929/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3930/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3931/// when they refer multiple MIOperands inside a single one.
3932void ARMAsmParser::
3933cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3934                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3935  // Create a writeback register dummy placeholder.
3936  Inst.addOperand(MCOperand::CreateImm(0));
3937  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3938  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3939  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3940}
3941
3942/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3943/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3944/// when they refer multiple MIOperands inside a single one.
3945void ARMAsmParser::
3946cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3947                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3948  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3949
3950  // Create a writeback register dummy placeholder.
3951  Inst.addOperand(MCOperand::CreateImm(0));
3952
3953  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3954  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3955}
3956
3957/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3958/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3959/// when they refer multiple MIOperands inside a single one.
3960void ARMAsmParser::
3961cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3962                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3963  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3964
3965  // Create a writeback register dummy placeholder.
3966  Inst.addOperand(MCOperand::CreateImm(0));
3967
3968  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3969  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3970}
3971
3972
3973/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3974/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3975/// when they refer multiple MIOperands inside a single one.
3976void ARMAsmParser::
3977cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3978                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3979  // Create a writeback register dummy placeholder.
3980  Inst.addOperand(MCOperand::CreateImm(0));
3981  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3982  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3983  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3984}
3985
3986/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3987/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3988/// when they refer multiple MIOperands inside a single one.
3989void ARMAsmParser::
3990cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3991                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3992  // Create a writeback register dummy placeholder.
3993  Inst.addOperand(MCOperand::CreateImm(0));
3994  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3995  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3996  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3997}
3998
3999/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4000/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4001/// when they refer multiple MIOperands inside a single one.
4002void ARMAsmParser::
4003cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
4004                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4005  // Create a writeback register dummy placeholder.
4006  Inst.addOperand(MCOperand::CreateImm(0));
4007  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4008  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4009  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4010}
4011
4012/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
4013/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4014/// when they refer multiple MIOperands inside a single one.
4015void ARMAsmParser::
4016cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
4017                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4018  // Rt
4019  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4020  // Create a writeback register dummy placeholder.
4021  Inst.addOperand(MCOperand::CreateImm(0));
4022  // addr
4023  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4024  // offset
4025  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4026  // pred
4027  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4028}
4029
4030/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
4031/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4032/// when they refer multiple MIOperands inside a single one.
4033void ARMAsmParser::
4034cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
4035                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4036  // Rt
4037  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4038  // Create a writeback register dummy placeholder.
4039  Inst.addOperand(MCOperand::CreateImm(0));
4040  // addr
4041  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4042  // offset
4043  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4044  // pred
4045  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4046}
4047
4048/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
4049/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4050/// when they refer multiple MIOperands inside a single one.
4051void ARMAsmParser::
4052cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
4053                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4054  // Create a writeback register dummy placeholder.
4055  Inst.addOperand(MCOperand::CreateImm(0));
4056  // Rt
4057  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4058  // addr
4059  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4060  // offset
4061  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4062  // pred
4063  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4064}
4065
4066/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
4067/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4068/// when they refer multiple MIOperands inside a single one.
4069void ARMAsmParser::
4070cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
4071                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4072  // Create a writeback register dummy placeholder.
4073  Inst.addOperand(MCOperand::CreateImm(0));
4074  // Rt
4075  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4076  // addr
4077  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4078  // offset
4079  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4080  // pred
4081  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4082}
4083
4084/// cvtLdrdPre - Convert parsed operands to MCInst.
4085/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4086/// when they refer multiple MIOperands inside a single one.
4087void ARMAsmParser::
4088cvtLdrdPre(MCInst &Inst, unsigned Opcode,
4089           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4090  // Rt, Rt2
4091  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4092  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4093  // Create a writeback register dummy placeholder.
4094  Inst.addOperand(MCOperand::CreateImm(0));
4095  // addr
4096  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4097  // pred
4098  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4099}
4100
4101/// cvtStrdPre - Convert parsed operands to MCInst.
4102/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4103/// when they refer multiple MIOperands inside a single one.
4104void ARMAsmParser::
4105cvtStrdPre(MCInst &Inst, unsigned Opcode,
4106           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4107  // Create a writeback register dummy placeholder.
4108  Inst.addOperand(MCOperand::CreateImm(0));
4109  // Rt, Rt2
4110  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4111  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4112  // addr
4113  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4114  // pred
4115  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4116}
4117
4118/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4119/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4120/// when they refer multiple MIOperands inside a single one.
4121void ARMAsmParser::
4122cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
4123                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4124  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4125  // Create a writeback register dummy placeholder.
4126  Inst.addOperand(MCOperand::CreateImm(0));
4127  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4128  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4129}
4130
4131/// cvtThumbMultiply - Convert parsed operands to MCInst.
4132/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4133/// when they refer multiple MIOperands inside a single one.
4134void ARMAsmParser::
4135cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
4136           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4137  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4138  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4139  // If we have a three-operand form, make sure to set Rn to be the operand
4140  // that isn't the same as Rd.
4141  unsigned RegOp = 4;
4142  if (Operands.size() == 6 &&
4143      ((ARMOperand*)Operands[4])->getReg() ==
4144        ((ARMOperand*)Operands[3])->getReg())
4145    RegOp = 5;
4146  ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4147  Inst.addOperand(Inst.getOperand(0));
4148  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4149}
4150
4151void ARMAsmParser::
4152cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
4153              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4154  // Vd
4155  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4156  // Create a writeback register dummy placeholder.
4157  Inst.addOperand(MCOperand::CreateImm(0));
4158  // Vn
4159  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4160  // pred
4161  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4162}
4163
4164void ARMAsmParser::
4165cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
4166                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4167  // Vd
4168  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4169  // Create a writeback register dummy placeholder.
4170  Inst.addOperand(MCOperand::CreateImm(0));
4171  // Vn
4172  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4173  // Vm
4174  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4175  // pred
4176  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4177}
4178
4179void ARMAsmParser::
4180cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
4181              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4182  // Create a writeback register dummy placeholder.
4183  Inst.addOperand(MCOperand::CreateImm(0));
4184  // Vn
4185  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4186  // Vt
4187  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4188  // pred
4189  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4190}
4191
4192void ARMAsmParser::
4193cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
4194                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4195  // Create a writeback register dummy placeholder.
4196  Inst.addOperand(MCOperand::CreateImm(0));
4197  // Vn
4198  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4199  // Vm
4200  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4201  // Vt
4202  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4203  // pred
4204  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4205}
4206
4207/// Parse an ARM memory expression, return false if successful else return true
4208/// or an error.  The first token must be a '[' when called.
4209bool ARMAsmParser::
4210parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4211  SMLoc S, E;
4212  assert(Parser.getTok().is(AsmToken::LBrac) &&
4213         "Token is not a Left Bracket");
4214  S = Parser.getTok().getLoc();
4215  Parser.Lex(); // Eat left bracket token.
4216
4217  const AsmToken &BaseRegTok = Parser.getTok();
4218  int BaseRegNum = tryParseRegister();
4219  if (BaseRegNum == -1)
4220    return Error(BaseRegTok.getLoc(), "register expected");
4221
4222  // The next token must either be a comma or a closing bracket.
4223  const AsmToken &Tok = Parser.getTok();
4224  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
4225    return Error(Tok.getLoc(), "malformed memory operand");
4226
4227  if (Tok.is(AsmToken::RBrac)) {
4228    E = Tok.getLoc();
4229    Parser.Lex(); // Eat right bracket token.
4230
4231    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4232                                             0, 0, false, S, E));
4233
4234    // If there's a pre-indexing writeback marker, '!', just add it as a token
4235    // operand. It's rather odd, but syntactically valid.
4236    if (Parser.getTok().is(AsmToken::Exclaim)) {
4237      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4238      Parser.Lex(); // Eat the '!'.
4239    }
4240
4241    return false;
4242  }
4243
4244  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
4245  Parser.Lex(); // Eat the comma.
4246
4247  // If we have a ':', it's an alignment specifier.
4248  if (Parser.getTok().is(AsmToken::Colon)) {
4249    Parser.Lex(); // Eat the ':'.
4250    E = Parser.getTok().getLoc();
4251
4252    const MCExpr *Expr;
4253    if (getParser().ParseExpression(Expr))
4254     return true;
4255
4256    // The expression has to be a constant. Memory references with relocations
4257    // don't come through here, as they use the <label> forms of the relevant
4258    // instructions.
4259    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4260    if (!CE)
4261      return Error (E, "constant expression expected");
4262
4263    unsigned Align = 0;
4264    switch (CE->getValue()) {
4265    default:
4266      return Error(E,
4267                   "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4268    case 16:  Align = 2; break;
4269    case 32:  Align = 4; break;
4270    case 64:  Align = 8; break;
4271    case 128: Align = 16; break;
4272    case 256: Align = 32; break;
4273    }
4274
4275    // Now we should have the closing ']'
4276    E = Parser.getTok().getLoc();
4277    if (Parser.getTok().isNot(AsmToken::RBrac))
4278      return Error(E, "']' expected");
4279    Parser.Lex(); // Eat right bracket token.
4280
4281    // Don't worry about range checking the value here. That's handled by
4282    // the is*() predicates.
4283    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4284                                             ARM_AM::no_shift, 0, Align,
4285                                             false, S, E));
4286
4287    // If there's a pre-indexing writeback marker, '!', just add it as a token
4288    // operand.
4289    if (Parser.getTok().is(AsmToken::Exclaim)) {
4290      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4291      Parser.Lex(); // Eat the '!'.
4292    }
4293
4294    return false;
4295  }
4296
4297  // If we have a '#', it's an immediate offset, else assume it's a register
4298  // offset. Be friendly and also accept a plain integer (without a leading
4299  // hash) for gas compatibility.
4300  if (Parser.getTok().is(AsmToken::Hash) ||
4301      Parser.getTok().is(AsmToken::Dollar) ||
4302      Parser.getTok().is(AsmToken::Integer)) {
4303    if (Parser.getTok().isNot(AsmToken::Integer))
4304      Parser.Lex(); // Eat the '#'.
4305    E = Parser.getTok().getLoc();
4306
4307    bool isNegative = getParser().getTok().is(AsmToken::Minus);
4308    const MCExpr *Offset;
4309    if (getParser().ParseExpression(Offset))
4310     return true;
4311
4312    // The expression has to be a constant. Memory references with relocations
4313    // don't come through here, as they use the <label> forms of the relevant
4314    // instructions.
4315    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4316    if (!CE)
4317      return Error (E, "constant expression expected");
4318
4319    // If the constant was #-0, represent it as INT32_MIN.
4320    int32_t Val = CE->getValue();
4321    if (isNegative && Val == 0)
4322      CE = MCConstantExpr::Create(INT32_MIN, getContext());
4323
4324    // Now we should have the closing ']'
4325    E = Parser.getTok().getLoc();
4326    if (Parser.getTok().isNot(AsmToken::RBrac))
4327      return Error(E, "']' expected");
4328    Parser.Lex(); // Eat right bracket token.
4329
4330    // Don't worry about range checking the value here. That's handled by
4331    // the is*() predicates.
4332    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4333                                             ARM_AM::no_shift, 0, 0,
4334                                             false, S, E));
4335
4336    // If there's a pre-indexing writeback marker, '!', just add it as a token
4337    // operand.
4338    if (Parser.getTok().is(AsmToken::Exclaim)) {
4339      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4340      Parser.Lex(); // Eat the '!'.
4341    }
4342
4343    return false;
4344  }
4345
4346  // The register offset is optionally preceded by a '+' or '-'
4347  bool isNegative = false;
4348  if (Parser.getTok().is(AsmToken::Minus)) {
4349    isNegative = true;
4350    Parser.Lex(); // Eat the '-'.
4351  } else if (Parser.getTok().is(AsmToken::Plus)) {
4352    // Nothing to do.
4353    Parser.Lex(); // Eat the '+'.
4354  }
4355
4356  E = Parser.getTok().getLoc();
4357  int OffsetRegNum = tryParseRegister();
4358  if (OffsetRegNum == -1)
4359    return Error(E, "register expected");
4360
4361  // If there's a shift operator, handle it.
4362  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4363  unsigned ShiftImm = 0;
4364  if (Parser.getTok().is(AsmToken::Comma)) {
4365    Parser.Lex(); // Eat the ','.
4366    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4367      return true;
4368  }
4369
4370  // Now we should have the closing ']'
4371  E = Parser.getTok().getLoc();
4372  if (Parser.getTok().isNot(AsmToken::RBrac))
4373    return Error(E, "']' expected");
4374  Parser.Lex(); // Eat right bracket token.
4375
4376  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4377                                           ShiftType, ShiftImm, 0, isNegative,
4378                                           S, E));
4379
4380  // If there's a pre-indexing writeback marker, '!', just add it as a token
4381  // operand.
4382  if (Parser.getTok().is(AsmToken::Exclaim)) {
4383    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4384    Parser.Lex(); // Eat the '!'.
4385  }
4386
4387  return false;
4388}
4389
4390/// parseMemRegOffsetShift - one of these two:
4391///   ( lsl | lsr | asr | ror ) , # shift_amount
4392///   rrx
4393/// return true if it parses a shift otherwise it returns false.
4394bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4395                                          unsigned &Amount) {
4396  SMLoc Loc = Parser.getTok().getLoc();
4397  const AsmToken &Tok = Parser.getTok();
4398  if (Tok.isNot(AsmToken::Identifier))
4399    return true;
4400  StringRef ShiftName = Tok.getString();
4401  if (ShiftName == "lsl" || ShiftName == "LSL" ||
4402      ShiftName == "asl" || ShiftName == "ASL")
4403    St = ARM_AM::lsl;
4404  else if (ShiftName == "lsr" || ShiftName == "LSR")
4405    St = ARM_AM::lsr;
4406  else if (ShiftName == "asr" || ShiftName == "ASR")
4407    St = ARM_AM::asr;
4408  else if (ShiftName == "ror" || ShiftName == "ROR")
4409    St = ARM_AM::ror;
4410  else if (ShiftName == "rrx" || ShiftName == "RRX")
4411    St = ARM_AM::rrx;
4412  else
4413    return Error(Loc, "illegal shift operator");
4414  Parser.Lex(); // Eat shift type token.
4415
4416  // rrx stands alone.
4417  Amount = 0;
4418  if (St != ARM_AM::rrx) {
4419    Loc = Parser.getTok().getLoc();
4420    // A '#' and a shift amount.
4421    const AsmToken &HashTok = Parser.getTok();
4422    if (HashTok.isNot(AsmToken::Hash) &&
4423        HashTok.isNot(AsmToken::Dollar))
4424      return Error(HashTok.getLoc(), "'#' expected");
4425    Parser.Lex(); // Eat hash token.
4426
4427    const MCExpr *Expr;
4428    if (getParser().ParseExpression(Expr))
4429      return true;
4430    // Range check the immediate.
4431    // lsl, ror: 0 <= imm <= 31
4432    // lsr, asr: 0 <= imm <= 32
4433    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4434    if (!CE)
4435      return Error(Loc, "shift amount must be an immediate");
4436    int64_t Imm = CE->getValue();
4437    if (Imm < 0 ||
4438        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4439        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4440      return Error(Loc, "immediate shift value out of range");
4441    Amount = Imm;
4442  }
4443
4444  return false;
4445}
4446
4447/// parseFPImm - A floating point immediate expression operand.
4448ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4449parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4450  // Anything that can accept a floating point constant as an operand
4451  // needs to go through here, as the regular ParseExpression is
4452  // integer only.
4453  //
4454  // This routine still creates a generic Immediate operand, containing
4455  // a bitcast of the 64-bit floating point value. The various operands
4456  // that accept floats can check whether the value is valid for them
4457  // via the standard is*() predicates.
4458
4459  SMLoc S = Parser.getTok().getLoc();
4460
4461  if (Parser.getTok().isNot(AsmToken::Hash) &&
4462      Parser.getTok().isNot(AsmToken::Dollar))
4463    return MatchOperand_NoMatch;
4464
4465  // Disambiguate the VMOV forms that can accept an FP immediate.
4466  // vmov.f32 <sreg>, #imm
4467  // vmov.f64 <dreg>, #imm
4468  // vmov.f32 <dreg>, #imm  @ vector f32x2
4469  // vmov.f32 <qreg>, #imm  @ vector f32x4
4470  //
4471  // There are also the NEON VMOV instructions which expect an
4472  // integer constant. Make sure we don't try to parse an FPImm
4473  // for these:
4474  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4475  ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4476  if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4477                           TyOp->getToken() != ".f64"))
4478    return MatchOperand_NoMatch;
4479
4480  Parser.Lex(); // Eat the '#'.
4481
4482  // Handle negation, as that still comes through as a separate token.
4483  bool isNegative = false;
4484  if (Parser.getTok().is(AsmToken::Minus)) {
4485    isNegative = true;
4486    Parser.Lex();
4487  }
4488  const AsmToken &Tok = Parser.getTok();
4489  SMLoc Loc = Tok.getLoc();
4490  if (Tok.is(AsmToken::Real)) {
4491    APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4492    uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4493    // If we had a '-' in front, toggle the sign bit.
4494    IntVal ^= (uint64_t)isNegative << 31;
4495    Parser.Lex(); // Eat the token.
4496    Operands.push_back(ARMOperand::CreateImm(
4497          MCConstantExpr::Create(IntVal, getContext()),
4498          S, Parser.getTok().getLoc()));
4499    return MatchOperand_Success;
4500  }
4501  // Also handle plain integers. Instructions which allow floating point
4502  // immediates also allow a raw encoded 8-bit value.
4503  if (Tok.is(AsmToken::Integer)) {
4504    int64_t Val = Tok.getIntVal();
4505    Parser.Lex(); // Eat the token.
4506    if (Val > 255 || Val < 0) {
4507      Error(Loc, "encoded floating point value out of range");
4508      return MatchOperand_ParseFail;
4509    }
4510    double RealVal = ARM_AM::getFPImmFloat(Val);
4511    Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4512    Operands.push_back(ARMOperand::CreateImm(
4513        MCConstantExpr::Create(Val, getContext()), S,
4514        Parser.getTok().getLoc()));
4515    return MatchOperand_Success;
4516  }
4517
4518  Error(Loc, "invalid floating point immediate");
4519  return MatchOperand_ParseFail;
4520}
4521
4522/// Parse a arm instruction operand.  For now this parses the operand regardless
4523/// of the mnemonic.
4524bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4525                                StringRef Mnemonic) {
4526  SMLoc S, E;
4527
4528  // Check if the current operand has a custom associated parser, if so, try to
4529  // custom parse the operand, or fallback to the general approach.
4530  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4531  if (ResTy == MatchOperand_Success)
4532    return false;
4533  // If there wasn't a custom match, try the generic matcher below. Otherwise,
4534  // there was a match, but an error occurred, in which case, just return that
4535  // the operand parsing failed.
4536  if (ResTy == MatchOperand_ParseFail)
4537    return true;
4538
4539  switch (getLexer().getKind()) {
4540  default:
4541    Error(Parser.getTok().getLoc(), "unexpected token in operand");
4542    return true;
4543  case AsmToken::Identifier: {
4544    if (!tryParseRegisterWithWriteBack(Operands))
4545      return false;
4546    int Res = tryParseShiftRegister(Operands);
4547    if (Res == 0) // success
4548      return false;
4549    else if (Res == -1) // irrecoverable error
4550      return true;
4551    // If this is VMRS, check for the apsr_nzcv operand.
4552    if (Mnemonic == "vmrs" &&
4553        Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4554      S = Parser.getTok().getLoc();
4555      Parser.Lex();
4556      Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4557      return false;
4558    }
4559
4560    // Fall though for the Identifier case that is not a register or a
4561    // special name.
4562  }
4563  case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4564  case AsmToken::Integer: // things like 1f and 2b as a branch targets
4565  case AsmToken::String:  // quoted label names.
4566  case AsmToken::Dot: {   // . as a branch target
4567    // This was not a register so parse other operands that start with an
4568    // identifier (like labels) as expressions and create them as immediates.
4569    const MCExpr *IdVal;
4570    S = Parser.getTok().getLoc();
4571    if (getParser().ParseExpression(IdVal))
4572      return true;
4573    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4574    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4575    return false;
4576  }
4577  case AsmToken::LBrac:
4578    return parseMemory(Operands);
4579  case AsmToken::LCurly:
4580    return parseRegisterList(Operands);
4581  case AsmToken::Dollar:
4582  case AsmToken::Hash: {
4583    // #42 -> immediate.
4584    S = Parser.getTok().getLoc();
4585    Parser.Lex();
4586
4587    if (Parser.getTok().isNot(AsmToken::Colon)) {
4588      bool isNegative = Parser.getTok().is(AsmToken::Minus);
4589      const MCExpr *ImmVal;
4590      if (getParser().ParseExpression(ImmVal))
4591        return true;
4592      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4593      if (CE) {
4594        int32_t Val = CE->getValue();
4595        if (isNegative && Val == 0)
4596          ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4597      }
4598      E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4599      Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4600      return false;
4601    }
4602    // w/ a ':' after the '#', it's just like a plain ':'.
4603    // FALLTHROUGH
4604  }
4605  case AsmToken::Colon: {
4606    // ":lower16:" and ":upper16:" expression prefixes
4607    // FIXME: Check it's an expression prefix,
4608    // e.g. (FOO - :lower16:BAR) isn't legal.
4609    ARMMCExpr::VariantKind RefKind;
4610    if (parsePrefix(RefKind))
4611      return true;
4612
4613    const MCExpr *SubExprVal;
4614    if (getParser().ParseExpression(SubExprVal))
4615      return true;
4616
4617    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4618                                                   getContext());
4619    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4620    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4621    return false;
4622  }
4623  }
4624}
4625
4626// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4627//  :lower16: and :upper16:.
4628bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4629  RefKind = ARMMCExpr::VK_ARM_None;
4630
4631  // :lower16: and :upper16: modifiers
4632  assert(getLexer().is(AsmToken::Colon) && "expected a :");
4633  Parser.Lex(); // Eat ':'
4634
4635  if (getLexer().isNot(AsmToken::Identifier)) {
4636    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4637    return true;
4638  }
4639
4640  StringRef IDVal = Parser.getTok().getIdentifier();
4641  if (IDVal == "lower16") {
4642    RefKind = ARMMCExpr::VK_ARM_LO16;
4643  } else if (IDVal == "upper16") {
4644    RefKind = ARMMCExpr::VK_ARM_HI16;
4645  } else {
4646    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4647    return true;
4648  }
4649  Parser.Lex();
4650
4651  if (getLexer().isNot(AsmToken::Colon)) {
4652    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4653    return true;
4654  }
4655  Parser.Lex(); // Eat the last ':'
4656  return false;
4657}
4658
4659/// \brief Given a mnemonic, split out possible predication code and carry
4660/// setting letters to form a canonical mnemonic and flags.
4661//
4662// FIXME: Would be nice to autogen this.
4663// FIXME: This is a bit of a maze of special cases.
4664StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4665                                      unsigned &PredicationCode,
4666                                      bool &CarrySetting,
4667                                      unsigned &ProcessorIMod,
4668                                      StringRef &ITMask) {
4669  PredicationCode = ARMCC::AL;
4670  CarrySetting = false;
4671  ProcessorIMod = 0;
4672
4673  // Ignore some mnemonics we know aren't predicated forms.
4674  //
4675  // FIXME: Would be nice to autogen this.
4676  if ((Mnemonic == "movs" && isThumb()) ||
4677      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
4678      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
4679      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
4680      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
4681      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
4682      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
4683      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4684      Mnemonic == "fmuls")
4685    return Mnemonic;
4686
4687  // First, split out any predication code. Ignore mnemonics we know aren't
4688  // predicated but do have a carry-set and so weren't caught above.
4689  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4690      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4691      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4692      Mnemonic != "sbcs" && Mnemonic != "rscs") {
4693    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4694      .Case("eq", ARMCC::EQ)
4695      .Case("ne", ARMCC::NE)
4696      .Case("hs", ARMCC::HS)
4697      .Case("cs", ARMCC::HS)
4698      .Case("lo", ARMCC::LO)
4699      .Case("cc", ARMCC::LO)
4700      .Case("mi", ARMCC::MI)
4701      .Case("pl", ARMCC::PL)
4702      .Case("vs", ARMCC::VS)
4703      .Case("vc", ARMCC::VC)
4704      .Case("hi", ARMCC::HI)
4705      .Case("ls", ARMCC::LS)
4706      .Case("ge", ARMCC::GE)
4707      .Case("lt", ARMCC::LT)
4708      .Case("gt", ARMCC::GT)
4709      .Case("le", ARMCC::LE)
4710      .Case("al", ARMCC::AL)
4711      .Default(~0U);
4712    if (CC != ~0U) {
4713      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4714      PredicationCode = CC;
4715    }
4716  }
4717
4718  // Next, determine if we have a carry setting bit. We explicitly ignore all
4719  // the instructions we know end in 's'.
4720  if (Mnemonic.endswith("s") &&
4721      !(Mnemonic == "cps" || Mnemonic == "mls" ||
4722        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4723        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4724        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4725        Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4726        Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4727        Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4728        Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4729        Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4730        (Mnemonic == "movs" && isThumb()))) {
4731    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4732    CarrySetting = true;
4733  }
4734
4735  // The "cps" instruction can have a interrupt mode operand which is glued into
4736  // the mnemonic. Check if this is the case, split it and parse the imod op
4737  if (Mnemonic.startswith("cps")) {
4738    // Split out any imod code.
4739    unsigned IMod =
4740      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4741      .Case("ie", ARM_PROC::IE)
4742      .Case("id", ARM_PROC::ID)
4743      .Default(~0U);
4744    if (IMod != ~0U) {
4745      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4746      ProcessorIMod = IMod;
4747    }
4748  }
4749
4750  // The "it" instruction has the condition mask on the end of the mnemonic.
4751  if (Mnemonic.startswith("it")) {
4752    ITMask = Mnemonic.slice(2, Mnemonic.size());
4753    Mnemonic = Mnemonic.slice(0, 2);
4754  }
4755
4756  return Mnemonic;
4757}
4758
4759/// \brief Given a canonical mnemonic, determine if the instruction ever allows
4760/// inclusion of carry set or predication code operands.
4761//
4762// FIXME: It would be nice to autogen this.
4763void ARMAsmParser::
4764getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4765                      bool &CanAcceptPredicationCode) {
4766  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4767      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4768      Mnemonic == "add" || Mnemonic == "adc" ||
4769      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4770      Mnemonic == "orr" || Mnemonic == "mvn" ||
4771      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4772      Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4773      Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4774      (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4775                      Mnemonic == "mla" || Mnemonic == "smlal" ||
4776                      Mnemonic == "umlal" || Mnemonic == "umull"))) {
4777    CanAcceptCarrySet = true;
4778  } else
4779    CanAcceptCarrySet = false;
4780
4781  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4782      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4783      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4784      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4785      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4786      (Mnemonic == "clrex" && !isThumb()) ||
4787      (Mnemonic == "nop" && isThumbOne()) ||
4788      ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4789        Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4790        Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4791      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4792       !isThumb()) ||
4793      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4794    CanAcceptPredicationCode = false;
4795  } else
4796    CanAcceptPredicationCode = true;
4797
4798  if (isThumb()) {
4799    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4800        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4801      CanAcceptPredicationCode = false;
4802  }
4803}
4804
4805bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4806                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4807  // FIXME: This is all horribly hacky. We really need a better way to deal
4808  // with optional operands like this in the matcher table.
4809
4810  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4811  // another does not. Specifically, the MOVW instruction does not. So we
4812  // special case it here and remove the defaulted (non-setting) cc_out
4813  // operand if that's the instruction we're trying to match.
4814  //
4815  // We do this as post-processing of the explicit operands rather than just
4816  // conditionally adding the cc_out in the first place because we need
4817  // to check the type of the parsed immediate operand.
4818  if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4819      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4820      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4821      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4822    return true;
4823
4824  // Register-register 'add' for thumb does not have a cc_out operand
4825  // when there are only two register operands.
4826  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4827      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4828      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4829      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4830    return true;
4831  // Register-register 'add' for thumb does not have a cc_out operand
4832  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4833  // have to check the immediate range here since Thumb2 has a variant
4834  // that can handle a different range and has a cc_out operand.
4835  if (((isThumb() && Mnemonic == "add") ||
4836       (isThumbTwo() && Mnemonic == "sub")) &&
4837      Operands.size() == 6 &&
4838      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4839      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4840      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4841      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4842      ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4843       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4844    return true;
4845  // For Thumb2, add/sub immediate does not have a cc_out operand for the
4846  // imm0_4095 variant. That's the least-preferred variant when
4847  // selecting via the generic "add" mnemonic, so to know that we
4848  // should remove the cc_out operand, we have to explicitly check that
4849  // it's not one of the other variants. Ugh.
4850  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4851      Operands.size() == 6 &&
4852      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4853      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4854      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4855    // Nest conditions rather than one big 'if' statement for readability.
4856    //
4857    // If either register is a high reg, it's either one of the SP
4858    // variants (handled above) or a 32-bit encoding, so we just
4859    // check against T3. If the second register is the PC, this is an
4860    // alternate form of ADR, which uses encoding T4, so check for that too.
4861    if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4862         !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4863        static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4864        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4865      return false;
4866    // If both registers are low, we're in an IT block, and the immediate is
4867    // in range, we should use encoding T1 instead, which has a cc_out.
4868    if (inITBlock() &&
4869        isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4870        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4871        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4872      return false;
4873
4874    // Otherwise, we use encoding T4, which does not have a cc_out
4875    // operand.
4876    return true;
4877  }
4878
4879  // The thumb2 multiply instruction doesn't have a CCOut register, so
4880  // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4881  // use the 16-bit encoding or not.
4882  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4883      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4884      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4885      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4886      static_cast<ARMOperand*>(Operands[5])->isReg() &&
4887      // If the registers aren't low regs, the destination reg isn't the
4888      // same as one of the source regs, or the cc_out operand is zero
4889      // outside of an IT block, we have to use the 32-bit encoding, so
4890      // remove the cc_out operand.
4891      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4892       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4893       !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4894       !inITBlock() ||
4895       (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4896        static_cast<ARMOperand*>(Operands[5])->getReg() &&
4897        static_cast<ARMOperand*>(Operands[3])->getReg() !=
4898        static_cast<ARMOperand*>(Operands[4])->getReg())))
4899    return true;
4900
4901  // Also check the 'mul' syntax variant that doesn't specify an explicit
4902  // destination register.
4903  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4904      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4905      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4906      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4907      // If the registers aren't low regs  or the cc_out operand is zero
4908      // outside of an IT block, we have to use the 32-bit encoding, so
4909      // remove the cc_out operand.
4910      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4911       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4912       !inITBlock()))
4913    return true;
4914
4915
4916
4917  // Register-register 'add/sub' for thumb does not have a cc_out operand
4918  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4919  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4920  // right, this will result in better diagnostics (which operand is off)
4921  // anyway.
4922  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4923      (Operands.size() == 5 || Operands.size() == 6) &&
4924      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4925      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4926      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4927      (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4928       (Operands.size() == 6 &&
4929        static_cast<ARMOperand*>(Operands[5])->isImm())))
4930    return true;
4931
4932  return false;
4933}
4934
4935static bool isDataTypeToken(StringRef Tok) {
4936  return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4937    Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4938    Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4939    Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4940    Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4941    Tok == ".f" || Tok == ".d";
4942}
4943
4944// FIXME: This bit should probably be handled via an explicit match class
4945// in the .td files that matches the suffix instead of having it be
4946// a literal string token the way it is now.
4947static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4948  return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4949}
4950
4951static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features);
4952/// Parse an arm instruction mnemonic followed by its operands.
4953bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4954                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4955  // Apply mnemonic aliases before doing anything else, as the destination
4956  // mnemnonic may include suffices and we want to handle them normally.
4957  // The generic tblgen'erated code does this later, at the start of
4958  // MatchInstructionImpl(), but that's too late for aliases that include
4959  // any sort of suffix.
4960  unsigned AvailableFeatures = getAvailableFeatures();
4961  applyMnemonicAliases(Name, AvailableFeatures);
4962
4963  // First check for the ARM-specific .req directive.
4964  if (Parser.getTok().is(AsmToken::Identifier) &&
4965      Parser.getTok().getIdentifier() == ".req") {
4966    parseDirectiveReq(Name, NameLoc);
4967    // We always return 'error' for this, as we're done with this
4968    // statement and don't need to match the 'instruction."
4969    return true;
4970  }
4971
4972  // Create the leading tokens for the mnemonic, split by '.' characters.
4973  size_t Start = 0, Next = Name.find('.');
4974  StringRef Mnemonic = Name.slice(Start, Next);
4975
4976  // Split out the predication code and carry setting flag from the mnemonic.
4977  unsigned PredicationCode;
4978  unsigned ProcessorIMod;
4979  bool CarrySetting;
4980  StringRef ITMask;
4981  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
4982                           ProcessorIMod, ITMask);
4983
4984  // In Thumb1, only the branch (B) instruction can be predicated.
4985  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
4986    Parser.EatToEndOfStatement();
4987    return Error(NameLoc, "conditional execution not supported in Thumb1");
4988  }
4989
4990  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
4991
4992  // Handle the IT instruction ITMask. Convert it to a bitmask. This
4993  // is the mask as it will be for the IT encoding if the conditional
4994  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
4995  // where the conditional bit0 is zero, the instruction post-processing
4996  // will adjust the mask accordingly.
4997  if (Mnemonic == "it") {
4998    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
4999    if (ITMask.size() > 3) {
5000      Parser.EatToEndOfStatement();
5001      return Error(Loc, "too many conditions on IT instruction");
5002    }
5003    unsigned Mask = 8;
5004    for (unsigned i = ITMask.size(); i != 0; --i) {
5005      char pos = ITMask[i - 1];
5006      if (pos != 't' && pos != 'e') {
5007        Parser.EatToEndOfStatement();
5008        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5009      }
5010      Mask >>= 1;
5011      if (ITMask[i - 1] == 't')
5012        Mask |= 8;
5013    }
5014    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5015  }
5016
5017  // FIXME: This is all a pretty gross hack. We should automatically handle
5018  // optional operands like this via tblgen.
5019
5020  // Next, add the CCOut and ConditionCode operands, if needed.
5021  //
5022  // For mnemonics which can ever incorporate a carry setting bit or predication
5023  // code, our matching model involves us always generating CCOut and
5024  // ConditionCode operands to match the mnemonic "as written" and then we let
5025  // the matcher deal with finding the right instruction or generating an
5026  // appropriate error.
5027  bool CanAcceptCarrySet, CanAcceptPredicationCode;
5028  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5029
5030  // If we had a carry-set on an instruction that can't do that, issue an
5031  // error.
5032  if (!CanAcceptCarrySet && CarrySetting) {
5033    Parser.EatToEndOfStatement();
5034    return Error(NameLoc, "instruction '" + Mnemonic +
5035                 "' can not set flags, but 's' suffix specified");
5036  }
5037  // If we had a predication code on an instruction that can't do that, issue an
5038  // error.
5039  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5040    Parser.EatToEndOfStatement();
5041    return Error(NameLoc, "instruction '" + Mnemonic +
5042                 "' is not predicable, but condition code specified");
5043  }
5044
5045  // Add the carry setting operand, if necessary.
5046  if (CanAcceptCarrySet) {
5047    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5048    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5049                                               Loc));
5050  }
5051
5052  // Add the predication code operand, if necessary.
5053  if (CanAcceptPredicationCode) {
5054    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5055                                      CarrySetting);
5056    Operands.push_back(ARMOperand::CreateCondCode(
5057                         ARMCC::CondCodes(PredicationCode), Loc));
5058  }
5059
5060  // Add the processor imod operand, if necessary.
5061  if (ProcessorIMod) {
5062    Operands.push_back(ARMOperand::CreateImm(
5063          MCConstantExpr::Create(ProcessorIMod, getContext()),
5064                                 NameLoc, NameLoc));
5065  }
5066
5067  // Add the remaining tokens in the mnemonic.
5068  while (Next != StringRef::npos) {
5069    Start = Next;
5070    Next = Name.find('.', Start + 1);
5071    StringRef ExtraToken = Name.slice(Start, Next);
5072
5073    // Some NEON instructions have an optional datatype suffix that is
5074    // completely ignored. Check for that.
5075    if (isDataTypeToken(ExtraToken) &&
5076        doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5077      continue;
5078
5079    if (ExtraToken != ".n") {
5080      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5081      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5082    }
5083  }
5084
5085  // Read the remaining operands.
5086  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5087    // Read the first operand.
5088    if (parseOperand(Operands, Mnemonic)) {
5089      Parser.EatToEndOfStatement();
5090      return true;
5091    }
5092
5093    while (getLexer().is(AsmToken::Comma)) {
5094      Parser.Lex();  // Eat the comma.
5095
5096      // Parse and remember the operand.
5097      if (parseOperand(Operands, Mnemonic)) {
5098        Parser.EatToEndOfStatement();
5099        return true;
5100      }
5101    }
5102  }
5103
5104  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5105    SMLoc Loc = getLexer().getLoc();
5106    Parser.EatToEndOfStatement();
5107    return Error(Loc, "unexpected token in argument list");
5108  }
5109
5110  Parser.Lex(); // Consume the EndOfStatement
5111
5112  // Some instructions, mostly Thumb, have forms for the same mnemonic that
5113  // do and don't have a cc_out optional-def operand. With some spot-checks
5114  // of the operand list, we can figure out which variant we're trying to
5115  // parse and adjust accordingly before actually matching. We shouldn't ever
5116  // try to remove a cc_out operand that was explicitly set on the the
5117  // mnemonic, of course (CarrySetting == true). Reason number #317 the
5118  // table driven matcher doesn't fit well with the ARM instruction set.
5119  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5120    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5121    Operands.erase(Operands.begin() + 1);
5122    delete Op;
5123  }
5124
5125  // ARM mode 'blx' need special handling, as the register operand version
5126  // is predicable, but the label operand version is not. So, we can't rely
5127  // on the Mnemonic based checking to correctly figure out when to put
5128  // a k_CondCode operand in the list. If we're trying to match the label
5129  // version, remove the k_CondCode operand here.
5130  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5131      static_cast<ARMOperand*>(Operands[2])->isImm()) {
5132    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5133    Operands.erase(Operands.begin() + 1);
5134    delete Op;
5135  }
5136
5137  // The vector-compare-to-zero instructions have a literal token "#0" at
5138  // the end that comes to here as an immediate operand. Convert it to a
5139  // token to play nicely with the matcher.
5140  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
5141      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
5142      static_cast<ARMOperand*>(Operands[5])->isImm()) {
5143    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5144    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5145    if (CE && CE->getValue() == 0) {
5146      Operands.erase(Operands.begin() + 5);
5147      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5148      delete Op;
5149    }
5150  }
5151  // VCMP{E} does the same thing, but with a different operand count.
5152  if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
5153      static_cast<ARMOperand*>(Operands[4])->isImm()) {
5154    ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
5155    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5156    if (CE && CE->getValue() == 0) {
5157      Operands.erase(Operands.begin() + 4);
5158      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5159      delete Op;
5160    }
5161  }
5162  // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
5163  // end. Convert it to a token here. Take care not to convert those
5164  // that should hit the Thumb2 encoding.
5165  if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
5166      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5167      static_cast<ARMOperand*>(Operands[4])->isReg() &&
5168      static_cast<ARMOperand*>(Operands[5])->isImm()) {
5169    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5170    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5171    if (CE && CE->getValue() == 0 &&
5172        (isThumbOne() ||
5173         // The cc_out operand matches the IT block.
5174         ((inITBlock() != CarrySetting) &&
5175         // Neither register operand is a high register.
5176         (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5177          isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){
5178      Operands.erase(Operands.begin() + 5);
5179      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5180      delete Op;
5181    }
5182  }
5183
5184  return false;
5185}
5186
5187// Validate context-sensitive operand constraints.
5188
5189// return 'true' if register list contains non-low GPR registers,
5190// 'false' otherwise. If Reg is in the register list or is HiReg, set
5191// 'containsReg' to true.
5192static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5193                                 unsigned HiReg, bool &containsReg) {
5194  containsReg = false;
5195  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5196    unsigned OpReg = Inst.getOperand(i).getReg();
5197    if (OpReg == Reg)
5198      containsReg = true;
5199    // Anything other than a low register isn't legal here.
5200    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5201      return true;
5202  }
5203  return false;
5204}
5205
5206// Check if the specified regisgter is in the register list of the inst,
5207// starting at the indicated operand number.
5208static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5209  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5210    unsigned OpReg = Inst.getOperand(i).getReg();
5211    if (OpReg == Reg)
5212      return true;
5213  }
5214  return false;
5215}
5216
5217// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5218// the ARMInsts array) instead. Getting that here requires awkward
5219// API changes, though. Better way?
5220namespace llvm {
5221extern const MCInstrDesc ARMInsts[];
5222}
5223static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5224  return ARMInsts[Opcode];
5225}
5226
5227// FIXME: We would really like to be able to tablegen'erate this.
5228bool ARMAsmParser::
5229validateInstruction(MCInst &Inst,
5230                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5231  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5232  SMLoc Loc = Operands[0]->getStartLoc();
5233  // Check the IT block state first.
5234  // NOTE: BKPT instruction has the interesting property of being
5235  // allowed in IT blocks, but not being predicable.  It just always
5236  // executes.
5237  if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5238      Inst.getOpcode() != ARM::BKPT) {
5239    unsigned bit = 1;
5240    if (ITState.FirstCond)
5241      ITState.FirstCond = false;
5242    else
5243      bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5244    // The instruction must be predicable.
5245    if (!MCID.isPredicable())
5246      return Error(Loc, "instructions in IT block must be predicable");
5247    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5248    unsigned ITCond = bit ? ITState.Cond :
5249      ARMCC::getOppositeCondition(ITState.Cond);
5250    if (Cond != ITCond) {
5251      // Find the condition code Operand to get its SMLoc information.
5252      SMLoc CondLoc;
5253      for (unsigned i = 1; i < Operands.size(); ++i)
5254        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5255          CondLoc = Operands[i]->getStartLoc();
5256      return Error(CondLoc, "incorrect condition in IT block; got '" +
5257                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5258                   "', but expected '" +
5259                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5260    }
5261  // Check for non-'al' condition codes outside of the IT block.
5262  } else if (isThumbTwo() && MCID.isPredicable() &&
5263             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5264             ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5265             Inst.getOpcode() != ARM::t2B)
5266    return Error(Loc, "predicated instructions must be in IT block");
5267
5268  switch (Inst.getOpcode()) {
5269  case ARM::LDRD:
5270  case ARM::LDRD_PRE:
5271  case ARM::LDRD_POST:
5272  case ARM::LDREXD: {
5273    // Rt2 must be Rt + 1.
5274    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5275    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5276    if (Rt2 != Rt + 1)
5277      return Error(Operands[3]->getStartLoc(),
5278                   "destination operands must be sequential");
5279    return false;
5280  }
5281  case ARM::STRD: {
5282    // Rt2 must be Rt + 1.
5283    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5284    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5285    if (Rt2 != Rt + 1)
5286      return Error(Operands[3]->getStartLoc(),
5287                   "source operands must be sequential");
5288    return false;
5289  }
5290  case ARM::STRD_PRE:
5291  case ARM::STRD_POST:
5292  case ARM::STREXD: {
5293    // Rt2 must be Rt + 1.
5294    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5295    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5296    if (Rt2 != Rt + 1)
5297      return Error(Operands[3]->getStartLoc(),
5298                   "source operands must be sequential");
5299    return false;
5300  }
5301  case ARM::SBFX:
5302  case ARM::UBFX: {
5303    // width must be in range [1, 32-lsb]
5304    unsigned lsb = Inst.getOperand(2).getImm();
5305    unsigned widthm1 = Inst.getOperand(3).getImm();
5306    if (widthm1 >= 32 - lsb)
5307      return Error(Operands[5]->getStartLoc(),
5308                   "bitfield width must be in range [1,32-lsb]");
5309    return false;
5310  }
5311  case ARM::tLDMIA: {
5312    // If we're parsing Thumb2, the .w variant is available and handles
5313    // most cases that are normally illegal for a Thumb1 LDM
5314    // instruction. We'll make the transformation in processInstruction()
5315    // if necessary.
5316    //
5317    // Thumb LDM instructions are writeback iff the base register is not
5318    // in the register list.
5319    unsigned Rn = Inst.getOperand(0).getReg();
5320    bool hasWritebackToken =
5321      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5322       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5323    bool listContainsBase;
5324    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5325      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5326                   "registers must be in range r0-r7");
5327    // If we should have writeback, then there should be a '!' token.
5328    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5329      return Error(Operands[2]->getStartLoc(),
5330                   "writeback operator '!' expected");
5331    // If we should not have writeback, there must not be a '!'. This is
5332    // true even for the 32-bit wide encodings.
5333    if (listContainsBase && hasWritebackToken)
5334      return Error(Operands[3]->getStartLoc(),
5335                   "writeback operator '!' not allowed when base register "
5336                   "in register list");
5337
5338    break;
5339  }
5340  case ARM::t2LDMIA_UPD: {
5341    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5342      return Error(Operands[4]->getStartLoc(),
5343                   "writeback operator '!' not allowed when base register "
5344                   "in register list");
5345    break;
5346  }
5347  case ARM::tMUL: {
5348    // The second source operand must be the same register as the destination
5349    // operand.
5350    //
5351    // In this case, we must directly check the parsed operands because the
5352    // cvtThumbMultiply() function is written in such a way that it guarantees
5353    // this first statement is always true for the new Inst.  Essentially, the
5354    // destination is unconditionally copied into the second source operand
5355    // without checking to see if it matches what we actually parsed.
5356    if (Operands.size() == 6 &&
5357        (((ARMOperand*)Operands[3])->getReg() !=
5358         ((ARMOperand*)Operands[5])->getReg()) &&
5359        (((ARMOperand*)Operands[3])->getReg() !=
5360         ((ARMOperand*)Operands[4])->getReg())) {
5361      return Error(Operands[3]->getStartLoc(),
5362                   "destination register must match source register");
5363    }
5364    break;
5365  }
5366  // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5367  // so only issue a diagnostic for thumb1. The instructions will be
5368  // switched to the t2 encodings in processInstruction() if necessary.
5369  case ARM::tPOP: {
5370    bool listContainsBase;
5371    if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5372        !isThumbTwo())
5373      return Error(Operands[2]->getStartLoc(),
5374                   "registers must be in range r0-r7 or pc");
5375    break;
5376  }
5377  case ARM::tPUSH: {
5378    bool listContainsBase;
5379    if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5380        !isThumbTwo())
5381      return Error(Operands[2]->getStartLoc(),
5382                   "registers must be in range r0-r7 or lr");
5383    break;
5384  }
5385  case ARM::tSTMIA_UPD: {
5386    bool listContainsBase;
5387    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5388      return Error(Operands[4]->getStartLoc(),
5389                   "registers must be in range r0-r7");
5390    break;
5391  }
5392  case ARM::tADDrSP: {
5393    // If the non-SP source operand and the destination operand are not the
5394    // same, we need thumb2 (for the wide encoding), or we have an error.
5395    if (!isThumbTwo() &&
5396        Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5397      return Error(Operands[4]->getStartLoc(),
5398                   "source register must be the same as destination");
5399    }
5400    break;
5401  }
5402  }
5403
5404  return false;
5405}
5406
5407static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5408  switch(Opc) {
5409  default: llvm_unreachable("unexpected opcode!");
5410  // VST1LN
5411  case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5412  case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5413  case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5414  case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5415  case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5416  case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5417  case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
5418  case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5419  case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5420
5421  // VST2LN
5422  case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5423  case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5424  case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5425  case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5426  case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5427
5428  case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5429  case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5430  case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5431  case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5432  case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5433
5434  case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
5435  case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5436  case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5437  case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5438  case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5439
5440  // VST3LN
5441  case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5442  case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5443  case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5444  case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5445  case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5446  case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5447  case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5448  case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5449  case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5450  case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5451  case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
5452  case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5453  case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5454  case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5455  case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5456
5457  // VST3
5458  case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5459  case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5460  case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5461  case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5462  case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5463  case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5464  case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5465  case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5466  case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5467  case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5468  case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5469  case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5470  case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
5471  case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5472  case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5473  case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
5474  case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5475  case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5476
5477  // VST4LN
5478  case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5479  case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5480  case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5481  case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5482  case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5483  case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5484  case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5485  case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5486  case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5487  case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5488  case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
5489  case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5490  case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5491  case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5492  case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5493
5494  // VST4
5495  case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5496  case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5497  case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5498  case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5499  case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5500  case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5501  case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5502  case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5503  case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5504  case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5505  case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5506  case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5507  case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
5508  case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5509  case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5510  case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
5511  case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5512  case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5513  }
5514}
5515
5516static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5517  switch(Opc) {
5518  default: llvm_unreachable("unexpected opcode!");
5519  // VLD1LN
5520  case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5521  case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5522  case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5523  case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5524  case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5525  case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5526  case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
5527  case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5528  case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5529
5530  // VLD2LN
5531  case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5532  case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5533  case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5534  case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5535  case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5536  case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5537  case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5538  case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5539  case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5540  case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5541  case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
5542  case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5543  case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5544  case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5545  case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5546
5547  // VLD3DUP
5548  case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5549  case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5550  case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5551  case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5552  case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5553  case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5554  case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5555  case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5556  case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5557  case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5558  case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5559  case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5560  case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
5561  case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5562  case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5563  case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5564  case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5565  case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5566
5567  // VLD3LN
5568  case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5569  case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5570  case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5571  case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5572  case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5573  case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5574  case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5575  case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5576  case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5577  case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5578  case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
5579  case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5580  case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5581  case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5582  case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5583
5584  // VLD3
5585  case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5586  case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5587  case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5588  case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5589  case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5590  case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5591  case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5592  case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5593  case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5594  case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5595  case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5596  case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5597  case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
5598  case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5599  case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5600  case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
5601  case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5602  case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5603
5604  // VLD4LN
5605  case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5606  case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5607  case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5608  case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5609  case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5610  case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5611  case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5612  case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5613  case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5614  case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5615  case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
5616  case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5617  case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5618  case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5619  case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5620
5621  // VLD4DUP
5622  case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5623  case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5624  case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5625  case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5626  case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5627  case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5628  case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5629  case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5630  case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5631  case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5632  case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5633  case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5634  case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
5635  case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5636  case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5637  case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5638  case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5639  case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5640
5641  // VLD4
5642  case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5643  case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5644  case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5645  case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5646  case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5647  case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5648  case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5649  case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5650  case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5651  case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5652  case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5653  case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5654  case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
5655  case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5656  case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5657  case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
5658  case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5659  case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5660  }
5661}
5662
5663bool ARMAsmParser::
5664processInstruction(MCInst &Inst,
5665                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5666  switch (Inst.getOpcode()) {
5667  // Aliases for alternate PC+imm syntax of LDR instructions.
5668  case ARM::t2LDRpcrel:
5669    Inst.setOpcode(ARM::t2LDRpci);
5670    return true;
5671  case ARM::t2LDRBpcrel:
5672    Inst.setOpcode(ARM::t2LDRBpci);
5673    return true;
5674  case ARM::t2LDRHpcrel:
5675    Inst.setOpcode(ARM::t2LDRHpci);
5676    return true;
5677  case ARM::t2LDRSBpcrel:
5678    Inst.setOpcode(ARM::t2LDRSBpci);
5679    return true;
5680  case ARM::t2LDRSHpcrel:
5681    Inst.setOpcode(ARM::t2LDRSHpci);
5682    return true;
5683  // Handle NEON VST complex aliases.
5684  case ARM::VST1LNdWB_register_Asm_8:
5685  case ARM::VST1LNdWB_register_Asm_16:
5686  case ARM::VST1LNdWB_register_Asm_32: {
5687    MCInst TmpInst;
5688    // Shuffle the operands around so the lane index operand is in the
5689    // right place.
5690    unsigned Spacing;
5691    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5692    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5693    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5694    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5695    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5696    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5697    TmpInst.addOperand(Inst.getOperand(1)); // lane
5698    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5699    TmpInst.addOperand(Inst.getOperand(6));
5700    Inst = TmpInst;
5701    return true;
5702  }
5703
5704  case ARM::VST2LNdWB_register_Asm_8:
5705  case ARM::VST2LNdWB_register_Asm_16:
5706  case ARM::VST2LNdWB_register_Asm_32:
5707  case ARM::VST2LNqWB_register_Asm_16:
5708  case ARM::VST2LNqWB_register_Asm_32: {
5709    MCInst TmpInst;
5710    // Shuffle the operands around so the lane index operand is in the
5711    // right place.
5712    unsigned Spacing;
5713    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5714    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5715    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5716    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5717    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5718    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5719    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5720                                            Spacing));
5721    TmpInst.addOperand(Inst.getOperand(1)); // lane
5722    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5723    TmpInst.addOperand(Inst.getOperand(6));
5724    Inst = TmpInst;
5725    return true;
5726  }
5727
5728  case ARM::VST3LNdWB_register_Asm_8:
5729  case ARM::VST3LNdWB_register_Asm_16:
5730  case ARM::VST3LNdWB_register_Asm_32:
5731  case ARM::VST3LNqWB_register_Asm_16:
5732  case ARM::VST3LNqWB_register_Asm_32: {
5733    MCInst TmpInst;
5734    // Shuffle the operands around so the lane index operand is in the
5735    // right place.
5736    unsigned Spacing;
5737    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5738    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5739    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5740    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5741    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5742    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5743    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5744                                            Spacing));
5745    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5746                                            Spacing * 2));
5747    TmpInst.addOperand(Inst.getOperand(1)); // lane
5748    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5749    TmpInst.addOperand(Inst.getOperand(6));
5750    Inst = TmpInst;
5751    return true;
5752  }
5753
5754  case ARM::VST4LNdWB_register_Asm_8:
5755  case ARM::VST4LNdWB_register_Asm_16:
5756  case ARM::VST4LNdWB_register_Asm_32:
5757  case ARM::VST4LNqWB_register_Asm_16:
5758  case ARM::VST4LNqWB_register_Asm_32: {
5759    MCInst TmpInst;
5760    // Shuffle the operands around so the lane index operand is in the
5761    // right place.
5762    unsigned Spacing;
5763    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5764    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5765    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5766    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5767    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5768    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5769    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5770                                            Spacing));
5771    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5772                                            Spacing * 2));
5773    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5774                                            Spacing * 3));
5775    TmpInst.addOperand(Inst.getOperand(1)); // lane
5776    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5777    TmpInst.addOperand(Inst.getOperand(6));
5778    Inst = TmpInst;
5779    return true;
5780  }
5781
5782  case ARM::VST1LNdWB_fixed_Asm_8:
5783  case ARM::VST1LNdWB_fixed_Asm_16:
5784  case ARM::VST1LNdWB_fixed_Asm_32: {
5785    MCInst TmpInst;
5786    // Shuffle the operands around so the lane index operand is in the
5787    // right place.
5788    unsigned Spacing;
5789    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5790    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5791    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5792    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5793    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5794    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5795    TmpInst.addOperand(Inst.getOperand(1)); // lane
5796    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5797    TmpInst.addOperand(Inst.getOperand(5));
5798    Inst = TmpInst;
5799    return true;
5800  }
5801
5802  case ARM::VST2LNdWB_fixed_Asm_8:
5803  case ARM::VST2LNdWB_fixed_Asm_16:
5804  case ARM::VST2LNdWB_fixed_Asm_32:
5805  case ARM::VST2LNqWB_fixed_Asm_16:
5806  case ARM::VST2LNqWB_fixed_Asm_32: {
5807    MCInst TmpInst;
5808    // Shuffle the operands around so the lane index operand is in the
5809    // right place.
5810    unsigned Spacing;
5811    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5812    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5813    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5814    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5815    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5816    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5817    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5818                                            Spacing));
5819    TmpInst.addOperand(Inst.getOperand(1)); // lane
5820    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5821    TmpInst.addOperand(Inst.getOperand(5));
5822    Inst = TmpInst;
5823    return true;
5824  }
5825
5826  case ARM::VST3LNdWB_fixed_Asm_8:
5827  case ARM::VST3LNdWB_fixed_Asm_16:
5828  case ARM::VST3LNdWB_fixed_Asm_32:
5829  case ARM::VST3LNqWB_fixed_Asm_16:
5830  case ARM::VST3LNqWB_fixed_Asm_32: {
5831    MCInst TmpInst;
5832    // Shuffle the operands around so the lane index operand is in the
5833    // right place.
5834    unsigned Spacing;
5835    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5836    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5837    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5838    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5839    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5840    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5841    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5842                                            Spacing));
5843    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5844                                            Spacing * 2));
5845    TmpInst.addOperand(Inst.getOperand(1)); // lane
5846    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5847    TmpInst.addOperand(Inst.getOperand(5));
5848    Inst = TmpInst;
5849    return true;
5850  }
5851
5852  case ARM::VST4LNdWB_fixed_Asm_8:
5853  case ARM::VST4LNdWB_fixed_Asm_16:
5854  case ARM::VST4LNdWB_fixed_Asm_32:
5855  case ARM::VST4LNqWB_fixed_Asm_16:
5856  case ARM::VST4LNqWB_fixed_Asm_32: {
5857    MCInst TmpInst;
5858    // Shuffle the operands around so the lane index operand is in the
5859    // right place.
5860    unsigned Spacing;
5861    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5862    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5863    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5864    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5865    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5866    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5867    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5868                                            Spacing));
5869    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5870                                            Spacing * 2));
5871    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5872                                            Spacing * 3));
5873    TmpInst.addOperand(Inst.getOperand(1)); // lane
5874    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5875    TmpInst.addOperand(Inst.getOperand(5));
5876    Inst = TmpInst;
5877    return true;
5878  }
5879
5880  case ARM::VST1LNdAsm_8:
5881  case ARM::VST1LNdAsm_16:
5882  case ARM::VST1LNdAsm_32: {
5883    MCInst TmpInst;
5884    // Shuffle the operands around so the lane index operand is in the
5885    // right place.
5886    unsigned Spacing;
5887    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5888    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5889    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5890    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5891    TmpInst.addOperand(Inst.getOperand(1)); // lane
5892    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5893    TmpInst.addOperand(Inst.getOperand(5));
5894    Inst = TmpInst;
5895    return true;
5896  }
5897
5898  case ARM::VST2LNdAsm_8:
5899  case ARM::VST2LNdAsm_16:
5900  case ARM::VST2LNdAsm_32:
5901  case ARM::VST2LNqAsm_16:
5902  case ARM::VST2LNqAsm_32: {
5903    MCInst TmpInst;
5904    // Shuffle the operands around so the lane index operand is in the
5905    // right place.
5906    unsigned Spacing;
5907    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5908    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5909    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5910    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5911    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5912                                            Spacing));
5913    TmpInst.addOperand(Inst.getOperand(1)); // lane
5914    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5915    TmpInst.addOperand(Inst.getOperand(5));
5916    Inst = TmpInst;
5917    return true;
5918  }
5919
5920  case ARM::VST3LNdAsm_8:
5921  case ARM::VST3LNdAsm_16:
5922  case ARM::VST3LNdAsm_32:
5923  case ARM::VST3LNqAsm_16:
5924  case ARM::VST3LNqAsm_32: {
5925    MCInst TmpInst;
5926    // Shuffle the operands around so the lane index operand is in the
5927    // right place.
5928    unsigned Spacing;
5929    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5930    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5931    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5932    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5933    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5934                                            Spacing));
5935    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5936                                            Spacing * 2));
5937    TmpInst.addOperand(Inst.getOperand(1)); // lane
5938    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5939    TmpInst.addOperand(Inst.getOperand(5));
5940    Inst = TmpInst;
5941    return true;
5942  }
5943
5944  case ARM::VST4LNdAsm_8:
5945  case ARM::VST4LNdAsm_16:
5946  case ARM::VST4LNdAsm_32:
5947  case ARM::VST4LNqAsm_16:
5948  case ARM::VST4LNqAsm_32: {
5949    MCInst TmpInst;
5950    // Shuffle the operands around so the lane index operand is in the
5951    // right place.
5952    unsigned Spacing;
5953    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5954    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5955    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5956    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5957    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5958                                            Spacing));
5959    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5960                                            Spacing * 2));
5961    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5962                                            Spacing * 3));
5963    TmpInst.addOperand(Inst.getOperand(1)); // lane
5964    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5965    TmpInst.addOperand(Inst.getOperand(5));
5966    Inst = TmpInst;
5967    return true;
5968  }
5969
5970  // Handle NEON VLD complex aliases.
5971  case ARM::VLD1LNdWB_register_Asm_8:
5972  case ARM::VLD1LNdWB_register_Asm_16:
5973  case ARM::VLD1LNdWB_register_Asm_32: {
5974    MCInst TmpInst;
5975    // Shuffle the operands around so the lane index operand is in the
5976    // right place.
5977    unsigned Spacing;
5978    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5979    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5980    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5981    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5982    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5983    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5984    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5985    TmpInst.addOperand(Inst.getOperand(1)); // lane
5986    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5987    TmpInst.addOperand(Inst.getOperand(6));
5988    Inst = TmpInst;
5989    return true;
5990  }
5991
5992  case ARM::VLD2LNdWB_register_Asm_8:
5993  case ARM::VLD2LNdWB_register_Asm_16:
5994  case ARM::VLD2LNdWB_register_Asm_32:
5995  case ARM::VLD2LNqWB_register_Asm_16:
5996  case ARM::VLD2LNqWB_register_Asm_32: {
5997    MCInst TmpInst;
5998    // Shuffle the operands around so the lane index operand is in the
5999    // right place.
6000    unsigned Spacing;
6001    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6002    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6003    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6004                                            Spacing));
6005    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6006    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6007    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6008    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6009    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6010    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6011                                            Spacing));
6012    TmpInst.addOperand(Inst.getOperand(1)); // lane
6013    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6014    TmpInst.addOperand(Inst.getOperand(6));
6015    Inst = TmpInst;
6016    return true;
6017  }
6018
6019  case ARM::VLD3LNdWB_register_Asm_8:
6020  case ARM::VLD3LNdWB_register_Asm_16:
6021  case ARM::VLD3LNdWB_register_Asm_32:
6022  case ARM::VLD3LNqWB_register_Asm_16:
6023  case ARM::VLD3LNqWB_register_Asm_32: {
6024    MCInst TmpInst;
6025    // Shuffle the operands around so the lane index operand is in the
6026    // right place.
6027    unsigned Spacing;
6028    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6029    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6030    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6031                                            Spacing));
6032    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6033                                            Spacing * 2));
6034    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6035    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6036    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6037    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6038    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6039    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6040                                            Spacing));
6041    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6042                                            Spacing * 2));
6043    TmpInst.addOperand(Inst.getOperand(1)); // lane
6044    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6045    TmpInst.addOperand(Inst.getOperand(6));
6046    Inst = TmpInst;
6047    return true;
6048  }
6049
6050  case ARM::VLD4LNdWB_register_Asm_8:
6051  case ARM::VLD4LNdWB_register_Asm_16:
6052  case ARM::VLD4LNdWB_register_Asm_32:
6053  case ARM::VLD4LNqWB_register_Asm_16:
6054  case ARM::VLD4LNqWB_register_Asm_32: {
6055    MCInst TmpInst;
6056    // Shuffle the operands around so the lane index operand is in the
6057    // right place.
6058    unsigned Spacing;
6059    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6060    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6061    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6062                                            Spacing));
6063    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6064                                            Spacing * 2));
6065    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6066                                            Spacing * 3));
6067    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6068    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6069    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6070    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6071    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6072    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6073                                            Spacing));
6074    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6075                                            Spacing * 2));
6076    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6077                                            Spacing * 3));
6078    TmpInst.addOperand(Inst.getOperand(1)); // lane
6079    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6080    TmpInst.addOperand(Inst.getOperand(6));
6081    Inst = TmpInst;
6082    return true;
6083  }
6084
6085  case ARM::VLD1LNdWB_fixed_Asm_8:
6086  case ARM::VLD1LNdWB_fixed_Asm_16:
6087  case ARM::VLD1LNdWB_fixed_Asm_32: {
6088    MCInst TmpInst;
6089    // Shuffle the operands around so the lane index operand is in the
6090    // right place.
6091    unsigned Spacing;
6092    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6093    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6094    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6095    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6096    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6097    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6098    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6099    TmpInst.addOperand(Inst.getOperand(1)); // lane
6100    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6101    TmpInst.addOperand(Inst.getOperand(5));
6102    Inst = TmpInst;
6103    return true;
6104  }
6105
6106  case ARM::VLD2LNdWB_fixed_Asm_8:
6107  case ARM::VLD2LNdWB_fixed_Asm_16:
6108  case ARM::VLD2LNdWB_fixed_Asm_32:
6109  case ARM::VLD2LNqWB_fixed_Asm_16:
6110  case ARM::VLD2LNqWB_fixed_Asm_32: {
6111    MCInst TmpInst;
6112    // Shuffle the operands around so the lane index operand is in the
6113    // right place.
6114    unsigned Spacing;
6115    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6116    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6117    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6118                                            Spacing));
6119    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6120    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6121    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6122    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6123    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6124    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6125                                            Spacing));
6126    TmpInst.addOperand(Inst.getOperand(1)); // lane
6127    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6128    TmpInst.addOperand(Inst.getOperand(5));
6129    Inst = TmpInst;
6130    return true;
6131  }
6132
6133  case ARM::VLD3LNdWB_fixed_Asm_8:
6134  case ARM::VLD3LNdWB_fixed_Asm_16:
6135  case ARM::VLD3LNdWB_fixed_Asm_32:
6136  case ARM::VLD3LNqWB_fixed_Asm_16:
6137  case ARM::VLD3LNqWB_fixed_Asm_32: {
6138    MCInst TmpInst;
6139    // Shuffle the operands around so the lane index operand is in the
6140    // right place.
6141    unsigned Spacing;
6142    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6143    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6144    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6145                                            Spacing));
6146    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6147                                            Spacing * 2));
6148    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6149    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6150    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6151    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6152    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6153    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6154                                            Spacing));
6155    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6156                                            Spacing * 2));
6157    TmpInst.addOperand(Inst.getOperand(1)); // lane
6158    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6159    TmpInst.addOperand(Inst.getOperand(5));
6160    Inst = TmpInst;
6161    return true;
6162  }
6163
6164  case ARM::VLD4LNdWB_fixed_Asm_8:
6165  case ARM::VLD4LNdWB_fixed_Asm_16:
6166  case ARM::VLD4LNdWB_fixed_Asm_32:
6167  case ARM::VLD4LNqWB_fixed_Asm_16:
6168  case ARM::VLD4LNqWB_fixed_Asm_32: {
6169    MCInst TmpInst;
6170    // Shuffle the operands around so the lane index operand is in the
6171    // right place.
6172    unsigned Spacing;
6173    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6174    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6175    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6176                                            Spacing));
6177    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6178                                            Spacing * 2));
6179    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6180                                            Spacing * 3));
6181    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6182    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6183    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6184    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6185    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6186    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6187                                            Spacing));
6188    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6189                                            Spacing * 2));
6190    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6191                                            Spacing * 3));
6192    TmpInst.addOperand(Inst.getOperand(1)); // lane
6193    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6194    TmpInst.addOperand(Inst.getOperand(5));
6195    Inst = TmpInst;
6196    return true;
6197  }
6198
6199  case ARM::VLD1LNdAsm_8:
6200  case ARM::VLD1LNdAsm_16:
6201  case ARM::VLD1LNdAsm_32: {
6202    MCInst TmpInst;
6203    // Shuffle the operands around so the lane index operand is in the
6204    // right place.
6205    unsigned Spacing;
6206    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6207    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6208    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6209    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6210    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6211    TmpInst.addOperand(Inst.getOperand(1)); // lane
6212    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6213    TmpInst.addOperand(Inst.getOperand(5));
6214    Inst = TmpInst;
6215    return true;
6216  }
6217
6218  case ARM::VLD2LNdAsm_8:
6219  case ARM::VLD2LNdAsm_16:
6220  case ARM::VLD2LNdAsm_32:
6221  case ARM::VLD2LNqAsm_16:
6222  case ARM::VLD2LNqAsm_32: {
6223    MCInst TmpInst;
6224    // Shuffle the operands around so the lane index operand is in the
6225    // right place.
6226    unsigned Spacing;
6227    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6228    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6229    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6230                                            Spacing));
6231    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6232    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6233    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6234    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6235                                            Spacing));
6236    TmpInst.addOperand(Inst.getOperand(1)); // lane
6237    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6238    TmpInst.addOperand(Inst.getOperand(5));
6239    Inst = TmpInst;
6240    return true;
6241  }
6242
6243  case ARM::VLD3LNdAsm_8:
6244  case ARM::VLD3LNdAsm_16:
6245  case ARM::VLD3LNdAsm_32:
6246  case ARM::VLD3LNqAsm_16:
6247  case ARM::VLD3LNqAsm_32: {
6248    MCInst TmpInst;
6249    // Shuffle the operands around so the lane index operand is in the
6250    // right place.
6251    unsigned Spacing;
6252    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6253    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6254    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6255                                            Spacing));
6256    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6257                                            Spacing * 2));
6258    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6259    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6260    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6261    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6262                                            Spacing));
6263    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6264                                            Spacing * 2));
6265    TmpInst.addOperand(Inst.getOperand(1)); // lane
6266    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6267    TmpInst.addOperand(Inst.getOperand(5));
6268    Inst = TmpInst;
6269    return true;
6270  }
6271
6272  case ARM::VLD4LNdAsm_8:
6273  case ARM::VLD4LNdAsm_16:
6274  case ARM::VLD4LNdAsm_32:
6275  case ARM::VLD4LNqAsm_16:
6276  case ARM::VLD4LNqAsm_32: {
6277    MCInst TmpInst;
6278    // Shuffle the operands around so the lane index operand is in the
6279    // right place.
6280    unsigned Spacing;
6281    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6282    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6283    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6284                                            Spacing));
6285    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6286                                            Spacing * 2));
6287    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6288                                            Spacing * 3));
6289    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6290    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6291    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6292    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6293                                            Spacing));
6294    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6295                                            Spacing * 2));
6296    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6297                                            Spacing * 3));
6298    TmpInst.addOperand(Inst.getOperand(1)); // lane
6299    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6300    TmpInst.addOperand(Inst.getOperand(5));
6301    Inst = TmpInst;
6302    return true;
6303  }
6304
6305  // VLD3DUP single 3-element structure to all lanes instructions.
6306  case ARM::VLD3DUPdAsm_8:
6307  case ARM::VLD3DUPdAsm_16:
6308  case ARM::VLD3DUPdAsm_32:
6309  case ARM::VLD3DUPqAsm_8:
6310  case ARM::VLD3DUPqAsm_16:
6311  case ARM::VLD3DUPqAsm_32: {
6312    MCInst TmpInst;
6313    unsigned Spacing;
6314    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6315    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6316    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6317                                            Spacing));
6318    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6319                                            Spacing * 2));
6320    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6321    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6322    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6323    TmpInst.addOperand(Inst.getOperand(4));
6324    Inst = TmpInst;
6325    return true;
6326  }
6327
6328  case ARM::VLD3DUPdWB_fixed_Asm_8:
6329  case ARM::VLD3DUPdWB_fixed_Asm_16:
6330  case ARM::VLD3DUPdWB_fixed_Asm_32:
6331  case ARM::VLD3DUPqWB_fixed_Asm_8:
6332  case ARM::VLD3DUPqWB_fixed_Asm_16:
6333  case ARM::VLD3DUPqWB_fixed_Asm_32: {
6334    MCInst TmpInst;
6335    unsigned Spacing;
6336    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6337    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6338    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6339                                            Spacing));
6340    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6341                                            Spacing * 2));
6342    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6343    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6344    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6345    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6346    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6347    TmpInst.addOperand(Inst.getOperand(4));
6348    Inst = TmpInst;
6349    return true;
6350  }
6351
6352  case ARM::VLD3DUPdWB_register_Asm_8:
6353  case ARM::VLD3DUPdWB_register_Asm_16:
6354  case ARM::VLD3DUPdWB_register_Asm_32:
6355  case ARM::VLD3DUPqWB_register_Asm_8:
6356  case ARM::VLD3DUPqWB_register_Asm_16:
6357  case ARM::VLD3DUPqWB_register_Asm_32: {
6358    MCInst TmpInst;
6359    unsigned Spacing;
6360    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6361    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6362    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6363                                            Spacing));
6364    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6365                                            Spacing * 2));
6366    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6367    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6368    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6369    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6370    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6371    TmpInst.addOperand(Inst.getOperand(5));
6372    Inst = TmpInst;
6373    return true;
6374  }
6375
6376  // VLD3 multiple 3-element structure instructions.
6377  case ARM::VLD3dAsm_8:
6378  case ARM::VLD3dAsm_16:
6379  case ARM::VLD3dAsm_32:
6380  case ARM::VLD3qAsm_8:
6381  case ARM::VLD3qAsm_16:
6382  case ARM::VLD3qAsm_32: {
6383    MCInst TmpInst;
6384    unsigned Spacing;
6385    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6386    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6387    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6388                                            Spacing));
6389    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6390                                            Spacing * 2));
6391    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6392    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6393    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6394    TmpInst.addOperand(Inst.getOperand(4));
6395    Inst = TmpInst;
6396    return true;
6397  }
6398
6399  case ARM::VLD3dWB_fixed_Asm_8:
6400  case ARM::VLD3dWB_fixed_Asm_16:
6401  case ARM::VLD3dWB_fixed_Asm_32:
6402  case ARM::VLD3qWB_fixed_Asm_8:
6403  case ARM::VLD3qWB_fixed_Asm_16:
6404  case ARM::VLD3qWB_fixed_Asm_32: {
6405    MCInst TmpInst;
6406    unsigned Spacing;
6407    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6408    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6409    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6410                                            Spacing));
6411    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6412                                            Spacing * 2));
6413    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6414    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6415    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6416    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6417    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6418    TmpInst.addOperand(Inst.getOperand(4));
6419    Inst = TmpInst;
6420    return true;
6421  }
6422
6423  case ARM::VLD3dWB_register_Asm_8:
6424  case ARM::VLD3dWB_register_Asm_16:
6425  case ARM::VLD3dWB_register_Asm_32:
6426  case ARM::VLD3qWB_register_Asm_8:
6427  case ARM::VLD3qWB_register_Asm_16:
6428  case ARM::VLD3qWB_register_Asm_32: {
6429    MCInst TmpInst;
6430    unsigned Spacing;
6431    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6432    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6433    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6434                                            Spacing));
6435    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6436                                            Spacing * 2));
6437    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6438    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6439    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6440    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6441    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6442    TmpInst.addOperand(Inst.getOperand(5));
6443    Inst = TmpInst;
6444    return true;
6445  }
6446
6447  // VLD4DUP single 3-element structure to all lanes instructions.
6448  case ARM::VLD4DUPdAsm_8:
6449  case ARM::VLD4DUPdAsm_16:
6450  case ARM::VLD4DUPdAsm_32:
6451  case ARM::VLD4DUPqAsm_8:
6452  case ARM::VLD4DUPqAsm_16:
6453  case ARM::VLD4DUPqAsm_32: {
6454    MCInst TmpInst;
6455    unsigned Spacing;
6456    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6457    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6458    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6459                                            Spacing));
6460    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6461                                            Spacing * 2));
6462    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6463                                            Spacing * 3));
6464    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6465    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6466    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6467    TmpInst.addOperand(Inst.getOperand(4));
6468    Inst = TmpInst;
6469    return true;
6470  }
6471
6472  case ARM::VLD4DUPdWB_fixed_Asm_8:
6473  case ARM::VLD4DUPdWB_fixed_Asm_16:
6474  case ARM::VLD4DUPdWB_fixed_Asm_32:
6475  case ARM::VLD4DUPqWB_fixed_Asm_8:
6476  case ARM::VLD4DUPqWB_fixed_Asm_16:
6477  case ARM::VLD4DUPqWB_fixed_Asm_32: {
6478    MCInst TmpInst;
6479    unsigned Spacing;
6480    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6481    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6482    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6483                                            Spacing));
6484    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6485                                            Spacing * 2));
6486    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6487                                            Spacing * 3));
6488    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6489    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6490    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6491    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6492    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6493    TmpInst.addOperand(Inst.getOperand(4));
6494    Inst = TmpInst;
6495    return true;
6496  }
6497
6498  case ARM::VLD4DUPdWB_register_Asm_8:
6499  case ARM::VLD4DUPdWB_register_Asm_16:
6500  case ARM::VLD4DUPdWB_register_Asm_32:
6501  case ARM::VLD4DUPqWB_register_Asm_8:
6502  case ARM::VLD4DUPqWB_register_Asm_16:
6503  case ARM::VLD4DUPqWB_register_Asm_32: {
6504    MCInst TmpInst;
6505    unsigned Spacing;
6506    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6507    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6508    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6509                                            Spacing));
6510    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6511                                            Spacing * 2));
6512    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6513                                            Spacing * 3));
6514    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6515    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6516    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6517    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6518    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6519    TmpInst.addOperand(Inst.getOperand(5));
6520    Inst = TmpInst;
6521    return true;
6522  }
6523
6524  // VLD4 multiple 4-element structure instructions.
6525  case ARM::VLD4dAsm_8:
6526  case ARM::VLD4dAsm_16:
6527  case ARM::VLD4dAsm_32:
6528  case ARM::VLD4qAsm_8:
6529  case ARM::VLD4qAsm_16:
6530  case ARM::VLD4qAsm_32: {
6531    MCInst TmpInst;
6532    unsigned Spacing;
6533    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6534    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6535    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6536                                            Spacing));
6537    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6538                                            Spacing * 2));
6539    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6540                                            Spacing * 3));
6541    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6542    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6543    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6544    TmpInst.addOperand(Inst.getOperand(4));
6545    Inst = TmpInst;
6546    return true;
6547  }
6548
6549  case ARM::VLD4dWB_fixed_Asm_8:
6550  case ARM::VLD4dWB_fixed_Asm_16:
6551  case ARM::VLD4dWB_fixed_Asm_32:
6552  case ARM::VLD4qWB_fixed_Asm_8:
6553  case ARM::VLD4qWB_fixed_Asm_16:
6554  case ARM::VLD4qWB_fixed_Asm_32: {
6555    MCInst TmpInst;
6556    unsigned Spacing;
6557    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6558    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6559    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6560                                            Spacing));
6561    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6562                                            Spacing * 2));
6563    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6564                                            Spacing * 3));
6565    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6566    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6567    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6568    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6569    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6570    TmpInst.addOperand(Inst.getOperand(4));
6571    Inst = TmpInst;
6572    return true;
6573  }
6574
6575  case ARM::VLD4dWB_register_Asm_8:
6576  case ARM::VLD4dWB_register_Asm_16:
6577  case ARM::VLD4dWB_register_Asm_32:
6578  case ARM::VLD4qWB_register_Asm_8:
6579  case ARM::VLD4qWB_register_Asm_16:
6580  case ARM::VLD4qWB_register_Asm_32: {
6581    MCInst TmpInst;
6582    unsigned Spacing;
6583    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6584    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6585    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6586                                            Spacing));
6587    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6588                                            Spacing * 2));
6589    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6590                                            Spacing * 3));
6591    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6592    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6593    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6594    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6595    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6596    TmpInst.addOperand(Inst.getOperand(5));
6597    Inst = TmpInst;
6598    return true;
6599  }
6600
6601  // VST3 multiple 3-element structure instructions.
6602  case ARM::VST3dAsm_8:
6603  case ARM::VST3dAsm_16:
6604  case ARM::VST3dAsm_32:
6605  case ARM::VST3qAsm_8:
6606  case ARM::VST3qAsm_16:
6607  case ARM::VST3qAsm_32: {
6608    MCInst TmpInst;
6609    unsigned Spacing;
6610    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6611    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6612    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6613    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6614    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6615                                            Spacing));
6616    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6617                                            Spacing * 2));
6618    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6619    TmpInst.addOperand(Inst.getOperand(4));
6620    Inst = TmpInst;
6621    return true;
6622  }
6623
6624  case ARM::VST3dWB_fixed_Asm_8:
6625  case ARM::VST3dWB_fixed_Asm_16:
6626  case ARM::VST3dWB_fixed_Asm_32:
6627  case ARM::VST3qWB_fixed_Asm_8:
6628  case ARM::VST3qWB_fixed_Asm_16:
6629  case ARM::VST3qWB_fixed_Asm_32: {
6630    MCInst TmpInst;
6631    unsigned Spacing;
6632    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6633    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6634    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6635    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6636    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6637    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6638    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6639                                            Spacing));
6640    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6641                                            Spacing * 2));
6642    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6643    TmpInst.addOperand(Inst.getOperand(4));
6644    Inst = TmpInst;
6645    return true;
6646  }
6647
6648  case ARM::VST3dWB_register_Asm_8:
6649  case ARM::VST3dWB_register_Asm_16:
6650  case ARM::VST3dWB_register_Asm_32:
6651  case ARM::VST3qWB_register_Asm_8:
6652  case ARM::VST3qWB_register_Asm_16:
6653  case ARM::VST3qWB_register_Asm_32: {
6654    MCInst TmpInst;
6655    unsigned Spacing;
6656    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6657    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6658    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6659    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6660    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6661    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6662    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6663                                            Spacing));
6664    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6665                                            Spacing * 2));
6666    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6667    TmpInst.addOperand(Inst.getOperand(5));
6668    Inst = TmpInst;
6669    return true;
6670  }
6671
6672  // VST4 multiple 3-element structure instructions.
6673  case ARM::VST4dAsm_8:
6674  case ARM::VST4dAsm_16:
6675  case ARM::VST4dAsm_32:
6676  case ARM::VST4qAsm_8:
6677  case ARM::VST4qAsm_16:
6678  case ARM::VST4qAsm_32: {
6679    MCInst TmpInst;
6680    unsigned Spacing;
6681    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6682    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6683    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6684    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6685    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6686                                            Spacing));
6687    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6688                                            Spacing * 2));
6689    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6690                                            Spacing * 3));
6691    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6692    TmpInst.addOperand(Inst.getOperand(4));
6693    Inst = TmpInst;
6694    return true;
6695  }
6696
6697  case ARM::VST4dWB_fixed_Asm_8:
6698  case ARM::VST4dWB_fixed_Asm_16:
6699  case ARM::VST4dWB_fixed_Asm_32:
6700  case ARM::VST4qWB_fixed_Asm_8:
6701  case ARM::VST4qWB_fixed_Asm_16:
6702  case ARM::VST4qWB_fixed_Asm_32: {
6703    MCInst TmpInst;
6704    unsigned Spacing;
6705    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6706    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6707    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6708    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6709    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6710    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6711    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6712                                            Spacing));
6713    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6714                                            Spacing * 2));
6715    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6716                                            Spacing * 3));
6717    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6718    TmpInst.addOperand(Inst.getOperand(4));
6719    Inst = TmpInst;
6720    return true;
6721  }
6722
6723  case ARM::VST4dWB_register_Asm_8:
6724  case ARM::VST4dWB_register_Asm_16:
6725  case ARM::VST4dWB_register_Asm_32:
6726  case ARM::VST4qWB_register_Asm_8:
6727  case ARM::VST4qWB_register_Asm_16:
6728  case ARM::VST4qWB_register_Asm_32: {
6729    MCInst TmpInst;
6730    unsigned Spacing;
6731    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6732    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6733    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6734    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6735    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6736    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6737    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6738                                            Spacing));
6739    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6740                                            Spacing * 2));
6741    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6742                                            Spacing * 3));
6743    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6744    TmpInst.addOperand(Inst.getOperand(5));
6745    Inst = TmpInst;
6746    return true;
6747  }
6748
6749  // Handle encoding choice for the shift-immediate instructions.
6750  case ARM::t2LSLri:
6751  case ARM::t2LSRri:
6752  case ARM::t2ASRri: {
6753    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6754        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6755        Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6756        !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6757         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6758      unsigned NewOpc;
6759      switch (Inst.getOpcode()) {
6760      default: llvm_unreachable("unexpected opcode");
6761      case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6762      case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6763      case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6764      }
6765      // The Thumb1 operands aren't in the same order. Awesome, eh?
6766      MCInst TmpInst;
6767      TmpInst.setOpcode(NewOpc);
6768      TmpInst.addOperand(Inst.getOperand(0));
6769      TmpInst.addOperand(Inst.getOperand(5));
6770      TmpInst.addOperand(Inst.getOperand(1));
6771      TmpInst.addOperand(Inst.getOperand(2));
6772      TmpInst.addOperand(Inst.getOperand(3));
6773      TmpInst.addOperand(Inst.getOperand(4));
6774      Inst = TmpInst;
6775      return true;
6776    }
6777    return false;
6778  }
6779
6780  // Handle the Thumb2 mode MOV complex aliases.
6781  case ARM::t2MOVsr:
6782  case ARM::t2MOVSsr: {
6783    // Which instruction to expand to depends on the CCOut operand and
6784    // whether we're in an IT block if the register operands are low
6785    // registers.
6786    bool isNarrow = false;
6787    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6788        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6789        isARMLowRegister(Inst.getOperand(2).getReg()) &&
6790        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6791        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6792      isNarrow = true;
6793    MCInst TmpInst;
6794    unsigned newOpc;
6795    switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6796    default: llvm_unreachable("unexpected opcode!");
6797    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6798    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6799    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6800    case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
6801    }
6802    TmpInst.setOpcode(newOpc);
6803    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6804    if (isNarrow)
6805      TmpInst.addOperand(MCOperand::CreateReg(
6806          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6807    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6808    TmpInst.addOperand(Inst.getOperand(2)); // Rm
6809    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6810    TmpInst.addOperand(Inst.getOperand(5));
6811    if (!isNarrow)
6812      TmpInst.addOperand(MCOperand::CreateReg(
6813          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6814    Inst = TmpInst;
6815    return true;
6816  }
6817  case ARM::t2MOVsi:
6818  case ARM::t2MOVSsi: {
6819    // Which instruction to expand to depends on the CCOut operand and
6820    // whether we're in an IT block if the register operands are low
6821    // registers.
6822    bool isNarrow = false;
6823    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6824        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6825        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6826      isNarrow = true;
6827    MCInst TmpInst;
6828    unsigned newOpc;
6829    switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6830    default: llvm_unreachable("unexpected opcode!");
6831    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6832    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6833    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6834    case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6835    case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6836    }
6837    unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6838    if (Amount == 32) Amount = 0;
6839    TmpInst.setOpcode(newOpc);
6840    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6841    if (isNarrow)
6842      TmpInst.addOperand(MCOperand::CreateReg(
6843          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6844    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6845    if (newOpc != ARM::t2RRX)
6846      TmpInst.addOperand(MCOperand::CreateImm(Amount));
6847    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6848    TmpInst.addOperand(Inst.getOperand(4));
6849    if (!isNarrow)
6850      TmpInst.addOperand(MCOperand::CreateReg(
6851          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6852    Inst = TmpInst;
6853    return true;
6854  }
6855  // Handle the ARM mode MOV complex aliases.
6856  case ARM::ASRr:
6857  case ARM::LSRr:
6858  case ARM::LSLr:
6859  case ARM::RORr: {
6860    ARM_AM::ShiftOpc ShiftTy;
6861    switch(Inst.getOpcode()) {
6862    default: llvm_unreachable("unexpected opcode!");
6863    case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6864    case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6865    case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6866    case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6867    }
6868    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6869    MCInst TmpInst;
6870    TmpInst.setOpcode(ARM::MOVsr);
6871    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6872    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6873    TmpInst.addOperand(Inst.getOperand(2)); // Rm
6874    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6875    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6876    TmpInst.addOperand(Inst.getOperand(4));
6877    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6878    Inst = TmpInst;
6879    return true;
6880  }
6881  case ARM::ASRi:
6882  case ARM::LSRi:
6883  case ARM::LSLi:
6884  case ARM::RORi: {
6885    ARM_AM::ShiftOpc ShiftTy;
6886    switch(Inst.getOpcode()) {
6887    default: llvm_unreachable("unexpected opcode!");
6888    case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6889    case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6890    case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
6891    case ARM::RORi: ShiftTy = ARM_AM::ror; break;
6892    }
6893    // A shift by zero is a plain MOVr, not a MOVsi.
6894    unsigned Amt = Inst.getOperand(2).getImm();
6895    unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6896    // A shift by 32 should be encoded as 0 when permitted
6897    if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
6898      Amt = 0;
6899    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
6900    MCInst TmpInst;
6901    TmpInst.setOpcode(Opc);
6902    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6903    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6904    if (Opc == ARM::MOVsi)
6905      TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6906    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6907    TmpInst.addOperand(Inst.getOperand(4));
6908    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6909    Inst = TmpInst;
6910    return true;
6911  }
6912  case ARM::RRXi: {
6913    unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
6914    MCInst TmpInst;
6915    TmpInst.setOpcode(ARM::MOVsi);
6916    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6917    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6918    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6919    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6920    TmpInst.addOperand(Inst.getOperand(3));
6921    TmpInst.addOperand(Inst.getOperand(4)); // cc_out
6922    Inst = TmpInst;
6923    return true;
6924  }
6925  case ARM::t2LDMIA_UPD: {
6926    // If this is a load of a single register, then we should use
6927    // a post-indexed LDR instruction instead, per the ARM ARM.
6928    if (Inst.getNumOperands() != 5)
6929      return false;
6930    MCInst TmpInst;
6931    TmpInst.setOpcode(ARM::t2LDR_POST);
6932    TmpInst.addOperand(Inst.getOperand(4)); // Rt
6933    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6934    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6935    TmpInst.addOperand(MCOperand::CreateImm(4));
6936    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6937    TmpInst.addOperand(Inst.getOperand(3));
6938    Inst = TmpInst;
6939    return true;
6940  }
6941  case ARM::t2STMDB_UPD: {
6942    // If this is a store of a single register, then we should use
6943    // a pre-indexed STR instruction instead, per the ARM ARM.
6944    if (Inst.getNumOperands() != 5)
6945      return false;
6946    MCInst TmpInst;
6947    TmpInst.setOpcode(ARM::t2STR_PRE);
6948    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6949    TmpInst.addOperand(Inst.getOperand(4)); // Rt
6950    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6951    TmpInst.addOperand(MCOperand::CreateImm(-4));
6952    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6953    TmpInst.addOperand(Inst.getOperand(3));
6954    Inst = TmpInst;
6955    return true;
6956  }
6957  case ARM::LDMIA_UPD:
6958    // If this is a load of a single register via a 'pop', then we should use
6959    // a post-indexed LDR instruction instead, per the ARM ARM.
6960    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
6961        Inst.getNumOperands() == 5) {
6962      MCInst TmpInst;
6963      TmpInst.setOpcode(ARM::LDR_POST_IMM);
6964      TmpInst.addOperand(Inst.getOperand(4)); // Rt
6965      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6966      TmpInst.addOperand(Inst.getOperand(1)); // Rn
6967      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
6968      TmpInst.addOperand(MCOperand::CreateImm(4));
6969      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6970      TmpInst.addOperand(Inst.getOperand(3));
6971      Inst = TmpInst;
6972      return true;
6973    }
6974    break;
6975  case ARM::STMDB_UPD:
6976    // If this is a store of a single register via a 'push', then we should use
6977    // a pre-indexed STR instruction instead, per the ARM ARM.
6978    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
6979        Inst.getNumOperands() == 5) {
6980      MCInst TmpInst;
6981      TmpInst.setOpcode(ARM::STR_PRE_IMM);
6982      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6983      TmpInst.addOperand(Inst.getOperand(4)); // Rt
6984      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
6985      TmpInst.addOperand(MCOperand::CreateImm(-4));
6986      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6987      TmpInst.addOperand(Inst.getOperand(3));
6988      Inst = TmpInst;
6989    }
6990    break;
6991  case ARM::t2ADDri12:
6992    // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
6993    // mnemonic was used (not "addw"), encoding T3 is preferred.
6994    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
6995        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
6996      break;
6997    Inst.setOpcode(ARM::t2ADDri);
6998    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
6999    break;
7000  case ARM::t2SUBri12:
7001    // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7002    // mnemonic was used (not "subw"), encoding T3 is preferred.
7003    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7004        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7005      break;
7006    Inst.setOpcode(ARM::t2SUBri);
7007    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7008    break;
7009  case ARM::tADDi8:
7010    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7011    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7012    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7013    // to encoding T1 if <Rd> is omitted."
7014    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7015      Inst.setOpcode(ARM::tADDi3);
7016      return true;
7017    }
7018    break;
7019  case ARM::tSUBi8:
7020    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7021    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7022    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7023    // to encoding T1 if <Rd> is omitted."
7024    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7025      Inst.setOpcode(ARM::tSUBi3);
7026      return true;
7027    }
7028    break;
7029  case ARM::t2ADDri:
7030  case ARM::t2SUBri: {
7031    // If the destination and first source operand are the same, and
7032    // the flags are compatible with the current IT status, use encoding T2
7033    // instead of T3. For compatibility with the system 'as'. Make sure the
7034    // wide encoding wasn't explicit.
7035    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7036        !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7037        (unsigned)Inst.getOperand(2).getImm() > 255 ||
7038        ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7039        (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7040        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7041         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7042      break;
7043    MCInst TmpInst;
7044    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7045                      ARM::tADDi8 : ARM::tSUBi8);
7046    TmpInst.addOperand(Inst.getOperand(0));
7047    TmpInst.addOperand(Inst.getOperand(5));
7048    TmpInst.addOperand(Inst.getOperand(0));
7049    TmpInst.addOperand(Inst.getOperand(2));
7050    TmpInst.addOperand(Inst.getOperand(3));
7051    TmpInst.addOperand(Inst.getOperand(4));
7052    Inst = TmpInst;
7053    return true;
7054  }
7055  case ARM::t2ADDrr: {
7056    // If the destination and first source operand are the same, and
7057    // there's no setting of the flags, use encoding T2 instead of T3.
7058    // Note that this is only for ADD, not SUB. This mirrors the system
7059    // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7060    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7061        Inst.getOperand(5).getReg() != 0 ||
7062        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7063         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7064      break;
7065    MCInst TmpInst;
7066    TmpInst.setOpcode(ARM::tADDhirr);
7067    TmpInst.addOperand(Inst.getOperand(0));
7068    TmpInst.addOperand(Inst.getOperand(0));
7069    TmpInst.addOperand(Inst.getOperand(2));
7070    TmpInst.addOperand(Inst.getOperand(3));
7071    TmpInst.addOperand(Inst.getOperand(4));
7072    Inst = TmpInst;
7073    return true;
7074  }
7075  case ARM::tADDrSP: {
7076    // If the non-SP source operand and the destination operand are not the
7077    // same, we need to use the 32-bit encoding if it's available.
7078    if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7079      Inst.setOpcode(ARM::t2ADDrr);
7080      Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7081      return true;
7082    }
7083    break;
7084  }
7085  case ARM::tB:
7086    // A Thumb conditional branch outside of an IT block is a tBcc.
7087    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7088      Inst.setOpcode(ARM::tBcc);
7089      return true;
7090    }
7091    break;
7092  case ARM::t2B:
7093    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7094    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7095      Inst.setOpcode(ARM::t2Bcc);
7096      return true;
7097    }
7098    break;
7099  case ARM::t2Bcc:
7100    // If the conditional is AL or we're in an IT block, we really want t2B.
7101    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7102      Inst.setOpcode(ARM::t2B);
7103      return true;
7104    }
7105    break;
7106  case ARM::tBcc:
7107    // If the conditional is AL, we really want tB.
7108    if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7109      Inst.setOpcode(ARM::tB);
7110      return true;
7111    }
7112    break;
7113  case ARM::tLDMIA: {
7114    // If the register list contains any high registers, or if the writeback
7115    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7116    // instead if we're in Thumb2. Otherwise, this should have generated
7117    // an error in validateInstruction().
7118    unsigned Rn = Inst.getOperand(0).getReg();
7119    bool hasWritebackToken =
7120      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7121       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7122    bool listContainsBase;
7123    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7124        (!listContainsBase && !hasWritebackToken) ||
7125        (listContainsBase && hasWritebackToken)) {
7126      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7127      assert (isThumbTwo());
7128      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7129      // If we're switching to the updating version, we need to insert
7130      // the writeback tied operand.
7131      if (hasWritebackToken)
7132        Inst.insert(Inst.begin(),
7133                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7134      return true;
7135    }
7136    break;
7137  }
7138  case ARM::tSTMIA_UPD: {
7139    // If the register list contains any high registers, we need to use
7140    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7141    // should have generated an error in validateInstruction().
7142    unsigned Rn = Inst.getOperand(0).getReg();
7143    bool listContainsBase;
7144    if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7145      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7146      assert (isThumbTwo());
7147      Inst.setOpcode(ARM::t2STMIA_UPD);
7148      return true;
7149    }
7150    break;
7151  }
7152  case ARM::tPOP: {
7153    bool listContainsBase;
7154    // If the register list contains any high registers, we need to use
7155    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7156    // should have generated an error in validateInstruction().
7157    if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7158      return false;
7159    assert (isThumbTwo());
7160    Inst.setOpcode(ARM::t2LDMIA_UPD);
7161    // Add the base register and writeback operands.
7162    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7163    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7164    return true;
7165  }
7166  case ARM::tPUSH: {
7167    bool listContainsBase;
7168    if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7169      return false;
7170    assert (isThumbTwo());
7171    Inst.setOpcode(ARM::t2STMDB_UPD);
7172    // Add the base register and writeback operands.
7173    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7174    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7175    return true;
7176  }
7177  case ARM::t2MOVi: {
7178    // If we can use the 16-bit encoding and the user didn't explicitly
7179    // request the 32-bit variant, transform it here.
7180    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7181        (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7182        ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7183         Inst.getOperand(4).getReg() == ARM::CPSR) ||
7184        (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7185        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7186         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7187      // The operands aren't in the same order for tMOVi8...
7188      MCInst TmpInst;
7189      TmpInst.setOpcode(ARM::tMOVi8);
7190      TmpInst.addOperand(Inst.getOperand(0));
7191      TmpInst.addOperand(Inst.getOperand(4));
7192      TmpInst.addOperand(Inst.getOperand(1));
7193      TmpInst.addOperand(Inst.getOperand(2));
7194      TmpInst.addOperand(Inst.getOperand(3));
7195      Inst = TmpInst;
7196      return true;
7197    }
7198    break;
7199  }
7200  case ARM::t2MOVr: {
7201    // If we can use the 16-bit encoding and the user didn't explicitly
7202    // request the 32-bit variant, transform it here.
7203    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7204        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7205        Inst.getOperand(2).getImm() == ARMCC::AL &&
7206        Inst.getOperand(4).getReg() == ARM::CPSR &&
7207        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7208         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7209      // The operands aren't the same for tMOV[S]r... (no cc_out)
7210      MCInst TmpInst;
7211      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7212      TmpInst.addOperand(Inst.getOperand(0));
7213      TmpInst.addOperand(Inst.getOperand(1));
7214      TmpInst.addOperand(Inst.getOperand(2));
7215      TmpInst.addOperand(Inst.getOperand(3));
7216      Inst = TmpInst;
7217      return true;
7218    }
7219    break;
7220  }
7221  case ARM::t2SXTH:
7222  case ARM::t2SXTB:
7223  case ARM::t2UXTH:
7224  case ARM::t2UXTB: {
7225    // If we can use the 16-bit encoding and the user didn't explicitly
7226    // request the 32-bit variant, transform it here.
7227    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7228        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7229        Inst.getOperand(2).getImm() == 0 &&
7230        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7231         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7232      unsigned NewOpc;
7233      switch (Inst.getOpcode()) {
7234      default: llvm_unreachable("Illegal opcode!");
7235      case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7236      case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7237      case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7238      case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7239      }
7240      // The operands aren't the same for thumb1 (no rotate operand).
7241      MCInst TmpInst;
7242      TmpInst.setOpcode(NewOpc);
7243      TmpInst.addOperand(Inst.getOperand(0));
7244      TmpInst.addOperand(Inst.getOperand(1));
7245      TmpInst.addOperand(Inst.getOperand(3));
7246      TmpInst.addOperand(Inst.getOperand(4));
7247      Inst = TmpInst;
7248      return true;
7249    }
7250    break;
7251  }
7252  case ARM::MOVsi: {
7253    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7254    // rrx shifts and asr/lsr of #32 is encoded as 0
7255    if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7256      return false;
7257    if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7258      // Shifting by zero is accepted as a vanilla 'MOVr'
7259      MCInst TmpInst;
7260      TmpInst.setOpcode(ARM::MOVr);
7261      TmpInst.addOperand(Inst.getOperand(0));
7262      TmpInst.addOperand(Inst.getOperand(1));
7263      TmpInst.addOperand(Inst.getOperand(3));
7264      TmpInst.addOperand(Inst.getOperand(4));
7265      TmpInst.addOperand(Inst.getOperand(5));
7266      Inst = TmpInst;
7267      return true;
7268    }
7269    return false;
7270  }
7271  case ARM::ANDrsi:
7272  case ARM::ORRrsi:
7273  case ARM::EORrsi:
7274  case ARM::BICrsi:
7275  case ARM::SUBrsi:
7276  case ARM::ADDrsi: {
7277    unsigned newOpc;
7278    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7279    if (SOpc == ARM_AM::rrx) return false;
7280    switch (Inst.getOpcode()) {
7281    default: llvm_unreachable("unexpected opcode!");
7282    case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7283    case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7284    case ARM::EORrsi: newOpc = ARM::EORrr; break;
7285    case ARM::BICrsi: newOpc = ARM::BICrr; break;
7286    case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7287    case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7288    }
7289    // If the shift is by zero, use the non-shifted instruction definition.
7290    // The exception is for right shifts, where 0 == 32
7291    if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7292        !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7293      MCInst TmpInst;
7294      TmpInst.setOpcode(newOpc);
7295      TmpInst.addOperand(Inst.getOperand(0));
7296      TmpInst.addOperand(Inst.getOperand(1));
7297      TmpInst.addOperand(Inst.getOperand(2));
7298      TmpInst.addOperand(Inst.getOperand(4));
7299      TmpInst.addOperand(Inst.getOperand(5));
7300      TmpInst.addOperand(Inst.getOperand(6));
7301      Inst = TmpInst;
7302      return true;
7303    }
7304    return false;
7305  }
7306  case ARM::ITasm:
7307  case ARM::t2IT: {
7308    // The mask bits for all but the first condition are represented as
7309    // the low bit of the condition code value implies 't'. We currently
7310    // always have 1 implies 't', so XOR toggle the bits if the low bit
7311    // of the condition code is zero.
7312    MCOperand &MO = Inst.getOperand(1);
7313    unsigned Mask = MO.getImm();
7314    unsigned OrigMask = Mask;
7315    unsigned TZ = CountTrailingZeros_32(Mask);
7316    if ((Inst.getOperand(0).getImm() & 1) == 0) {
7317      assert(Mask && TZ <= 3 && "illegal IT mask value!");
7318      for (unsigned i = 3; i != TZ; --i)
7319        Mask ^= 1 << i;
7320    }
7321    MO.setImm(Mask);
7322
7323    // Set up the IT block state according to the IT instruction we just
7324    // matched.
7325    assert(!inITBlock() && "nested IT blocks?!");
7326    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7327    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7328    ITState.CurPosition = 0;
7329    ITState.FirstCond = true;
7330    break;
7331  }
7332  case ARM::t2LSLrr:
7333  case ARM::t2LSRrr:
7334  case ARM::t2ASRrr:
7335  case ARM::t2SBCrr:
7336  case ARM::t2RORrr:
7337  case ARM::t2BICrr:
7338  {
7339    // Assemblers should use the narrow encodings of these instructions when permissible.
7340    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7341         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7342        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7343        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7344         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7345        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7346         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7347      unsigned NewOpc;
7348      switch (Inst.getOpcode()) {
7349        default: llvm_unreachable("unexpected opcode");
7350        case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7351        case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7352        case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7353        case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7354        case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7355        case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7356      }
7357      MCInst TmpInst;
7358      TmpInst.setOpcode(NewOpc);
7359      TmpInst.addOperand(Inst.getOperand(0));
7360      TmpInst.addOperand(Inst.getOperand(5));
7361      TmpInst.addOperand(Inst.getOperand(1));
7362      TmpInst.addOperand(Inst.getOperand(2));
7363      TmpInst.addOperand(Inst.getOperand(3));
7364      TmpInst.addOperand(Inst.getOperand(4));
7365      Inst = TmpInst;
7366      return true;
7367    }
7368    return false;
7369  }
7370  case ARM::t2ANDrr:
7371  case ARM::t2EORrr:
7372  case ARM::t2ADCrr:
7373  case ARM::t2ORRrr:
7374  {
7375    // Assemblers should use the narrow encodings of these instructions when permissible.
7376    // These instructions are special in that they are commutable, so shorter encodings
7377    // are available more often.
7378    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7379         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7380        (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7381         Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7382        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7383         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7384        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7385         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7386      unsigned NewOpc;
7387      switch (Inst.getOpcode()) {
7388        default: llvm_unreachable("unexpected opcode");
7389        case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7390        case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7391        case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7392        case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7393      }
7394      MCInst TmpInst;
7395      TmpInst.setOpcode(NewOpc);
7396      TmpInst.addOperand(Inst.getOperand(0));
7397      TmpInst.addOperand(Inst.getOperand(5));
7398      if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7399        TmpInst.addOperand(Inst.getOperand(1));
7400        TmpInst.addOperand(Inst.getOperand(2));
7401      } else {
7402        TmpInst.addOperand(Inst.getOperand(2));
7403        TmpInst.addOperand(Inst.getOperand(1));
7404      }
7405      TmpInst.addOperand(Inst.getOperand(3));
7406      TmpInst.addOperand(Inst.getOperand(4));
7407      Inst = TmpInst;
7408      return true;
7409    }
7410    return false;
7411  }
7412  }
7413  return false;
7414}
7415
7416unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7417  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7418  // suffix depending on whether they're in an IT block or not.
7419  unsigned Opc = Inst.getOpcode();
7420  const MCInstrDesc &MCID = getInstDesc(Opc);
7421  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7422    assert(MCID.hasOptionalDef() &&
7423           "optionally flag setting instruction missing optional def operand");
7424    assert(MCID.NumOperands == Inst.getNumOperands() &&
7425           "operand count mismatch!");
7426    // Find the optional-def operand (cc_out).
7427    unsigned OpNo;
7428    for (OpNo = 0;
7429         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7430         ++OpNo)
7431      ;
7432    // If we're parsing Thumb1, reject it completely.
7433    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7434      return Match_MnemonicFail;
7435    // If we're parsing Thumb2, which form is legal depends on whether we're
7436    // in an IT block.
7437    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7438        !inITBlock())
7439      return Match_RequiresITBlock;
7440    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7441        inITBlock())
7442      return Match_RequiresNotITBlock;
7443  }
7444  // Some high-register supporting Thumb1 encodings only allow both registers
7445  // to be from r0-r7 when in Thumb2.
7446  else if (Opc == ARM::tADDhirr && isThumbOne() &&
7447           isARMLowRegister(Inst.getOperand(1).getReg()) &&
7448           isARMLowRegister(Inst.getOperand(2).getReg()))
7449    return Match_RequiresThumb2;
7450  // Others only require ARMv6 or later.
7451  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7452           isARMLowRegister(Inst.getOperand(0).getReg()) &&
7453           isARMLowRegister(Inst.getOperand(1).getReg()))
7454    return Match_RequiresV6;
7455  return Match_Success;
7456}
7457
7458static const char *getSubtargetFeatureName(unsigned Val);
7459bool ARMAsmParser::
7460MatchAndEmitInstruction(SMLoc IDLoc,
7461                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7462                        MCStreamer &Out) {
7463  MCInst Inst;
7464  unsigned ErrorInfo;
7465  unsigned MatchResult;
7466  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
7467  switch (MatchResult) {
7468  default: break;
7469  case Match_Success:
7470    // Context sensitive operand constraints aren't handled by the matcher,
7471    // so check them here.
7472    if (validateInstruction(Inst, Operands)) {
7473      // Still progress the IT block, otherwise one wrong condition causes
7474      // nasty cascading errors.
7475      forwardITPosition();
7476      return true;
7477    }
7478
7479    // Some instructions need post-processing to, for example, tweak which
7480    // encoding is selected. Loop on it while changes happen so the
7481    // individual transformations can chain off each other. E.g.,
7482    // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7483    while (processInstruction(Inst, Operands))
7484      ;
7485
7486    // Only move forward at the very end so that everything in validate
7487    // and process gets a consistent answer about whether we're in an IT
7488    // block.
7489    forwardITPosition();
7490
7491    // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7492    // doesn't actually encode.
7493    if (Inst.getOpcode() == ARM::ITasm)
7494      return false;
7495
7496    Inst.setLoc(IDLoc);
7497    Out.EmitInstruction(Inst);
7498    return false;
7499  case Match_MissingFeature: {
7500    assert(ErrorInfo && "Unknown missing feature!");
7501    // Special case the error message for the very common case where only
7502    // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7503    std::string Msg = "instruction requires:";
7504    unsigned Mask = 1;
7505    for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7506      if (ErrorInfo & Mask) {
7507        Msg += " ";
7508        Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7509      }
7510      Mask <<= 1;
7511    }
7512    return Error(IDLoc, Msg);
7513  }
7514  case Match_InvalidOperand: {
7515    SMLoc ErrorLoc = IDLoc;
7516    if (ErrorInfo != ~0U) {
7517      if (ErrorInfo >= Operands.size())
7518        return Error(IDLoc, "too few operands for instruction");
7519
7520      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7521      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7522    }
7523
7524    return Error(ErrorLoc, "invalid operand for instruction");
7525  }
7526  case Match_MnemonicFail:
7527    return Error(IDLoc, "invalid instruction",
7528                 ((ARMOperand*)Operands[0])->getLocRange());
7529  case Match_RequiresNotITBlock:
7530    return Error(IDLoc, "flag setting instruction only valid outside IT block");
7531  case Match_RequiresITBlock:
7532    return Error(IDLoc, "instruction only valid inside IT block");
7533  case Match_RequiresV6:
7534    return Error(IDLoc, "instruction variant requires ARMv6 or later");
7535  case Match_RequiresThumb2:
7536    return Error(IDLoc, "instruction variant requires Thumb2");
7537  case Match_ImmRange0_15: {
7538    SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7539    if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7540    return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7541  }
7542  }
7543
7544  llvm_unreachable("Implement any new match types added!");
7545}
7546
7547/// parseDirective parses the arm specific directives
7548bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7549  StringRef IDVal = DirectiveID.getIdentifier();
7550  if (IDVal == ".word")
7551    return parseDirectiveWord(4, DirectiveID.getLoc());
7552  else if (IDVal == ".thumb")
7553    return parseDirectiveThumb(DirectiveID.getLoc());
7554  else if (IDVal == ".arm")
7555    return parseDirectiveARM(DirectiveID.getLoc());
7556  else if (IDVal == ".thumb_func")
7557    return parseDirectiveThumbFunc(DirectiveID.getLoc());
7558  else if (IDVal == ".code")
7559    return parseDirectiveCode(DirectiveID.getLoc());
7560  else if (IDVal == ".syntax")
7561    return parseDirectiveSyntax(DirectiveID.getLoc());
7562  else if (IDVal == ".unreq")
7563    return parseDirectiveUnreq(DirectiveID.getLoc());
7564  else if (IDVal == ".arch")
7565    return parseDirectiveArch(DirectiveID.getLoc());
7566  else if (IDVal == ".eabi_attribute")
7567    return parseDirectiveEabiAttr(DirectiveID.getLoc());
7568  return true;
7569}
7570
7571/// parseDirectiveWord
7572///  ::= .word [ expression (, expression)* ]
7573bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7574  if (getLexer().isNot(AsmToken::EndOfStatement)) {
7575    for (;;) {
7576      const MCExpr *Value;
7577      if (getParser().ParseExpression(Value))
7578        return true;
7579
7580      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
7581
7582      if (getLexer().is(AsmToken::EndOfStatement))
7583        break;
7584
7585      // FIXME: Improve diagnostic.
7586      if (getLexer().isNot(AsmToken::Comma))
7587        return Error(L, "unexpected token in directive");
7588      Parser.Lex();
7589    }
7590  }
7591
7592  Parser.Lex();
7593  return false;
7594}
7595
7596/// parseDirectiveThumb
7597///  ::= .thumb
7598bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7599  if (getLexer().isNot(AsmToken::EndOfStatement))
7600    return Error(L, "unexpected token in directive");
7601  Parser.Lex();
7602
7603  if (!isThumb())
7604    SwitchMode();
7605  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7606  return false;
7607}
7608
7609/// parseDirectiveARM
7610///  ::= .arm
7611bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7612  if (getLexer().isNot(AsmToken::EndOfStatement))
7613    return Error(L, "unexpected token in directive");
7614  Parser.Lex();
7615
7616  if (isThumb())
7617    SwitchMode();
7618  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7619  return false;
7620}
7621
7622/// parseDirectiveThumbFunc
7623///  ::= .thumbfunc symbol_name
7624bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7625  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
7626  bool isMachO = MAI.hasSubsectionsViaSymbols();
7627  StringRef Name;
7628  bool needFuncName = true;
7629
7630  // Darwin asm has (optionally) function name after .thumb_func direction
7631  // ELF doesn't
7632  if (isMachO) {
7633    const AsmToken &Tok = Parser.getTok();
7634    if (Tok.isNot(AsmToken::EndOfStatement)) {
7635      if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7636        return Error(L, "unexpected token in .thumb_func directive");
7637      Name = Tok.getIdentifier();
7638      Parser.Lex(); // Consume the identifier token.
7639      needFuncName = false;
7640    }
7641  }
7642
7643  if (getLexer().isNot(AsmToken::EndOfStatement))
7644    return Error(L, "unexpected token in directive");
7645
7646  // Eat the end of statement and any blank lines that follow.
7647  while (getLexer().is(AsmToken::EndOfStatement))
7648    Parser.Lex();
7649
7650  // FIXME: assuming function name will be the line following .thumb_func
7651  // We really should be checking the next symbol definition even if there's
7652  // stuff in between.
7653  if (needFuncName) {
7654    Name = Parser.getTok().getIdentifier();
7655  }
7656
7657  // Mark symbol as a thumb symbol.
7658  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7659  getParser().getStreamer().EmitThumbFunc(Func);
7660  return false;
7661}
7662
7663/// parseDirectiveSyntax
7664///  ::= .syntax unified | divided
7665bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7666  const AsmToken &Tok = Parser.getTok();
7667  if (Tok.isNot(AsmToken::Identifier))
7668    return Error(L, "unexpected token in .syntax directive");
7669  StringRef Mode = Tok.getString();
7670  if (Mode == "unified" || Mode == "UNIFIED")
7671    Parser.Lex();
7672  else if (Mode == "divided" || Mode == "DIVIDED")
7673    return Error(L, "'.syntax divided' arm asssembly not supported");
7674  else
7675    return Error(L, "unrecognized syntax mode in .syntax directive");
7676
7677  if (getLexer().isNot(AsmToken::EndOfStatement))
7678    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7679  Parser.Lex();
7680
7681  // TODO tell the MC streamer the mode
7682  // getParser().getStreamer().Emit???();
7683  return false;
7684}
7685
7686/// parseDirectiveCode
7687///  ::= .code 16 | 32
7688bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7689  const AsmToken &Tok = Parser.getTok();
7690  if (Tok.isNot(AsmToken::Integer))
7691    return Error(L, "unexpected token in .code directive");
7692  int64_t Val = Parser.getTok().getIntVal();
7693  if (Val == 16)
7694    Parser.Lex();
7695  else if (Val == 32)
7696    Parser.Lex();
7697  else
7698    return Error(L, "invalid operand to .code directive");
7699
7700  if (getLexer().isNot(AsmToken::EndOfStatement))
7701    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7702  Parser.Lex();
7703
7704  if (Val == 16) {
7705    if (!isThumb())
7706      SwitchMode();
7707    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7708  } else {
7709    if (isThumb())
7710      SwitchMode();
7711    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7712  }
7713
7714  return false;
7715}
7716
7717/// parseDirectiveReq
7718///  ::= name .req registername
7719bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7720  Parser.Lex(); // Eat the '.req' token.
7721  unsigned Reg;
7722  SMLoc SRegLoc, ERegLoc;
7723  if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7724    Parser.EatToEndOfStatement();
7725    return Error(SRegLoc, "register name expected");
7726  }
7727
7728  // Shouldn't be anything else.
7729  if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7730    Parser.EatToEndOfStatement();
7731    return Error(Parser.getTok().getLoc(),
7732                 "unexpected input in .req directive.");
7733  }
7734
7735  Parser.Lex(); // Consume the EndOfStatement
7736
7737  if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7738    return Error(SRegLoc, "redefinition of '" + Name +
7739                          "' does not match original.");
7740
7741  return false;
7742}
7743
7744/// parseDirectiveUneq
7745///  ::= .unreq registername
7746bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7747  if (Parser.getTok().isNot(AsmToken::Identifier)) {
7748    Parser.EatToEndOfStatement();
7749    return Error(L, "unexpected input in .unreq directive.");
7750  }
7751  RegisterReqs.erase(Parser.getTok().getIdentifier());
7752  Parser.Lex(); // Eat the identifier.
7753  return false;
7754}
7755
7756/// parseDirectiveArch
7757///  ::= .arch token
7758bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7759  return true;
7760}
7761
7762/// parseDirectiveEabiAttr
7763///  ::= .eabi_attribute int, int
7764bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7765  return true;
7766}
7767
7768extern "C" void LLVMInitializeARMAsmLexer();
7769
7770/// Force static initialization.
7771extern "C" void LLVMInitializeARMAsmParser() {
7772  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
7773  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
7774  LLVMInitializeARMAsmLexer();
7775}
7776
7777#define GET_REGISTER_MATCHER
7778#define GET_SUBTARGET_FEATURE_NAME
7779#define GET_MATCHER_IMPLEMENTATION
7780#include "ARMGenAsmMatcher.inc"
7781