ARMAsmParser.cpp revision 55dcefbc4006204c0d2816d5a7c921517c53383c 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "llvm/MC/MCTargetAsmParser.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMBaseInfo.h"
13#include "MCTargetDesc/ARMMCExpr.h"
14#include "llvm/ADT/BitVector.h"
15#include "llvm/ADT/OwningPtr.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/ADT/Twine.h"
20#include "llvm/MC/MCAsmInfo.h"
21#include "llvm/MC/MCAssembler.h"
22#include "llvm/MC/MCContext.h"
23#include "llvm/MC/MCELFStreamer.h"
24#include "llvm/MC/MCExpr.h"
25#include "llvm/MC/MCInst.h"
26#include "llvm/MC/MCInstrDesc.h"
27#include "llvm/MC/MCParser/MCAsmLexer.h"
28#include "llvm/MC/MCParser/MCAsmParser.h"
29#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
30#include "llvm/MC/MCRegisterInfo.h"
31#include "llvm/MC/MCStreamer.h"
32#include "llvm/MC/MCSubtargetInfo.h"
33#include "llvm/Support/ELF.h"
34#include "llvm/Support/MathExtras.h"
35#include "llvm/Support/SourceMgr.h"
36#include "llvm/Support/TargetRegistry.h"
37#include "llvm/Support/raw_ostream.h"
38
39using namespace llvm;
40
41namespace {
42
43class ARMOperand;
44
45enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
46
47class ARMAsmParser : public MCTargetAsmParser {
48  MCSubtargetInfo &STI;
49  MCAsmParser &Parser;
50  const MCRegisterInfo *MRI;
51
52  // Unwind directives state
53  SMLoc FnStartLoc;
54  SMLoc CantUnwindLoc;
55  SMLoc PersonalityLoc;
56  SMLoc HandlerDataLoc;
57  int FPReg;
58  void resetUnwindDirectiveParserState() {
59    FnStartLoc = SMLoc();
60    CantUnwindLoc = SMLoc();
61    PersonalityLoc = SMLoc();
62    HandlerDataLoc = SMLoc();
63    FPReg = -1;
64  }
65
66  // Map of register aliases registers via the .req directive.
67  StringMap<unsigned> RegisterReqs;
68
69  struct {
70    ARMCC::CondCodes Cond;    // Condition for IT block.
71    unsigned Mask:4;          // Condition mask for instructions.
72                              // Starting at first 1 (from lsb).
73                              //   '1'  condition as indicated in IT.
74                              //   '0'  inverse of condition (else).
75                              // Count of instructions in IT block is
76                              // 4 - trailingzeroes(mask)
77
78    bool FirstCond;           // Explicit flag for when we're parsing the
79                              // First instruction in the IT block. It's
80                              // implied in the mask, so needs special
81                              // handling.
82
83    unsigned CurPosition;     // Current position in parsing of IT
84                              // block. In range [0,3]. Initialized
85                              // according to count of instructions in block.
86                              // ~0U if no active IT block.
87  } ITState;
88  bool inITBlock() { return ITState.CurPosition != ~0U;}
89  void forwardITPosition() {
90    if (!inITBlock()) return;
91    // Move to the next instruction in the IT block, if there is one. If not,
92    // mark the block as done.
93    unsigned TZ = countTrailingZeros(ITState.Mask);
94    if (++ITState.CurPosition == 5 - TZ)
95      ITState.CurPosition = ~0U; // Done with the IT block after this.
96  }
97
98
99  MCAsmParser &getParser() const { return Parser; }
100  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
101
102  bool Warning(SMLoc L, const Twine &Msg,
103               ArrayRef<SMRange> Ranges = None) {
104    return Parser.Warning(L, Msg, Ranges);
105  }
106  bool Error(SMLoc L, const Twine &Msg,
107             ArrayRef<SMRange> Ranges = None) {
108    return Parser.Error(L, Msg, Ranges);
109  }
110
111  int tryParseRegister();
112  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
113  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
114  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
115  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
116  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
117  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
118  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
119                              unsigned &ShiftAmount);
120  bool parseDirectiveWord(unsigned Size, SMLoc L);
121  bool parseDirectiveThumb(SMLoc L);
122  bool parseDirectiveARM(SMLoc L);
123  bool parseDirectiveThumbFunc(SMLoc L);
124  bool parseDirectiveCode(SMLoc L);
125  bool parseDirectiveSyntax(SMLoc L);
126  bool parseDirectiveReq(StringRef Name, SMLoc L);
127  bool parseDirectiveUnreq(SMLoc L);
128  bool parseDirectiveArch(SMLoc L);
129  bool parseDirectiveEabiAttr(SMLoc L);
130  bool parseDirectiveFnStart(SMLoc L);
131  bool parseDirectiveFnEnd(SMLoc L);
132  bool parseDirectiveCantUnwind(SMLoc L);
133  bool parseDirectivePersonality(SMLoc L);
134  bool parseDirectiveHandlerData(SMLoc L);
135  bool parseDirectiveSetFP(SMLoc L);
136  bool parseDirectivePad(SMLoc L);
137  bool parseDirectiveRegSave(SMLoc L, bool IsVector);
138
139  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
140                          bool &CarrySetting, unsigned &ProcessorIMod,
141                          StringRef &ITMask);
142  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
143                             bool &CanAcceptPredicationCode);
144
145  bool isThumb() const {
146    // FIXME: Can tablegen auto-generate this?
147    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
148  }
149  bool isThumbOne() const {
150    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
151  }
152  bool isThumbTwo() const {
153    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
154  }
155  bool hasThumb() const {
156    return STI.getFeatureBits() & ARM::HasV4TOps;
157  }
158  bool hasV6Ops() const {
159    return STI.getFeatureBits() & ARM::HasV6Ops;
160  }
161  bool hasV7Ops() const {
162    return STI.getFeatureBits() & ARM::HasV7Ops;
163  }
164  bool hasV8Ops() const {
165    return STI.getFeatureBits() & ARM::HasV8Ops;
166  }
167  bool hasARM() const {
168    return !(STI.getFeatureBits() & ARM::FeatureNoARM);
169  }
170
171  void SwitchMode() {
172    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
173    setAvailableFeatures(FB);
174  }
175  bool isMClass() const {
176    return STI.getFeatureBits() & ARM::FeatureMClass;
177  }
178
179  /// @name Auto-generated Match Functions
180  /// {
181
182#define GET_ASSEMBLER_HEADER
183#include "ARMGenAsmMatcher.inc"
184
185  /// }
186
187  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
188  OperandMatchResultTy parseCoprocNumOperand(
189    SmallVectorImpl<MCParsedAsmOperand*>&);
190  OperandMatchResultTy parseCoprocRegOperand(
191    SmallVectorImpl<MCParsedAsmOperand*>&);
192  OperandMatchResultTy parseCoprocOptionOperand(
193    SmallVectorImpl<MCParsedAsmOperand*>&);
194  OperandMatchResultTy parseMemBarrierOptOperand(
195    SmallVectorImpl<MCParsedAsmOperand*>&);
196  OperandMatchResultTy parseInstSyncBarrierOptOperand(
197    SmallVectorImpl<MCParsedAsmOperand*>&);
198  OperandMatchResultTy parseProcIFlagsOperand(
199    SmallVectorImpl<MCParsedAsmOperand*>&);
200  OperandMatchResultTy parseMSRMaskOperand(
201    SmallVectorImpl<MCParsedAsmOperand*>&);
202  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
203                                   StringRef Op, int Low, int High);
204  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
205    return parsePKHImm(O, "lsl", 0, 31);
206  }
207  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
208    return parsePKHImm(O, "asr", 1, 32);
209  }
210  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
211  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
212  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
213  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
214  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
215  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
216  OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
217  OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
218  OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
219                                       SMLoc &EndLoc);
220
221  // Asm Match Converter Methods
222  void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
223  void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
224  void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
225                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
226  void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
227                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
228  void cvtLdWriteBackRegAddrMode2(MCInst &Inst,
229                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
230  void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
231                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
232  void cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
233                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
234  void cvtStWriteBackRegAddrMode2(MCInst &Inst,
235                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
236  void cvtStWriteBackRegAddrMode3(MCInst &Inst,
237                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
238  void cvtLdExtTWriteBackImm(MCInst &Inst,
239                             const SmallVectorImpl<MCParsedAsmOperand*> &);
240  void cvtLdExtTWriteBackReg(MCInst &Inst,
241                             const SmallVectorImpl<MCParsedAsmOperand*> &);
242  void cvtStExtTWriteBackImm(MCInst &Inst,
243                             const SmallVectorImpl<MCParsedAsmOperand*> &);
244  void cvtStExtTWriteBackReg(MCInst &Inst,
245                             const SmallVectorImpl<MCParsedAsmOperand*> &);
246  void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
247  void cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
248  void cvtLdWriteBackRegAddrMode3(MCInst &Inst,
249                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
250  void cvtThumbMultiply(MCInst &Inst,
251                        const SmallVectorImpl<MCParsedAsmOperand*> &);
252  void cvtVLDwbFixed(MCInst &Inst,
253                     const SmallVectorImpl<MCParsedAsmOperand*> &);
254  void cvtVLDwbRegister(MCInst &Inst,
255                        const SmallVectorImpl<MCParsedAsmOperand*> &);
256  void cvtVSTwbFixed(MCInst &Inst,
257                     const SmallVectorImpl<MCParsedAsmOperand*> &);
258  void cvtVSTwbRegister(MCInst &Inst,
259                        const SmallVectorImpl<MCParsedAsmOperand*> &);
260  bool validateInstruction(MCInst &Inst,
261                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
262  bool processInstruction(MCInst &Inst,
263                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
264  bool shouldOmitCCOutOperand(StringRef Mnemonic,
265                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
266  bool shouldOmitPredicateOperand(StringRef Mnemonic,
267                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
268
269public:
270  enum ARMMatchResultTy {
271    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
272    Match_RequiresNotITBlock,
273    Match_RequiresV6,
274    Match_RequiresThumb2,
275#define GET_OPERAND_DIAGNOSTIC_TYPES
276#include "ARMGenAsmMatcher.inc"
277
278  };
279
280  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
281    : MCTargetAsmParser(), STI(_STI), Parser(_Parser), FPReg(-1) {
282    MCAsmParserExtension::Initialize(_Parser);
283
284    // Cache the MCRegisterInfo.
285    MRI = getContext().getRegisterInfo();
286
287    // Initialize the set of available features.
288    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
289
290    // Not in an ITBlock to start with.
291    ITState.CurPosition = ~0U;
292
293    // Set ELF header flags.
294    // FIXME: This should eventually end up somewhere else where more
295    // intelligent flag decisions can be made. For now we are just maintaining
296    // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default.
297    if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&Parser.getStreamer()))
298      MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
299  }
300
301  // Implementation of the MCTargetAsmParser interface:
302  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
303  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
304                        SMLoc NameLoc,
305                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
306  bool ParseDirective(AsmToken DirectiveID);
307
308  unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
309  unsigned checkTargetMatchPredicate(MCInst &Inst);
310
311  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
312                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
313                               MCStreamer &Out, unsigned &ErrorInfo,
314                               bool MatchingInlineAsm);
315};
316} // end anonymous namespace
317
318namespace {
319
320/// ARMOperand - Instances of this class represent a parsed ARM machine
321/// operand.
322class ARMOperand : public MCParsedAsmOperand {
323  enum KindTy {
324    k_CondCode,
325    k_CCOut,
326    k_ITCondMask,
327    k_CoprocNum,
328    k_CoprocReg,
329    k_CoprocOption,
330    k_Immediate,
331    k_MemBarrierOpt,
332    k_InstSyncBarrierOpt,
333    k_Memory,
334    k_PostIndexRegister,
335    k_MSRMask,
336    k_ProcIFlags,
337    k_VectorIndex,
338    k_Register,
339    k_RegisterList,
340    k_DPRRegisterList,
341    k_SPRRegisterList,
342    k_VectorList,
343    k_VectorListAllLanes,
344    k_VectorListIndexed,
345    k_ShiftedRegister,
346    k_ShiftedImmediate,
347    k_ShifterImmediate,
348    k_RotateImmediate,
349    k_BitfieldDescriptor,
350    k_Token
351  } Kind;
352
353  SMLoc StartLoc, EndLoc;
354  SmallVector<unsigned, 8> Registers;
355
356  struct CCOp {
357    ARMCC::CondCodes Val;
358  };
359
360  struct CopOp {
361    unsigned Val;
362  };
363
364  struct CoprocOptionOp {
365    unsigned Val;
366  };
367
368  struct ITMaskOp {
369    unsigned Mask:4;
370  };
371
372  struct MBOptOp {
373    ARM_MB::MemBOpt Val;
374  };
375
376  struct ISBOptOp {
377    ARM_ISB::InstSyncBOpt Val;
378  };
379
380  struct IFlagsOp {
381    ARM_PROC::IFlags Val;
382  };
383
384  struct MMaskOp {
385    unsigned Val;
386  };
387
388  struct TokOp {
389    const char *Data;
390    unsigned Length;
391  };
392
393  struct RegOp {
394    unsigned RegNum;
395  };
396
397  // A vector register list is a sequential list of 1 to 4 registers.
398  struct VectorListOp {
399    unsigned RegNum;
400    unsigned Count;
401    unsigned LaneIndex;
402    bool isDoubleSpaced;
403  };
404
405  struct VectorIndexOp {
406    unsigned Val;
407  };
408
409  struct ImmOp {
410    const MCExpr *Val;
411  };
412
413  /// Combined record for all forms of ARM address expressions.
414  struct MemoryOp {
415    unsigned BaseRegNum;
416    // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
417    // was specified.
418    const MCConstantExpr *OffsetImm;  // Offset immediate value
419    unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
420    ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
421    unsigned ShiftImm;        // shift for OffsetReg.
422    unsigned Alignment;       // 0 = no alignment specified
423    // n = alignment in bytes (2, 4, 8, 16, or 32)
424    unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
425  };
426
427  struct PostIdxRegOp {
428    unsigned RegNum;
429    bool isAdd;
430    ARM_AM::ShiftOpc ShiftTy;
431    unsigned ShiftImm;
432  };
433
434  struct ShifterImmOp {
435    bool isASR;
436    unsigned Imm;
437  };
438
439  struct RegShiftedRegOp {
440    ARM_AM::ShiftOpc ShiftTy;
441    unsigned SrcReg;
442    unsigned ShiftReg;
443    unsigned ShiftImm;
444  };
445
446  struct RegShiftedImmOp {
447    ARM_AM::ShiftOpc ShiftTy;
448    unsigned SrcReg;
449    unsigned ShiftImm;
450  };
451
452  struct RotImmOp {
453    unsigned Imm;
454  };
455
456  struct BitfieldOp {
457    unsigned LSB;
458    unsigned Width;
459  };
460
461  union {
462    struct CCOp CC;
463    struct CopOp Cop;
464    struct CoprocOptionOp CoprocOption;
465    struct MBOptOp MBOpt;
466    struct ISBOptOp ISBOpt;
467    struct ITMaskOp ITMask;
468    struct IFlagsOp IFlags;
469    struct MMaskOp MMask;
470    struct TokOp Tok;
471    struct RegOp Reg;
472    struct VectorListOp VectorList;
473    struct VectorIndexOp VectorIndex;
474    struct ImmOp Imm;
475    struct MemoryOp Memory;
476    struct PostIdxRegOp PostIdxReg;
477    struct ShifterImmOp ShifterImm;
478    struct RegShiftedRegOp RegShiftedReg;
479    struct RegShiftedImmOp RegShiftedImm;
480    struct RotImmOp RotImm;
481    struct BitfieldOp Bitfield;
482  };
483
484  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
485public:
486  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
487    Kind = o.Kind;
488    StartLoc = o.StartLoc;
489    EndLoc = o.EndLoc;
490    switch (Kind) {
491    case k_CondCode:
492      CC = o.CC;
493      break;
494    case k_ITCondMask:
495      ITMask = o.ITMask;
496      break;
497    case k_Token:
498      Tok = o.Tok;
499      break;
500    case k_CCOut:
501    case k_Register:
502      Reg = o.Reg;
503      break;
504    case k_RegisterList:
505    case k_DPRRegisterList:
506    case k_SPRRegisterList:
507      Registers = o.Registers;
508      break;
509    case k_VectorList:
510    case k_VectorListAllLanes:
511    case k_VectorListIndexed:
512      VectorList = o.VectorList;
513      break;
514    case k_CoprocNum:
515    case k_CoprocReg:
516      Cop = o.Cop;
517      break;
518    case k_CoprocOption:
519      CoprocOption = o.CoprocOption;
520      break;
521    case k_Immediate:
522      Imm = o.Imm;
523      break;
524    case k_MemBarrierOpt:
525      MBOpt = o.MBOpt;
526      break;
527    case k_InstSyncBarrierOpt:
528      ISBOpt = o.ISBOpt;
529    case k_Memory:
530      Memory = o.Memory;
531      break;
532    case k_PostIndexRegister:
533      PostIdxReg = o.PostIdxReg;
534      break;
535    case k_MSRMask:
536      MMask = o.MMask;
537      break;
538    case k_ProcIFlags:
539      IFlags = o.IFlags;
540      break;
541    case k_ShifterImmediate:
542      ShifterImm = o.ShifterImm;
543      break;
544    case k_ShiftedRegister:
545      RegShiftedReg = o.RegShiftedReg;
546      break;
547    case k_ShiftedImmediate:
548      RegShiftedImm = o.RegShiftedImm;
549      break;
550    case k_RotateImmediate:
551      RotImm = o.RotImm;
552      break;
553    case k_BitfieldDescriptor:
554      Bitfield = o.Bitfield;
555      break;
556    case k_VectorIndex:
557      VectorIndex = o.VectorIndex;
558      break;
559    }
560  }
561
562  /// getStartLoc - Get the location of the first token of this operand.
563  SMLoc getStartLoc() const { return StartLoc; }
564  /// getEndLoc - Get the location of the last token of this operand.
565  SMLoc getEndLoc() const { return EndLoc; }
566  /// getLocRange - Get the range between the first and last token of this
567  /// operand.
568  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
569
570  ARMCC::CondCodes getCondCode() const {
571    assert(Kind == k_CondCode && "Invalid access!");
572    return CC.Val;
573  }
574
575  unsigned getCoproc() const {
576    assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
577    return Cop.Val;
578  }
579
580  StringRef getToken() const {
581    assert(Kind == k_Token && "Invalid access!");
582    return StringRef(Tok.Data, Tok.Length);
583  }
584
585  unsigned getReg() const {
586    assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
587    return Reg.RegNum;
588  }
589
590  const SmallVectorImpl<unsigned> &getRegList() const {
591    assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
592            Kind == k_SPRRegisterList) && "Invalid access!");
593    return Registers;
594  }
595
596  const MCExpr *getImm() const {
597    assert(isImm() && "Invalid access!");
598    return Imm.Val;
599  }
600
601  unsigned getVectorIndex() const {
602    assert(Kind == k_VectorIndex && "Invalid access!");
603    return VectorIndex.Val;
604  }
605
606  ARM_MB::MemBOpt getMemBarrierOpt() const {
607    assert(Kind == k_MemBarrierOpt && "Invalid access!");
608    return MBOpt.Val;
609  }
610
611  ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
612    assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
613    return ISBOpt.Val;
614  }
615
616  ARM_PROC::IFlags getProcIFlags() const {
617    assert(Kind == k_ProcIFlags && "Invalid access!");
618    return IFlags.Val;
619  }
620
621  unsigned getMSRMask() const {
622    assert(Kind == k_MSRMask && "Invalid access!");
623    return MMask.Val;
624  }
625
626  bool isCoprocNum() const { return Kind == k_CoprocNum; }
627  bool isCoprocReg() const { return Kind == k_CoprocReg; }
628  bool isCoprocOption() const { return Kind == k_CoprocOption; }
629  bool isCondCode() const { return Kind == k_CondCode; }
630  bool isCCOut() const { return Kind == k_CCOut; }
631  bool isITMask() const { return Kind == k_ITCondMask; }
632  bool isITCondCode() const { return Kind == k_CondCode; }
633  bool isImm() const { return Kind == k_Immediate; }
634  // checks whether this operand is an unsigned offset which fits is a field
635  // of specified width and scaled by a specific number of bits
636  template<unsigned width, unsigned scale>
637  bool isUnsignedOffset() const {
638    if (!isImm()) return false;
639    if (dyn_cast<MCSymbolRefExpr>(Imm.Val)) return true;
640    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
641      int64_t Val = CE->getValue();
642      int64_t Align = 1LL << scale;
643      int64_t Max = Align * ((1LL << width) - 1);
644      return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
645    }
646    return false;
647  }
648  bool isFPImm() const {
649    if (!isImm()) return false;
650    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
651    if (!CE) return false;
652    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
653    return Val != -1;
654  }
655  bool isFBits16() const {
656    if (!isImm()) return false;
657    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
658    if (!CE) return false;
659    int64_t Value = CE->getValue();
660    return Value >= 0 && Value <= 16;
661  }
662  bool isFBits32() const {
663    if (!isImm()) return false;
664    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
665    if (!CE) return false;
666    int64_t Value = CE->getValue();
667    return Value >= 1 && Value <= 32;
668  }
669  bool isImm8s4() const {
670    if (!isImm()) return false;
671    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
672    if (!CE) return false;
673    int64_t Value = CE->getValue();
674    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
675  }
676  bool isImm0_4() const {
677    if (!isImm()) return false;
678    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
679    if (!CE) return false;
680    int64_t Value = CE->getValue();
681    return Value >= 0 && Value < 5;
682  }
683  bool isImm0_1020s4() const {
684    if (!isImm()) return false;
685    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
686    if (!CE) return false;
687    int64_t Value = CE->getValue();
688    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
689  }
690  bool isImm0_508s4() const {
691    if (!isImm()) return false;
692    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
693    if (!CE) return false;
694    int64_t Value = CE->getValue();
695    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
696  }
697  bool isImm0_508s4Neg() const {
698    if (!isImm()) return false;
699    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
700    if (!CE) return false;
701    int64_t Value = -CE->getValue();
702    // explicitly exclude zero. we want that to use the normal 0_508 version.
703    return ((Value & 3) == 0) && Value > 0 && Value <= 508;
704  }
705  bool isImm0_255() const {
706    if (!isImm()) return false;
707    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
708    if (!CE) return false;
709    int64_t Value = CE->getValue();
710    return Value >= 0 && Value < 256;
711  }
712  bool isImm0_4095() const {
713    if (!isImm()) return false;
714    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
715    if (!CE) return false;
716    int64_t Value = CE->getValue();
717    return Value >= 0 && Value < 4096;
718  }
719  bool isImm0_4095Neg() const {
720    if (!isImm()) return false;
721    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
722    if (!CE) return false;
723    int64_t Value = -CE->getValue();
724    return Value > 0 && Value < 4096;
725  }
726  bool isImm0_1() const {
727    if (!isImm()) return false;
728    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
729    if (!CE) return false;
730    int64_t Value = CE->getValue();
731    return Value >= 0 && Value < 2;
732  }
733  bool isImm0_3() const {
734    if (!isImm()) return false;
735    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
736    if (!CE) return false;
737    int64_t Value = CE->getValue();
738    return Value >= 0 && Value < 4;
739  }
740  bool isImm0_7() const {
741    if (!isImm()) return false;
742    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
743    if (!CE) return false;
744    int64_t Value = CE->getValue();
745    return Value >= 0 && Value < 8;
746  }
747  bool isImm0_15() const {
748    if (!isImm()) return false;
749    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
750    if (!CE) return false;
751    int64_t Value = CE->getValue();
752    return Value >= 0 && Value < 16;
753  }
754  bool isImm0_31() const {
755    if (!isImm()) return false;
756    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
757    if (!CE) return false;
758    int64_t Value = CE->getValue();
759    return Value >= 0 && Value < 32;
760  }
761  bool isImm0_63() const {
762    if (!isImm()) return false;
763    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
764    if (!CE) return false;
765    int64_t Value = CE->getValue();
766    return Value >= 0 && Value < 64;
767  }
768  bool isImm8() const {
769    if (!isImm()) return false;
770    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
771    if (!CE) return false;
772    int64_t Value = CE->getValue();
773    return Value == 8;
774  }
775  bool isImm16() const {
776    if (!isImm()) return false;
777    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
778    if (!CE) return false;
779    int64_t Value = CE->getValue();
780    return Value == 16;
781  }
782  bool isImm32() const {
783    if (!isImm()) return false;
784    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
785    if (!CE) return false;
786    int64_t Value = CE->getValue();
787    return Value == 32;
788  }
789  bool isShrImm8() const {
790    if (!isImm()) return false;
791    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
792    if (!CE) return false;
793    int64_t Value = CE->getValue();
794    return Value > 0 && Value <= 8;
795  }
796  bool isShrImm16() const {
797    if (!isImm()) return false;
798    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
799    if (!CE) return false;
800    int64_t Value = CE->getValue();
801    return Value > 0 && Value <= 16;
802  }
803  bool isShrImm32() const {
804    if (!isImm()) return false;
805    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
806    if (!CE) return false;
807    int64_t Value = CE->getValue();
808    return Value > 0 && Value <= 32;
809  }
810  bool isShrImm64() const {
811    if (!isImm()) return false;
812    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
813    if (!CE) return false;
814    int64_t Value = CE->getValue();
815    return Value > 0 && Value <= 64;
816  }
817  bool isImm1_7() const {
818    if (!isImm()) return false;
819    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
820    if (!CE) return false;
821    int64_t Value = CE->getValue();
822    return Value > 0 && Value < 8;
823  }
824  bool isImm1_15() const {
825    if (!isImm()) return false;
826    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
827    if (!CE) return false;
828    int64_t Value = CE->getValue();
829    return Value > 0 && Value < 16;
830  }
831  bool isImm1_31() const {
832    if (!isImm()) return false;
833    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
834    if (!CE) return false;
835    int64_t Value = CE->getValue();
836    return Value > 0 && Value < 32;
837  }
838  bool isImm1_16() const {
839    if (!isImm()) return false;
840    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
841    if (!CE) return false;
842    int64_t Value = CE->getValue();
843    return Value > 0 && Value < 17;
844  }
845  bool isImm1_32() const {
846    if (!isImm()) return false;
847    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
848    if (!CE) return false;
849    int64_t Value = CE->getValue();
850    return Value > 0 && Value < 33;
851  }
852  bool isImm0_32() const {
853    if (!isImm()) return false;
854    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
855    if (!CE) return false;
856    int64_t Value = CE->getValue();
857    return Value >= 0 && Value < 33;
858  }
859  bool isImm0_65535() const {
860    if (!isImm()) return false;
861    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
862    if (!CE) return false;
863    int64_t Value = CE->getValue();
864    return Value >= 0 && Value < 65536;
865  }
866  bool isImm0_65535Expr() const {
867    if (!isImm()) return false;
868    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
869    // If it's not a constant expression, it'll generate a fixup and be
870    // handled later.
871    if (!CE) return true;
872    int64_t Value = CE->getValue();
873    return Value >= 0 && Value < 65536;
874  }
875  bool isImm24bit() const {
876    if (!isImm()) return false;
877    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
878    if (!CE) return false;
879    int64_t Value = CE->getValue();
880    return Value >= 0 && Value <= 0xffffff;
881  }
882  bool isImmThumbSR() const {
883    if (!isImm()) return false;
884    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
885    if (!CE) return false;
886    int64_t Value = CE->getValue();
887    return Value > 0 && Value < 33;
888  }
889  bool isPKHLSLImm() const {
890    if (!isImm()) return false;
891    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
892    if (!CE) return false;
893    int64_t Value = CE->getValue();
894    return Value >= 0 && Value < 32;
895  }
896  bool isPKHASRImm() const {
897    if (!isImm()) return false;
898    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
899    if (!CE) return false;
900    int64_t Value = CE->getValue();
901    return Value > 0 && Value <= 32;
902  }
903  bool isAdrLabel() const {
904    // If we have an immediate that's not a constant, treat it as a label
905    // reference needing a fixup. If it is a constant, but it can't fit
906    // into shift immediate encoding, we reject it.
907    if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
908    else return (isARMSOImm() || isARMSOImmNeg());
909  }
910  bool isARMSOImm() const {
911    if (!isImm()) return false;
912    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
913    if (!CE) return false;
914    int64_t Value = CE->getValue();
915    return ARM_AM::getSOImmVal(Value) != -1;
916  }
917  bool isARMSOImmNot() const {
918    if (!isImm()) return false;
919    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
920    if (!CE) return false;
921    int64_t Value = CE->getValue();
922    return ARM_AM::getSOImmVal(~Value) != -1;
923  }
924  bool isARMSOImmNeg() const {
925    if (!isImm()) return false;
926    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
927    if (!CE) return false;
928    int64_t Value = CE->getValue();
929    // Only use this when not representable as a plain so_imm.
930    return ARM_AM::getSOImmVal(Value) == -1 &&
931      ARM_AM::getSOImmVal(-Value) != -1;
932  }
933  bool isT2SOImm() const {
934    if (!isImm()) return false;
935    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
936    if (!CE) return false;
937    int64_t Value = CE->getValue();
938    return ARM_AM::getT2SOImmVal(Value) != -1;
939  }
940  bool isT2SOImmNot() const {
941    if (!isImm()) return false;
942    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
943    if (!CE) return false;
944    int64_t Value = CE->getValue();
945    return ARM_AM::getT2SOImmVal(~Value) != -1;
946  }
947  bool isT2SOImmNeg() const {
948    if (!isImm()) return false;
949    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
950    if (!CE) return false;
951    int64_t Value = CE->getValue();
952    // Only use this when not representable as a plain so_imm.
953    return ARM_AM::getT2SOImmVal(Value) == -1 &&
954      ARM_AM::getT2SOImmVal(-Value) != -1;
955  }
956  bool isSetEndImm() const {
957    if (!isImm()) return false;
958    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
959    if (!CE) return false;
960    int64_t Value = CE->getValue();
961    return Value == 1 || Value == 0;
962  }
963  bool isReg() const { return Kind == k_Register; }
964  bool isRegList() const { return Kind == k_RegisterList; }
965  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
966  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
967  bool isToken() const { return Kind == k_Token; }
968  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
969  bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
970  bool isMem() const { return Kind == k_Memory; }
971  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
972  bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
973  bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
974  bool isRotImm() const { return Kind == k_RotateImmediate; }
975  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
976  bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
977  bool isPostIdxReg() const {
978    return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
979  }
980  bool isMemNoOffset(bool alignOK = false) const {
981    if (!isMem())
982      return false;
983    // No offset of any kind.
984    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
985     (alignOK || Memory.Alignment == 0);
986  }
987  bool isMemPCRelImm12() const {
988    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
989      return false;
990    // Base register must be PC.
991    if (Memory.BaseRegNum != ARM::PC)
992      return false;
993    // Immediate offset in range [-4095, 4095].
994    if (!Memory.OffsetImm) return true;
995    int64_t Val = Memory.OffsetImm->getValue();
996    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
997  }
998  bool isAlignedMemory() const {
999    return isMemNoOffset(true);
1000  }
1001  bool isAddrMode2() const {
1002    if (!isMem() || Memory.Alignment != 0) return false;
1003    // Check for register offset.
1004    if (Memory.OffsetRegNum) return true;
1005    // Immediate offset in range [-4095, 4095].
1006    if (!Memory.OffsetImm) return true;
1007    int64_t Val = Memory.OffsetImm->getValue();
1008    return Val > -4096 && Val < 4096;
1009  }
1010  bool isAM2OffsetImm() const {
1011    if (!isImm()) return false;
1012    // Immediate offset in range [-4095, 4095].
1013    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1014    if (!CE) return false;
1015    int64_t Val = CE->getValue();
1016    return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1017  }
1018  bool isAddrMode3() const {
1019    // If we have an immediate that's not a constant, treat it as a label
1020    // reference needing a fixup. If it is a constant, it's something else
1021    // and we reject it.
1022    if (isImm() && !isa<MCConstantExpr>(getImm()))
1023      return true;
1024    if (!isMem() || Memory.Alignment != 0) return false;
1025    // No shifts are legal for AM3.
1026    if (Memory.ShiftType != ARM_AM::no_shift) return false;
1027    // Check for register offset.
1028    if (Memory.OffsetRegNum) return true;
1029    // Immediate offset in range [-255, 255].
1030    if (!Memory.OffsetImm) return true;
1031    int64_t Val = Memory.OffsetImm->getValue();
1032    // The #-0 offset is encoded as INT32_MIN, and we have to check
1033    // for this too.
1034    return (Val > -256 && Val < 256) || Val == INT32_MIN;
1035  }
1036  bool isAM3Offset() const {
1037    if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1038      return false;
1039    if (Kind == k_PostIndexRegister)
1040      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1041    // Immediate offset in range [-255, 255].
1042    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1043    if (!CE) return false;
1044    int64_t Val = CE->getValue();
1045    // Special case, #-0 is INT32_MIN.
1046    return (Val > -256 && Val < 256) || Val == INT32_MIN;
1047  }
1048  bool isAddrMode5() const {
1049    // If we have an immediate that's not a constant, treat it as a label
1050    // reference needing a fixup. If it is a constant, it's something else
1051    // and we reject it.
1052    if (isImm() && !isa<MCConstantExpr>(getImm()))
1053      return true;
1054    if (!isMem() || Memory.Alignment != 0) return false;
1055    // Check for register offset.
1056    if (Memory.OffsetRegNum) return false;
1057    // Immediate offset in range [-1020, 1020] and a multiple of 4.
1058    if (!Memory.OffsetImm) return true;
1059    int64_t Val = Memory.OffsetImm->getValue();
1060    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1061      Val == INT32_MIN;
1062  }
1063  bool isMemTBB() const {
1064    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1065        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1066      return false;
1067    return true;
1068  }
1069  bool isMemTBH() const {
1070    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1071        Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1072        Memory.Alignment != 0 )
1073      return false;
1074    return true;
1075  }
1076  bool isMemRegOffset() const {
1077    if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1078      return false;
1079    return true;
1080  }
1081  bool isT2MemRegOffset() const {
1082    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1083        Memory.Alignment != 0)
1084      return false;
1085    // Only lsl #{0, 1, 2, 3} allowed.
1086    if (Memory.ShiftType == ARM_AM::no_shift)
1087      return true;
1088    if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1089      return false;
1090    return true;
1091  }
1092  bool isMemThumbRR() const {
1093    // Thumb reg+reg addressing is simple. Just two registers, a base and
1094    // an offset. No shifts, negations or any other complicating factors.
1095    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1096        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1097      return false;
1098    return isARMLowRegister(Memory.BaseRegNum) &&
1099      (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1100  }
1101  bool isMemThumbRIs4() const {
1102    if (!isMem() || Memory.OffsetRegNum != 0 ||
1103        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1104      return false;
1105    // Immediate offset, multiple of 4 in range [0, 124].
1106    if (!Memory.OffsetImm) return true;
1107    int64_t Val = Memory.OffsetImm->getValue();
1108    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1109  }
1110  bool isMemThumbRIs2() const {
1111    if (!isMem() || Memory.OffsetRegNum != 0 ||
1112        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1113      return false;
1114    // Immediate offset, multiple of 4 in range [0, 62].
1115    if (!Memory.OffsetImm) return true;
1116    int64_t Val = Memory.OffsetImm->getValue();
1117    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1118  }
1119  bool isMemThumbRIs1() const {
1120    if (!isMem() || Memory.OffsetRegNum != 0 ||
1121        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1122      return false;
1123    // Immediate offset in range [0, 31].
1124    if (!Memory.OffsetImm) return true;
1125    int64_t Val = Memory.OffsetImm->getValue();
1126    return Val >= 0 && Val <= 31;
1127  }
1128  bool isMemThumbSPI() const {
1129    if (!isMem() || Memory.OffsetRegNum != 0 ||
1130        Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1131      return false;
1132    // Immediate offset, multiple of 4 in range [0, 1020].
1133    if (!Memory.OffsetImm) return true;
1134    int64_t Val = Memory.OffsetImm->getValue();
1135    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1136  }
1137  bool isMemImm8s4Offset() const {
1138    // If we have an immediate that's not a constant, treat it as a label
1139    // reference needing a fixup. If it is a constant, it's something else
1140    // and we reject it.
1141    if (isImm() && !isa<MCConstantExpr>(getImm()))
1142      return true;
1143    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1144      return false;
1145    // Immediate offset a multiple of 4 in range [-1020, 1020].
1146    if (!Memory.OffsetImm) return true;
1147    int64_t Val = Memory.OffsetImm->getValue();
1148    // Special case, #-0 is INT32_MIN.
1149    return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1150  }
1151  bool isMemImm0_1020s4Offset() const {
1152    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1153      return false;
1154    // Immediate offset a multiple of 4 in range [0, 1020].
1155    if (!Memory.OffsetImm) return true;
1156    int64_t Val = Memory.OffsetImm->getValue();
1157    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1158  }
1159  bool isMemImm8Offset() const {
1160    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1161      return false;
1162    // Base reg of PC isn't allowed for these encodings.
1163    if (Memory.BaseRegNum == ARM::PC) return false;
1164    // Immediate offset in range [-255, 255].
1165    if (!Memory.OffsetImm) return true;
1166    int64_t Val = Memory.OffsetImm->getValue();
1167    return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1168  }
1169  bool isMemPosImm8Offset() const {
1170    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1171      return false;
1172    // Immediate offset in range [0, 255].
1173    if (!Memory.OffsetImm) return true;
1174    int64_t Val = Memory.OffsetImm->getValue();
1175    return Val >= 0 && Val < 256;
1176  }
1177  bool isMemNegImm8Offset() const {
1178    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1179      return false;
1180    // Base reg of PC isn't allowed for these encodings.
1181    if (Memory.BaseRegNum == ARM::PC) return false;
1182    // Immediate offset in range [-255, -1].
1183    if (!Memory.OffsetImm) return false;
1184    int64_t Val = Memory.OffsetImm->getValue();
1185    return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1186  }
1187  bool isMemUImm12Offset() const {
1188    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1189      return false;
1190    // Immediate offset in range [0, 4095].
1191    if (!Memory.OffsetImm) return true;
1192    int64_t Val = Memory.OffsetImm->getValue();
1193    return (Val >= 0 && Val < 4096);
1194  }
1195  bool isMemImm12Offset() const {
1196    // If we have an immediate that's not a constant, treat it as a label
1197    // reference needing a fixup. If it is a constant, it's something else
1198    // and we reject it.
1199    if (isImm() && !isa<MCConstantExpr>(getImm()))
1200      return true;
1201
1202    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1203      return false;
1204    // Immediate offset in range [-4095, 4095].
1205    if (!Memory.OffsetImm) return true;
1206    int64_t Val = Memory.OffsetImm->getValue();
1207    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1208  }
1209  bool isPostIdxImm8() const {
1210    if (!isImm()) return false;
1211    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1212    if (!CE) return false;
1213    int64_t Val = CE->getValue();
1214    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1215  }
1216  bool isPostIdxImm8s4() const {
1217    if (!isImm()) return false;
1218    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1219    if (!CE) return false;
1220    int64_t Val = CE->getValue();
1221    return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1222      (Val == INT32_MIN);
1223  }
1224
1225  bool isMSRMask() const { return Kind == k_MSRMask; }
1226  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1227
1228  // NEON operands.
1229  bool isSingleSpacedVectorList() const {
1230    return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1231  }
1232  bool isDoubleSpacedVectorList() const {
1233    return Kind == k_VectorList && VectorList.isDoubleSpaced;
1234  }
1235  bool isVecListOneD() const {
1236    if (!isSingleSpacedVectorList()) return false;
1237    return VectorList.Count == 1;
1238  }
1239
1240  bool isVecListDPair() const {
1241    if (!isSingleSpacedVectorList()) return false;
1242    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1243              .contains(VectorList.RegNum));
1244  }
1245
1246  bool isVecListThreeD() const {
1247    if (!isSingleSpacedVectorList()) return false;
1248    return VectorList.Count == 3;
1249  }
1250
1251  bool isVecListFourD() const {
1252    if (!isSingleSpacedVectorList()) return false;
1253    return VectorList.Count == 4;
1254  }
1255
1256  bool isVecListDPairSpaced() const {
1257    if (isSingleSpacedVectorList()) return false;
1258    return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1259              .contains(VectorList.RegNum));
1260  }
1261
1262  bool isVecListThreeQ() const {
1263    if (!isDoubleSpacedVectorList()) return false;
1264    return VectorList.Count == 3;
1265  }
1266
1267  bool isVecListFourQ() const {
1268    if (!isDoubleSpacedVectorList()) return false;
1269    return VectorList.Count == 4;
1270  }
1271
1272  bool isSingleSpacedVectorAllLanes() const {
1273    return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1274  }
1275  bool isDoubleSpacedVectorAllLanes() const {
1276    return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1277  }
1278  bool isVecListOneDAllLanes() const {
1279    if (!isSingleSpacedVectorAllLanes()) return false;
1280    return VectorList.Count == 1;
1281  }
1282
1283  bool isVecListDPairAllLanes() const {
1284    if (!isSingleSpacedVectorAllLanes()) return false;
1285    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1286              .contains(VectorList.RegNum));
1287  }
1288
1289  bool isVecListDPairSpacedAllLanes() const {
1290    if (!isDoubleSpacedVectorAllLanes()) return false;
1291    return VectorList.Count == 2;
1292  }
1293
1294  bool isVecListThreeDAllLanes() const {
1295    if (!isSingleSpacedVectorAllLanes()) return false;
1296    return VectorList.Count == 3;
1297  }
1298
1299  bool isVecListThreeQAllLanes() const {
1300    if (!isDoubleSpacedVectorAllLanes()) return false;
1301    return VectorList.Count == 3;
1302  }
1303
1304  bool isVecListFourDAllLanes() const {
1305    if (!isSingleSpacedVectorAllLanes()) return false;
1306    return VectorList.Count == 4;
1307  }
1308
1309  bool isVecListFourQAllLanes() const {
1310    if (!isDoubleSpacedVectorAllLanes()) return false;
1311    return VectorList.Count == 4;
1312  }
1313
1314  bool isSingleSpacedVectorIndexed() const {
1315    return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1316  }
1317  bool isDoubleSpacedVectorIndexed() const {
1318    return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1319  }
1320  bool isVecListOneDByteIndexed() const {
1321    if (!isSingleSpacedVectorIndexed()) return false;
1322    return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1323  }
1324
1325  bool isVecListOneDHWordIndexed() const {
1326    if (!isSingleSpacedVectorIndexed()) return false;
1327    return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1328  }
1329
1330  bool isVecListOneDWordIndexed() const {
1331    if (!isSingleSpacedVectorIndexed()) return false;
1332    return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1333  }
1334
1335  bool isVecListTwoDByteIndexed() const {
1336    if (!isSingleSpacedVectorIndexed()) return false;
1337    return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1338  }
1339
1340  bool isVecListTwoDHWordIndexed() const {
1341    if (!isSingleSpacedVectorIndexed()) return false;
1342    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1343  }
1344
1345  bool isVecListTwoQWordIndexed() const {
1346    if (!isDoubleSpacedVectorIndexed()) return false;
1347    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1348  }
1349
1350  bool isVecListTwoQHWordIndexed() const {
1351    if (!isDoubleSpacedVectorIndexed()) return false;
1352    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1353  }
1354
1355  bool isVecListTwoDWordIndexed() const {
1356    if (!isSingleSpacedVectorIndexed()) return false;
1357    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1358  }
1359
1360  bool isVecListThreeDByteIndexed() const {
1361    if (!isSingleSpacedVectorIndexed()) return false;
1362    return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1363  }
1364
1365  bool isVecListThreeDHWordIndexed() const {
1366    if (!isSingleSpacedVectorIndexed()) return false;
1367    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1368  }
1369
1370  bool isVecListThreeQWordIndexed() const {
1371    if (!isDoubleSpacedVectorIndexed()) return false;
1372    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1373  }
1374
1375  bool isVecListThreeQHWordIndexed() const {
1376    if (!isDoubleSpacedVectorIndexed()) return false;
1377    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1378  }
1379
1380  bool isVecListThreeDWordIndexed() const {
1381    if (!isSingleSpacedVectorIndexed()) return false;
1382    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1383  }
1384
1385  bool isVecListFourDByteIndexed() const {
1386    if (!isSingleSpacedVectorIndexed()) return false;
1387    return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1388  }
1389
1390  bool isVecListFourDHWordIndexed() const {
1391    if (!isSingleSpacedVectorIndexed()) return false;
1392    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1393  }
1394
1395  bool isVecListFourQWordIndexed() const {
1396    if (!isDoubleSpacedVectorIndexed()) return false;
1397    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1398  }
1399
1400  bool isVecListFourQHWordIndexed() const {
1401    if (!isDoubleSpacedVectorIndexed()) return false;
1402    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1403  }
1404
1405  bool isVecListFourDWordIndexed() const {
1406    if (!isSingleSpacedVectorIndexed()) return false;
1407    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1408  }
1409
1410  bool isVectorIndex8() const {
1411    if (Kind != k_VectorIndex) return false;
1412    return VectorIndex.Val < 8;
1413  }
1414  bool isVectorIndex16() const {
1415    if (Kind != k_VectorIndex) return false;
1416    return VectorIndex.Val < 4;
1417  }
1418  bool isVectorIndex32() const {
1419    if (Kind != k_VectorIndex) return false;
1420    return VectorIndex.Val < 2;
1421  }
1422
1423  bool isNEONi8splat() const {
1424    if (!isImm()) return false;
1425    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1426    // Must be a constant.
1427    if (!CE) return false;
1428    int64_t Value = CE->getValue();
1429    // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1430    // value.
1431    return Value >= 0 && Value < 256;
1432  }
1433
1434  bool isNEONi16splat() const {
1435    if (!isImm()) return false;
1436    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1437    // Must be a constant.
1438    if (!CE) return false;
1439    int64_t Value = CE->getValue();
1440    // i16 value in the range [0,255] or [0x0100, 0xff00]
1441    return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1442  }
1443
1444  bool isNEONi32splat() const {
1445    if (!isImm()) return false;
1446    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1447    // Must be a constant.
1448    if (!CE) return false;
1449    int64_t Value = CE->getValue();
1450    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1451    return (Value >= 0 && Value < 256) ||
1452      (Value >= 0x0100 && Value <= 0xff00) ||
1453      (Value >= 0x010000 && Value <= 0xff0000) ||
1454      (Value >= 0x01000000 && Value <= 0xff000000);
1455  }
1456
1457  bool isNEONi32vmov() const {
1458    if (!isImm()) return false;
1459    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1460    // Must be a constant.
1461    if (!CE) return false;
1462    int64_t Value = CE->getValue();
1463    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1464    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1465    return (Value >= 0 && Value < 256) ||
1466      (Value >= 0x0100 && Value <= 0xff00) ||
1467      (Value >= 0x010000 && Value <= 0xff0000) ||
1468      (Value >= 0x01000000 && Value <= 0xff000000) ||
1469      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1470      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1471  }
1472  bool isNEONi32vmovNeg() const {
1473    if (!isImm()) return false;
1474    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1475    // Must be a constant.
1476    if (!CE) return false;
1477    int64_t Value = ~CE->getValue();
1478    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1479    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1480    return (Value >= 0 && Value < 256) ||
1481      (Value >= 0x0100 && Value <= 0xff00) ||
1482      (Value >= 0x010000 && Value <= 0xff0000) ||
1483      (Value >= 0x01000000 && Value <= 0xff000000) ||
1484      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1485      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1486  }
1487
1488  bool isNEONi64splat() const {
1489    if (!isImm()) return false;
1490    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1491    // Must be a constant.
1492    if (!CE) return false;
1493    uint64_t Value = CE->getValue();
1494    // i64 value with each byte being either 0 or 0xff.
1495    for (unsigned i = 0; i < 8; ++i)
1496      if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1497    return true;
1498  }
1499
1500  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1501    // Add as immediates when possible.  Null MCExpr = 0.
1502    if (Expr == 0)
1503      Inst.addOperand(MCOperand::CreateImm(0));
1504    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1505      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1506    else
1507      Inst.addOperand(MCOperand::CreateExpr(Expr));
1508  }
1509
1510  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1511    assert(N == 2 && "Invalid number of operands!");
1512    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1513    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1514    Inst.addOperand(MCOperand::CreateReg(RegNum));
1515  }
1516
1517  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1518    assert(N == 1 && "Invalid number of operands!");
1519    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1520  }
1521
1522  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1523    assert(N == 1 && "Invalid number of operands!");
1524    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1525  }
1526
1527  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1528    assert(N == 1 && "Invalid number of operands!");
1529    Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1530  }
1531
1532  void addITMaskOperands(MCInst &Inst, unsigned N) const {
1533    assert(N == 1 && "Invalid number of operands!");
1534    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1535  }
1536
1537  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1538    assert(N == 1 && "Invalid number of operands!");
1539    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1540  }
1541
1542  void addCCOutOperands(MCInst &Inst, unsigned N) const {
1543    assert(N == 1 && "Invalid number of operands!");
1544    Inst.addOperand(MCOperand::CreateReg(getReg()));
1545  }
1546
1547  void addRegOperands(MCInst &Inst, unsigned N) const {
1548    assert(N == 1 && "Invalid number of operands!");
1549    Inst.addOperand(MCOperand::CreateReg(getReg()));
1550  }
1551
1552  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1553    assert(N == 3 && "Invalid number of operands!");
1554    assert(isRegShiftedReg() &&
1555           "addRegShiftedRegOperands() on non RegShiftedReg!");
1556    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1557    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1558    Inst.addOperand(MCOperand::CreateImm(
1559      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1560  }
1561
1562  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1563    assert(N == 2 && "Invalid number of operands!");
1564    assert(isRegShiftedImm() &&
1565           "addRegShiftedImmOperands() on non RegShiftedImm!");
1566    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1567    // Shift of #32 is encoded as 0 where permitted
1568    unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1569    Inst.addOperand(MCOperand::CreateImm(
1570      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1571  }
1572
1573  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1574    assert(N == 1 && "Invalid number of operands!");
1575    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1576                                         ShifterImm.Imm));
1577  }
1578
1579  void addRegListOperands(MCInst &Inst, unsigned N) const {
1580    assert(N == 1 && "Invalid number of operands!");
1581    const SmallVectorImpl<unsigned> &RegList = getRegList();
1582    for (SmallVectorImpl<unsigned>::const_iterator
1583           I = RegList.begin(), E = RegList.end(); I != E; ++I)
1584      Inst.addOperand(MCOperand::CreateReg(*I));
1585  }
1586
1587  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1588    addRegListOperands(Inst, N);
1589  }
1590
1591  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1592    addRegListOperands(Inst, N);
1593  }
1594
1595  void addRotImmOperands(MCInst &Inst, unsigned N) const {
1596    assert(N == 1 && "Invalid number of operands!");
1597    // Encoded as val>>3. The printer handles display as 8, 16, 24.
1598    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1599  }
1600
1601  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1602    assert(N == 1 && "Invalid number of operands!");
1603    // Munge the lsb/width into a bitfield mask.
1604    unsigned lsb = Bitfield.LSB;
1605    unsigned width = Bitfield.Width;
1606    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1607    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1608                      (32 - (lsb + width)));
1609    Inst.addOperand(MCOperand::CreateImm(Mask));
1610  }
1611
1612  void addImmOperands(MCInst &Inst, unsigned N) const {
1613    assert(N == 1 && "Invalid number of operands!");
1614    addExpr(Inst, getImm());
1615  }
1616
1617  void addFBits16Operands(MCInst &Inst, unsigned N) const {
1618    assert(N == 1 && "Invalid number of operands!");
1619    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1620    Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1621  }
1622
1623  void addFBits32Operands(MCInst &Inst, unsigned N) const {
1624    assert(N == 1 && "Invalid number of operands!");
1625    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1626    Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1627  }
1628
1629  void addFPImmOperands(MCInst &Inst, unsigned N) const {
1630    assert(N == 1 && "Invalid number of operands!");
1631    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1632    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1633    Inst.addOperand(MCOperand::CreateImm(Val));
1634  }
1635
1636  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1637    assert(N == 1 && "Invalid number of operands!");
1638    // FIXME: We really want to scale the value here, but the LDRD/STRD
1639    // instruction don't encode operands that way yet.
1640    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1641    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1642  }
1643
1644  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1645    assert(N == 1 && "Invalid number of operands!");
1646    // The immediate is scaled by four in the encoding and is stored
1647    // in the MCInst as such. Lop off the low two bits here.
1648    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1649    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1650  }
1651
1652  void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1653    assert(N == 1 && "Invalid number of operands!");
1654    // The immediate is scaled by four in the encoding and is stored
1655    // in the MCInst as such. Lop off the low two bits here.
1656    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1657    Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1658  }
1659
1660  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1661    assert(N == 1 && "Invalid number of operands!");
1662    // The immediate is scaled by four in the encoding and is stored
1663    // in the MCInst as such. Lop off the low two bits here.
1664    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1665    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1666  }
1667
1668  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1669    assert(N == 1 && "Invalid number of operands!");
1670    // The constant encodes as the immediate-1, and we store in the instruction
1671    // the bits as encoded, so subtract off one here.
1672    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1673    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1674  }
1675
1676  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1677    assert(N == 1 && "Invalid number of operands!");
1678    // The constant encodes as the immediate-1, and we store in the instruction
1679    // the bits as encoded, so subtract off one here.
1680    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1681    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1682  }
1683
1684  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1685    assert(N == 1 && "Invalid number of operands!");
1686    // The constant encodes as the immediate, except for 32, which encodes as
1687    // zero.
1688    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1689    unsigned Imm = CE->getValue();
1690    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1691  }
1692
1693  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1694    assert(N == 1 && "Invalid number of operands!");
1695    // An ASR value of 32 encodes as 0, so that's how we want to add it to
1696    // the instruction as well.
1697    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1698    int Val = CE->getValue();
1699    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1700  }
1701
1702  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1703    assert(N == 1 && "Invalid number of operands!");
1704    // The operand is actually a t2_so_imm, but we have its bitwise
1705    // negation in the assembly source, so twiddle it here.
1706    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1707    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1708  }
1709
1710  void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1711    assert(N == 1 && "Invalid number of operands!");
1712    // The operand is actually a t2_so_imm, but we have its
1713    // negation in the assembly source, so twiddle it here.
1714    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1715    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1716  }
1717
1718  void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1719    assert(N == 1 && "Invalid number of operands!");
1720    // The operand is actually an imm0_4095, but we have its
1721    // negation in the assembly source, so twiddle it here.
1722    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1723    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1724  }
1725
1726  void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1727    if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1728      Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1729      return;
1730    }
1731
1732    const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1733    assert(SR && "Unknown value type!");
1734    Inst.addOperand(MCOperand::CreateExpr(SR));
1735  }
1736
1737  void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1738    assert(N == 1 && "Invalid number of operands!");
1739    // The operand is actually a so_imm, but we have its bitwise
1740    // negation in the assembly source, so twiddle it here.
1741    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1742    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1743  }
1744
1745  void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1746    assert(N == 1 && "Invalid number of operands!");
1747    // The operand is actually a so_imm, but we have its
1748    // negation in the assembly source, so twiddle it here.
1749    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1750    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1751  }
1752
1753  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1754    assert(N == 1 && "Invalid number of operands!");
1755    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1756  }
1757
1758  void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1759    assert(N == 1 && "Invalid number of operands!");
1760    Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1761  }
1762
1763  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1764    assert(N == 1 && "Invalid number of operands!");
1765    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1766  }
1767
1768  void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1769    assert(N == 1 && "Invalid number of operands!");
1770    int32_t Imm = Memory.OffsetImm->getValue();
1771    // FIXME: Handle #-0
1772    if (Imm == INT32_MIN) Imm = 0;
1773    Inst.addOperand(MCOperand::CreateImm(Imm));
1774  }
1775
1776  void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1777    assert(N == 1 && "Invalid number of operands!");
1778    assert(isImm() && "Not an immediate!");
1779
1780    // If we have an immediate that's not a constant, treat it as a label
1781    // reference needing a fixup.
1782    if (!isa<MCConstantExpr>(getImm())) {
1783      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1784      return;
1785    }
1786
1787    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1788    int Val = CE->getValue();
1789    Inst.addOperand(MCOperand::CreateImm(Val));
1790  }
1791
1792  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1793    assert(N == 2 && "Invalid number of operands!");
1794    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1795    Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1796  }
1797
1798  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1799    assert(N == 3 && "Invalid number of operands!");
1800    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1801    if (!Memory.OffsetRegNum) {
1802      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1803      // Special case for #-0
1804      if (Val == INT32_MIN) Val = 0;
1805      if (Val < 0) Val = -Val;
1806      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1807    } else {
1808      // For register offset, we encode the shift type and negation flag
1809      // here.
1810      Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1811                              Memory.ShiftImm, Memory.ShiftType);
1812    }
1813    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1814    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1815    Inst.addOperand(MCOperand::CreateImm(Val));
1816  }
1817
1818  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1819    assert(N == 2 && "Invalid number of operands!");
1820    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1821    assert(CE && "non-constant AM2OffsetImm operand!");
1822    int32_t Val = CE->getValue();
1823    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1824    // Special case for #-0
1825    if (Val == INT32_MIN) Val = 0;
1826    if (Val < 0) Val = -Val;
1827    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1828    Inst.addOperand(MCOperand::CreateReg(0));
1829    Inst.addOperand(MCOperand::CreateImm(Val));
1830  }
1831
1832  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1833    assert(N == 3 && "Invalid number of operands!");
1834    // If we have an immediate that's not a constant, treat it as a label
1835    // reference needing a fixup. If it is a constant, it's something else
1836    // and we reject it.
1837    if (isImm()) {
1838      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1839      Inst.addOperand(MCOperand::CreateReg(0));
1840      Inst.addOperand(MCOperand::CreateImm(0));
1841      return;
1842    }
1843
1844    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1845    if (!Memory.OffsetRegNum) {
1846      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1847      // Special case for #-0
1848      if (Val == INT32_MIN) Val = 0;
1849      if (Val < 0) Val = -Val;
1850      Val = ARM_AM::getAM3Opc(AddSub, Val);
1851    } else {
1852      // For register offset, we encode the shift type and negation flag
1853      // here.
1854      Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1855    }
1856    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1857    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1858    Inst.addOperand(MCOperand::CreateImm(Val));
1859  }
1860
1861  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1862    assert(N == 2 && "Invalid number of operands!");
1863    if (Kind == k_PostIndexRegister) {
1864      int32_t Val =
1865        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1866      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1867      Inst.addOperand(MCOperand::CreateImm(Val));
1868      return;
1869    }
1870
1871    // Constant offset.
1872    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1873    int32_t Val = CE->getValue();
1874    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1875    // Special case for #-0
1876    if (Val == INT32_MIN) Val = 0;
1877    if (Val < 0) Val = -Val;
1878    Val = ARM_AM::getAM3Opc(AddSub, Val);
1879    Inst.addOperand(MCOperand::CreateReg(0));
1880    Inst.addOperand(MCOperand::CreateImm(Val));
1881  }
1882
1883  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1884    assert(N == 2 && "Invalid number of operands!");
1885    // If we have an immediate that's not a constant, treat it as a label
1886    // reference needing a fixup. If it is a constant, it's something else
1887    // and we reject it.
1888    if (isImm()) {
1889      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1890      Inst.addOperand(MCOperand::CreateImm(0));
1891      return;
1892    }
1893
1894    // The lower two bits are always zero and as such are not encoded.
1895    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1896    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1897    // Special case for #-0
1898    if (Val == INT32_MIN) Val = 0;
1899    if (Val < 0) Val = -Val;
1900    Val = ARM_AM::getAM5Opc(AddSub, Val);
1901    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1902    Inst.addOperand(MCOperand::CreateImm(Val));
1903  }
1904
1905  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1906    assert(N == 2 && "Invalid number of operands!");
1907    // If we have an immediate that's not a constant, treat it as a label
1908    // reference needing a fixup. If it is a constant, it's something else
1909    // and we reject it.
1910    if (isImm()) {
1911      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1912      Inst.addOperand(MCOperand::CreateImm(0));
1913      return;
1914    }
1915
1916    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1917    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1918    Inst.addOperand(MCOperand::CreateImm(Val));
1919  }
1920
1921  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1922    assert(N == 2 && "Invalid number of operands!");
1923    // The lower two bits are always zero and as such are not encoded.
1924    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1925    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1926    Inst.addOperand(MCOperand::CreateImm(Val));
1927  }
1928
1929  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1930    assert(N == 2 && "Invalid number of operands!");
1931    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1932    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1933    Inst.addOperand(MCOperand::CreateImm(Val));
1934  }
1935
1936  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1937    addMemImm8OffsetOperands(Inst, N);
1938  }
1939
1940  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1941    addMemImm8OffsetOperands(Inst, N);
1942  }
1943
1944  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1945    assert(N == 2 && "Invalid number of operands!");
1946    // If this is an immediate, it's a label reference.
1947    if (isImm()) {
1948      addExpr(Inst, getImm());
1949      Inst.addOperand(MCOperand::CreateImm(0));
1950      return;
1951    }
1952
1953    // Otherwise, it's a normal memory reg+offset.
1954    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1955    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1956    Inst.addOperand(MCOperand::CreateImm(Val));
1957  }
1958
1959  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1960    assert(N == 2 && "Invalid number of operands!");
1961    // If this is an immediate, it's a label reference.
1962    if (isImm()) {
1963      addExpr(Inst, getImm());
1964      Inst.addOperand(MCOperand::CreateImm(0));
1965      return;
1966    }
1967
1968    // Otherwise, it's a normal memory reg+offset.
1969    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1970    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1971    Inst.addOperand(MCOperand::CreateImm(Val));
1972  }
1973
1974  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1975    assert(N == 2 && "Invalid number of operands!");
1976    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1977    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1978  }
1979
1980  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1981    assert(N == 2 && "Invalid number of operands!");
1982    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1983    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1984  }
1985
1986  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1987    assert(N == 3 && "Invalid number of operands!");
1988    unsigned Val =
1989      ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1990                        Memory.ShiftImm, Memory.ShiftType);
1991    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1992    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1993    Inst.addOperand(MCOperand::CreateImm(Val));
1994  }
1995
1996  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1997    assert(N == 3 && "Invalid number of operands!");
1998    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1999    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2000    Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2001  }
2002
2003  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2004    assert(N == 2 && "Invalid number of operands!");
2005    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2006    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2007  }
2008
2009  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2010    assert(N == 2 && "Invalid number of operands!");
2011    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2012    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2013    Inst.addOperand(MCOperand::CreateImm(Val));
2014  }
2015
2016  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2017    assert(N == 2 && "Invalid number of operands!");
2018    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2019    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2020    Inst.addOperand(MCOperand::CreateImm(Val));
2021  }
2022
2023  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2024    assert(N == 2 && "Invalid number of operands!");
2025    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2026    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2027    Inst.addOperand(MCOperand::CreateImm(Val));
2028  }
2029
2030  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2031    assert(N == 2 && "Invalid number of operands!");
2032    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2033    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2034    Inst.addOperand(MCOperand::CreateImm(Val));
2035  }
2036
2037  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2038    assert(N == 1 && "Invalid number of operands!");
2039    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2040    assert(CE && "non-constant post-idx-imm8 operand!");
2041    int Imm = CE->getValue();
2042    bool isAdd = Imm >= 0;
2043    if (Imm == INT32_MIN) Imm = 0;
2044    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2045    Inst.addOperand(MCOperand::CreateImm(Imm));
2046  }
2047
2048  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2049    assert(N == 1 && "Invalid number of operands!");
2050    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2051    assert(CE && "non-constant post-idx-imm8s4 operand!");
2052    int Imm = CE->getValue();
2053    bool isAdd = Imm >= 0;
2054    if (Imm == INT32_MIN) Imm = 0;
2055    // Immediate is scaled by 4.
2056    Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2057    Inst.addOperand(MCOperand::CreateImm(Imm));
2058  }
2059
2060  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2061    assert(N == 2 && "Invalid number of operands!");
2062    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2063    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2064  }
2065
2066  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2067    assert(N == 2 && "Invalid number of operands!");
2068    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2069    // The sign, shift type, and shift amount are encoded in a single operand
2070    // using the AM2 encoding helpers.
2071    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2072    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2073                                     PostIdxReg.ShiftTy);
2074    Inst.addOperand(MCOperand::CreateImm(Imm));
2075  }
2076
2077  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2078    assert(N == 1 && "Invalid number of operands!");
2079    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2080  }
2081
2082  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2083    assert(N == 1 && "Invalid number of operands!");
2084    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2085  }
2086
2087  void addVecListOperands(MCInst &Inst, unsigned N) const {
2088    assert(N == 1 && "Invalid number of operands!");
2089    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2090  }
2091
2092  void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2093    assert(N == 2 && "Invalid number of operands!");
2094    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2095    Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2096  }
2097
2098  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2099    assert(N == 1 && "Invalid number of operands!");
2100    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2101  }
2102
2103  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2104    assert(N == 1 && "Invalid number of operands!");
2105    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2106  }
2107
2108  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2109    assert(N == 1 && "Invalid number of operands!");
2110    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2111  }
2112
2113  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2114    assert(N == 1 && "Invalid number of operands!");
2115    // The immediate encodes the type of constant as well as the value.
2116    // Mask in that this is an i8 splat.
2117    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2118    Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2119  }
2120
2121  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2122    assert(N == 1 && "Invalid number of operands!");
2123    // The immediate encodes the type of constant as well as the value.
2124    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2125    unsigned Value = CE->getValue();
2126    if (Value >= 256)
2127      Value = (Value >> 8) | 0xa00;
2128    else
2129      Value |= 0x800;
2130    Inst.addOperand(MCOperand::CreateImm(Value));
2131  }
2132
2133  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2134    assert(N == 1 && "Invalid number of operands!");
2135    // The immediate encodes the type of constant as well as the value.
2136    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2137    unsigned Value = CE->getValue();
2138    if (Value >= 256 && Value <= 0xff00)
2139      Value = (Value >> 8) | 0x200;
2140    else if (Value > 0xffff && Value <= 0xff0000)
2141      Value = (Value >> 16) | 0x400;
2142    else if (Value > 0xffffff)
2143      Value = (Value >> 24) | 0x600;
2144    Inst.addOperand(MCOperand::CreateImm(Value));
2145  }
2146
2147  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2148    assert(N == 1 && "Invalid number of operands!");
2149    // The immediate encodes the type of constant as well as the value.
2150    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2151    unsigned Value = CE->getValue();
2152    if (Value >= 256 && Value <= 0xffff)
2153      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2154    else if (Value > 0xffff && Value <= 0xffffff)
2155      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2156    else if (Value > 0xffffff)
2157      Value = (Value >> 24) | 0x600;
2158    Inst.addOperand(MCOperand::CreateImm(Value));
2159  }
2160
2161  void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2162    assert(N == 1 && "Invalid number of operands!");
2163    // The immediate encodes the type of constant as well as the value.
2164    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2165    unsigned Value = ~CE->getValue();
2166    if (Value >= 256 && Value <= 0xffff)
2167      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2168    else if (Value > 0xffff && Value <= 0xffffff)
2169      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2170    else if (Value > 0xffffff)
2171      Value = (Value >> 24) | 0x600;
2172    Inst.addOperand(MCOperand::CreateImm(Value));
2173  }
2174
2175  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2176    assert(N == 1 && "Invalid number of operands!");
2177    // The immediate encodes the type of constant as well as the value.
2178    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2179    uint64_t Value = CE->getValue();
2180    unsigned Imm = 0;
2181    for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2182      Imm |= (Value & 1) << i;
2183    }
2184    Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2185  }
2186
2187  virtual void print(raw_ostream &OS) const;
2188
2189  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2190    ARMOperand *Op = new ARMOperand(k_ITCondMask);
2191    Op->ITMask.Mask = Mask;
2192    Op->StartLoc = S;
2193    Op->EndLoc = S;
2194    return Op;
2195  }
2196
2197  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2198    ARMOperand *Op = new ARMOperand(k_CondCode);
2199    Op->CC.Val = CC;
2200    Op->StartLoc = S;
2201    Op->EndLoc = S;
2202    return Op;
2203  }
2204
2205  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2206    ARMOperand *Op = new ARMOperand(k_CoprocNum);
2207    Op->Cop.Val = CopVal;
2208    Op->StartLoc = S;
2209    Op->EndLoc = S;
2210    return Op;
2211  }
2212
2213  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2214    ARMOperand *Op = new ARMOperand(k_CoprocReg);
2215    Op->Cop.Val = CopVal;
2216    Op->StartLoc = S;
2217    Op->EndLoc = S;
2218    return Op;
2219  }
2220
2221  static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2222    ARMOperand *Op = new ARMOperand(k_CoprocOption);
2223    Op->Cop.Val = Val;
2224    Op->StartLoc = S;
2225    Op->EndLoc = E;
2226    return Op;
2227  }
2228
2229  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2230    ARMOperand *Op = new ARMOperand(k_CCOut);
2231    Op->Reg.RegNum = RegNum;
2232    Op->StartLoc = S;
2233    Op->EndLoc = S;
2234    return Op;
2235  }
2236
2237  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2238    ARMOperand *Op = new ARMOperand(k_Token);
2239    Op->Tok.Data = Str.data();
2240    Op->Tok.Length = Str.size();
2241    Op->StartLoc = S;
2242    Op->EndLoc = S;
2243    return Op;
2244  }
2245
2246  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2247    ARMOperand *Op = new ARMOperand(k_Register);
2248    Op->Reg.RegNum = RegNum;
2249    Op->StartLoc = S;
2250    Op->EndLoc = E;
2251    return Op;
2252  }
2253
2254  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2255                                           unsigned SrcReg,
2256                                           unsigned ShiftReg,
2257                                           unsigned ShiftImm,
2258                                           SMLoc S, SMLoc E) {
2259    ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2260    Op->RegShiftedReg.ShiftTy = ShTy;
2261    Op->RegShiftedReg.SrcReg = SrcReg;
2262    Op->RegShiftedReg.ShiftReg = ShiftReg;
2263    Op->RegShiftedReg.ShiftImm = ShiftImm;
2264    Op->StartLoc = S;
2265    Op->EndLoc = E;
2266    return Op;
2267  }
2268
2269  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2270                                            unsigned SrcReg,
2271                                            unsigned ShiftImm,
2272                                            SMLoc S, SMLoc E) {
2273    ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2274    Op->RegShiftedImm.ShiftTy = ShTy;
2275    Op->RegShiftedImm.SrcReg = SrcReg;
2276    Op->RegShiftedImm.ShiftImm = ShiftImm;
2277    Op->StartLoc = S;
2278    Op->EndLoc = E;
2279    return Op;
2280  }
2281
2282  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2283                                   SMLoc S, SMLoc E) {
2284    ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2285    Op->ShifterImm.isASR = isASR;
2286    Op->ShifterImm.Imm = Imm;
2287    Op->StartLoc = S;
2288    Op->EndLoc = E;
2289    return Op;
2290  }
2291
2292  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2293    ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2294    Op->RotImm.Imm = Imm;
2295    Op->StartLoc = S;
2296    Op->EndLoc = E;
2297    return Op;
2298  }
2299
2300  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2301                                    SMLoc S, SMLoc E) {
2302    ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2303    Op->Bitfield.LSB = LSB;
2304    Op->Bitfield.Width = Width;
2305    Op->StartLoc = S;
2306    Op->EndLoc = E;
2307    return Op;
2308  }
2309
2310  static ARMOperand *
2311  CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2312                SMLoc StartLoc, SMLoc EndLoc) {
2313    assert (Regs.size() > 0 && "RegList contains no registers?");
2314    KindTy Kind = k_RegisterList;
2315
2316    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2317      Kind = k_DPRRegisterList;
2318    else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2319             contains(Regs.front().second))
2320      Kind = k_SPRRegisterList;
2321
2322    // Sort based on the register encoding values.
2323    array_pod_sort(Regs.begin(), Regs.end());
2324
2325    ARMOperand *Op = new ARMOperand(Kind);
2326    for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2327           I = Regs.begin(), E = Regs.end(); I != E; ++I)
2328      Op->Registers.push_back(I->second);
2329    Op->StartLoc = StartLoc;
2330    Op->EndLoc = EndLoc;
2331    return Op;
2332  }
2333
2334  static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2335                                      bool isDoubleSpaced, SMLoc S, SMLoc E) {
2336    ARMOperand *Op = new ARMOperand(k_VectorList);
2337    Op->VectorList.RegNum = RegNum;
2338    Op->VectorList.Count = Count;
2339    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2340    Op->StartLoc = S;
2341    Op->EndLoc = E;
2342    return Op;
2343  }
2344
2345  static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2346                                              bool isDoubleSpaced,
2347                                              SMLoc S, SMLoc E) {
2348    ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2349    Op->VectorList.RegNum = RegNum;
2350    Op->VectorList.Count = Count;
2351    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2352    Op->StartLoc = S;
2353    Op->EndLoc = E;
2354    return Op;
2355  }
2356
2357  static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2358                                             unsigned Index,
2359                                             bool isDoubleSpaced,
2360                                             SMLoc S, SMLoc E) {
2361    ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2362    Op->VectorList.RegNum = RegNum;
2363    Op->VectorList.Count = Count;
2364    Op->VectorList.LaneIndex = Index;
2365    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2366    Op->StartLoc = S;
2367    Op->EndLoc = E;
2368    return Op;
2369  }
2370
2371  static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2372                                       MCContext &Ctx) {
2373    ARMOperand *Op = new ARMOperand(k_VectorIndex);
2374    Op->VectorIndex.Val = Idx;
2375    Op->StartLoc = S;
2376    Op->EndLoc = E;
2377    return Op;
2378  }
2379
2380  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2381    ARMOperand *Op = new ARMOperand(k_Immediate);
2382    Op->Imm.Val = Val;
2383    Op->StartLoc = S;
2384    Op->EndLoc = E;
2385    return Op;
2386  }
2387
2388  static ARMOperand *CreateMem(unsigned BaseRegNum,
2389                               const MCConstantExpr *OffsetImm,
2390                               unsigned OffsetRegNum,
2391                               ARM_AM::ShiftOpc ShiftType,
2392                               unsigned ShiftImm,
2393                               unsigned Alignment,
2394                               bool isNegative,
2395                               SMLoc S, SMLoc E) {
2396    ARMOperand *Op = new ARMOperand(k_Memory);
2397    Op->Memory.BaseRegNum = BaseRegNum;
2398    Op->Memory.OffsetImm = OffsetImm;
2399    Op->Memory.OffsetRegNum = OffsetRegNum;
2400    Op->Memory.ShiftType = ShiftType;
2401    Op->Memory.ShiftImm = ShiftImm;
2402    Op->Memory.Alignment = Alignment;
2403    Op->Memory.isNegative = isNegative;
2404    Op->StartLoc = S;
2405    Op->EndLoc = E;
2406    return Op;
2407  }
2408
2409  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2410                                      ARM_AM::ShiftOpc ShiftTy,
2411                                      unsigned ShiftImm,
2412                                      SMLoc S, SMLoc E) {
2413    ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2414    Op->PostIdxReg.RegNum = RegNum;
2415    Op->PostIdxReg.isAdd = isAdd;
2416    Op->PostIdxReg.ShiftTy = ShiftTy;
2417    Op->PostIdxReg.ShiftImm = ShiftImm;
2418    Op->StartLoc = S;
2419    Op->EndLoc = E;
2420    return Op;
2421  }
2422
2423  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2424    ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2425    Op->MBOpt.Val = Opt;
2426    Op->StartLoc = S;
2427    Op->EndLoc = S;
2428    return Op;
2429  }
2430
2431  static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2432                                              SMLoc S) {
2433    ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2434    Op->ISBOpt.Val = Opt;
2435    Op->StartLoc = S;
2436    Op->EndLoc = S;
2437    return Op;
2438  }
2439
2440  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2441    ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2442    Op->IFlags.Val = IFlags;
2443    Op->StartLoc = S;
2444    Op->EndLoc = S;
2445    return Op;
2446  }
2447
2448  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2449    ARMOperand *Op = new ARMOperand(k_MSRMask);
2450    Op->MMask.Val = MMask;
2451    Op->StartLoc = S;
2452    Op->EndLoc = S;
2453    return Op;
2454  }
2455};
2456
2457} // end anonymous namespace.
2458
2459void ARMOperand::print(raw_ostream &OS) const {
2460  switch (Kind) {
2461  case k_CondCode:
2462    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2463    break;
2464  case k_CCOut:
2465    OS << "<ccout " << getReg() << ">";
2466    break;
2467  case k_ITCondMask: {
2468    static const char *const MaskStr[] = {
2469      "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2470      "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2471    };
2472    assert((ITMask.Mask & 0xf) == ITMask.Mask);
2473    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2474    break;
2475  }
2476  case k_CoprocNum:
2477    OS << "<coprocessor number: " << getCoproc() << ">";
2478    break;
2479  case k_CoprocReg:
2480    OS << "<coprocessor register: " << getCoproc() << ">";
2481    break;
2482  case k_CoprocOption:
2483    OS << "<coprocessor option: " << CoprocOption.Val << ">";
2484    break;
2485  case k_MSRMask:
2486    OS << "<mask: " << getMSRMask() << ">";
2487    break;
2488  case k_Immediate:
2489    getImm()->print(OS);
2490    break;
2491  case k_MemBarrierOpt:
2492    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2493    break;
2494  case k_InstSyncBarrierOpt:
2495    OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2496    break;
2497  case k_Memory:
2498    OS << "<memory "
2499       << " base:" << Memory.BaseRegNum;
2500    OS << ">";
2501    break;
2502  case k_PostIndexRegister:
2503    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2504       << PostIdxReg.RegNum;
2505    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2506      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2507         << PostIdxReg.ShiftImm;
2508    OS << ">";
2509    break;
2510  case k_ProcIFlags: {
2511    OS << "<ARM_PROC::";
2512    unsigned IFlags = getProcIFlags();
2513    for (int i=2; i >= 0; --i)
2514      if (IFlags & (1 << i))
2515        OS << ARM_PROC::IFlagsToString(1 << i);
2516    OS << ">";
2517    break;
2518  }
2519  case k_Register:
2520    OS << "<register " << getReg() << ">";
2521    break;
2522  case k_ShifterImmediate:
2523    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2524       << " #" << ShifterImm.Imm << ">";
2525    break;
2526  case k_ShiftedRegister:
2527    OS << "<so_reg_reg "
2528       << RegShiftedReg.SrcReg << " "
2529       << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2530       << " " << RegShiftedReg.ShiftReg << ">";
2531    break;
2532  case k_ShiftedImmediate:
2533    OS << "<so_reg_imm "
2534       << RegShiftedImm.SrcReg << " "
2535       << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2536       << " #" << RegShiftedImm.ShiftImm << ">";
2537    break;
2538  case k_RotateImmediate:
2539    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2540    break;
2541  case k_BitfieldDescriptor:
2542    OS << "<bitfield " << "lsb: " << Bitfield.LSB
2543       << ", width: " << Bitfield.Width << ">";
2544    break;
2545  case k_RegisterList:
2546  case k_DPRRegisterList:
2547  case k_SPRRegisterList: {
2548    OS << "<register_list ";
2549
2550    const SmallVectorImpl<unsigned> &RegList = getRegList();
2551    for (SmallVectorImpl<unsigned>::const_iterator
2552           I = RegList.begin(), E = RegList.end(); I != E; ) {
2553      OS << *I;
2554      if (++I < E) OS << ", ";
2555    }
2556
2557    OS << ">";
2558    break;
2559  }
2560  case k_VectorList:
2561    OS << "<vector_list " << VectorList.Count << " * "
2562       << VectorList.RegNum << ">";
2563    break;
2564  case k_VectorListAllLanes:
2565    OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2566       << VectorList.RegNum << ">";
2567    break;
2568  case k_VectorListIndexed:
2569    OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2570       << VectorList.Count << " * " << VectorList.RegNum << ">";
2571    break;
2572  case k_Token:
2573    OS << "'" << getToken() << "'";
2574    break;
2575  case k_VectorIndex:
2576    OS << "<vectorindex " << getVectorIndex() << ">";
2577    break;
2578  }
2579}
2580
2581/// @name Auto-generated Match Functions
2582/// {
2583
2584static unsigned MatchRegisterName(StringRef Name);
2585
2586/// }
2587
2588bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2589                                 SMLoc &StartLoc, SMLoc &EndLoc) {
2590  StartLoc = Parser.getTok().getLoc();
2591  EndLoc = Parser.getTok().getEndLoc();
2592  RegNo = tryParseRegister();
2593
2594  return (RegNo == (unsigned)-1);
2595}
2596
2597/// Try to parse a register name.  The token must be an Identifier when called,
2598/// and if it is a register name the token is eaten and the register number is
2599/// returned.  Otherwise return -1.
2600///
2601int ARMAsmParser::tryParseRegister() {
2602  const AsmToken &Tok = Parser.getTok();
2603  if (Tok.isNot(AsmToken::Identifier)) return -1;
2604
2605  std::string lowerCase = Tok.getString().lower();
2606  unsigned RegNum = MatchRegisterName(lowerCase);
2607  if (!RegNum) {
2608    RegNum = StringSwitch<unsigned>(lowerCase)
2609      .Case("r13", ARM::SP)
2610      .Case("r14", ARM::LR)
2611      .Case("r15", ARM::PC)
2612      .Case("ip", ARM::R12)
2613      // Additional register name aliases for 'gas' compatibility.
2614      .Case("a1", ARM::R0)
2615      .Case("a2", ARM::R1)
2616      .Case("a3", ARM::R2)
2617      .Case("a4", ARM::R3)
2618      .Case("v1", ARM::R4)
2619      .Case("v2", ARM::R5)
2620      .Case("v3", ARM::R6)
2621      .Case("v4", ARM::R7)
2622      .Case("v5", ARM::R8)
2623      .Case("v6", ARM::R9)
2624      .Case("v7", ARM::R10)
2625      .Case("v8", ARM::R11)
2626      .Case("sb", ARM::R9)
2627      .Case("sl", ARM::R10)
2628      .Case("fp", ARM::R11)
2629      .Default(0);
2630  }
2631  if (!RegNum) {
2632    // Check for aliases registered via .req. Canonicalize to lower case.
2633    // That's more consistent since register names are case insensitive, and
2634    // it's how the original entry was passed in from MC/MCParser/AsmParser.
2635    StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2636    // If no match, return failure.
2637    if (Entry == RegisterReqs.end())
2638      return -1;
2639    Parser.Lex(); // Eat identifier token.
2640    return Entry->getValue();
2641  }
2642
2643  Parser.Lex(); // Eat identifier token.
2644
2645  return RegNum;
2646}
2647
2648// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2649// If a recoverable error occurs, return 1. If an irrecoverable error
2650// occurs, return -1. An irrecoverable error is one where tokens have been
2651// consumed in the process of trying to parse the shifter (i.e., when it is
2652// indeed a shifter operand, but malformed).
2653int ARMAsmParser::tryParseShiftRegister(
2654                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2655  SMLoc S = Parser.getTok().getLoc();
2656  const AsmToken &Tok = Parser.getTok();
2657  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2658
2659  std::string lowerCase = Tok.getString().lower();
2660  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2661      .Case("asl", ARM_AM::lsl)
2662      .Case("lsl", ARM_AM::lsl)
2663      .Case("lsr", ARM_AM::lsr)
2664      .Case("asr", ARM_AM::asr)
2665      .Case("ror", ARM_AM::ror)
2666      .Case("rrx", ARM_AM::rrx)
2667      .Default(ARM_AM::no_shift);
2668
2669  if (ShiftTy == ARM_AM::no_shift)
2670    return 1;
2671
2672  Parser.Lex(); // Eat the operator.
2673
2674  // The source register for the shift has already been added to the
2675  // operand list, so we need to pop it off and combine it into the shifted
2676  // register operand instead.
2677  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2678  if (!PrevOp->isReg())
2679    return Error(PrevOp->getStartLoc(), "shift must be of a register");
2680  int SrcReg = PrevOp->getReg();
2681
2682  SMLoc EndLoc;
2683  int64_t Imm = 0;
2684  int ShiftReg = 0;
2685  if (ShiftTy == ARM_AM::rrx) {
2686    // RRX Doesn't have an explicit shift amount. The encoder expects
2687    // the shift register to be the same as the source register. Seems odd,
2688    // but OK.
2689    ShiftReg = SrcReg;
2690  } else {
2691    // Figure out if this is shifted by a constant or a register (for non-RRX).
2692    if (Parser.getTok().is(AsmToken::Hash) ||
2693        Parser.getTok().is(AsmToken::Dollar)) {
2694      Parser.Lex(); // Eat hash.
2695      SMLoc ImmLoc = Parser.getTok().getLoc();
2696      const MCExpr *ShiftExpr = 0;
2697      if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2698        Error(ImmLoc, "invalid immediate shift value");
2699        return -1;
2700      }
2701      // The expression must be evaluatable as an immediate.
2702      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2703      if (!CE) {
2704        Error(ImmLoc, "invalid immediate shift value");
2705        return -1;
2706      }
2707      // Range check the immediate.
2708      // lsl, ror: 0 <= imm <= 31
2709      // lsr, asr: 0 <= imm <= 32
2710      Imm = CE->getValue();
2711      if (Imm < 0 ||
2712          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2713          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2714        Error(ImmLoc, "immediate shift value out of range");
2715        return -1;
2716      }
2717      // shift by zero is a nop. Always send it through as lsl.
2718      // ('as' compatibility)
2719      if (Imm == 0)
2720        ShiftTy = ARM_AM::lsl;
2721    } else if (Parser.getTok().is(AsmToken::Identifier)) {
2722      SMLoc L = Parser.getTok().getLoc();
2723      EndLoc = Parser.getTok().getEndLoc();
2724      ShiftReg = tryParseRegister();
2725      if (ShiftReg == -1) {
2726        Error (L, "expected immediate or register in shift operand");
2727        return -1;
2728      }
2729    } else {
2730      Error (Parser.getTok().getLoc(),
2731                    "expected immediate or register in shift operand");
2732      return -1;
2733    }
2734  }
2735
2736  if (ShiftReg && ShiftTy != ARM_AM::rrx)
2737    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2738                                                         ShiftReg, Imm,
2739                                                         S, EndLoc));
2740  else
2741    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2742                                                          S, EndLoc));
2743
2744  return 0;
2745}
2746
2747
2748/// Try to parse a register name.  The token must be an Identifier when called.
2749/// If it's a register, an AsmOperand is created. Another AsmOperand is created
2750/// if there is a "writeback". 'true' if it's not a register.
2751///
2752/// TODO this is likely to change to allow different register types and or to
2753/// parse for a specific register type.
2754bool ARMAsmParser::
2755tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2756  const AsmToken &RegTok = Parser.getTok();
2757  int RegNo = tryParseRegister();
2758  if (RegNo == -1)
2759    return true;
2760
2761  Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2762                                           RegTok.getEndLoc()));
2763
2764  const AsmToken &ExclaimTok = Parser.getTok();
2765  if (ExclaimTok.is(AsmToken::Exclaim)) {
2766    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2767                                               ExclaimTok.getLoc()));
2768    Parser.Lex(); // Eat exclaim token
2769    return false;
2770  }
2771
2772  // Also check for an index operand. This is only legal for vector registers,
2773  // but that'll get caught OK in operand matching, so we don't need to
2774  // explicitly filter everything else out here.
2775  if (Parser.getTok().is(AsmToken::LBrac)) {
2776    SMLoc SIdx = Parser.getTok().getLoc();
2777    Parser.Lex(); // Eat left bracket token.
2778
2779    const MCExpr *ImmVal;
2780    if (getParser().parseExpression(ImmVal))
2781      return true;
2782    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2783    if (!MCE)
2784      return TokError("immediate value expected for vector index");
2785
2786    if (Parser.getTok().isNot(AsmToken::RBrac))
2787      return Error(Parser.getTok().getLoc(), "']' expected");
2788
2789    SMLoc E = Parser.getTok().getEndLoc();
2790    Parser.Lex(); // Eat right bracket token.
2791
2792    Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2793                                                     SIdx, E,
2794                                                     getContext()));
2795  }
2796
2797  return false;
2798}
2799
2800/// MatchCoprocessorOperandName - Try to parse an coprocessor related
2801/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2802/// "c5", ...
2803static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2804  // Use the same layout as the tablegen'erated register name matcher. Ugly,
2805  // but efficient.
2806  switch (Name.size()) {
2807  default: return -1;
2808  case 2:
2809    if (Name[0] != CoprocOp)
2810      return -1;
2811    switch (Name[1]) {
2812    default:  return -1;
2813    case '0': return 0;
2814    case '1': return 1;
2815    case '2': return 2;
2816    case '3': return 3;
2817    case '4': return 4;
2818    case '5': return 5;
2819    case '6': return 6;
2820    case '7': return 7;
2821    case '8': return 8;
2822    case '9': return 9;
2823    }
2824  case 3:
2825    if (Name[0] != CoprocOp || Name[1] != '1')
2826      return -1;
2827    switch (Name[2]) {
2828    default:  return -1;
2829    case '0': return 10;
2830    case '1': return 11;
2831    case '2': return 12;
2832    case '3': return 13;
2833    case '4': return 14;
2834    case '5': return 15;
2835    }
2836  }
2837}
2838
2839/// parseITCondCode - Try to parse a condition code for an IT instruction.
2840ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2841parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2842  SMLoc S = Parser.getTok().getLoc();
2843  const AsmToken &Tok = Parser.getTok();
2844  if (!Tok.is(AsmToken::Identifier))
2845    return MatchOperand_NoMatch;
2846  unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2847    .Case("eq", ARMCC::EQ)
2848    .Case("ne", ARMCC::NE)
2849    .Case("hs", ARMCC::HS)
2850    .Case("cs", ARMCC::HS)
2851    .Case("lo", ARMCC::LO)
2852    .Case("cc", ARMCC::LO)
2853    .Case("mi", ARMCC::MI)
2854    .Case("pl", ARMCC::PL)
2855    .Case("vs", ARMCC::VS)
2856    .Case("vc", ARMCC::VC)
2857    .Case("hi", ARMCC::HI)
2858    .Case("ls", ARMCC::LS)
2859    .Case("ge", ARMCC::GE)
2860    .Case("lt", ARMCC::LT)
2861    .Case("gt", ARMCC::GT)
2862    .Case("le", ARMCC::LE)
2863    .Case("al", ARMCC::AL)
2864    .Default(~0U);
2865  if (CC == ~0U)
2866    return MatchOperand_NoMatch;
2867  Parser.Lex(); // Eat the token.
2868
2869  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2870
2871  return MatchOperand_Success;
2872}
2873
2874/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2875/// token must be an Identifier when called, and if it is a coprocessor
2876/// number, the token is eaten and the operand is added to the operand list.
2877ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2878parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2879  SMLoc S = Parser.getTok().getLoc();
2880  const AsmToken &Tok = Parser.getTok();
2881  if (Tok.isNot(AsmToken::Identifier))
2882    return MatchOperand_NoMatch;
2883
2884  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2885  if (Num == -1)
2886    return MatchOperand_NoMatch;
2887
2888  Parser.Lex(); // Eat identifier token.
2889  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2890  return MatchOperand_Success;
2891}
2892
2893/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2894/// token must be an Identifier when called, and if it is a coprocessor
2895/// number, the token is eaten and the operand is added to the operand list.
2896ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2897parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2898  SMLoc S = Parser.getTok().getLoc();
2899  const AsmToken &Tok = Parser.getTok();
2900  if (Tok.isNot(AsmToken::Identifier))
2901    return MatchOperand_NoMatch;
2902
2903  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2904  if (Reg == -1)
2905    return MatchOperand_NoMatch;
2906
2907  Parser.Lex(); // Eat identifier token.
2908  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2909  return MatchOperand_Success;
2910}
2911
2912/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2913/// coproc_option : '{' imm0_255 '}'
2914ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2915parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2916  SMLoc S = Parser.getTok().getLoc();
2917
2918  // If this isn't a '{', this isn't a coprocessor immediate operand.
2919  if (Parser.getTok().isNot(AsmToken::LCurly))
2920    return MatchOperand_NoMatch;
2921  Parser.Lex(); // Eat the '{'
2922
2923  const MCExpr *Expr;
2924  SMLoc Loc = Parser.getTok().getLoc();
2925  if (getParser().parseExpression(Expr)) {
2926    Error(Loc, "illegal expression");
2927    return MatchOperand_ParseFail;
2928  }
2929  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2930  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2931    Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2932    return MatchOperand_ParseFail;
2933  }
2934  int Val = CE->getValue();
2935
2936  // Check for and consume the closing '}'
2937  if (Parser.getTok().isNot(AsmToken::RCurly))
2938    return MatchOperand_ParseFail;
2939  SMLoc E = Parser.getTok().getEndLoc();
2940  Parser.Lex(); // Eat the '}'
2941
2942  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2943  return MatchOperand_Success;
2944}
2945
2946// For register list parsing, we need to map from raw GPR register numbering
2947// to the enumeration values. The enumeration values aren't sorted by
2948// register number due to our using "sp", "lr" and "pc" as canonical names.
2949static unsigned getNextRegister(unsigned Reg) {
2950  // If this is a GPR, we need to do it manually, otherwise we can rely
2951  // on the sort ordering of the enumeration since the other reg-classes
2952  // are sane.
2953  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2954    return Reg + 1;
2955  switch(Reg) {
2956  default: llvm_unreachable("Invalid GPR number!");
2957  case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
2958  case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
2959  case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
2960  case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
2961  case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
2962  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2963  case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
2964  case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
2965  }
2966}
2967
2968// Return the low-subreg of a given Q register.
2969static unsigned getDRegFromQReg(unsigned QReg) {
2970  switch (QReg) {
2971  default: llvm_unreachable("expected a Q register!");
2972  case ARM::Q0:  return ARM::D0;
2973  case ARM::Q1:  return ARM::D2;
2974  case ARM::Q2:  return ARM::D4;
2975  case ARM::Q3:  return ARM::D6;
2976  case ARM::Q4:  return ARM::D8;
2977  case ARM::Q5:  return ARM::D10;
2978  case ARM::Q6:  return ARM::D12;
2979  case ARM::Q7:  return ARM::D14;
2980  case ARM::Q8:  return ARM::D16;
2981  case ARM::Q9:  return ARM::D18;
2982  case ARM::Q10: return ARM::D20;
2983  case ARM::Q11: return ARM::D22;
2984  case ARM::Q12: return ARM::D24;
2985  case ARM::Q13: return ARM::D26;
2986  case ARM::Q14: return ARM::D28;
2987  case ARM::Q15: return ARM::D30;
2988  }
2989}
2990
2991/// Parse a register list.
2992bool ARMAsmParser::
2993parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2994  assert(Parser.getTok().is(AsmToken::LCurly) &&
2995         "Token is not a Left Curly Brace");
2996  SMLoc S = Parser.getTok().getLoc();
2997  Parser.Lex(); // Eat '{' token.
2998  SMLoc RegLoc = Parser.getTok().getLoc();
2999
3000  // Check the first register in the list to see what register class
3001  // this is a list of.
3002  int Reg = tryParseRegister();
3003  if (Reg == -1)
3004    return Error(RegLoc, "register expected");
3005
3006  // The reglist instructions have at most 16 registers, so reserve
3007  // space for that many.
3008  int EReg = 0;
3009  SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3010
3011  // Allow Q regs and just interpret them as the two D sub-registers.
3012  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3013    Reg = getDRegFromQReg(Reg);
3014    EReg = MRI->getEncodingValue(Reg);
3015    Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3016    ++Reg;
3017  }
3018  const MCRegisterClass *RC;
3019  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3020    RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3021  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3022    RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3023  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3024    RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3025  else
3026    return Error(RegLoc, "invalid register in register list");
3027
3028  // Store the register.
3029  EReg = MRI->getEncodingValue(Reg);
3030  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3031
3032  // This starts immediately after the first register token in the list,
3033  // so we can see either a comma or a minus (range separator) as a legal
3034  // next token.
3035  while (Parser.getTok().is(AsmToken::Comma) ||
3036         Parser.getTok().is(AsmToken::Minus)) {
3037    if (Parser.getTok().is(AsmToken::Minus)) {
3038      Parser.Lex(); // Eat the minus.
3039      SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3040      int EndReg = tryParseRegister();
3041      if (EndReg == -1)
3042        return Error(AfterMinusLoc, "register expected");
3043      // Allow Q regs and just interpret them as the two D sub-registers.
3044      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3045        EndReg = getDRegFromQReg(EndReg) + 1;
3046      // If the register is the same as the start reg, there's nothing
3047      // more to do.
3048      if (Reg == EndReg)
3049        continue;
3050      // The register must be in the same register class as the first.
3051      if (!RC->contains(EndReg))
3052        return Error(AfterMinusLoc, "invalid register in register list");
3053      // Ranges must go from low to high.
3054      if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3055        return Error(AfterMinusLoc, "bad range in register list");
3056
3057      // Add all the registers in the range to the register list.
3058      while (Reg != EndReg) {
3059        Reg = getNextRegister(Reg);
3060        EReg = MRI->getEncodingValue(Reg);
3061        Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3062      }
3063      continue;
3064    }
3065    Parser.Lex(); // Eat the comma.
3066    RegLoc = Parser.getTok().getLoc();
3067    int OldReg = Reg;
3068    const AsmToken RegTok = Parser.getTok();
3069    Reg = tryParseRegister();
3070    if (Reg == -1)
3071      return Error(RegLoc, "register expected");
3072    // Allow Q regs and just interpret them as the two D sub-registers.
3073    bool isQReg = false;
3074    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3075      Reg = getDRegFromQReg(Reg);
3076      isQReg = true;
3077    }
3078    // The register must be in the same register class as the first.
3079    if (!RC->contains(Reg))
3080      return Error(RegLoc, "invalid register in register list");
3081    // List must be monotonically increasing.
3082    if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3083      if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3084        Warning(RegLoc, "register list not in ascending order");
3085      else
3086        return Error(RegLoc, "register list not in ascending order");
3087    }
3088    if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3089      Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3090              ") in register list");
3091      continue;
3092    }
3093    // VFP register lists must also be contiguous.
3094    if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3095        Reg != OldReg + 1)
3096      return Error(RegLoc, "non-contiguous register range");
3097    EReg = MRI->getEncodingValue(Reg);
3098    Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3099    if (isQReg) {
3100      EReg = MRI->getEncodingValue(++Reg);
3101      Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3102    }
3103  }
3104
3105  if (Parser.getTok().isNot(AsmToken::RCurly))
3106    return Error(Parser.getTok().getLoc(), "'}' expected");
3107  SMLoc E = Parser.getTok().getEndLoc();
3108  Parser.Lex(); // Eat '}' token.
3109
3110  // Push the register list operand.
3111  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3112
3113  // The ARM system instruction variants for LDM/STM have a '^' token here.
3114  if (Parser.getTok().is(AsmToken::Caret)) {
3115    Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3116    Parser.Lex(); // Eat '^' token.
3117  }
3118
3119  return false;
3120}
3121
3122// Helper function to parse the lane index for vector lists.
3123ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3124parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3125  Index = 0; // Always return a defined index value.
3126  if (Parser.getTok().is(AsmToken::LBrac)) {
3127    Parser.Lex(); // Eat the '['.
3128    if (Parser.getTok().is(AsmToken::RBrac)) {
3129      // "Dn[]" is the 'all lanes' syntax.
3130      LaneKind = AllLanes;
3131      EndLoc = Parser.getTok().getEndLoc();
3132      Parser.Lex(); // Eat the ']'.
3133      return MatchOperand_Success;
3134    }
3135
3136    // There's an optional '#' token here. Normally there wouldn't be, but
3137    // inline assemble puts one in, and it's friendly to accept that.
3138    if (Parser.getTok().is(AsmToken::Hash))
3139      Parser.Lex(); // Eat '#' or '$'.
3140
3141    const MCExpr *LaneIndex;
3142    SMLoc Loc = Parser.getTok().getLoc();
3143    if (getParser().parseExpression(LaneIndex)) {
3144      Error(Loc, "illegal expression");
3145      return MatchOperand_ParseFail;
3146    }
3147    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3148    if (!CE) {
3149      Error(Loc, "lane index must be empty or an integer");
3150      return MatchOperand_ParseFail;
3151    }
3152    if (Parser.getTok().isNot(AsmToken::RBrac)) {
3153      Error(Parser.getTok().getLoc(), "']' expected");
3154      return MatchOperand_ParseFail;
3155    }
3156    EndLoc = Parser.getTok().getEndLoc();
3157    Parser.Lex(); // Eat the ']'.
3158    int64_t Val = CE->getValue();
3159
3160    // FIXME: Make this range check context sensitive for .8, .16, .32.
3161    if (Val < 0 || Val > 7) {
3162      Error(Parser.getTok().getLoc(), "lane index out of range");
3163      return MatchOperand_ParseFail;
3164    }
3165    Index = Val;
3166    LaneKind = IndexedLane;
3167    return MatchOperand_Success;
3168  }
3169  LaneKind = NoLanes;
3170  return MatchOperand_Success;
3171}
3172
3173// parse a vector register list
3174ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3175parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3176  VectorLaneTy LaneKind;
3177  unsigned LaneIndex;
3178  SMLoc S = Parser.getTok().getLoc();
3179  // As an extension (to match gas), support a plain D register or Q register
3180  // (without encosing curly braces) as a single or double entry list,
3181  // respectively.
3182  if (Parser.getTok().is(AsmToken::Identifier)) {
3183    SMLoc E = Parser.getTok().getEndLoc();
3184    int Reg = tryParseRegister();
3185    if (Reg == -1)
3186      return MatchOperand_NoMatch;
3187    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3188      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3189      if (Res != MatchOperand_Success)
3190        return Res;
3191      switch (LaneKind) {
3192      case NoLanes:
3193        Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3194        break;
3195      case AllLanes:
3196        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3197                                                                S, E));
3198        break;
3199      case IndexedLane:
3200        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3201                                                               LaneIndex,
3202                                                               false, S, E));
3203        break;
3204      }
3205      return MatchOperand_Success;
3206    }
3207    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3208      Reg = getDRegFromQReg(Reg);
3209      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3210      if (Res != MatchOperand_Success)
3211        return Res;
3212      switch (LaneKind) {
3213      case NoLanes:
3214        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3215                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3216        Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3217        break;
3218      case AllLanes:
3219        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3220                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3221        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3222                                                                S, E));
3223        break;
3224      case IndexedLane:
3225        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3226                                                               LaneIndex,
3227                                                               false, S, E));
3228        break;
3229      }
3230      return MatchOperand_Success;
3231    }
3232    Error(S, "vector register expected");
3233    return MatchOperand_ParseFail;
3234  }
3235
3236  if (Parser.getTok().isNot(AsmToken::LCurly))
3237    return MatchOperand_NoMatch;
3238
3239  Parser.Lex(); // Eat '{' token.
3240  SMLoc RegLoc = Parser.getTok().getLoc();
3241
3242  int Reg = tryParseRegister();
3243  if (Reg == -1) {
3244    Error(RegLoc, "register expected");
3245    return MatchOperand_ParseFail;
3246  }
3247  unsigned Count = 1;
3248  int Spacing = 0;
3249  unsigned FirstReg = Reg;
3250  // The list is of D registers, but we also allow Q regs and just interpret
3251  // them as the two D sub-registers.
3252  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3253    FirstReg = Reg = getDRegFromQReg(Reg);
3254    Spacing = 1; // double-spacing requires explicit D registers, otherwise
3255                 // it's ambiguous with four-register single spaced.
3256    ++Reg;
3257    ++Count;
3258  }
3259
3260  SMLoc E;
3261  if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3262    return MatchOperand_ParseFail;
3263
3264  while (Parser.getTok().is(AsmToken::Comma) ||
3265         Parser.getTok().is(AsmToken::Minus)) {
3266    if (Parser.getTok().is(AsmToken::Minus)) {
3267      if (!Spacing)
3268        Spacing = 1; // Register range implies a single spaced list.
3269      else if (Spacing == 2) {
3270        Error(Parser.getTok().getLoc(),
3271              "sequential registers in double spaced list");
3272        return MatchOperand_ParseFail;
3273      }
3274      Parser.Lex(); // Eat the minus.
3275      SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3276      int EndReg = tryParseRegister();
3277      if (EndReg == -1) {
3278        Error(AfterMinusLoc, "register expected");
3279        return MatchOperand_ParseFail;
3280      }
3281      // Allow Q regs and just interpret them as the two D sub-registers.
3282      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3283        EndReg = getDRegFromQReg(EndReg) + 1;
3284      // If the register is the same as the start reg, there's nothing
3285      // more to do.
3286      if (Reg == EndReg)
3287        continue;
3288      // The register must be in the same register class as the first.
3289      if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3290        Error(AfterMinusLoc, "invalid register in register list");
3291        return MatchOperand_ParseFail;
3292      }
3293      // Ranges must go from low to high.
3294      if (Reg > EndReg) {
3295        Error(AfterMinusLoc, "bad range in register list");
3296        return MatchOperand_ParseFail;
3297      }
3298      // Parse the lane specifier if present.
3299      VectorLaneTy NextLaneKind;
3300      unsigned NextLaneIndex;
3301      if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3302          MatchOperand_Success)
3303        return MatchOperand_ParseFail;
3304      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3305        Error(AfterMinusLoc, "mismatched lane index in register list");
3306        return MatchOperand_ParseFail;
3307      }
3308
3309      // Add all the registers in the range to the register list.
3310      Count += EndReg - Reg;
3311      Reg = EndReg;
3312      continue;
3313    }
3314    Parser.Lex(); // Eat the comma.
3315    RegLoc = Parser.getTok().getLoc();
3316    int OldReg = Reg;
3317    Reg = tryParseRegister();
3318    if (Reg == -1) {
3319      Error(RegLoc, "register expected");
3320      return MatchOperand_ParseFail;
3321    }
3322    // vector register lists must be contiguous.
3323    // It's OK to use the enumeration values directly here rather, as the
3324    // VFP register classes have the enum sorted properly.
3325    //
3326    // The list is of D registers, but we also allow Q regs and just interpret
3327    // them as the two D sub-registers.
3328    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3329      if (!Spacing)
3330        Spacing = 1; // Register range implies a single spaced list.
3331      else if (Spacing == 2) {
3332        Error(RegLoc,
3333              "invalid register in double-spaced list (must be 'D' register')");
3334        return MatchOperand_ParseFail;
3335      }
3336      Reg = getDRegFromQReg(Reg);
3337      if (Reg != OldReg + 1) {
3338        Error(RegLoc, "non-contiguous register range");
3339        return MatchOperand_ParseFail;
3340      }
3341      ++Reg;
3342      Count += 2;
3343      // Parse the lane specifier if present.
3344      VectorLaneTy NextLaneKind;
3345      unsigned NextLaneIndex;
3346      SMLoc LaneLoc = Parser.getTok().getLoc();
3347      if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3348          MatchOperand_Success)
3349        return MatchOperand_ParseFail;
3350      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3351        Error(LaneLoc, "mismatched lane index in register list");
3352        return MatchOperand_ParseFail;
3353      }
3354      continue;
3355    }
3356    // Normal D register.
3357    // Figure out the register spacing (single or double) of the list if
3358    // we don't know it already.
3359    if (!Spacing)
3360      Spacing = 1 + (Reg == OldReg + 2);
3361
3362    // Just check that it's contiguous and keep going.
3363    if (Reg != OldReg + Spacing) {
3364      Error(RegLoc, "non-contiguous register range");
3365      return MatchOperand_ParseFail;
3366    }
3367    ++Count;
3368    // Parse the lane specifier if present.
3369    VectorLaneTy NextLaneKind;
3370    unsigned NextLaneIndex;
3371    SMLoc EndLoc = Parser.getTok().getLoc();
3372    if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3373      return MatchOperand_ParseFail;
3374    if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3375      Error(EndLoc, "mismatched lane index in register list");
3376      return MatchOperand_ParseFail;
3377    }
3378  }
3379
3380  if (Parser.getTok().isNot(AsmToken::RCurly)) {
3381    Error(Parser.getTok().getLoc(), "'}' expected");
3382    return MatchOperand_ParseFail;
3383  }
3384  E = Parser.getTok().getEndLoc();
3385  Parser.Lex(); // Eat '}' token.
3386
3387  switch (LaneKind) {
3388  case NoLanes:
3389    // Two-register operands have been converted to the
3390    // composite register classes.
3391    if (Count == 2) {
3392      const MCRegisterClass *RC = (Spacing == 1) ?
3393        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3394        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3395      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3396    }
3397
3398    Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3399                                                    (Spacing == 2), S, E));
3400    break;
3401  case AllLanes:
3402    // Two-register operands have been converted to the
3403    // composite register classes.
3404    if (Count == 2) {
3405      const MCRegisterClass *RC = (Spacing == 1) ?
3406        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3407        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3408      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3409    }
3410    Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3411                                                            (Spacing == 2),
3412                                                            S, E));
3413    break;
3414  case IndexedLane:
3415    Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3416                                                           LaneIndex,
3417                                                           (Spacing == 2),
3418                                                           S, E));
3419    break;
3420  }
3421  return MatchOperand_Success;
3422}
3423
3424/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3425ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3426parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3427  SMLoc S = Parser.getTok().getLoc();
3428  const AsmToken &Tok = Parser.getTok();
3429  unsigned Opt;
3430
3431  if (Tok.is(AsmToken::Identifier)) {
3432    StringRef OptStr = Tok.getString();
3433
3434    Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3435      .Case("sy",    ARM_MB::SY)
3436      .Case("st",    ARM_MB::ST)
3437      .Case("sh",    ARM_MB::ISH)
3438      .Case("ish",   ARM_MB::ISH)
3439      .Case("shst",  ARM_MB::ISHST)
3440      .Case("ishst", ARM_MB::ISHST)
3441      .Case("nsh",   ARM_MB::NSH)
3442      .Case("un",    ARM_MB::NSH)
3443      .Case("nshst", ARM_MB::NSHST)
3444      .Case("unst",  ARM_MB::NSHST)
3445      .Case("osh",   ARM_MB::OSH)
3446      .Case("oshst", ARM_MB::OSHST)
3447      .Default(~0U);
3448
3449    if (Opt == ~0U)
3450      return MatchOperand_NoMatch;
3451
3452    Parser.Lex(); // Eat identifier token.
3453  } else if (Tok.is(AsmToken::Hash) ||
3454             Tok.is(AsmToken::Dollar) ||
3455             Tok.is(AsmToken::Integer)) {
3456    if (Parser.getTok().isNot(AsmToken::Integer))
3457      Parser.Lex(); // Eat '#' or '$'.
3458    SMLoc Loc = Parser.getTok().getLoc();
3459
3460    const MCExpr *MemBarrierID;
3461    if (getParser().parseExpression(MemBarrierID)) {
3462      Error(Loc, "illegal expression");
3463      return MatchOperand_ParseFail;
3464    }
3465
3466    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3467    if (!CE) {
3468      Error(Loc, "constant expression expected");
3469      return MatchOperand_ParseFail;
3470    }
3471
3472    int Val = CE->getValue();
3473    if (Val & ~0xf) {
3474      Error(Loc, "immediate value out of range");
3475      return MatchOperand_ParseFail;
3476    }
3477
3478    Opt = ARM_MB::RESERVED_0 + Val;
3479  } else
3480    return MatchOperand_ParseFail;
3481
3482  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3483  return MatchOperand_Success;
3484}
3485
3486/// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3487ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3488parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3489  SMLoc S = Parser.getTok().getLoc();
3490  const AsmToken &Tok = Parser.getTok();
3491  unsigned Opt;
3492
3493  if (Tok.is(AsmToken::Identifier)) {
3494    StringRef OptStr = Tok.getString();
3495
3496    if (OptStr.lower() == "sy")
3497      Opt = ARM_ISB::SY;
3498    else
3499      return MatchOperand_NoMatch;
3500
3501    Parser.Lex(); // Eat identifier token.
3502  } else if (Tok.is(AsmToken::Hash) ||
3503             Tok.is(AsmToken::Dollar) ||
3504             Tok.is(AsmToken::Integer)) {
3505    if (Parser.getTok().isNot(AsmToken::Integer))
3506      Parser.Lex(); // Eat '#' or '$'.
3507    SMLoc Loc = Parser.getTok().getLoc();
3508
3509    const MCExpr *ISBarrierID;
3510    if (getParser().parseExpression(ISBarrierID)) {
3511      Error(Loc, "illegal expression");
3512      return MatchOperand_ParseFail;
3513    }
3514
3515    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3516    if (!CE) {
3517      Error(Loc, "constant expression expected");
3518      return MatchOperand_ParseFail;
3519    }
3520
3521    int Val = CE->getValue();
3522    if (Val & ~0xf) {
3523      Error(Loc, "immediate value out of range");
3524      return MatchOperand_ParseFail;
3525    }
3526
3527    Opt = ARM_ISB::RESERVED_0 + Val;
3528  } else
3529    return MatchOperand_ParseFail;
3530
3531  Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3532          (ARM_ISB::InstSyncBOpt)Opt, S));
3533  return MatchOperand_Success;
3534}
3535
3536
3537/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3538ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3539parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3540  SMLoc S = Parser.getTok().getLoc();
3541  const AsmToken &Tok = Parser.getTok();
3542  if (!Tok.is(AsmToken::Identifier))
3543    return MatchOperand_NoMatch;
3544  StringRef IFlagsStr = Tok.getString();
3545
3546  // An iflags string of "none" is interpreted to mean that none of the AIF
3547  // bits are set.  Not a terribly useful instruction, but a valid encoding.
3548  unsigned IFlags = 0;
3549  if (IFlagsStr != "none") {
3550        for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3551      unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3552        .Case("a", ARM_PROC::A)
3553        .Case("i", ARM_PROC::I)
3554        .Case("f", ARM_PROC::F)
3555        .Default(~0U);
3556
3557      // If some specific iflag is already set, it means that some letter is
3558      // present more than once, this is not acceptable.
3559      if (Flag == ~0U || (IFlags & Flag))
3560        return MatchOperand_NoMatch;
3561
3562      IFlags |= Flag;
3563    }
3564  }
3565
3566  Parser.Lex(); // Eat identifier token.
3567  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3568  return MatchOperand_Success;
3569}
3570
3571/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3572ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3573parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3574  SMLoc S = Parser.getTok().getLoc();
3575  const AsmToken &Tok = Parser.getTok();
3576  if (!Tok.is(AsmToken::Identifier))
3577    return MatchOperand_NoMatch;
3578  StringRef Mask = Tok.getString();
3579
3580  if (isMClass()) {
3581    // See ARMv6-M 10.1.1
3582    std::string Name = Mask.lower();
3583    unsigned FlagsVal = StringSwitch<unsigned>(Name)
3584      // Note: in the documentation:
3585      //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3586      //  for MSR APSR_nzcvq.
3587      // but we do make it an alias here.  This is so to get the "mask encoding"
3588      // bits correct on MSR APSR writes.
3589      //
3590      // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3591      // should really only be allowed when writing a special register.  Note
3592      // they get dropped in the MRS instruction reading a special register as
3593      // the SYSm field is only 8 bits.
3594      //
3595      // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3596      // includes the DSP extension but that is not checked.
3597      .Case("apsr", 0x800)
3598      .Case("apsr_nzcvq", 0x800)
3599      .Case("apsr_g", 0x400)
3600      .Case("apsr_nzcvqg", 0xc00)
3601      .Case("iapsr", 0x801)
3602      .Case("iapsr_nzcvq", 0x801)
3603      .Case("iapsr_g", 0x401)
3604      .Case("iapsr_nzcvqg", 0xc01)
3605      .Case("eapsr", 0x802)
3606      .Case("eapsr_nzcvq", 0x802)
3607      .Case("eapsr_g", 0x402)
3608      .Case("eapsr_nzcvqg", 0xc02)
3609      .Case("xpsr", 0x803)
3610      .Case("xpsr_nzcvq", 0x803)
3611      .Case("xpsr_g", 0x403)
3612      .Case("xpsr_nzcvqg", 0xc03)
3613      .Case("ipsr", 0x805)
3614      .Case("epsr", 0x806)
3615      .Case("iepsr", 0x807)
3616      .Case("msp", 0x808)
3617      .Case("psp", 0x809)
3618      .Case("primask", 0x810)
3619      .Case("basepri", 0x811)
3620      .Case("basepri_max", 0x812)
3621      .Case("faultmask", 0x813)
3622      .Case("control", 0x814)
3623      .Default(~0U);
3624
3625    if (FlagsVal == ~0U)
3626      return MatchOperand_NoMatch;
3627
3628    if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3629      // basepri, basepri_max and faultmask only valid for V7m.
3630      return MatchOperand_NoMatch;
3631
3632    Parser.Lex(); // Eat identifier token.
3633    Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3634    return MatchOperand_Success;
3635  }
3636
3637  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3638  size_t Start = 0, Next = Mask.find('_');
3639  StringRef Flags = "";
3640  std::string SpecReg = Mask.slice(Start, Next).lower();
3641  if (Next != StringRef::npos)
3642    Flags = Mask.slice(Next+1, Mask.size());
3643
3644  // FlagsVal contains the complete mask:
3645  // 3-0: Mask
3646  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3647  unsigned FlagsVal = 0;
3648
3649  if (SpecReg == "apsr") {
3650    FlagsVal = StringSwitch<unsigned>(Flags)
3651    .Case("nzcvq",  0x8) // same as CPSR_f
3652    .Case("g",      0x4) // same as CPSR_s
3653    .Case("nzcvqg", 0xc) // same as CPSR_fs
3654    .Default(~0U);
3655
3656    if (FlagsVal == ~0U) {
3657      if (!Flags.empty())
3658        return MatchOperand_NoMatch;
3659      else
3660        FlagsVal = 8; // No flag
3661    }
3662  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3663    // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3664    if (Flags == "all" || Flags == "")
3665      Flags = "fc";
3666    for (int i = 0, e = Flags.size(); i != e; ++i) {
3667      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3668      .Case("c", 1)
3669      .Case("x", 2)
3670      .Case("s", 4)
3671      .Case("f", 8)
3672      .Default(~0U);
3673
3674      // If some specific flag is already set, it means that some letter is
3675      // present more than once, this is not acceptable.
3676      if (FlagsVal == ~0U || (FlagsVal & Flag))
3677        return MatchOperand_NoMatch;
3678      FlagsVal |= Flag;
3679    }
3680  } else // No match for special register.
3681    return MatchOperand_NoMatch;
3682
3683  // Special register without flags is NOT equivalent to "fc" flags.
3684  // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
3685  // two lines would enable gas compatibility at the expense of breaking
3686  // round-tripping.
3687  //
3688  // if (!FlagsVal)
3689  //  FlagsVal = 0x9;
3690
3691  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3692  if (SpecReg == "spsr")
3693    FlagsVal |= 16;
3694
3695  Parser.Lex(); // Eat identifier token.
3696  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3697  return MatchOperand_Success;
3698}
3699
3700ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3701parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3702            int Low, int High) {
3703  const AsmToken &Tok = Parser.getTok();
3704  if (Tok.isNot(AsmToken::Identifier)) {
3705    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3706    return MatchOperand_ParseFail;
3707  }
3708  StringRef ShiftName = Tok.getString();
3709  std::string LowerOp = Op.lower();
3710  std::string UpperOp = Op.upper();
3711  if (ShiftName != LowerOp && ShiftName != UpperOp) {
3712    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3713    return MatchOperand_ParseFail;
3714  }
3715  Parser.Lex(); // Eat shift type token.
3716
3717  // There must be a '#' and a shift amount.
3718  if (Parser.getTok().isNot(AsmToken::Hash) &&
3719      Parser.getTok().isNot(AsmToken::Dollar)) {
3720    Error(Parser.getTok().getLoc(), "'#' expected");
3721    return MatchOperand_ParseFail;
3722  }
3723  Parser.Lex(); // Eat hash token.
3724
3725  const MCExpr *ShiftAmount;
3726  SMLoc Loc = Parser.getTok().getLoc();
3727  SMLoc EndLoc;
3728  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3729    Error(Loc, "illegal expression");
3730    return MatchOperand_ParseFail;
3731  }
3732  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3733  if (!CE) {
3734    Error(Loc, "constant expression expected");
3735    return MatchOperand_ParseFail;
3736  }
3737  int Val = CE->getValue();
3738  if (Val < Low || Val > High) {
3739    Error(Loc, "immediate value out of range");
3740    return MatchOperand_ParseFail;
3741  }
3742
3743  Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3744
3745  return MatchOperand_Success;
3746}
3747
3748ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3749parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3750  const AsmToken &Tok = Parser.getTok();
3751  SMLoc S = Tok.getLoc();
3752  if (Tok.isNot(AsmToken::Identifier)) {
3753    Error(S, "'be' or 'le' operand expected");
3754    return MatchOperand_ParseFail;
3755  }
3756  int Val = StringSwitch<int>(Tok.getString().lower())
3757    .Case("be", 1)
3758    .Case("le", 0)
3759    .Default(-1);
3760  Parser.Lex(); // Eat the token.
3761
3762  if (Val == -1) {
3763    Error(S, "'be' or 'le' operand expected");
3764    return MatchOperand_ParseFail;
3765  }
3766  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3767                                                                  getContext()),
3768                                           S, Tok.getEndLoc()));
3769  return MatchOperand_Success;
3770}
3771
3772/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3773/// instructions. Legal values are:
3774///     lsl #n  'n' in [0,31]
3775///     asr #n  'n' in [1,32]
3776///             n == 32 encoded as n == 0.
3777ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3778parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3779  const AsmToken &Tok = Parser.getTok();
3780  SMLoc S = Tok.getLoc();
3781  if (Tok.isNot(AsmToken::Identifier)) {
3782    Error(S, "shift operator 'asr' or 'lsl' expected");
3783    return MatchOperand_ParseFail;
3784  }
3785  StringRef ShiftName = Tok.getString();
3786  bool isASR;
3787  if (ShiftName == "lsl" || ShiftName == "LSL")
3788    isASR = false;
3789  else if (ShiftName == "asr" || ShiftName == "ASR")
3790    isASR = true;
3791  else {
3792    Error(S, "shift operator 'asr' or 'lsl' expected");
3793    return MatchOperand_ParseFail;
3794  }
3795  Parser.Lex(); // Eat the operator.
3796
3797  // A '#' and a shift amount.
3798  if (Parser.getTok().isNot(AsmToken::Hash) &&
3799      Parser.getTok().isNot(AsmToken::Dollar)) {
3800    Error(Parser.getTok().getLoc(), "'#' expected");
3801    return MatchOperand_ParseFail;
3802  }
3803  Parser.Lex(); // Eat hash token.
3804  SMLoc ExLoc = Parser.getTok().getLoc();
3805
3806  const MCExpr *ShiftAmount;
3807  SMLoc EndLoc;
3808  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3809    Error(ExLoc, "malformed shift expression");
3810    return MatchOperand_ParseFail;
3811  }
3812  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3813  if (!CE) {
3814    Error(ExLoc, "shift amount must be an immediate");
3815    return MatchOperand_ParseFail;
3816  }
3817
3818  int64_t Val = CE->getValue();
3819  if (isASR) {
3820    // Shift amount must be in [1,32]
3821    if (Val < 1 || Val > 32) {
3822      Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3823      return MatchOperand_ParseFail;
3824    }
3825    // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3826    if (isThumb() && Val == 32) {
3827      Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3828      return MatchOperand_ParseFail;
3829    }
3830    if (Val == 32) Val = 0;
3831  } else {
3832    // Shift amount must be in [1,32]
3833    if (Val < 0 || Val > 31) {
3834      Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3835      return MatchOperand_ParseFail;
3836    }
3837  }
3838
3839  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3840
3841  return MatchOperand_Success;
3842}
3843
3844/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3845/// of instructions. Legal values are:
3846///     ror #n  'n' in {0, 8, 16, 24}
3847ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3848parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3849  const AsmToken &Tok = Parser.getTok();
3850  SMLoc S = Tok.getLoc();
3851  if (Tok.isNot(AsmToken::Identifier))
3852    return MatchOperand_NoMatch;
3853  StringRef ShiftName = Tok.getString();
3854  if (ShiftName != "ror" && ShiftName != "ROR")
3855    return MatchOperand_NoMatch;
3856  Parser.Lex(); // Eat the operator.
3857
3858  // A '#' and a rotate amount.
3859  if (Parser.getTok().isNot(AsmToken::Hash) &&
3860      Parser.getTok().isNot(AsmToken::Dollar)) {
3861    Error(Parser.getTok().getLoc(), "'#' expected");
3862    return MatchOperand_ParseFail;
3863  }
3864  Parser.Lex(); // Eat hash token.
3865  SMLoc ExLoc = Parser.getTok().getLoc();
3866
3867  const MCExpr *ShiftAmount;
3868  SMLoc EndLoc;
3869  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3870    Error(ExLoc, "malformed rotate expression");
3871    return MatchOperand_ParseFail;
3872  }
3873  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3874  if (!CE) {
3875    Error(ExLoc, "rotate amount must be an immediate");
3876    return MatchOperand_ParseFail;
3877  }
3878
3879  int64_t Val = CE->getValue();
3880  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3881  // normally, zero is represented in asm by omitting the rotate operand
3882  // entirely.
3883  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3884    Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
3885    return MatchOperand_ParseFail;
3886  }
3887
3888  Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
3889
3890  return MatchOperand_Success;
3891}
3892
3893ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3894parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3895  SMLoc S = Parser.getTok().getLoc();
3896  // The bitfield descriptor is really two operands, the LSB and the width.
3897  if (Parser.getTok().isNot(AsmToken::Hash) &&
3898      Parser.getTok().isNot(AsmToken::Dollar)) {
3899    Error(Parser.getTok().getLoc(), "'#' expected");
3900    return MatchOperand_ParseFail;
3901  }
3902  Parser.Lex(); // Eat hash token.
3903
3904  const MCExpr *LSBExpr;
3905  SMLoc E = Parser.getTok().getLoc();
3906  if (getParser().parseExpression(LSBExpr)) {
3907    Error(E, "malformed immediate expression");
3908    return MatchOperand_ParseFail;
3909  }
3910  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3911  if (!CE) {
3912    Error(E, "'lsb' operand must be an immediate");
3913    return MatchOperand_ParseFail;
3914  }
3915
3916  int64_t LSB = CE->getValue();
3917  // The LSB must be in the range [0,31]
3918  if (LSB < 0 || LSB > 31) {
3919    Error(E, "'lsb' operand must be in the range [0,31]");
3920    return MatchOperand_ParseFail;
3921  }
3922  E = Parser.getTok().getLoc();
3923
3924  // Expect another immediate operand.
3925  if (Parser.getTok().isNot(AsmToken::Comma)) {
3926    Error(Parser.getTok().getLoc(), "too few operands");
3927    return MatchOperand_ParseFail;
3928  }
3929  Parser.Lex(); // Eat hash token.
3930  if (Parser.getTok().isNot(AsmToken::Hash) &&
3931      Parser.getTok().isNot(AsmToken::Dollar)) {
3932    Error(Parser.getTok().getLoc(), "'#' expected");
3933    return MatchOperand_ParseFail;
3934  }
3935  Parser.Lex(); // Eat hash token.
3936
3937  const MCExpr *WidthExpr;
3938  SMLoc EndLoc;
3939  if (getParser().parseExpression(WidthExpr, EndLoc)) {
3940    Error(E, "malformed immediate expression");
3941    return MatchOperand_ParseFail;
3942  }
3943  CE = dyn_cast<MCConstantExpr>(WidthExpr);
3944  if (!CE) {
3945    Error(E, "'width' operand must be an immediate");
3946    return MatchOperand_ParseFail;
3947  }
3948
3949  int64_t Width = CE->getValue();
3950  // The LSB must be in the range [1,32-lsb]
3951  if (Width < 1 || Width > 32 - LSB) {
3952    Error(E, "'width' operand must be in the range [1,32-lsb]");
3953    return MatchOperand_ParseFail;
3954  }
3955
3956  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
3957
3958  return MatchOperand_Success;
3959}
3960
3961ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3962parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3963  // Check for a post-index addressing register operand. Specifically:
3964  // postidx_reg := '+' register {, shift}
3965  //              | '-' register {, shift}
3966  //              | register {, shift}
3967
3968  // This method must return MatchOperand_NoMatch without consuming any tokens
3969  // in the case where there is no match, as other alternatives take other
3970  // parse methods.
3971  AsmToken Tok = Parser.getTok();
3972  SMLoc S = Tok.getLoc();
3973  bool haveEaten = false;
3974  bool isAdd = true;
3975  if (Tok.is(AsmToken::Plus)) {
3976    Parser.Lex(); // Eat the '+' token.
3977    haveEaten = true;
3978  } else if (Tok.is(AsmToken::Minus)) {
3979    Parser.Lex(); // Eat the '-' token.
3980    isAdd = false;
3981    haveEaten = true;
3982  }
3983
3984  SMLoc E = Parser.getTok().getEndLoc();
3985  int Reg = tryParseRegister();
3986  if (Reg == -1) {
3987    if (!haveEaten)
3988      return MatchOperand_NoMatch;
3989    Error(Parser.getTok().getLoc(), "register expected");
3990    return MatchOperand_ParseFail;
3991  }
3992
3993  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3994  unsigned ShiftImm = 0;
3995  if (Parser.getTok().is(AsmToken::Comma)) {
3996    Parser.Lex(); // Eat the ','.
3997    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3998      return MatchOperand_ParseFail;
3999
4000    // FIXME: Only approximates end...may include intervening whitespace.
4001    E = Parser.getTok().getLoc();
4002  }
4003
4004  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4005                                                  ShiftImm, S, E));
4006
4007  return MatchOperand_Success;
4008}
4009
4010ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4011parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4012  // Check for a post-index addressing register operand. Specifically:
4013  // am3offset := '+' register
4014  //              | '-' register
4015  //              | register
4016  //              | # imm
4017  //              | # + imm
4018  //              | # - imm
4019
4020  // This method must return MatchOperand_NoMatch without consuming any tokens
4021  // in the case where there is no match, as other alternatives take other
4022  // parse methods.
4023  AsmToken Tok = Parser.getTok();
4024  SMLoc S = Tok.getLoc();
4025
4026  // Do immediates first, as we always parse those if we have a '#'.
4027  if (Parser.getTok().is(AsmToken::Hash) ||
4028      Parser.getTok().is(AsmToken::Dollar)) {
4029    Parser.Lex(); // Eat '#' or '$'.
4030    // Explicitly look for a '-', as we need to encode negative zero
4031    // differently.
4032    bool isNegative = Parser.getTok().is(AsmToken::Minus);
4033    const MCExpr *Offset;
4034    SMLoc E;
4035    if (getParser().parseExpression(Offset, E))
4036      return MatchOperand_ParseFail;
4037    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4038    if (!CE) {
4039      Error(S, "constant expression expected");
4040      return MatchOperand_ParseFail;
4041    }
4042    // Negative zero is encoded as the flag value INT32_MIN.
4043    int32_t Val = CE->getValue();
4044    if (isNegative && Val == 0)
4045      Val = INT32_MIN;
4046
4047    Operands.push_back(
4048      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4049
4050    return MatchOperand_Success;
4051  }
4052
4053
4054  bool haveEaten = false;
4055  bool isAdd = true;
4056  if (Tok.is(AsmToken::Plus)) {
4057    Parser.Lex(); // Eat the '+' token.
4058    haveEaten = true;
4059  } else if (Tok.is(AsmToken::Minus)) {
4060    Parser.Lex(); // Eat the '-' token.
4061    isAdd = false;
4062    haveEaten = true;
4063  }
4064
4065  Tok = Parser.getTok();
4066  int Reg = tryParseRegister();
4067  if (Reg == -1) {
4068    if (!haveEaten)
4069      return MatchOperand_NoMatch;
4070    Error(Tok.getLoc(), "register expected");
4071    return MatchOperand_ParseFail;
4072  }
4073
4074  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4075                                                  0, S, Tok.getEndLoc()));
4076
4077  return MatchOperand_Success;
4078}
4079
4080/// cvtT2LdrdPre - Convert parsed operands to MCInst.
4081/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4082/// when they refer multiple MIOperands inside a single one.
4083void ARMAsmParser::
4084cvtT2LdrdPre(MCInst &Inst,
4085             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4086  // Rt, Rt2
4087  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4088  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4089  // Create a writeback register dummy placeholder.
4090  Inst.addOperand(MCOperand::CreateReg(0));
4091  // addr
4092  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
4093  // pred
4094  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4095}
4096
4097/// cvtT2StrdPre - Convert parsed operands to MCInst.
4098/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4099/// when they refer multiple MIOperands inside a single one.
4100void ARMAsmParser::
4101cvtT2StrdPre(MCInst &Inst,
4102             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4103  // Create a writeback register dummy placeholder.
4104  Inst.addOperand(MCOperand::CreateReg(0));
4105  // Rt, Rt2
4106  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4107  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4108  // addr
4109  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
4110  // pred
4111  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4112}
4113
4114/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
4115/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4116/// when they refer multiple MIOperands inside a single one.
4117void ARMAsmParser::
4118cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
4119                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4120  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4121
4122  // Create a writeback register dummy placeholder.
4123  Inst.addOperand(MCOperand::CreateImm(0));
4124
4125  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
4126  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4127}
4128
4129/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
4130/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4131/// when they refer multiple MIOperands inside a single one.
4132void ARMAsmParser::
4133cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
4134                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4135  // Create a writeback register dummy placeholder.
4136  Inst.addOperand(MCOperand::CreateImm(0));
4137  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4138  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
4139  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4140}
4141
4142/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
4143/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4144/// when they refer multiple MIOperands inside a single one.
4145void ARMAsmParser::
4146cvtLdWriteBackRegAddrMode2(MCInst &Inst,
4147                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4148  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4149
4150  // Create a writeback register dummy placeholder.
4151  Inst.addOperand(MCOperand::CreateImm(0));
4152
4153  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
4154  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4155}
4156
4157/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
4158/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4159/// when they refer multiple MIOperands inside a single one.
4160void ARMAsmParser::
4161cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
4162                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4163  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4164
4165  // Create a writeback register dummy placeholder.
4166  Inst.addOperand(MCOperand::CreateImm(0));
4167
4168  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
4169  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4170}
4171
4172
4173/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
4174/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4175/// when they refer multiple MIOperands inside a single one.
4176void ARMAsmParser::
4177cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
4178                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4179  // Create a writeback register dummy placeholder.
4180  Inst.addOperand(MCOperand::CreateImm(0));
4181  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4182  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
4183  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4184}
4185
4186/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
4187/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4188/// when they refer multiple MIOperands inside a single one.
4189void ARMAsmParser::
4190cvtStWriteBackRegAddrMode2(MCInst &Inst,
4191                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4192  // Create a writeback register dummy placeholder.
4193  Inst.addOperand(MCOperand::CreateImm(0));
4194  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4195  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
4196  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4197}
4198
4199/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4200/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4201/// when they refer multiple MIOperands inside a single one.
4202void ARMAsmParser::
4203cvtStWriteBackRegAddrMode3(MCInst &Inst,
4204                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4205  // Create a writeback register dummy placeholder.
4206  Inst.addOperand(MCOperand::CreateImm(0));
4207  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4208  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4209  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4210}
4211
4212/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
4213/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4214/// when they refer multiple MIOperands inside a single one.
4215void ARMAsmParser::
4216cvtLdExtTWriteBackImm(MCInst &Inst,
4217                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4218  // Rt
4219  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4220  // Create a writeback register dummy placeholder.
4221  Inst.addOperand(MCOperand::CreateImm(0));
4222  // addr
4223  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4224  // offset
4225  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4226  // pred
4227  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4228}
4229
4230/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
4231/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4232/// when they refer multiple MIOperands inside a single one.
4233void ARMAsmParser::
4234cvtLdExtTWriteBackReg(MCInst &Inst,
4235                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4236  // Rt
4237  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4238  // Create a writeback register dummy placeholder.
4239  Inst.addOperand(MCOperand::CreateImm(0));
4240  // addr
4241  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4242  // offset
4243  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4244  // pred
4245  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4246}
4247
4248/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
4249/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4250/// when they refer multiple MIOperands inside a single one.
4251void ARMAsmParser::
4252cvtStExtTWriteBackImm(MCInst &Inst,
4253                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4254  // Create a writeback register dummy placeholder.
4255  Inst.addOperand(MCOperand::CreateImm(0));
4256  // Rt
4257  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4258  // addr
4259  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4260  // offset
4261  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4262  // pred
4263  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4264}
4265
4266/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
4267/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4268/// when they refer multiple MIOperands inside a single one.
4269void ARMAsmParser::
4270cvtStExtTWriteBackReg(MCInst &Inst,
4271                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4272  // Create a writeback register dummy placeholder.
4273  Inst.addOperand(MCOperand::CreateImm(0));
4274  // Rt
4275  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4276  // addr
4277  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4278  // offset
4279  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4280  // pred
4281  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4282}
4283
4284/// cvtLdrdPre - Convert parsed operands to MCInst.
4285/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4286/// when they refer multiple MIOperands inside a single one.
4287void ARMAsmParser::
4288cvtLdrdPre(MCInst &Inst,
4289           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4290  // Rt, Rt2
4291  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4292  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4293  // Create a writeback register dummy placeholder.
4294  Inst.addOperand(MCOperand::CreateImm(0));
4295  // addr
4296  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4297  // pred
4298  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4299}
4300
4301/// cvtStrdPre - Convert parsed operands to MCInst.
4302/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4303/// when they refer multiple MIOperands inside a single one.
4304void ARMAsmParser::
4305cvtStrdPre(MCInst &Inst,
4306           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4307  // Create a writeback register dummy placeholder.
4308  Inst.addOperand(MCOperand::CreateImm(0));
4309  // Rt, Rt2
4310  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4311  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4312  // addr
4313  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4314  // pred
4315  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4316}
4317
4318/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4319/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4320/// when they refer multiple MIOperands inside a single one.
4321void ARMAsmParser::
4322cvtLdWriteBackRegAddrMode3(MCInst &Inst,
4323                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4324  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4325  // Create a writeback register dummy placeholder.
4326  Inst.addOperand(MCOperand::CreateImm(0));
4327  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4328  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4329}
4330
4331/// cvtThumbMultiply - Convert parsed operands to MCInst.
4332/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4333/// when they refer multiple MIOperands inside a single one.
4334void ARMAsmParser::
4335cvtThumbMultiply(MCInst &Inst,
4336           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4337  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4338  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4339  // If we have a three-operand form, make sure to set Rn to be the operand
4340  // that isn't the same as Rd.
4341  unsigned RegOp = 4;
4342  if (Operands.size() == 6 &&
4343      ((ARMOperand*)Operands[4])->getReg() ==
4344        ((ARMOperand*)Operands[3])->getReg())
4345    RegOp = 5;
4346  ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4347  Inst.addOperand(Inst.getOperand(0));
4348  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4349}
4350
4351void ARMAsmParser::
4352cvtVLDwbFixed(MCInst &Inst,
4353              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4354  // Vd
4355  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4356  // Create a writeback register dummy placeholder.
4357  Inst.addOperand(MCOperand::CreateImm(0));
4358  // Vn
4359  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4360  // pred
4361  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4362}
4363
4364void ARMAsmParser::
4365cvtVLDwbRegister(MCInst &Inst,
4366                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4367  // Vd
4368  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4369  // Create a writeback register dummy placeholder.
4370  Inst.addOperand(MCOperand::CreateImm(0));
4371  // Vn
4372  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4373  // Vm
4374  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4375  // pred
4376  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4377}
4378
4379void ARMAsmParser::
4380cvtVSTwbFixed(MCInst &Inst,
4381              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4382  // Create a writeback register dummy placeholder.
4383  Inst.addOperand(MCOperand::CreateImm(0));
4384  // Vn
4385  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4386  // Vt
4387  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4388  // pred
4389  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4390}
4391
4392void ARMAsmParser::
4393cvtVSTwbRegister(MCInst &Inst,
4394                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4395  // Create a writeback register dummy placeholder.
4396  Inst.addOperand(MCOperand::CreateImm(0));
4397  // Vn
4398  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4399  // Vm
4400  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4401  // Vt
4402  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4403  // pred
4404  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4405}
4406
4407/// Parse an ARM memory expression, return false if successful else return true
4408/// or an error.  The first token must be a '[' when called.
4409bool ARMAsmParser::
4410parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4411  SMLoc S, E;
4412  assert(Parser.getTok().is(AsmToken::LBrac) &&
4413         "Token is not a Left Bracket");
4414  S = Parser.getTok().getLoc();
4415  Parser.Lex(); // Eat left bracket token.
4416
4417  const AsmToken &BaseRegTok = Parser.getTok();
4418  int BaseRegNum = tryParseRegister();
4419  if (BaseRegNum == -1)
4420    return Error(BaseRegTok.getLoc(), "register expected");
4421
4422  // The next token must either be a comma, a colon or a closing bracket.
4423  const AsmToken &Tok = Parser.getTok();
4424  if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4425      !Tok.is(AsmToken::RBrac))
4426    return Error(Tok.getLoc(), "malformed memory operand");
4427
4428  if (Tok.is(AsmToken::RBrac)) {
4429    E = Tok.getEndLoc();
4430    Parser.Lex(); // Eat right bracket token.
4431
4432    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4433                                             0, 0, false, S, E));
4434
4435    // If there's a pre-indexing writeback marker, '!', just add it as a token
4436    // operand. It's rather odd, but syntactically valid.
4437    if (Parser.getTok().is(AsmToken::Exclaim)) {
4438      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4439      Parser.Lex(); // Eat the '!'.
4440    }
4441
4442    return false;
4443  }
4444
4445  assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4446         "Lost colon or comma in memory operand?!");
4447  if (Tok.is(AsmToken::Comma)) {
4448    Parser.Lex(); // Eat the comma.
4449  }
4450
4451  // If we have a ':', it's an alignment specifier.
4452  if (Parser.getTok().is(AsmToken::Colon)) {
4453    Parser.Lex(); // Eat the ':'.
4454    E = Parser.getTok().getLoc();
4455
4456    const MCExpr *Expr;
4457    if (getParser().parseExpression(Expr))
4458     return true;
4459
4460    // The expression has to be a constant. Memory references with relocations
4461    // don't come through here, as they use the <label> forms of the relevant
4462    // instructions.
4463    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4464    if (!CE)
4465      return Error (E, "constant expression expected");
4466
4467    unsigned Align = 0;
4468    switch (CE->getValue()) {
4469    default:
4470      return Error(E,
4471                   "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4472    case 16:  Align = 2; break;
4473    case 32:  Align = 4; break;
4474    case 64:  Align = 8; break;
4475    case 128: Align = 16; break;
4476    case 256: Align = 32; break;
4477    }
4478
4479    // Now we should have the closing ']'
4480    if (Parser.getTok().isNot(AsmToken::RBrac))
4481      return Error(Parser.getTok().getLoc(), "']' expected");
4482    E = Parser.getTok().getEndLoc();
4483    Parser.Lex(); // Eat right bracket token.
4484
4485    // Don't worry about range checking the value here. That's handled by
4486    // the is*() predicates.
4487    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4488                                             ARM_AM::no_shift, 0, Align,
4489                                             false, S, E));
4490
4491    // If there's a pre-indexing writeback marker, '!', just add it as a token
4492    // operand.
4493    if (Parser.getTok().is(AsmToken::Exclaim)) {
4494      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4495      Parser.Lex(); // Eat the '!'.
4496    }
4497
4498    return false;
4499  }
4500
4501  // If we have a '#', it's an immediate offset, else assume it's a register
4502  // offset. Be friendly and also accept a plain integer (without a leading
4503  // hash) for gas compatibility.
4504  if (Parser.getTok().is(AsmToken::Hash) ||
4505      Parser.getTok().is(AsmToken::Dollar) ||
4506      Parser.getTok().is(AsmToken::Integer)) {
4507    if (Parser.getTok().isNot(AsmToken::Integer))
4508      Parser.Lex(); // Eat '#' or '$'.
4509    E = Parser.getTok().getLoc();
4510
4511    bool isNegative = getParser().getTok().is(AsmToken::Minus);
4512    const MCExpr *Offset;
4513    if (getParser().parseExpression(Offset))
4514     return true;
4515
4516    // The expression has to be a constant. Memory references with relocations
4517    // don't come through here, as they use the <label> forms of the relevant
4518    // instructions.
4519    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4520    if (!CE)
4521      return Error (E, "constant expression expected");
4522
4523    // If the constant was #-0, represent it as INT32_MIN.
4524    int32_t Val = CE->getValue();
4525    if (isNegative && Val == 0)
4526      CE = MCConstantExpr::Create(INT32_MIN, getContext());
4527
4528    // Now we should have the closing ']'
4529    if (Parser.getTok().isNot(AsmToken::RBrac))
4530      return Error(Parser.getTok().getLoc(), "']' expected");
4531    E = Parser.getTok().getEndLoc();
4532    Parser.Lex(); // Eat right bracket token.
4533
4534    // Don't worry about range checking the value here. That's handled by
4535    // the is*() predicates.
4536    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4537                                             ARM_AM::no_shift, 0, 0,
4538                                             false, S, E));
4539
4540    // If there's a pre-indexing writeback marker, '!', just add it as a token
4541    // operand.
4542    if (Parser.getTok().is(AsmToken::Exclaim)) {
4543      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4544      Parser.Lex(); // Eat the '!'.
4545    }
4546
4547    return false;
4548  }
4549
4550  // The register offset is optionally preceded by a '+' or '-'
4551  bool isNegative = false;
4552  if (Parser.getTok().is(AsmToken::Minus)) {
4553    isNegative = true;
4554    Parser.Lex(); // Eat the '-'.
4555  } else if (Parser.getTok().is(AsmToken::Plus)) {
4556    // Nothing to do.
4557    Parser.Lex(); // Eat the '+'.
4558  }
4559
4560  E = Parser.getTok().getLoc();
4561  int OffsetRegNum = tryParseRegister();
4562  if (OffsetRegNum == -1)
4563    return Error(E, "register expected");
4564
4565  // If there's a shift operator, handle it.
4566  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4567  unsigned ShiftImm = 0;
4568  if (Parser.getTok().is(AsmToken::Comma)) {
4569    Parser.Lex(); // Eat the ','.
4570    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4571      return true;
4572  }
4573
4574  // Now we should have the closing ']'
4575  if (Parser.getTok().isNot(AsmToken::RBrac))
4576    return Error(Parser.getTok().getLoc(), "']' expected");
4577  E = Parser.getTok().getEndLoc();
4578  Parser.Lex(); // Eat right bracket token.
4579
4580  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4581                                           ShiftType, ShiftImm, 0, isNegative,
4582                                           S, E));
4583
4584  // If there's a pre-indexing writeback marker, '!', just add it as a token
4585  // operand.
4586  if (Parser.getTok().is(AsmToken::Exclaim)) {
4587    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4588    Parser.Lex(); // Eat the '!'.
4589  }
4590
4591  return false;
4592}
4593
4594/// parseMemRegOffsetShift - one of these two:
4595///   ( lsl | lsr | asr | ror ) , # shift_amount
4596///   rrx
4597/// return true if it parses a shift otherwise it returns false.
4598bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4599                                          unsigned &Amount) {
4600  SMLoc Loc = Parser.getTok().getLoc();
4601  const AsmToken &Tok = Parser.getTok();
4602  if (Tok.isNot(AsmToken::Identifier))
4603    return true;
4604  StringRef ShiftName = Tok.getString();
4605  if (ShiftName == "lsl" || ShiftName == "LSL" ||
4606      ShiftName == "asl" || ShiftName == "ASL")
4607    St = ARM_AM::lsl;
4608  else if (ShiftName == "lsr" || ShiftName == "LSR")
4609    St = ARM_AM::lsr;
4610  else if (ShiftName == "asr" || ShiftName == "ASR")
4611    St = ARM_AM::asr;
4612  else if (ShiftName == "ror" || ShiftName == "ROR")
4613    St = ARM_AM::ror;
4614  else if (ShiftName == "rrx" || ShiftName == "RRX")
4615    St = ARM_AM::rrx;
4616  else
4617    return Error(Loc, "illegal shift operator");
4618  Parser.Lex(); // Eat shift type token.
4619
4620  // rrx stands alone.
4621  Amount = 0;
4622  if (St != ARM_AM::rrx) {
4623    Loc = Parser.getTok().getLoc();
4624    // A '#' and a shift amount.
4625    const AsmToken &HashTok = Parser.getTok();
4626    if (HashTok.isNot(AsmToken::Hash) &&
4627        HashTok.isNot(AsmToken::Dollar))
4628      return Error(HashTok.getLoc(), "'#' expected");
4629    Parser.Lex(); // Eat hash token.
4630
4631    const MCExpr *Expr;
4632    if (getParser().parseExpression(Expr))
4633      return true;
4634    // Range check the immediate.
4635    // lsl, ror: 0 <= imm <= 31
4636    // lsr, asr: 0 <= imm <= 32
4637    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4638    if (!CE)
4639      return Error(Loc, "shift amount must be an immediate");
4640    int64_t Imm = CE->getValue();
4641    if (Imm < 0 ||
4642        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4643        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4644      return Error(Loc, "immediate shift value out of range");
4645    // If <ShiftTy> #0, turn it into a no_shift.
4646    if (Imm == 0)
4647      St = ARM_AM::lsl;
4648    // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4649    if (Imm == 32)
4650      Imm = 0;
4651    Amount = Imm;
4652  }
4653
4654  return false;
4655}
4656
4657/// parseFPImm - A floating point immediate expression operand.
4658ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4659parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4660  // Anything that can accept a floating point constant as an operand
4661  // needs to go through here, as the regular parseExpression is
4662  // integer only.
4663  //
4664  // This routine still creates a generic Immediate operand, containing
4665  // a bitcast of the 64-bit floating point value. The various operands
4666  // that accept floats can check whether the value is valid for them
4667  // via the standard is*() predicates.
4668
4669  SMLoc S = Parser.getTok().getLoc();
4670
4671  if (Parser.getTok().isNot(AsmToken::Hash) &&
4672      Parser.getTok().isNot(AsmToken::Dollar))
4673    return MatchOperand_NoMatch;
4674
4675  // Disambiguate the VMOV forms that can accept an FP immediate.
4676  // vmov.f32 <sreg>, #imm
4677  // vmov.f64 <dreg>, #imm
4678  // vmov.f32 <dreg>, #imm  @ vector f32x2
4679  // vmov.f32 <qreg>, #imm  @ vector f32x4
4680  //
4681  // There are also the NEON VMOV instructions which expect an
4682  // integer constant. Make sure we don't try to parse an FPImm
4683  // for these:
4684  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4685  ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4686  if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4687                           TyOp->getToken() != ".f64"))
4688    return MatchOperand_NoMatch;
4689
4690  Parser.Lex(); // Eat '#' or '$'.
4691
4692  // Handle negation, as that still comes through as a separate token.
4693  bool isNegative = false;
4694  if (Parser.getTok().is(AsmToken::Minus)) {
4695    isNegative = true;
4696    Parser.Lex();
4697  }
4698  const AsmToken &Tok = Parser.getTok();
4699  SMLoc Loc = Tok.getLoc();
4700  if (Tok.is(AsmToken::Real)) {
4701    APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4702    uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4703    // If we had a '-' in front, toggle the sign bit.
4704    IntVal ^= (uint64_t)isNegative << 31;
4705    Parser.Lex(); // Eat the token.
4706    Operands.push_back(ARMOperand::CreateImm(
4707          MCConstantExpr::Create(IntVal, getContext()),
4708          S, Parser.getTok().getLoc()));
4709    return MatchOperand_Success;
4710  }
4711  // Also handle plain integers. Instructions which allow floating point
4712  // immediates also allow a raw encoded 8-bit value.
4713  if (Tok.is(AsmToken::Integer)) {
4714    int64_t Val = Tok.getIntVal();
4715    Parser.Lex(); // Eat the token.
4716    if (Val > 255 || Val < 0) {
4717      Error(Loc, "encoded floating point value out of range");
4718      return MatchOperand_ParseFail;
4719    }
4720    double RealVal = ARM_AM::getFPImmFloat(Val);
4721    Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4722    Operands.push_back(ARMOperand::CreateImm(
4723        MCConstantExpr::Create(Val, getContext()), S,
4724        Parser.getTok().getLoc()));
4725    return MatchOperand_Success;
4726  }
4727
4728  Error(Loc, "invalid floating point immediate");
4729  return MatchOperand_ParseFail;
4730}
4731
4732/// Parse a arm instruction operand.  For now this parses the operand regardless
4733/// of the mnemonic.
4734bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4735                                StringRef Mnemonic) {
4736  SMLoc S, E;
4737
4738  // Check if the current operand has a custom associated parser, if so, try to
4739  // custom parse the operand, or fallback to the general approach.
4740  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4741  if (ResTy == MatchOperand_Success)
4742    return false;
4743  // If there wasn't a custom match, try the generic matcher below. Otherwise,
4744  // there was a match, but an error occurred, in which case, just return that
4745  // the operand parsing failed.
4746  if (ResTy == MatchOperand_ParseFail)
4747    return true;
4748
4749  switch (getLexer().getKind()) {
4750  default:
4751    Error(Parser.getTok().getLoc(), "unexpected token in operand");
4752    return true;
4753  case AsmToken::Identifier: {
4754    // If we've seen a branch mnemonic, the next operand must be a label.  This
4755    // is true even if the label is a register name.  So "br r1" means branch to
4756    // label "r1".
4757    bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4758    if (!ExpectLabel) {
4759      if (!tryParseRegisterWithWriteBack(Operands))
4760        return false;
4761      int Res = tryParseShiftRegister(Operands);
4762      if (Res == 0) // success
4763        return false;
4764      else if (Res == -1) // irrecoverable error
4765        return true;
4766      // If this is VMRS, check for the apsr_nzcv operand.
4767      if (Mnemonic == "vmrs" &&
4768          Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4769        S = Parser.getTok().getLoc();
4770        Parser.Lex();
4771        Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4772        return false;
4773      }
4774    }
4775
4776    // Fall though for the Identifier case that is not a register or a
4777    // special name.
4778  }
4779  case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4780  case AsmToken::Integer: // things like 1f and 2b as a branch targets
4781  case AsmToken::String:  // quoted label names.
4782  case AsmToken::Dot: {   // . as a branch target
4783    // This was not a register so parse other operands that start with an
4784    // identifier (like labels) as expressions and create them as immediates.
4785    const MCExpr *IdVal;
4786    S = Parser.getTok().getLoc();
4787    if (getParser().parseExpression(IdVal))
4788      return true;
4789    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4790    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4791    return false;
4792  }
4793  case AsmToken::LBrac:
4794    return parseMemory(Operands);
4795  case AsmToken::LCurly:
4796    return parseRegisterList(Operands);
4797  case AsmToken::Dollar:
4798  case AsmToken::Hash: {
4799    // #42 -> immediate.
4800    S = Parser.getTok().getLoc();
4801    Parser.Lex();
4802
4803    if (Parser.getTok().isNot(AsmToken::Colon)) {
4804      bool isNegative = Parser.getTok().is(AsmToken::Minus);
4805      const MCExpr *ImmVal;
4806      if (getParser().parseExpression(ImmVal))
4807        return true;
4808      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4809      if (CE) {
4810        int32_t Val = CE->getValue();
4811        if (isNegative && Val == 0)
4812          ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4813      }
4814      E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4815      Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4816
4817      // There can be a trailing '!' on operands that we want as a separate
4818      // '!' Token operand. Handle that here. For example, the compatibilty
4819      // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4820      if (Parser.getTok().is(AsmToken::Exclaim)) {
4821        Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4822                                                   Parser.getTok().getLoc()));
4823        Parser.Lex(); // Eat exclaim token
4824      }
4825      return false;
4826    }
4827    // w/ a ':' after the '#', it's just like a plain ':'.
4828    // FALLTHROUGH
4829  }
4830  case AsmToken::Colon: {
4831    // ":lower16:" and ":upper16:" expression prefixes
4832    // FIXME: Check it's an expression prefix,
4833    // e.g. (FOO - :lower16:BAR) isn't legal.
4834    ARMMCExpr::VariantKind RefKind;
4835    if (parsePrefix(RefKind))
4836      return true;
4837
4838    const MCExpr *SubExprVal;
4839    if (getParser().parseExpression(SubExprVal))
4840      return true;
4841
4842    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4843                                              getContext());
4844    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4845    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4846    return false;
4847  }
4848  }
4849}
4850
4851// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4852//  :lower16: and :upper16:.
4853bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4854  RefKind = ARMMCExpr::VK_ARM_None;
4855
4856  // :lower16: and :upper16: modifiers
4857  assert(getLexer().is(AsmToken::Colon) && "expected a :");
4858  Parser.Lex(); // Eat ':'
4859
4860  if (getLexer().isNot(AsmToken::Identifier)) {
4861    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4862    return true;
4863  }
4864
4865  StringRef IDVal = Parser.getTok().getIdentifier();
4866  if (IDVal == "lower16") {
4867    RefKind = ARMMCExpr::VK_ARM_LO16;
4868  } else if (IDVal == "upper16") {
4869    RefKind = ARMMCExpr::VK_ARM_HI16;
4870  } else {
4871    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4872    return true;
4873  }
4874  Parser.Lex();
4875
4876  if (getLexer().isNot(AsmToken::Colon)) {
4877    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4878    return true;
4879  }
4880  Parser.Lex(); // Eat the last ':'
4881  return false;
4882}
4883
4884/// \brief Given a mnemonic, split out possible predication code and carry
4885/// setting letters to form a canonical mnemonic and flags.
4886//
4887// FIXME: Would be nice to autogen this.
4888// FIXME: This is a bit of a maze of special cases.
4889StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4890                                      unsigned &PredicationCode,
4891                                      bool &CarrySetting,
4892                                      unsigned &ProcessorIMod,
4893                                      StringRef &ITMask) {
4894  PredicationCode = ARMCC::AL;
4895  CarrySetting = false;
4896  ProcessorIMod = 0;
4897
4898  // Ignore some mnemonics we know aren't predicated forms.
4899  //
4900  // FIXME: Would be nice to autogen this.
4901  if ((Mnemonic == "movs" && isThumb()) ||
4902      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
4903      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
4904      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
4905      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
4906      Mnemonic == "vaclt" || Mnemonic == "vacle"  ||
4907      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
4908      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
4909      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4910      Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4911      Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
4912      Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4913      Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4914    return Mnemonic;
4915
4916  // First, split out any predication code. Ignore mnemonics we know aren't
4917  // predicated but do have a carry-set and so weren't caught above.
4918  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4919      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4920      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4921      Mnemonic != "sbcs" && Mnemonic != "rscs") {
4922    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4923      .Case("eq", ARMCC::EQ)
4924      .Case("ne", ARMCC::NE)
4925      .Case("hs", ARMCC::HS)
4926      .Case("cs", ARMCC::HS)
4927      .Case("lo", ARMCC::LO)
4928      .Case("cc", ARMCC::LO)
4929      .Case("mi", ARMCC::MI)
4930      .Case("pl", ARMCC::PL)
4931      .Case("vs", ARMCC::VS)
4932      .Case("vc", ARMCC::VC)
4933      .Case("hi", ARMCC::HI)
4934      .Case("ls", ARMCC::LS)
4935      .Case("ge", ARMCC::GE)
4936      .Case("lt", ARMCC::LT)
4937      .Case("gt", ARMCC::GT)
4938      .Case("le", ARMCC::LE)
4939      .Case("al", ARMCC::AL)
4940      .Default(~0U);
4941    if (CC != ~0U) {
4942      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4943      PredicationCode = CC;
4944    }
4945  }
4946
4947  // Next, determine if we have a carry setting bit. We explicitly ignore all
4948  // the instructions we know end in 's'.
4949  if (Mnemonic.endswith("s") &&
4950      !(Mnemonic == "cps" || Mnemonic == "mls" ||
4951        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4952        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4953        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4954        Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4955        Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4956        Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4957        Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4958        Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4959        (Mnemonic == "movs" && isThumb()))) {
4960    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4961    CarrySetting = true;
4962  }
4963
4964  // The "cps" instruction can have a interrupt mode operand which is glued into
4965  // the mnemonic. Check if this is the case, split it and parse the imod op
4966  if (Mnemonic.startswith("cps")) {
4967    // Split out any imod code.
4968    unsigned IMod =
4969      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4970      .Case("ie", ARM_PROC::IE)
4971      .Case("id", ARM_PROC::ID)
4972      .Default(~0U);
4973    if (IMod != ~0U) {
4974      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4975      ProcessorIMod = IMod;
4976    }
4977  }
4978
4979  // The "it" instruction has the condition mask on the end of the mnemonic.
4980  if (Mnemonic.startswith("it")) {
4981    ITMask = Mnemonic.slice(2, Mnemonic.size());
4982    Mnemonic = Mnemonic.slice(0, 2);
4983  }
4984
4985  return Mnemonic;
4986}
4987
4988/// \brief Given a canonical mnemonic, determine if the instruction ever allows
4989/// inclusion of carry set or predication code operands.
4990//
4991// FIXME: It would be nice to autogen this.
4992void ARMAsmParser::
4993getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4994                      bool &CanAcceptPredicationCode) {
4995  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4996      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4997      Mnemonic == "add" || Mnemonic == "adc" ||
4998      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4999      Mnemonic == "orr" || Mnemonic == "mvn" ||
5000      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
5001      Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
5002      Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5003      (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
5004                      Mnemonic == "mla" || Mnemonic == "smlal" ||
5005                      Mnemonic == "umlal" || Mnemonic == "umull"))) {
5006    CanAcceptCarrySet = true;
5007  } else
5008    CanAcceptCarrySet = false;
5009
5010  if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5011      Mnemonic == "cps" ||  Mnemonic == "it" ||  Mnemonic == "cbz" ||
5012      Mnemonic == "trap" || Mnemonic == "setend" ||
5013      Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
5014      Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
5015      Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
5016      Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
5017      Mnemonic == "vrintm") {
5018    // These mnemonics are never predicable
5019    CanAcceptPredicationCode = false;
5020  } else if (!isThumb()) {
5021    // Some instructions are only predicable in Thumb mode
5022    CanAcceptPredicationCode
5023      = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5024        Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5025        Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5026        Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5027        Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5028        Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5029        !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5030  } else if (isThumbOne()) {
5031    CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5032  } else
5033    CanAcceptPredicationCode = true;
5034}
5035
5036bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5037                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5038  // FIXME: This is all horribly hacky. We really need a better way to deal
5039  // with optional operands like this in the matcher table.
5040
5041  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5042  // another does not. Specifically, the MOVW instruction does not. So we
5043  // special case it here and remove the defaulted (non-setting) cc_out
5044  // operand if that's the instruction we're trying to match.
5045  //
5046  // We do this as post-processing of the explicit operands rather than just
5047  // conditionally adding the cc_out in the first place because we need
5048  // to check the type of the parsed immediate operand.
5049  if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5050      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
5051      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
5052      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5053    return true;
5054
5055  // Register-register 'add' for thumb does not have a cc_out operand
5056  // when there are only two register operands.
5057  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5058      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5059      static_cast<ARMOperand*>(Operands[4])->isReg() &&
5060      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5061    return true;
5062  // Register-register 'add' for thumb does not have a cc_out operand
5063  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5064  // have to check the immediate range here since Thumb2 has a variant
5065  // that can handle a different range and has a cc_out operand.
5066  if (((isThumb() && Mnemonic == "add") ||
5067       (isThumbTwo() && Mnemonic == "sub")) &&
5068      Operands.size() == 6 &&
5069      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5070      static_cast<ARMOperand*>(Operands[4])->isReg() &&
5071      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
5072      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5073      ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
5074       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
5075    return true;
5076  // For Thumb2, add/sub immediate does not have a cc_out operand for the
5077  // imm0_4095 variant. That's the least-preferred variant when
5078  // selecting via the generic "add" mnemonic, so to know that we
5079  // should remove the cc_out operand, we have to explicitly check that
5080  // it's not one of the other variants. Ugh.
5081  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5082      Operands.size() == 6 &&
5083      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5084      static_cast<ARMOperand*>(Operands[4])->isReg() &&
5085      static_cast<ARMOperand*>(Operands[5])->isImm()) {
5086    // Nest conditions rather than one big 'if' statement for readability.
5087    //
5088    // If both registers are low, we're in an IT block, and the immediate is
5089    // in range, we should use encoding T1 instead, which has a cc_out.
5090    if (inITBlock() &&
5091        isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5092        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
5093        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
5094      return false;
5095    // Check against T3. If the second register is the PC, this is an
5096    // alternate form of ADR, which uses encoding T4, so check for that too.
5097    if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
5098        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
5099      return false;
5100
5101    // Otherwise, we use encoding T4, which does not have a cc_out
5102    // operand.
5103    return true;
5104  }
5105
5106  // The thumb2 multiply instruction doesn't have a CCOut register, so
5107  // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5108  // use the 16-bit encoding or not.
5109  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5110      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5111      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5112      static_cast<ARMOperand*>(Operands[4])->isReg() &&
5113      static_cast<ARMOperand*>(Operands[5])->isReg() &&
5114      // If the registers aren't low regs, the destination reg isn't the
5115      // same as one of the source regs, or the cc_out operand is zero
5116      // outside of an IT block, we have to use the 32-bit encoding, so
5117      // remove the cc_out operand.
5118      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5119       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5120       !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
5121       !inITBlock() ||
5122       (static_cast<ARMOperand*>(Operands[3])->getReg() !=
5123        static_cast<ARMOperand*>(Operands[5])->getReg() &&
5124        static_cast<ARMOperand*>(Operands[3])->getReg() !=
5125        static_cast<ARMOperand*>(Operands[4])->getReg())))
5126    return true;
5127
5128  // Also check the 'mul' syntax variant that doesn't specify an explicit
5129  // destination register.
5130  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5131      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5132      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5133      static_cast<ARMOperand*>(Operands[4])->isReg() &&
5134      // If the registers aren't low regs  or the cc_out operand is zero
5135      // outside of an IT block, we have to use the 32-bit encoding, so
5136      // remove the cc_out operand.
5137      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5138       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5139       !inITBlock()))
5140    return true;
5141
5142
5143
5144  // Register-register 'add/sub' for thumb does not have a cc_out operand
5145  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5146  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5147  // right, this will result in better diagnostics (which operand is off)
5148  // anyway.
5149  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5150      (Operands.size() == 5 || Operands.size() == 6) &&
5151      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5152      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
5153      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5154      (static_cast<ARMOperand*>(Operands[4])->isImm() ||
5155       (Operands.size() == 6 &&
5156        static_cast<ARMOperand*>(Operands[5])->isImm())))
5157    return true;
5158
5159  return false;
5160}
5161
5162bool ARMAsmParser::shouldOmitPredicateOperand(
5163    StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
5164  // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5165  unsigned RegIdx = 3;
5166  if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5167      static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
5168    if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
5169        static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
5170      RegIdx = 4;
5171
5172    if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
5173        (ARMMCRegisterClasses[ARM::DPRRegClassID]
5174             .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
5175         ARMMCRegisterClasses[ARM::QPRRegClassID]
5176             .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
5177      return true;
5178  }
5179  return false;
5180}
5181
5182static bool isDataTypeToken(StringRef Tok) {
5183  return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5184    Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5185    Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5186    Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5187    Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5188    Tok == ".f" || Tok == ".d";
5189}
5190
5191// FIXME: This bit should probably be handled via an explicit match class
5192// in the .td files that matches the suffix instead of having it be
5193// a literal string token the way it is now.
5194static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5195  return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5196}
5197static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5198                                 unsigned VariantID);
5199/// Parse an arm instruction mnemonic followed by its operands.
5200bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5201                                    SMLoc NameLoc,
5202                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5203  // Apply mnemonic aliases before doing anything else, as the destination
5204  // mnemnonic may include suffices and we want to handle them normally.
5205  // The generic tblgen'erated code does this later, at the start of
5206  // MatchInstructionImpl(), but that's too late for aliases that include
5207  // any sort of suffix.
5208  unsigned AvailableFeatures = getAvailableFeatures();
5209  unsigned AssemblerDialect = getParser().getAssemblerDialect();
5210  applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5211
5212  // First check for the ARM-specific .req directive.
5213  if (Parser.getTok().is(AsmToken::Identifier) &&
5214      Parser.getTok().getIdentifier() == ".req") {
5215    parseDirectiveReq(Name, NameLoc);
5216    // We always return 'error' for this, as we're done with this
5217    // statement and don't need to match the 'instruction."
5218    return true;
5219  }
5220
5221  // Create the leading tokens for the mnemonic, split by '.' characters.
5222  size_t Start = 0, Next = Name.find('.');
5223  StringRef Mnemonic = Name.slice(Start, Next);
5224
5225  // Split out the predication code and carry setting flag from the mnemonic.
5226  unsigned PredicationCode;
5227  unsigned ProcessorIMod;
5228  bool CarrySetting;
5229  StringRef ITMask;
5230  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5231                           ProcessorIMod, ITMask);
5232
5233  // In Thumb1, only the branch (B) instruction can be predicated.
5234  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5235    Parser.eatToEndOfStatement();
5236    return Error(NameLoc, "conditional execution not supported in Thumb1");
5237  }
5238
5239  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5240
5241  // Handle the IT instruction ITMask. Convert it to a bitmask. This
5242  // is the mask as it will be for the IT encoding if the conditional
5243  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5244  // where the conditional bit0 is zero, the instruction post-processing
5245  // will adjust the mask accordingly.
5246  if (Mnemonic == "it") {
5247    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5248    if (ITMask.size() > 3) {
5249      Parser.eatToEndOfStatement();
5250      return Error(Loc, "too many conditions on IT instruction");
5251    }
5252    unsigned Mask = 8;
5253    for (unsigned i = ITMask.size(); i != 0; --i) {
5254      char pos = ITMask[i - 1];
5255      if (pos != 't' && pos != 'e') {
5256        Parser.eatToEndOfStatement();
5257        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5258      }
5259      Mask >>= 1;
5260      if (ITMask[i - 1] == 't')
5261        Mask |= 8;
5262    }
5263    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5264  }
5265
5266  // FIXME: This is all a pretty gross hack. We should automatically handle
5267  // optional operands like this via tblgen.
5268
5269  // Next, add the CCOut and ConditionCode operands, if needed.
5270  //
5271  // For mnemonics which can ever incorporate a carry setting bit or predication
5272  // code, our matching model involves us always generating CCOut and
5273  // ConditionCode operands to match the mnemonic "as written" and then we let
5274  // the matcher deal with finding the right instruction or generating an
5275  // appropriate error.
5276  bool CanAcceptCarrySet, CanAcceptPredicationCode;
5277  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5278
5279  // If we had a carry-set on an instruction that can't do that, issue an
5280  // error.
5281  if (!CanAcceptCarrySet && CarrySetting) {
5282    Parser.eatToEndOfStatement();
5283    return Error(NameLoc, "instruction '" + Mnemonic +
5284                 "' can not set flags, but 's' suffix specified");
5285  }
5286  // If we had a predication code on an instruction that can't do that, issue an
5287  // error.
5288  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5289    Parser.eatToEndOfStatement();
5290    return Error(NameLoc, "instruction '" + Mnemonic +
5291                 "' is not predicable, but condition code specified");
5292  }
5293
5294  // Add the carry setting operand, if necessary.
5295  if (CanAcceptCarrySet) {
5296    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5297    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5298                                               Loc));
5299  }
5300
5301  // Add the predication code operand, if necessary.
5302  if (CanAcceptPredicationCode) {
5303    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5304                                      CarrySetting);
5305    Operands.push_back(ARMOperand::CreateCondCode(
5306                         ARMCC::CondCodes(PredicationCode), Loc));
5307  }
5308
5309  // Add the processor imod operand, if necessary.
5310  if (ProcessorIMod) {
5311    Operands.push_back(ARMOperand::CreateImm(
5312          MCConstantExpr::Create(ProcessorIMod, getContext()),
5313                                 NameLoc, NameLoc));
5314  }
5315
5316  // Add the remaining tokens in the mnemonic.
5317  while (Next != StringRef::npos) {
5318    Start = Next;
5319    Next = Name.find('.', Start + 1);
5320    StringRef ExtraToken = Name.slice(Start, Next);
5321
5322    // Some NEON instructions have an optional datatype suffix that is
5323    // completely ignored. Check for that.
5324    if (isDataTypeToken(ExtraToken) &&
5325        doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5326      continue;
5327
5328    // For for ARM mode generate an error if the .n qualifier is used.
5329    if (ExtraToken == ".n" && !isThumb()) {
5330      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5331      return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5332                   "arm mode");
5333    }
5334
5335    // The .n qualifier is always discarded as that is what the tables
5336    // and matcher expect.  In ARM mode the .w qualifier has no effect,
5337    // so discard it to avoid errors that can be caused by the matcher.
5338    if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5339      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5340      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5341    }
5342  }
5343
5344  // Read the remaining operands.
5345  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5346    // Read the first operand.
5347    if (parseOperand(Operands, Mnemonic)) {
5348      Parser.eatToEndOfStatement();
5349      return true;
5350    }
5351
5352    while (getLexer().is(AsmToken::Comma)) {
5353      Parser.Lex();  // Eat the comma.
5354
5355      // Parse and remember the operand.
5356      if (parseOperand(Operands, Mnemonic)) {
5357        Parser.eatToEndOfStatement();
5358        return true;
5359      }
5360    }
5361  }
5362
5363  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5364    SMLoc Loc = getLexer().getLoc();
5365    Parser.eatToEndOfStatement();
5366    return Error(Loc, "unexpected token in argument list");
5367  }
5368
5369  Parser.Lex(); // Consume the EndOfStatement
5370
5371  // Some instructions, mostly Thumb, have forms for the same mnemonic that
5372  // do and don't have a cc_out optional-def operand. With some spot-checks
5373  // of the operand list, we can figure out which variant we're trying to
5374  // parse and adjust accordingly before actually matching. We shouldn't ever
5375  // try to remove a cc_out operand that was explicitly set on the the
5376  // mnemonic, of course (CarrySetting == true). Reason number #317 the
5377  // table driven matcher doesn't fit well with the ARM instruction set.
5378  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5379    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5380    Operands.erase(Operands.begin() + 1);
5381    delete Op;
5382  }
5383
5384  // Some instructions have the same mnemonic, but don't always
5385  // have a predicate. Distinguish them here and delete the
5386  // predicate if needed.
5387  if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5388    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5389    Operands.erase(Operands.begin() + 1);
5390    delete Op;
5391  }
5392
5393  // ARM mode 'blx' need special handling, as the register operand version
5394  // is predicable, but the label operand version is not. So, we can't rely
5395  // on the Mnemonic based checking to correctly figure out when to put
5396  // a k_CondCode operand in the list. If we're trying to match the label
5397  // version, remove the k_CondCode operand here.
5398  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5399      static_cast<ARMOperand*>(Operands[2])->isImm()) {
5400    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5401    Operands.erase(Operands.begin() + 1);
5402    delete Op;
5403  }
5404
5405  // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5406  // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5407  // a single GPRPair reg operand is used in the .td file to replace the two
5408  // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5409  // expressed as a GPRPair, so we have to manually merge them.
5410  // FIXME: We would really like to be able to tablegen'erate this.
5411  if (!isThumb() && Operands.size() > 4 &&
5412      (Mnemonic == "ldrexd" || Mnemonic == "strexd")) {
5413    bool isLoad = (Mnemonic == "ldrexd");
5414    unsigned Idx = isLoad ? 2 : 3;
5415    ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5416    ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5417
5418    const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5419    // Adjust only if Op1 and Op2 are GPRs.
5420    if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5421        MRC.contains(Op2->getReg())) {
5422      unsigned Reg1 = Op1->getReg();
5423      unsigned Reg2 = Op2->getReg();
5424      unsigned Rt = MRI->getEncodingValue(Reg1);
5425      unsigned Rt2 = MRI->getEncodingValue(Reg2);
5426
5427      // Rt2 must be Rt + 1 and Rt must be even.
5428      if (Rt + 1 != Rt2 || (Rt & 1)) {
5429        Error(Op2->getStartLoc(), isLoad ?
5430            "destination operands must be sequential" :
5431            "source operands must be sequential");
5432        return true;
5433      }
5434      unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5435          &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5436      Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5437      Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5438            NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5439      delete Op1;
5440      delete Op2;
5441    }
5442  }
5443
5444  return false;
5445}
5446
5447// Validate context-sensitive operand constraints.
5448
5449// return 'true' if register list contains non-low GPR registers,
5450// 'false' otherwise. If Reg is in the register list or is HiReg, set
5451// 'containsReg' to true.
5452static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5453                                 unsigned HiReg, bool &containsReg) {
5454  containsReg = false;
5455  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5456    unsigned OpReg = Inst.getOperand(i).getReg();
5457    if (OpReg == Reg)
5458      containsReg = true;
5459    // Anything other than a low register isn't legal here.
5460    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5461      return true;
5462  }
5463  return false;
5464}
5465
5466// Check if the specified regisgter is in the register list of the inst,
5467// starting at the indicated operand number.
5468static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5469  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5470    unsigned OpReg = Inst.getOperand(i).getReg();
5471    if (OpReg == Reg)
5472      return true;
5473  }
5474  return false;
5475}
5476
5477// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5478// the ARMInsts array) instead. Getting that here requires awkward
5479// API changes, though. Better way?
5480namespace llvm {
5481extern const MCInstrDesc ARMInsts[];
5482}
5483static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5484  return ARMInsts[Opcode];
5485}
5486
5487// FIXME: We would really like to be able to tablegen'erate this.
5488bool ARMAsmParser::
5489validateInstruction(MCInst &Inst,
5490                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5491  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5492  SMLoc Loc = Operands[0]->getStartLoc();
5493  // Check the IT block state first.
5494  // NOTE: BKPT instruction has the interesting property of being
5495  // allowed in IT blocks, but not being predicable.  It just always
5496  // executes.
5497  if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5498      Inst.getOpcode() != ARM::BKPT) {
5499    unsigned bit = 1;
5500    if (ITState.FirstCond)
5501      ITState.FirstCond = false;
5502    else
5503      bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5504    // The instruction must be predicable.
5505    if (!MCID.isPredicable())
5506      return Error(Loc, "instructions in IT block must be predicable");
5507    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5508    unsigned ITCond = bit ? ITState.Cond :
5509      ARMCC::getOppositeCondition(ITState.Cond);
5510    if (Cond != ITCond) {
5511      // Find the condition code Operand to get its SMLoc information.
5512      SMLoc CondLoc;
5513      for (unsigned i = 1; i < Operands.size(); ++i)
5514        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5515          CondLoc = Operands[i]->getStartLoc();
5516      return Error(CondLoc, "incorrect condition in IT block; got '" +
5517                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5518                   "', but expected '" +
5519                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5520    }
5521  // Check for non-'al' condition codes outside of the IT block.
5522  } else if (isThumbTwo() && MCID.isPredicable() &&
5523             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5524             ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5525             Inst.getOpcode() != ARM::t2B)
5526    return Error(Loc, "predicated instructions must be in IT block");
5527
5528  switch (Inst.getOpcode()) {
5529  case ARM::LDRD:
5530  case ARM::LDRD_PRE:
5531  case ARM::LDRD_POST: {
5532    // Rt2 must be Rt + 1.
5533    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5534    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5535    if (Rt2 != Rt + 1)
5536      return Error(Operands[3]->getStartLoc(),
5537                   "destination operands must be sequential");
5538    return false;
5539  }
5540  case ARM::STRD: {
5541    // Rt2 must be Rt + 1.
5542    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5543    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5544    if (Rt2 != Rt + 1)
5545      return Error(Operands[3]->getStartLoc(),
5546                   "source operands must be sequential");
5547    return false;
5548  }
5549  case ARM::STRD_PRE:
5550  case ARM::STRD_POST: {
5551    // Rt2 must be Rt + 1.
5552    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5553    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5554    if (Rt2 != Rt + 1)
5555      return Error(Operands[3]->getStartLoc(),
5556                   "source operands must be sequential");
5557    return false;
5558  }
5559  case ARM::SBFX:
5560  case ARM::UBFX: {
5561    // width must be in range [1, 32-lsb]
5562    unsigned lsb = Inst.getOperand(2).getImm();
5563    unsigned widthm1 = Inst.getOperand(3).getImm();
5564    if (widthm1 >= 32 - lsb)
5565      return Error(Operands[5]->getStartLoc(),
5566                   "bitfield width must be in range [1,32-lsb]");
5567    return false;
5568  }
5569  case ARM::tLDMIA: {
5570    // If we're parsing Thumb2, the .w variant is available and handles
5571    // most cases that are normally illegal for a Thumb1 LDM
5572    // instruction. We'll make the transformation in processInstruction()
5573    // if necessary.
5574    //
5575    // Thumb LDM instructions are writeback iff the base register is not
5576    // in the register list.
5577    unsigned Rn = Inst.getOperand(0).getReg();
5578    bool hasWritebackToken =
5579      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5580       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5581    bool listContainsBase;
5582    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5583      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5584                   "registers must be in range r0-r7");
5585    // If we should have writeback, then there should be a '!' token.
5586    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5587      return Error(Operands[2]->getStartLoc(),
5588                   "writeback operator '!' expected");
5589    // If we should not have writeback, there must not be a '!'. This is
5590    // true even for the 32-bit wide encodings.
5591    if (listContainsBase && hasWritebackToken)
5592      return Error(Operands[3]->getStartLoc(),
5593                   "writeback operator '!' not allowed when base register "
5594                   "in register list");
5595
5596    break;
5597  }
5598  case ARM::t2LDMIA_UPD: {
5599    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5600      return Error(Operands[4]->getStartLoc(),
5601                   "writeback operator '!' not allowed when base register "
5602                   "in register list");
5603    break;
5604  }
5605  case ARM::tMUL: {
5606    // The second source operand must be the same register as the destination
5607    // operand.
5608    //
5609    // In this case, we must directly check the parsed operands because the
5610    // cvtThumbMultiply() function is written in such a way that it guarantees
5611    // this first statement is always true for the new Inst.  Essentially, the
5612    // destination is unconditionally copied into the second source operand
5613    // without checking to see if it matches what we actually parsed.
5614    if (Operands.size() == 6 &&
5615        (((ARMOperand*)Operands[3])->getReg() !=
5616         ((ARMOperand*)Operands[5])->getReg()) &&
5617        (((ARMOperand*)Operands[3])->getReg() !=
5618         ((ARMOperand*)Operands[4])->getReg())) {
5619      return Error(Operands[3]->getStartLoc(),
5620                   "destination register must match source register");
5621    }
5622    break;
5623  }
5624  // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5625  // so only issue a diagnostic for thumb1. The instructions will be
5626  // switched to the t2 encodings in processInstruction() if necessary.
5627  case ARM::tPOP: {
5628    bool listContainsBase;
5629    if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5630        !isThumbTwo())
5631      return Error(Operands[2]->getStartLoc(),
5632                   "registers must be in range r0-r7 or pc");
5633    break;
5634  }
5635  case ARM::tPUSH: {
5636    bool listContainsBase;
5637    if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5638        !isThumbTwo())
5639      return Error(Operands[2]->getStartLoc(),
5640                   "registers must be in range r0-r7 or lr");
5641    break;
5642  }
5643  case ARM::tSTMIA_UPD: {
5644    bool listContainsBase;
5645    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5646      return Error(Operands[4]->getStartLoc(),
5647                   "registers must be in range r0-r7");
5648    break;
5649  }
5650  case ARM::tADDrSP: {
5651    // If the non-SP source operand and the destination operand are not the
5652    // same, we need thumb2 (for the wide encoding), or we have an error.
5653    if (!isThumbTwo() &&
5654        Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5655      return Error(Operands[4]->getStartLoc(),
5656                   "source register must be the same as destination");
5657    }
5658    break;
5659  }
5660  }
5661
5662  return false;
5663}
5664
5665static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5666  switch(Opc) {
5667  default: llvm_unreachable("unexpected opcode!");
5668  // VST1LN
5669  case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5670  case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5671  case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5672  case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5673  case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5674  case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5675  case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
5676  case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5677  case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5678
5679  // VST2LN
5680  case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5681  case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5682  case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5683  case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5684  case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5685
5686  case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5687  case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5688  case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5689  case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5690  case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5691
5692  case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
5693  case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5694  case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5695  case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5696  case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5697
5698  // VST3LN
5699  case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5700  case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5701  case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5702  case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5703  case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5704  case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5705  case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5706  case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5707  case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5708  case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5709  case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
5710  case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5711  case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5712  case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5713  case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5714
5715  // VST3
5716  case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5717  case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5718  case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5719  case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5720  case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5721  case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5722  case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5723  case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5724  case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5725  case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5726  case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5727  case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5728  case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
5729  case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5730  case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5731  case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
5732  case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5733  case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5734
5735  // VST4LN
5736  case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5737  case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5738  case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5739  case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5740  case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5741  case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5742  case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5743  case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5744  case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5745  case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5746  case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
5747  case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5748  case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5749  case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5750  case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5751
5752  // VST4
5753  case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5754  case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5755  case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5756  case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5757  case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5758  case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5759  case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5760  case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5761  case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5762  case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5763  case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5764  case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5765  case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
5766  case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5767  case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5768  case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
5769  case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5770  case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5771  }
5772}
5773
5774static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5775  switch(Opc) {
5776  default: llvm_unreachable("unexpected opcode!");
5777  // VLD1LN
5778  case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5779  case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5780  case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5781  case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5782  case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5783  case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5784  case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
5785  case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5786  case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5787
5788  // VLD2LN
5789  case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5790  case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5791  case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5792  case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5793  case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5794  case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5795  case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5796  case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5797  case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5798  case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5799  case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
5800  case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5801  case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5802  case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5803  case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5804
5805  // VLD3DUP
5806  case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5807  case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5808  case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5809  case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5810  case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5811  case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5812  case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5813  case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5814  case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5815  case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5816  case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5817  case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5818  case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
5819  case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5820  case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5821  case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5822  case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5823  case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5824
5825  // VLD3LN
5826  case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5827  case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5828  case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5829  case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5830  case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5831  case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5832  case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5833  case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5834  case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5835  case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5836  case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
5837  case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5838  case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5839  case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5840  case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5841
5842  // VLD3
5843  case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5844  case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5845  case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5846  case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5847  case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5848  case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5849  case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5850  case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5851  case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5852  case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5853  case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5854  case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5855  case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
5856  case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5857  case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5858  case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
5859  case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5860  case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5861
5862  // VLD4LN
5863  case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5864  case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5865  case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5866  case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5867  case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5868  case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5869  case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5870  case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5871  case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5872  case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5873  case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
5874  case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5875  case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5876  case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5877  case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5878
5879  // VLD4DUP
5880  case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5881  case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5882  case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5883  case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5884  case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5885  case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5886  case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5887  case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5888  case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5889  case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5890  case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5891  case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5892  case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
5893  case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5894  case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5895  case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5896  case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5897  case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5898
5899  // VLD4
5900  case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5901  case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5902  case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5903  case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5904  case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5905  case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5906  case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5907  case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5908  case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5909  case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5910  case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5911  case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5912  case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
5913  case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5914  case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5915  case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
5916  case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5917  case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5918  }
5919}
5920
5921bool ARMAsmParser::
5922processInstruction(MCInst &Inst,
5923                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5924  switch (Inst.getOpcode()) {
5925  // Alias for alternate form of 'ADR Rd, #imm' instruction.
5926  case ARM::ADDri: {
5927    if (Inst.getOperand(1).getReg() != ARM::PC ||
5928        Inst.getOperand(5).getReg() != 0)
5929      return false;
5930    MCInst TmpInst;
5931    TmpInst.setOpcode(ARM::ADR);
5932    TmpInst.addOperand(Inst.getOperand(0));
5933    TmpInst.addOperand(Inst.getOperand(2));
5934    TmpInst.addOperand(Inst.getOperand(3));
5935    TmpInst.addOperand(Inst.getOperand(4));
5936    Inst = TmpInst;
5937    return true;
5938  }
5939  // Aliases for alternate PC+imm syntax of LDR instructions.
5940  case ARM::t2LDRpcrel:
5941    // Select the narrow version if the immediate will fit.
5942    if (Inst.getOperand(1).getImm() > 0 &&
5943        Inst.getOperand(1).getImm() <= 0xff &&
5944        !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
5945         static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
5946      Inst.setOpcode(ARM::tLDRpci);
5947    else
5948      Inst.setOpcode(ARM::t2LDRpci);
5949    return true;
5950  case ARM::t2LDRBpcrel:
5951    Inst.setOpcode(ARM::t2LDRBpci);
5952    return true;
5953  case ARM::t2LDRHpcrel:
5954    Inst.setOpcode(ARM::t2LDRHpci);
5955    return true;
5956  case ARM::t2LDRSBpcrel:
5957    Inst.setOpcode(ARM::t2LDRSBpci);
5958    return true;
5959  case ARM::t2LDRSHpcrel:
5960    Inst.setOpcode(ARM::t2LDRSHpci);
5961    return true;
5962  // Handle NEON VST complex aliases.
5963  case ARM::VST1LNdWB_register_Asm_8:
5964  case ARM::VST1LNdWB_register_Asm_16:
5965  case ARM::VST1LNdWB_register_Asm_32: {
5966    MCInst TmpInst;
5967    // Shuffle the operands around so the lane index operand is in the
5968    // right place.
5969    unsigned Spacing;
5970    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5971    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5972    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5973    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5974    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5975    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5976    TmpInst.addOperand(Inst.getOperand(1)); // lane
5977    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5978    TmpInst.addOperand(Inst.getOperand(6));
5979    Inst = TmpInst;
5980    return true;
5981  }
5982
5983  case ARM::VST2LNdWB_register_Asm_8:
5984  case ARM::VST2LNdWB_register_Asm_16:
5985  case ARM::VST2LNdWB_register_Asm_32:
5986  case ARM::VST2LNqWB_register_Asm_16:
5987  case ARM::VST2LNqWB_register_Asm_32: {
5988    MCInst TmpInst;
5989    // Shuffle the operands around so the lane index operand is in the
5990    // right place.
5991    unsigned Spacing;
5992    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5993    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5994    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5995    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5996    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5997    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5998    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5999                                            Spacing));
6000    TmpInst.addOperand(Inst.getOperand(1)); // lane
6001    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6002    TmpInst.addOperand(Inst.getOperand(6));
6003    Inst = TmpInst;
6004    return true;
6005  }
6006
6007  case ARM::VST3LNdWB_register_Asm_8:
6008  case ARM::VST3LNdWB_register_Asm_16:
6009  case ARM::VST3LNdWB_register_Asm_32:
6010  case ARM::VST3LNqWB_register_Asm_16:
6011  case ARM::VST3LNqWB_register_Asm_32: {
6012    MCInst TmpInst;
6013    // Shuffle the operands around so the lane index operand is in the
6014    // right place.
6015    unsigned Spacing;
6016    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6017    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6018    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6019    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6020    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6021    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6022    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6023                                            Spacing));
6024    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6025                                            Spacing * 2));
6026    TmpInst.addOperand(Inst.getOperand(1)); // lane
6027    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6028    TmpInst.addOperand(Inst.getOperand(6));
6029    Inst = TmpInst;
6030    return true;
6031  }
6032
6033  case ARM::VST4LNdWB_register_Asm_8:
6034  case ARM::VST4LNdWB_register_Asm_16:
6035  case ARM::VST4LNdWB_register_Asm_32:
6036  case ARM::VST4LNqWB_register_Asm_16:
6037  case ARM::VST4LNqWB_register_Asm_32: {
6038    MCInst TmpInst;
6039    // Shuffle the operands around so the lane index operand is in the
6040    // right place.
6041    unsigned Spacing;
6042    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6043    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6044    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6045    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6046    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6047    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6048    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6049                                            Spacing));
6050    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6051                                            Spacing * 2));
6052    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6053                                            Spacing * 3));
6054    TmpInst.addOperand(Inst.getOperand(1)); // lane
6055    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6056    TmpInst.addOperand(Inst.getOperand(6));
6057    Inst = TmpInst;
6058    return true;
6059  }
6060
6061  case ARM::VST1LNdWB_fixed_Asm_8:
6062  case ARM::VST1LNdWB_fixed_Asm_16:
6063  case ARM::VST1LNdWB_fixed_Asm_32: {
6064    MCInst TmpInst;
6065    // Shuffle the operands around so the lane index operand is in the
6066    // right place.
6067    unsigned Spacing;
6068    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6069    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6070    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6071    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6072    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6073    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6074    TmpInst.addOperand(Inst.getOperand(1)); // lane
6075    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6076    TmpInst.addOperand(Inst.getOperand(5));
6077    Inst = TmpInst;
6078    return true;
6079  }
6080
6081  case ARM::VST2LNdWB_fixed_Asm_8:
6082  case ARM::VST2LNdWB_fixed_Asm_16:
6083  case ARM::VST2LNdWB_fixed_Asm_32:
6084  case ARM::VST2LNqWB_fixed_Asm_16:
6085  case ARM::VST2LNqWB_fixed_Asm_32: {
6086    MCInst TmpInst;
6087    // Shuffle the operands around so the lane index operand is in the
6088    // right place.
6089    unsigned Spacing;
6090    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6091    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6092    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6093    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6094    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6095    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6096    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6097                                            Spacing));
6098    TmpInst.addOperand(Inst.getOperand(1)); // lane
6099    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6100    TmpInst.addOperand(Inst.getOperand(5));
6101    Inst = TmpInst;
6102    return true;
6103  }
6104
6105  case ARM::VST3LNdWB_fixed_Asm_8:
6106  case ARM::VST3LNdWB_fixed_Asm_16:
6107  case ARM::VST3LNdWB_fixed_Asm_32:
6108  case ARM::VST3LNqWB_fixed_Asm_16:
6109  case ARM::VST3LNqWB_fixed_Asm_32: {
6110    MCInst TmpInst;
6111    // Shuffle the operands around so the lane index operand is in the
6112    // right place.
6113    unsigned Spacing;
6114    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6115    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6116    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6117    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6118    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6119    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6120    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6121                                            Spacing));
6122    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6123                                            Spacing * 2));
6124    TmpInst.addOperand(Inst.getOperand(1)); // lane
6125    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6126    TmpInst.addOperand(Inst.getOperand(5));
6127    Inst = TmpInst;
6128    return true;
6129  }
6130
6131  case ARM::VST4LNdWB_fixed_Asm_8:
6132  case ARM::VST4LNdWB_fixed_Asm_16:
6133  case ARM::VST4LNdWB_fixed_Asm_32:
6134  case ARM::VST4LNqWB_fixed_Asm_16:
6135  case ARM::VST4LNqWB_fixed_Asm_32: {
6136    MCInst TmpInst;
6137    // Shuffle the operands around so the lane index operand is in the
6138    // right place.
6139    unsigned Spacing;
6140    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6141    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6142    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6143    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6144    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6145    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6146    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6147                                            Spacing));
6148    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6149                                            Spacing * 2));
6150    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6151                                            Spacing * 3));
6152    TmpInst.addOperand(Inst.getOperand(1)); // lane
6153    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6154    TmpInst.addOperand(Inst.getOperand(5));
6155    Inst = TmpInst;
6156    return true;
6157  }
6158
6159  case ARM::VST1LNdAsm_8:
6160  case ARM::VST1LNdAsm_16:
6161  case ARM::VST1LNdAsm_32: {
6162    MCInst TmpInst;
6163    // Shuffle the operands around so the lane index operand is in the
6164    // right place.
6165    unsigned Spacing;
6166    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6167    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6168    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6169    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6170    TmpInst.addOperand(Inst.getOperand(1)); // lane
6171    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6172    TmpInst.addOperand(Inst.getOperand(5));
6173    Inst = TmpInst;
6174    return true;
6175  }
6176
6177  case ARM::VST2LNdAsm_8:
6178  case ARM::VST2LNdAsm_16:
6179  case ARM::VST2LNdAsm_32:
6180  case ARM::VST2LNqAsm_16:
6181  case ARM::VST2LNqAsm_32: {
6182    MCInst TmpInst;
6183    // Shuffle the operands around so the lane index operand is in the
6184    // right place.
6185    unsigned Spacing;
6186    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6187    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6188    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6189    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6190    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6191                                            Spacing));
6192    TmpInst.addOperand(Inst.getOperand(1)); // lane
6193    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6194    TmpInst.addOperand(Inst.getOperand(5));
6195    Inst = TmpInst;
6196    return true;
6197  }
6198
6199  case ARM::VST3LNdAsm_8:
6200  case ARM::VST3LNdAsm_16:
6201  case ARM::VST3LNdAsm_32:
6202  case ARM::VST3LNqAsm_16:
6203  case ARM::VST3LNqAsm_32: {
6204    MCInst TmpInst;
6205    // Shuffle the operands around so the lane index operand is in the
6206    // right place.
6207    unsigned Spacing;
6208    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6209    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6210    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6211    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6212    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6213                                            Spacing));
6214    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6215                                            Spacing * 2));
6216    TmpInst.addOperand(Inst.getOperand(1)); // lane
6217    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6218    TmpInst.addOperand(Inst.getOperand(5));
6219    Inst = TmpInst;
6220    return true;
6221  }
6222
6223  case ARM::VST4LNdAsm_8:
6224  case ARM::VST4LNdAsm_16:
6225  case ARM::VST4LNdAsm_32:
6226  case ARM::VST4LNqAsm_16:
6227  case ARM::VST4LNqAsm_32: {
6228    MCInst TmpInst;
6229    // Shuffle the operands around so the lane index operand is in the
6230    // right place.
6231    unsigned Spacing;
6232    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6233    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6234    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6235    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6236    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6237                                            Spacing));
6238    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6239                                            Spacing * 2));
6240    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6241                                            Spacing * 3));
6242    TmpInst.addOperand(Inst.getOperand(1)); // lane
6243    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6244    TmpInst.addOperand(Inst.getOperand(5));
6245    Inst = TmpInst;
6246    return true;
6247  }
6248
6249  // Handle NEON VLD complex aliases.
6250  case ARM::VLD1LNdWB_register_Asm_8:
6251  case ARM::VLD1LNdWB_register_Asm_16:
6252  case ARM::VLD1LNdWB_register_Asm_32: {
6253    MCInst TmpInst;
6254    // Shuffle the operands around so the lane index operand is in the
6255    // right place.
6256    unsigned Spacing;
6257    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6258    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6259    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6260    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6261    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6262    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6263    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6264    TmpInst.addOperand(Inst.getOperand(1)); // lane
6265    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6266    TmpInst.addOperand(Inst.getOperand(6));
6267    Inst = TmpInst;
6268    return true;
6269  }
6270
6271  case ARM::VLD2LNdWB_register_Asm_8:
6272  case ARM::VLD2LNdWB_register_Asm_16:
6273  case ARM::VLD2LNdWB_register_Asm_32:
6274  case ARM::VLD2LNqWB_register_Asm_16:
6275  case ARM::VLD2LNqWB_register_Asm_32: {
6276    MCInst TmpInst;
6277    // Shuffle the operands around so the lane index operand is in the
6278    // right place.
6279    unsigned Spacing;
6280    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6281    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6282    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6283                                            Spacing));
6284    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6285    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6286    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6287    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6288    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6289    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6290                                            Spacing));
6291    TmpInst.addOperand(Inst.getOperand(1)); // lane
6292    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6293    TmpInst.addOperand(Inst.getOperand(6));
6294    Inst = TmpInst;
6295    return true;
6296  }
6297
6298  case ARM::VLD3LNdWB_register_Asm_8:
6299  case ARM::VLD3LNdWB_register_Asm_16:
6300  case ARM::VLD3LNdWB_register_Asm_32:
6301  case ARM::VLD3LNqWB_register_Asm_16:
6302  case ARM::VLD3LNqWB_register_Asm_32: {
6303    MCInst TmpInst;
6304    // Shuffle the operands around so the lane index operand is in the
6305    // right place.
6306    unsigned Spacing;
6307    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6308    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6309    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6310                                            Spacing));
6311    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6312                                            Spacing * 2));
6313    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6314    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6315    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6316    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6317    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6318    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6319                                            Spacing));
6320    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6321                                            Spacing * 2));
6322    TmpInst.addOperand(Inst.getOperand(1)); // lane
6323    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6324    TmpInst.addOperand(Inst.getOperand(6));
6325    Inst = TmpInst;
6326    return true;
6327  }
6328
6329  case ARM::VLD4LNdWB_register_Asm_8:
6330  case ARM::VLD4LNdWB_register_Asm_16:
6331  case ARM::VLD4LNdWB_register_Asm_32:
6332  case ARM::VLD4LNqWB_register_Asm_16:
6333  case ARM::VLD4LNqWB_register_Asm_32: {
6334    MCInst TmpInst;
6335    // Shuffle the operands around so the lane index operand is in the
6336    // right place.
6337    unsigned Spacing;
6338    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6339    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6340    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6341                                            Spacing));
6342    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6343                                            Spacing * 2));
6344    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6345                                            Spacing * 3));
6346    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6347    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6348    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6349    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6350    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6351    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6352                                            Spacing));
6353    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6354                                            Spacing * 2));
6355    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6356                                            Spacing * 3));
6357    TmpInst.addOperand(Inst.getOperand(1)); // lane
6358    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6359    TmpInst.addOperand(Inst.getOperand(6));
6360    Inst = TmpInst;
6361    return true;
6362  }
6363
6364  case ARM::VLD1LNdWB_fixed_Asm_8:
6365  case ARM::VLD1LNdWB_fixed_Asm_16:
6366  case ARM::VLD1LNdWB_fixed_Asm_32: {
6367    MCInst TmpInst;
6368    // Shuffle the operands around so the lane index operand is in the
6369    // right place.
6370    unsigned Spacing;
6371    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6372    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6373    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6374    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6375    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6376    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6377    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6378    TmpInst.addOperand(Inst.getOperand(1)); // lane
6379    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6380    TmpInst.addOperand(Inst.getOperand(5));
6381    Inst = TmpInst;
6382    return true;
6383  }
6384
6385  case ARM::VLD2LNdWB_fixed_Asm_8:
6386  case ARM::VLD2LNdWB_fixed_Asm_16:
6387  case ARM::VLD2LNdWB_fixed_Asm_32:
6388  case ARM::VLD2LNqWB_fixed_Asm_16:
6389  case ARM::VLD2LNqWB_fixed_Asm_32: {
6390    MCInst TmpInst;
6391    // Shuffle the operands around so the lane index operand is in the
6392    // right place.
6393    unsigned Spacing;
6394    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6395    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6396    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6397                                            Spacing));
6398    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6399    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6400    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6401    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6402    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6403    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6404                                            Spacing));
6405    TmpInst.addOperand(Inst.getOperand(1)); // lane
6406    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6407    TmpInst.addOperand(Inst.getOperand(5));
6408    Inst = TmpInst;
6409    return true;
6410  }
6411
6412  case ARM::VLD3LNdWB_fixed_Asm_8:
6413  case ARM::VLD3LNdWB_fixed_Asm_16:
6414  case ARM::VLD3LNdWB_fixed_Asm_32:
6415  case ARM::VLD3LNqWB_fixed_Asm_16:
6416  case ARM::VLD3LNqWB_fixed_Asm_32: {
6417    MCInst TmpInst;
6418    // Shuffle the operands around so the lane index operand is in the
6419    // right place.
6420    unsigned Spacing;
6421    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6422    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6423    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6424                                            Spacing));
6425    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6426                                            Spacing * 2));
6427    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6428    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6429    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6430    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6431    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6432    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6433                                            Spacing));
6434    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6435                                            Spacing * 2));
6436    TmpInst.addOperand(Inst.getOperand(1)); // lane
6437    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6438    TmpInst.addOperand(Inst.getOperand(5));
6439    Inst = TmpInst;
6440    return true;
6441  }
6442
6443  case ARM::VLD4LNdWB_fixed_Asm_8:
6444  case ARM::VLD4LNdWB_fixed_Asm_16:
6445  case ARM::VLD4LNdWB_fixed_Asm_32:
6446  case ARM::VLD4LNqWB_fixed_Asm_16:
6447  case ARM::VLD4LNqWB_fixed_Asm_32: {
6448    MCInst TmpInst;
6449    // Shuffle the operands around so the lane index operand is in the
6450    // right place.
6451    unsigned Spacing;
6452    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6453    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6454    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6455                                            Spacing));
6456    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6457                                            Spacing * 2));
6458    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6459                                            Spacing * 3));
6460    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6461    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6462    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6463    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6464    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6465    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6466                                            Spacing));
6467    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6468                                            Spacing * 2));
6469    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6470                                            Spacing * 3));
6471    TmpInst.addOperand(Inst.getOperand(1)); // lane
6472    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6473    TmpInst.addOperand(Inst.getOperand(5));
6474    Inst = TmpInst;
6475    return true;
6476  }
6477
6478  case ARM::VLD1LNdAsm_8:
6479  case ARM::VLD1LNdAsm_16:
6480  case ARM::VLD1LNdAsm_32: {
6481    MCInst TmpInst;
6482    // Shuffle the operands around so the lane index operand is in the
6483    // right place.
6484    unsigned Spacing;
6485    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6486    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6487    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6488    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6489    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6490    TmpInst.addOperand(Inst.getOperand(1)); // lane
6491    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6492    TmpInst.addOperand(Inst.getOperand(5));
6493    Inst = TmpInst;
6494    return true;
6495  }
6496
6497  case ARM::VLD2LNdAsm_8:
6498  case ARM::VLD2LNdAsm_16:
6499  case ARM::VLD2LNdAsm_32:
6500  case ARM::VLD2LNqAsm_16:
6501  case ARM::VLD2LNqAsm_32: {
6502    MCInst TmpInst;
6503    // Shuffle the operands around so the lane index operand is in the
6504    // right place.
6505    unsigned Spacing;
6506    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6507    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6508    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6509                                            Spacing));
6510    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6511    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6512    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6513    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6514                                            Spacing));
6515    TmpInst.addOperand(Inst.getOperand(1)); // lane
6516    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6517    TmpInst.addOperand(Inst.getOperand(5));
6518    Inst = TmpInst;
6519    return true;
6520  }
6521
6522  case ARM::VLD3LNdAsm_8:
6523  case ARM::VLD3LNdAsm_16:
6524  case ARM::VLD3LNdAsm_32:
6525  case ARM::VLD3LNqAsm_16:
6526  case ARM::VLD3LNqAsm_32: {
6527    MCInst TmpInst;
6528    // Shuffle the operands around so the lane index operand is in the
6529    // right place.
6530    unsigned Spacing;
6531    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6532    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6533    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6534                                            Spacing));
6535    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6536                                            Spacing * 2));
6537    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6538    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6539    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6540    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6541                                            Spacing));
6542    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6543                                            Spacing * 2));
6544    TmpInst.addOperand(Inst.getOperand(1)); // lane
6545    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6546    TmpInst.addOperand(Inst.getOperand(5));
6547    Inst = TmpInst;
6548    return true;
6549  }
6550
6551  case ARM::VLD4LNdAsm_8:
6552  case ARM::VLD4LNdAsm_16:
6553  case ARM::VLD4LNdAsm_32:
6554  case ARM::VLD4LNqAsm_16:
6555  case ARM::VLD4LNqAsm_32: {
6556    MCInst TmpInst;
6557    // Shuffle the operands around so the lane index operand is in the
6558    // right place.
6559    unsigned Spacing;
6560    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6561    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6562    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6563                                            Spacing));
6564    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6565                                            Spacing * 2));
6566    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6567                                            Spacing * 3));
6568    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6569    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6570    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6571    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6572                                            Spacing));
6573    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6574                                            Spacing * 2));
6575    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6576                                            Spacing * 3));
6577    TmpInst.addOperand(Inst.getOperand(1)); // lane
6578    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6579    TmpInst.addOperand(Inst.getOperand(5));
6580    Inst = TmpInst;
6581    return true;
6582  }
6583
6584  // VLD3DUP single 3-element structure to all lanes instructions.
6585  case ARM::VLD3DUPdAsm_8:
6586  case ARM::VLD3DUPdAsm_16:
6587  case ARM::VLD3DUPdAsm_32:
6588  case ARM::VLD3DUPqAsm_8:
6589  case ARM::VLD3DUPqAsm_16:
6590  case ARM::VLD3DUPqAsm_32: {
6591    MCInst TmpInst;
6592    unsigned Spacing;
6593    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6594    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6595    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6596                                            Spacing));
6597    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6598                                            Spacing * 2));
6599    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6600    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6601    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6602    TmpInst.addOperand(Inst.getOperand(4));
6603    Inst = TmpInst;
6604    return true;
6605  }
6606
6607  case ARM::VLD3DUPdWB_fixed_Asm_8:
6608  case ARM::VLD3DUPdWB_fixed_Asm_16:
6609  case ARM::VLD3DUPdWB_fixed_Asm_32:
6610  case ARM::VLD3DUPqWB_fixed_Asm_8:
6611  case ARM::VLD3DUPqWB_fixed_Asm_16:
6612  case ARM::VLD3DUPqWB_fixed_Asm_32: {
6613    MCInst TmpInst;
6614    unsigned Spacing;
6615    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6616    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6617    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6618                                            Spacing));
6619    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6620                                            Spacing * 2));
6621    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6622    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6623    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6624    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6625    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6626    TmpInst.addOperand(Inst.getOperand(4));
6627    Inst = TmpInst;
6628    return true;
6629  }
6630
6631  case ARM::VLD3DUPdWB_register_Asm_8:
6632  case ARM::VLD3DUPdWB_register_Asm_16:
6633  case ARM::VLD3DUPdWB_register_Asm_32:
6634  case ARM::VLD3DUPqWB_register_Asm_8:
6635  case ARM::VLD3DUPqWB_register_Asm_16:
6636  case ARM::VLD3DUPqWB_register_Asm_32: {
6637    MCInst TmpInst;
6638    unsigned Spacing;
6639    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6640    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6641    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6642                                            Spacing));
6643    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6644                                            Spacing * 2));
6645    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6646    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6647    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6648    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6649    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6650    TmpInst.addOperand(Inst.getOperand(5));
6651    Inst = TmpInst;
6652    return true;
6653  }
6654
6655  // VLD3 multiple 3-element structure instructions.
6656  case ARM::VLD3dAsm_8:
6657  case ARM::VLD3dAsm_16:
6658  case ARM::VLD3dAsm_32:
6659  case ARM::VLD3qAsm_8:
6660  case ARM::VLD3qAsm_16:
6661  case ARM::VLD3qAsm_32: {
6662    MCInst TmpInst;
6663    unsigned Spacing;
6664    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6665    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6666    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6667                                            Spacing));
6668    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6669                                            Spacing * 2));
6670    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6671    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6672    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6673    TmpInst.addOperand(Inst.getOperand(4));
6674    Inst = TmpInst;
6675    return true;
6676  }
6677
6678  case ARM::VLD3dWB_fixed_Asm_8:
6679  case ARM::VLD3dWB_fixed_Asm_16:
6680  case ARM::VLD3dWB_fixed_Asm_32:
6681  case ARM::VLD3qWB_fixed_Asm_8:
6682  case ARM::VLD3qWB_fixed_Asm_16:
6683  case ARM::VLD3qWB_fixed_Asm_32: {
6684    MCInst TmpInst;
6685    unsigned Spacing;
6686    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6687    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6688    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6689                                            Spacing));
6690    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6691                                            Spacing * 2));
6692    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6693    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6694    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6695    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6696    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6697    TmpInst.addOperand(Inst.getOperand(4));
6698    Inst = TmpInst;
6699    return true;
6700  }
6701
6702  case ARM::VLD3dWB_register_Asm_8:
6703  case ARM::VLD3dWB_register_Asm_16:
6704  case ARM::VLD3dWB_register_Asm_32:
6705  case ARM::VLD3qWB_register_Asm_8:
6706  case ARM::VLD3qWB_register_Asm_16:
6707  case ARM::VLD3qWB_register_Asm_32: {
6708    MCInst TmpInst;
6709    unsigned Spacing;
6710    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6711    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6712    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6713                                            Spacing));
6714    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6715                                            Spacing * 2));
6716    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6717    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6718    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6719    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6720    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6721    TmpInst.addOperand(Inst.getOperand(5));
6722    Inst = TmpInst;
6723    return true;
6724  }
6725
6726  // VLD4DUP single 3-element structure to all lanes instructions.
6727  case ARM::VLD4DUPdAsm_8:
6728  case ARM::VLD4DUPdAsm_16:
6729  case ARM::VLD4DUPdAsm_32:
6730  case ARM::VLD4DUPqAsm_8:
6731  case ARM::VLD4DUPqAsm_16:
6732  case ARM::VLD4DUPqAsm_32: {
6733    MCInst TmpInst;
6734    unsigned Spacing;
6735    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6736    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6737    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6738                                            Spacing));
6739    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6740                                            Spacing * 2));
6741    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6742                                            Spacing * 3));
6743    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6744    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6745    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6746    TmpInst.addOperand(Inst.getOperand(4));
6747    Inst = TmpInst;
6748    return true;
6749  }
6750
6751  case ARM::VLD4DUPdWB_fixed_Asm_8:
6752  case ARM::VLD4DUPdWB_fixed_Asm_16:
6753  case ARM::VLD4DUPdWB_fixed_Asm_32:
6754  case ARM::VLD4DUPqWB_fixed_Asm_8:
6755  case ARM::VLD4DUPqWB_fixed_Asm_16:
6756  case ARM::VLD4DUPqWB_fixed_Asm_32: {
6757    MCInst TmpInst;
6758    unsigned Spacing;
6759    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6760    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6761    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6762                                            Spacing));
6763    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6764                                            Spacing * 2));
6765    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6766                                            Spacing * 3));
6767    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6768    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6769    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6770    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6771    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6772    TmpInst.addOperand(Inst.getOperand(4));
6773    Inst = TmpInst;
6774    return true;
6775  }
6776
6777  case ARM::VLD4DUPdWB_register_Asm_8:
6778  case ARM::VLD4DUPdWB_register_Asm_16:
6779  case ARM::VLD4DUPdWB_register_Asm_32:
6780  case ARM::VLD4DUPqWB_register_Asm_8:
6781  case ARM::VLD4DUPqWB_register_Asm_16:
6782  case ARM::VLD4DUPqWB_register_Asm_32: {
6783    MCInst TmpInst;
6784    unsigned Spacing;
6785    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6786    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6787    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6788                                            Spacing));
6789    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6790                                            Spacing * 2));
6791    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6792                                            Spacing * 3));
6793    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6794    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6795    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6796    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6797    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6798    TmpInst.addOperand(Inst.getOperand(5));
6799    Inst = TmpInst;
6800    return true;
6801  }
6802
6803  // VLD4 multiple 4-element structure instructions.
6804  case ARM::VLD4dAsm_8:
6805  case ARM::VLD4dAsm_16:
6806  case ARM::VLD4dAsm_32:
6807  case ARM::VLD4qAsm_8:
6808  case ARM::VLD4qAsm_16:
6809  case ARM::VLD4qAsm_32: {
6810    MCInst TmpInst;
6811    unsigned Spacing;
6812    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6813    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6814    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6815                                            Spacing));
6816    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6817                                            Spacing * 2));
6818    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6819                                            Spacing * 3));
6820    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6821    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6822    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6823    TmpInst.addOperand(Inst.getOperand(4));
6824    Inst = TmpInst;
6825    return true;
6826  }
6827
6828  case ARM::VLD4dWB_fixed_Asm_8:
6829  case ARM::VLD4dWB_fixed_Asm_16:
6830  case ARM::VLD4dWB_fixed_Asm_32:
6831  case ARM::VLD4qWB_fixed_Asm_8:
6832  case ARM::VLD4qWB_fixed_Asm_16:
6833  case ARM::VLD4qWB_fixed_Asm_32: {
6834    MCInst TmpInst;
6835    unsigned Spacing;
6836    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6837    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6838    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6839                                            Spacing));
6840    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6841                                            Spacing * 2));
6842    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6843                                            Spacing * 3));
6844    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6845    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6846    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6847    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6848    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6849    TmpInst.addOperand(Inst.getOperand(4));
6850    Inst = TmpInst;
6851    return true;
6852  }
6853
6854  case ARM::VLD4dWB_register_Asm_8:
6855  case ARM::VLD4dWB_register_Asm_16:
6856  case ARM::VLD4dWB_register_Asm_32:
6857  case ARM::VLD4qWB_register_Asm_8:
6858  case ARM::VLD4qWB_register_Asm_16:
6859  case ARM::VLD4qWB_register_Asm_32: {
6860    MCInst TmpInst;
6861    unsigned Spacing;
6862    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6863    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6864    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6865                                            Spacing));
6866    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6867                                            Spacing * 2));
6868    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6869                                            Spacing * 3));
6870    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6871    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6872    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6873    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6874    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6875    TmpInst.addOperand(Inst.getOperand(5));
6876    Inst = TmpInst;
6877    return true;
6878  }
6879
6880  // VST3 multiple 3-element structure instructions.
6881  case ARM::VST3dAsm_8:
6882  case ARM::VST3dAsm_16:
6883  case ARM::VST3dAsm_32:
6884  case ARM::VST3qAsm_8:
6885  case ARM::VST3qAsm_16:
6886  case ARM::VST3qAsm_32: {
6887    MCInst TmpInst;
6888    unsigned Spacing;
6889    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6890    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6891    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6892    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6893    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6894                                            Spacing));
6895    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6896                                            Spacing * 2));
6897    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6898    TmpInst.addOperand(Inst.getOperand(4));
6899    Inst = TmpInst;
6900    return true;
6901  }
6902
6903  case ARM::VST3dWB_fixed_Asm_8:
6904  case ARM::VST3dWB_fixed_Asm_16:
6905  case ARM::VST3dWB_fixed_Asm_32:
6906  case ARM::VST3qWB_fixed_Asm_8:
6907  case ARM::VST3qWB_fixed_Asm_16:
6908  case ARM::VST3qWB_fixed_Asm_32: {
6909    MCInst TmpInst;
6910    unsigned Spacing;
6911    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6912    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6913    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6914    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6915    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6916    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6917    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6918                                            Spacing));
6919    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6920                                            Spacing * 2));
6921    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6922    TmpInst.addOperand(Inst.getOperand(4));
6923    Inst = TmpInst;
6924    return true;
6925  }
6926
6927  case ARM::VST3dWB_register_Asm_8:
6928  case ARM::VST3dWB_register_Asm_16:
6929  case ARM::VST3dWB_register_Asm_32:
6930  case ARM::VST3qWB_register_Asm_8:
6931  case ARM::VST3qWB_register_Asm_16:
6932  case ARM::VST3qWB_register_Asm_32: {
6933    MCInst TmpInst;
6934    unsigned Spacing;
6935    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6936    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6937    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6938    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6939    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6940    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6941    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6942                                            Spacing));
6943    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6944                                            Spacing * 2));
6945    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6946    TmpInst.addOperand(Inst.getOperand(5));
6947    Inst = TmpInst;
6948    return true;
6949  }
6950
6951  // VST4 multiple 3-element structure instructions.
6952  case ARM::VST4dAsm_8:
6953  case ARM::VST4dAsm_16:
6954  case ARM::VST4dAsm_32:
6955  case ARM::VST4qAsm_8:
6956  case ARM::VST4qAsm_16:
6957  case ARM::VST4qAsm_32: {
6958    MCInst TmpInst;
6959    unsigned Spacing;
6960    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6961    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6962    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6963    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6964    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6965                                            Spacing));
6966    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6967                                            Spacing * 2));
6968    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6969                                            Spacing * 3));
6970    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6971    TmpInst.addOperand(Inst.getOperand(4));
6972    Inst = TmpInst;
6973    return true;
6974  }
6975
6976  case ARM::VST4dWB_fixed_Asm_8:
6977  case ARM::VST4dWB_fixed_Asm_16:
6978  case ARM::VST4dWB_fixed_Asm_32:
6979  case ARM::VST4qWB_fixed_Asm_8:
6980  case ARM::VST4qWB_fixed_Asm_16:
6981  case ARM::VST4qWB_fixed_Asm_32: {
6982    MCInst TmpInst;
6983    unsigned Spacing;
6984    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6985    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6986    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6987    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6988    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6989    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6990    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6991                                            Spacing));
6992    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6993                                            Spacing * 2));
6994    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6995                                            Spacing * 3));
6996    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6997    TmpInst.addOperand(Inst.getOperand(4));
6998    Inst = TmpInst;
6999    return true;
7000  }
7001
7002  case ARM::VST4dWB_register_Asm_8:
7003  case ARM::VST4dWB_register_Asm_16:
7004  case ARM::VST4dWB_register_Asm_32:
7005  case ARM::VST4qWB_register_Asm_8:
7006  case ARM::VST4qWB_register_Asm_16:
7007  case ARM::VST4qWB_register_Asm_32: {
7008    MCInst TmpInst;
7009    unsigned Spacing;
7010    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7011    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7012    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7013    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7014    TmpInst.addOperand(Inst.getOperand(3)); // Rm
7015    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7016    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7017                                            Spacing));
7018    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7019                                            Spacing * 2));
7020    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7021                                            Spacing * 3));
7022    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7023    TmpInst.addOperand(Inst.getOperand(5));
7024    Inst = TmpInst;
7025    return true;
7026  }
7027
7028  // Handle encoding choice for the shift-immediate instructions.
7029  case ARM::t2LSLri:
7030  case ARM::t2LSRri:
7031  case ARM::t2ASRri: {
7032    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7033        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7034        Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7035        !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
7036         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
7037      unsigned NewOpc;
7038      switch (Inst.getOpcode()) {
7039      default: llvm_unreachable("unexpected opcode");
7040      case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7041      case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7042      case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7043      }
7044      // The Thumb1 operands aren't in the same order. Awesome, eh?
7045      MCInst TmpInst;
7046      TmpInst.setOpcode(NewOpc);
7047      TmpInst.addOperand(Inst.getOperand(0));
7048      TmpInst.addOperand(Inst.getOperand(5));
7049      TmpInst.addOperand(Inst.getOperand(1));
7050      TmpInst.addOperand(Inst.getOperand(2));
7051      TmpInst.addOperand(Inst.getOperand(3));
7052      TmpInst.addOperand(Inst.getOperand(4));
7053      Inst = TmpInst;
7054      return true;
7055    }
7056    return false;
7057  }
7058
7059  // Handle the Thumb2 mode MOV complex aliases.
7060  case ARM::t2MOVsr:
7061  case ARM::t2MOVSsr: {
7062    // Which instruction to expand to depends on the CCOut operand and
7063    // whether we're in an IT block if the register operands are low
7064    // registers.
7065    bool isNarrow = false;
7066    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7067        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7068        isARMLowRegister(Inst.getOperand(2).getReg()) &&
7069        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7070        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7071      isNarrow = true;
7072    MCInst TmpInst;
7073    unsigned newOpc;
7074    switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7075    default: llvm_unreachable("unexpected opcode!");
7076    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7077    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7078    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7079    case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
7080    }
7081    TmpInst.setOpcode(newOpc);
7082    TmpInst.addOperand(Inst.getOperand(0)); // Rd
7083    if (isNarrow)
7084      TmpInst.addOperand(MCOperand::CreateReg(
7085          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7086    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7087    TmpInst.addOperand(Inst.getOperand(2)); // Rm
7088    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7089    TmpInst.addOperand(Inst.getOperand(5));
7090    if (!isNarrow)
7091      TmpInst.addOperand(MCOperand::CreateReg(
7092          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7093    Inst = TmpInst;
7094    return true;
7095  }
7096  case ARM::t2MOVsi:
7097  case ARM::t2MOVSsi: {
7098    // Which instruction to expand to depends on the CCOut operand and
7099    // whether we're in an IT block if the register operands are low
7100    // registers.
7101    bool isNarrow = false;
7102    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7103        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7104        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7105      isNarrow = true;
7106    MCInst TmpInst;
7107    unsigned newOpc;
7108    switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7109    default: llvm_unreachable("unexpected opcode!");
7110    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7111    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7112    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7113    case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7114    case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7115    }
7116    unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7117    if (Amount == 32) Amount = 0;
7118    TmpInst.setOpcode(newOpc);
7119    TmpInst.addOperand(Inst.getOperand(0)); // Rd
7120    if (isNarrow)
7121      TmpInst.addOperand(MCOperand::CreateReg(
7122          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7123    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7124    if (newOpc != ARM::t2RRX)
7125      TmpInst.addOperand(MCOperand::CreateImm(Amount));
7126    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7127    TmpInst.addOperand(Inst.getOperand(4));
7128    if (!isNarrow)
7129      TmpInst.addOperand(MCOperand::CreateReg(
7130          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7131    Inst = TmpInst;
7132    return true;
7133  }
7134  // Handle the ARM mode MOV complex aliases.
7135  case ARM::ASRr:
7136  case ARM::LSRr:
7137  case ARM::LSLr:
7138  case ARM::RORr: {
7139    ARM_AM::ShiftOpc ShiftTy;
7140    switch(Inst.getOpcode()) {
7141    default: llvm_unreachable("unexpected opcode!");
7142    case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7143    case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7144    case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7145    case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7146    }
7147    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7148    MCInst TmpInst;
7149    TmpInst.setOpcode(ARM::MOVsr);
7150    TmpInst.addOperand(Inst.getOperand(0)); // Rd
7151    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7152    TmpInst.addOperand(Inst.getOperand(2)); // Rm
7153    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7154    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7155    TmpInst.addOperand(Inst.getOperand(4));
7156    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7157    Inst = TmpInst;
7158    return true;
7159  }
7160  case ARM::ASRi:
7161  case ARM::LSRi:
7162  case ARM::LSLi:
7163  case ARM::RORi: {
7164    ARM_AM::ShiftOpc ShiftTy;
7165    switch(Inst.getOpcode()) {
7166    default: llvm_unreachable("unexpected opcode!");
7167    case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7168    case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7169    case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7170    case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7171    }
7172    // A shift by zero is a plain MOVr, not a MOVsi.
7173    unsigned Amt = Inst.getOperand(2).getImm();
7174    unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7175    // A shift by 32 should be encoded as 0 when permitted
7176    if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7177      Amt = 0;
7178    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7179    MCInst TmpInst;
7180    TmpInst.setOpcode(Opc);
7181    TmpInst.addOperand(Inst.getOperand(0)); // Rd
7182    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7183    if (Opc == ARM::MOVsi)
7184      TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7185    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7186    TmpInst.addOperand(Inst.getOperand(4));
7187    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7188    Inst = TmpInst;
7189    return true;
7190  }
7191  case ARM::RRXi: {
7192    unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7193    MCInst TmpInst;
7194    TmpInst.setOpcode(ARM::MOVsi);
7195    TmpInst.addOperand(Inst.getOperand(0)); // Rd
7196    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7197    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7198    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7199    TmpInst.addOperand(Inst.getOperand(3));
7200    TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7201    Inst = TmpInst;
7202    return true;
7203  }
7204  case ARM::t2LDMIA_UPD: {
7205    // If this is a load of a single register, then we should use
7206    // a post-indexed LDR instruction instead, per the ARM ARM.
7207    if (Inst.getNumOperands() != 5)
7208      return false;
7209    MCInst TmpInst;
7210    TmpInst.setOpcode(ARM::t2LDR_POST);
7211    TmpInst.addOperand(Inst.getOperand(4)); // Rt
7212    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7213    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7214    TmpInst.addOperand(MCOperand::CreateImm(4));
7215    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7216    TmpInst.addOperand(Inst.getOperand(3));
7217    Inst = TmpInst;
7218    return true;
7219  }
7220  case ARM::t2STMDB_UPD: {
7221    // If this is a store of a single register, then we should use
7222    // a pre-indexed STR instruction instead, per the ARM ARM.
7223    if (Inst.getNumOperands() != 5)
7224      return false;
7225    MCInst TmpInst;
7226    TmpInst.setOpcode(ARM::t2STR_PRE);
7227    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7228    TmpInst.addOperand(Inst.getOperand(4)); // Rt
7229    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7230    TmpInst.addOperand(MCOperand::CreateImm(-4));
7231    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7232    TmpInst.addOperand(Inst.getOperand(3));
7233    Inst = TmpInst;
7234    return true;
7235  }
7236  case ARM::LDMIA_UPD:
7237    // If this is a load of a single register via a 'pop', then we should use
7238    // a post-indexed LDR instruction instead, per the ARM ARM.
7239    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7240        Inst.getNumOperands() == 5) {
7241      MCInst TmpInst;
7242      TmpInst.setOpcode(ARM::LDR_POST_IMM);
7243      TmpInst.addOperand(Inst.getOperand(4)); // Rt
7244      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7245      TmpInst.addOperand(Inst.getOperand(1)); // Rn
7246      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
7247      TmpInst.addOperand(MCOperand::CreateImm(4));
7248      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7249      TmpInst.addOperand(Inst.getOperand(3));
7250      Inst = TmpInst;
7251      return true;
7252    }
7253    break;
7254  case ARM::STMDB_UPD:
7255    // If this is a store of a single register via a 'push', then we should use
7256    // a pre-indexed STR instruction instead, per the ARM ARM.
7257    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7258        Inst.getNumOperands() == 5) {
7259      MCInst TmpInst;
7260      TmpInst.setOpcode(ARM::STR_PRE_IMM);
7261      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7262      TmpInst.addOperand(Inst.getOperand(4)); // Rt
7263      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7264      TmpInst.addOperand(MCOperand::CreateImm(-4));
7265      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7266      TmpInst.addOperand(Inst.getOperand(3));
7267      Inst = TmpInst;
7268    }
7269    break;
7270  case ARM::t2ADDri12:
7271    // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7272    // mnemonic was used (not "addw"), encoding T3 is preferred.
7273    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7274        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7275      break;
7276    Inst.setOpcode(ARM::t2ADDri);
7277    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7278    break;
7279  case ARM::t2SUBri12:
7280    // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7281    // mnemonic was used (not "subw"), encoding T3 is preferred.
7282    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7283        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7284      break;
7285    Inst.setOpcode(ARM::t2SUBri);
7286    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7287    break;
7288  case ARM::tADDi8:
7289    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7290    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7291    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7292    // to encoding T1 if <Rd> is omitted."
7293    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7294      Inst.setOpcode(ARM::tADDi3);
7295      return true;
7296    }
7297    break;
7298  case ARM::tSUBi8:
7299    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7300    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7301    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7302    // to encoding T1 if <Rd> is omitted."
7303    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7304      Inst.setOpcode(ARM::tSUBi3);
7305      return true;
7306    }
7307    break;
7308  case ARM::t2ADDri:
7309  case ARM::t2SUBri: {
7310    // If the destination and first source operand are the same, and
7311    // the flags are compatible with the current IT status, use encoding T2
7312    // instead of T3. For compatibility with the system 'as'. Make sure the
7313    // wide encoding wasn't explicit.
7314    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7315        !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7316        (unsigned)Inst.getOperand(2).getImm() > 255 ||
7317        ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7318        (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7319        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7320         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7321      break;
7322    MCInst TmpInst;
7323    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7324                      ARM::tADDi8 : ARM::tSUBi8);
7325    TmpInst.addOperand(Inst.getOperand(0));
7326    TmpInst.addOperand(Inst.getOperand(5));
7327    TmpInst.addOperand(Inst.getOperand(0));
7328    TmpInst.addOperand(Inst.getOperand(2));
7329    TmpInst.addOperand(Inst.getOperand(3));
7330    TmpInst.addOperand(Inst.getOperand(4));
7331    Inst = TmpInst;
7332    return true;
7333  }
7334  case ARM::t2ADDrr: {
7335    // If the destination and first source operand are the same, and
7336    // there's no setting of the flags, use encoding T2 instead of T3.
7337    // Note that this is only for ADD, not SUB. This mirrors the system
7338    // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7339    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7340        Inst.getOperand(5).getReg() != 0 ||
7341        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7342         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7343      break;
7344    MCInst TmpInst;
7345    TmpInst.setOpcode(ARM::tADDhirr);
7346    TmpInst.addOperand(Inst.getOperand(0));
7347    TmpInst.addOperand(Inst.getOperand(0));
7348    TmpInst.addOperand(Inst.getOperand(2));
7349    TmpInst.addOperand(Inst.getOperand(3));
7350    TmpInst.addOperand(Inst.getOperand(4));
7351    Inst = TmpInst;
7352    return true;
7353  }
7354  case ARM::tADDrSP: {
7355    // If the non-SP source operand and the destination operand are not the
7356    // same, we need to use the 32-bit encoding if it's available.
7357    if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7358      Inst.setOpcode(ARM::t2ADDrr);
7359      Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7360      return true;
7361    }
7362    break;
7363  }
7364  case ARM::tB:
7365    // A Thumb conditional branch outside of an IT block is a tBcc.
7366    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7367      Inst.setOpcode(ARM::tBcc);
7368      return true;
7369    }
7370    break;
7371  case ARM::t2B:
7372    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7373    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7374      Inst.setOpcode(ARM::t2Bcc);
7375      return true;
7376    }
7377    break;
7378  case ARM::t2Bcc:
7379    // If the conditional is AL or we're in an IT block, we really want t2B.
7380    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7381      Inst.setOpcode(ARM::t2B);
7382      return true;
7383    }
7384    break;
7385  case ARM::tBcc:
7386    // If the conditional is AL, we really want tB.
7387    if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7388      Inst.setOpcode(ARM::tB);
7389      return true;
7390    }
7391    break;
7392  case ARM::tLDMIA: {
7393    // If the register list contains any high registers, or if the writeback
7394    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7395    // instead if we're in Thumb2. Otherwise, this should have generated
7396    // an error in validateInstruction().
7397    unsigned Rn = Inst.getOperand(0).getReg();
7398    bool hasWritebackToken =
7399      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7400       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7401    bool listContainsBase;
7402    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7403        (!listContainsBase && !hasWritebackToken) ||
7404        (listContainsBase && hasWritebackToken)) {
7405      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7406      assert (isThumbTwo());
7407      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7408      // If we're switching to the updating version, we need to insert
7409      // the writeback tied operand.
7410      if (hasWritebackToken)
7411        Inst.insert(Inst.begin(),
7412                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7413      return true;
7414    }
7415    break;
7416  }
7417  case ARM::tSTMIA_UPD: {
7418    // If the register list contains any high registers, we need to use
7419    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7420    // should have generated an error in validateInstruction().
7421    unsigned Rn = Inst.getOperand(0).getReg();
7422    bool listContainsBase;
7423    if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7424      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7425      assert (isThumbTwo());
7426      Inst.setOpcode(ARM::t2STMIA_UPD);
7427      return true;
7428    }
7429    break;
7430  }
7431  case ARM::tPOP: {
7432    bool listContainsBase;
7433    // If the register list contains any high registers, we need to use
7434    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7435    // should have generated an error in validateInstruction().
7436    if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7437      return false;
7438    assert (isThumbTwo());
7439    Inst.setOpcode(ARM::t2LDMIA_UPD);
7440    // Add the base register and writeback operands.
7441    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7442    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7443    return true;
7444  }
7445  case ARM::tPUSH: {
7446    bool listContainsBase;
7447    if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7448      return false;
7449    assert (isThumbTwo());
7450    Inst.setOpcode(ARM::t2STMDB_UPD);
7451    // Add the base register and writeback operands.
7452    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7453    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7454    return true;
7455  }
7456  case ARM::t2MOVi: {
7457    // If we can use the 16-bit encoding and the user didn't explicitly
7458    // request the 32-bit variant, transform it here.
7459    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7460        (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7461        ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7462         Inst.getOperand(4).getReg() == ARM::CPSR) ||
7463        (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7464        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7465         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7466      // The operands aren't in the same order for tMOVi8...
7467      MCInst TmpInst;
7468      TmpInst.setOpcode(ARM::tMOVi8);
7469      TmpInst.addOperand(Inst.getOperand(0));
7470      TmpInst.addOperand(Inst.getOperand(4));
7471      TmpInst.addOperand(Inst.getOperand(1));
7472      TmpInst.addOperand(Inst.getOperand(2));
7473      TmpInst.addOperand(Inst.getOperand(3));
7474      Inst = TmpInst;
7475      return true;
7476    }
7477    break;
7478  }
7479  case ARM::t2MOVr: {
7480    // If we can use the 16-bit encoding and the user didn't explicitly
7481    // request the 32-bit variant, transform it here.
7482    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7483        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7484        Inst.getOperand(2).getImm() == ARMCC::AL &&
7485        Inst.getOperand(4).getReg() == ARM::CPSR &&
7486        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7487         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7488      // The operands aren't the same for tMOV[S]r... (no cc_out)
7489      MCInst TmpInst;
7490      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7491      TmpInst.addOperand(Inst.getOperand(0));
7492      TmpInst.addOperand(Inst.getOperand(1));
7493      TmpInst.addOperand(Inst.getOperand(2));
7494      TmpInst.addOperand(Inst.getOperand(3));
7495      Inst = TmpInst;
7496      return true;
7497    }
7498    break;
7499  }
7500  case ARM::t2SXTH:
7501  case ARM::t2SXTB:
7502  case ARM::t2UXTH:
7503  case ARM::t2UXTB: {
7504    // If we can use the 16-bit encoding and the user didn't explicitly
7505    // request the 32-bit variant, transform it here.
7506    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7507        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7508        Inst.getOperand(2).getImm() == 0 &&
7509        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7510         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7511      unsigned NewOpc;
7512      switch (Inst.getOpcode()) {
7513      default: llvm_unreachable("Illegal opcode!");
7514      case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7515      case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7516      case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7517      case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7518      }
7519      // The operands aren't the same for thumb1 (no rotate operand).
7520      MCInst TmpInst;
7521      TmpInst.setOpcode(NewOpc);
7522      TmpInst.addOperand(Inst.getOperand(0));
7523      TmpInst.addOperand(Inst.getOperand(1));
7524      TmpInst.addOperand(Inst.getOperand(3));
7525      TmpInst.addOperand(Inst.getOperand(4));
7526      Inst = TmpInst;
7527      return true;
7528    }
7529    break;
7530  }
7531  case ARM::MOVsi: {
7532    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7533    // rrx shifts and asr/lsr of #32 is encoded as 0
7534    if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7535      return false;
7536    if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7537      // Shifting by zero is accepted as a vanilla 'MOVr'
7538      MCInst TmpInst;
7539      TmpInst.setOpcode(ARM::MOVr);
7540      TmpInst.addOperand(Inst.getOperand(0));
7541      TmpInst.addOperand(Inst.getOperand(1));
7542      TmpInst.addOperand(Inst.getOperand(3));
7543      TmpInst.addOperand(Inst.getOperand(4));
7544      TmpInst.addOperand(Inst.getOperand(5));
7545      Inst = TmpInst;
7546      return true;
7547    }
7548    return false;
7549  }
7550  case ARM::ANDrsi:
7551  case ARM::ORRrsi:
7552  case ARM::EORrsi:
7553  case ARM::BICrsi:
7554  case ARM::SUBrsi:
7555  case ARM::ADDrsi: {
7556    unsigned newOpc;
7557    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7558    if (SOpc == ARM_AM::rrx) return false;
7559    switch (Inst.getOpcode()) {
7560    default: llvm_unreachable("unexpected opcode!");
7561    case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7562    case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7563    case ARM::EORrsi: newOpc = ARM::EORrr; break;
7564    case ARM::BICrsi: newOpc = ARM::BICrr; break;
7565    case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7566    case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7567    }
7568    // If the shift is by zero, use the non-shifted instruction definition.
7569    // The exception is for right shifts, where 0 == 32
7570    if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7571        !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7572      MCInst TmpInst;
7573      TmpInst.setOpcode(newOpc);
7574      TmpInst.addOperand(Inst.getOperand(0));
7575      TmpInst.addOperand(Inst.getOperand(1));
7576      TmpInst.addOperand(Inst.getOperand(2));
7577      TmpInst.addOperand(Inst.getOperand(4));
7578      TmpInst.addOperand(Inst.getOperand(5));
7579      TmpInst.addOperand(Inst.getOperand(6));
7580      Inst = TmpInst;
7581      return true;
7582    }
7583    return false;
7584  }
7585  case ARM::ITasm:
7586  case ARM::t2IT: {
7587    // The mask bits for all but the first condition are represented as
7588    // the low bit of the condition code value implies 't'. We currently
7589    // always have 1 implies 't', so XOR toggle the bits if the low bit
7590    // of the condition code is zero.
7591    MCOperand &MO = Inst.getOperand(1);
7592    unsigned Mask = MO.getImm();
7593    unsigned OrigMask = Mask;
7594    unsigned TZ = countTrailingZeros(Mask);
7595    if ((Inst.getOperand(0).getImm() & 1) == 0) {
7596      assert(Mask && TZ <= 3 && "illegal IT mask value!");
7597      Mask ^= (0xE << TZ) & 0xF;
7598    }
7599    MO.setImm(Mask);
7600
7601    // Set up the IT block state according to the IT instruction we just
7602    // matched.
7603    assert(!inITBlock() && "nested IT blocks?!");
7604    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7605    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7606    ITState.CurPosition = 0;
7607    ITState.FirstCond = true;
7608    break;
7609  }
7610  case ARM::t2LSLrr:
7611  case ARM::t2LSRrr:
7612  case ARM::t2ASRrr:
7613  case ARM::t2SBCrr:
7614  case ARM::t2RORrr:
7615  case ARM::t2BICrr:
7616  {
7617    // Assemblers should use the narrow encodings of these instructions when permissible.
7618    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7619         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7620        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7621        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7622         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7623        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7624         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7625      unsigned NewOpc;
7626      switch (Inst.getOpcode()) {
7627        default: llvm_unreachable("unexpected opcode");
7628        case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7629        case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7630        case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7631        case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7632        case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7633        case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7634      }
7635      MCInst TmpInst;
7636      TmpInst.setOpcode(NewOpc);
7637      TmpInst.addOperand(Inst.getOperand(0));
7638      TmpInst.addOperand(Inst.getOperand(5));
7639      TmpInst.addOperand(Inst.getOperand(1));
7640      TmpInst.addOperand(Inst.getOperand(2));
7641      TmpInst.addOperand(Inst.getOperand(3));
7642      TmpInst.addOperand(Inst.getOperand(4));
7643      Inst = TmpInst;
7644      return true;
7645    }
7646    return false;
7647  }
7648  case ARM::t2ANDrr:
7649  case ARM::t2EORrr:
7650  case ARM::t2ADCrr:
7651  case ARM::t2ORRrr:
7652  {
7653    // Assemblers should use the narrow encodings of these instructions when permissible.
7654    // These instructions are special in that they are commutable, so shorter encodings
7655    // are available more often.
7656    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7657         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7658        (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7659         Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7660        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7661         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7662        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7663         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7664      unsigned NewOpc;
7665      switch (Inst.getOpcode()) {
7666        default: llvm_unreachable("unexpected opcode");
7667        case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7668        case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7669        case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7670        case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7671      }
7672      MCInst TmpInst;
7673      TmpInst.setOpcode(NewOpc);
7674      TmpInst.addOperand(Inst.getOperand(0));
7675      TmpInst.addOperand(Inst.getOperand(5));
7676      if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7677        TmpInst.addOperand(Inst.getOperand(1));
7678        TmpInst.addOperand(Inst.getOperand(2));
7679      } else {
7680        TmpInst.addOperand(Inst.getOperand(2));
7681        TmpInst.addOperand(Inst.getOperand(1));
7682      }
7683      TmpInst.addOperand(Inst.getOperand(3));
7684      TmpInst.addOperand(Inst.getOperand(4));
7685      Inst = TmpInst;
7686      return true;
7687    }
7688    return false;
7689  }
7690  }
7691  return false;
7692}
7693
7694unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7695  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7696  // suffix depending on whether they're in an IT block or not.
7697  unsigned Opc = Inst.getOpcode();
7698  const MCInstrDesc &MCID = getInstDesc(Opc);
7699  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7700    assert(MCID.hasOptionalDef() &&
7701           "optionally flag setting instruction missing optional def operand");
7702    assert(MCID.NumOperands == Inst.getNumOperands() &&
7703           "operand count mismatch!");
7704    // Find the optional-def operand (cc_out).
7705    unsigned OpNo;
7706    for (OpNo = 0;
7707         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7708         ++OpNo)
7709      ;
7710    // If we're parsing Thumb1, reject it completely.
7711    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7712      return Match_MnemonicFail;
7713    // If we're parsing Thumb2, which form is legal depends on whether we're
7714    // in an IT block.
7715    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7716        !inITBlock())
7717      return Match_RequiresITBlock;
7718    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7719        inITBlock())
7720      return Match_RequiresNotITBlock;
7721  }
7722  // Some high-register supporting Thumb1 encodings only allow both registers
7723  // to be from r0-r7 when in Thumb2.
7724  else if (Opc == ARM::tADDhirr && isThumbOne() &&
7725           isARMLowRegister(Inst.getOperand(1).getReg()) &&
7726           isARMLowRegister(Inst.getOperand(2).getReg()))
7727    return Match_RequiresThumb2;
7728  // Others only require ARMv6 or later.
7729  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7730           isARMLowRegister(Inst.getOperand(0).getReg()) &&
7731           isARMLowRegister(Inst.getOperand(1).getReg()))
7732    return Match_RequiresV6;
7733  return Match_Success;
7734}
7735
7736static const char *getSubtargetFeatureName(unsigned Val);
7737bool ARMAsmParser::
7738MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7739                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7740                        MCStreamer &Out, unsigned &ErrorInfo,
7741                        bool MatchingInlineAsm) {
7742  MCInst Inst;
7743  unsigned MatchResult;
7744
7745  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7746                                     MatchingInlineAsm);
7747  switch (MatchResult) {
7748  default: break;
7749  case Match_Success:
7750    // Context sensitive operand constraints aren't handled by the matcher,
7751    // so check them here.
7752    if (validateInstruction(Inst, Operands)) {
7753      // Still progress the IT block, otherwise one wrong condition causes
7754      // nasty cascading errors.
7755      forwardITPosition();
7756      return true;
7757    }
7758
7759    // Some instructions need post-processing to, for example, tweak which
7760    // encoding is selected. Loop on it while changes happen so the
7761    // individual transformations can chain off each other. E.g.,
7762    // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7763    while (processInstruction(Inst, Operands))
7764      ;
7765
7766    // Only move forward at the very end so that everything in validate
7767    // and process gets a consistent answer about whether we're in an IT
7768    // block.
7769    forwardITPosition();
7770
7771    // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7772    // doesn't actually encode.
7773    if (Inst.getOpcode() == ARM::ITasm)
7774      return false;
7775
7776    Inst.setLoc(IDLoc);
7777    Out.EmitInstruction(Inst);
7778    return false;
7779  case Match_MissingFeature: {
7780    assert(ErrorInfo && "Unknown missing feature!");
7781    // Special case the error message for the very common case where only
7782    // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7783    std::string Msg = "instruction requires:";
7784    unsigned Mask = 1;
7785    for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7786      if (ErrorInfo & Mask) {
7787        Msg += " ";
7788        Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7789      }
7790      Mask <<= 1;
7791    }
7792    return Error(IDLoc, Msg);
7793  }
7794  case Match_InvalidOperand: {
7795    SMLoc ErrorLoc = IDLoc;
7796    if (ErrorInfo != ~0U) {
7797      if (ErrorInfo >= Operands.size())
7798        return Error(IDLoc, "too few operands for instruction");
7799
7800      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7801      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7802    }
7803
7804    return Error(ErrorLoc, "invalid operand for instruction");
7805  }
7806  case Match_MnemonicFail:
7807    return Error(IDLoc, "invalid instruction",
7808                 ((ARMOperand*)Operands[0])->getLocRange());
7809  case Match_RequiresNotITBlock:
7810    return Error(IDLoc, "flag setting instruction only valid outside IT block");
7811  case Match_RequiresITBlock:
7812    return Error(IDLoc, "instruction only valid inside IT block");
7813  case Match_RequiresV6:
7814    return Error(IDLoc, "instruction variant requires ARMv6 or later");
7815  case Match_RequiresThumb2:
7816    return Error(IDLoc, "instruction variant requires Thumb2");
7817  case Match_ImmRange0_4: {
7818    SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7819    if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7820    return Error(ErrorLoc, "immediate operand must be in the range [0,4]");
7821  }
7822  case Match_ImmRange0_15: {
7823    SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7824    if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7825    return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7826  }
7827  }
7828
7829  llvm_unreachable("Implement any new match types added!");
7830}
7831
7832/// parseDirective parses the arm specific directives
7833bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7834  StringRef IDVal = DirectiveID.getIdentifier();
7835  if (IDVal == ".word")
7836    return parseDirectiveWord(4, DirectiveID.getLoc());
7837  else if (IDVal == ".thumb")
7838    return parseDirectiveThumb(DirectiveID.getLoc());
7839  else if (IDVal == ".arm")
7840    return parseDirectiveARM(DirectiveID.getLoc());
7841  else if (IDVal == ".thumb_func")
7842    return parseDirectiveThumbFunc(DirectiveID.getLoc());
7843  else if (IDVal == ".code")
7844    return parseDirectiveCode(DirectiveID.getLoc());
7845  else if (IDVal == ".syntax")
7846    return parseDirectiveSyntax(DirectiveID.getLoc());
7847  else if (IDVal == ".unreq")
7848    return parseDirectiveUnreq(DirectiveID.getLoc());
7849  else if (IDVal == ".arch")
7850    return parseDirectiveArch(DirectiveID.getLoc());
7851  else if (IDVal == ".eabi_attribute")
7852    return parseDirectiveEabiAttr(DirectiveID.getLoc());
7853  else if (IDVal == ".fnstart")
7854    return parseDirectiveFnStart(DirectiveID.getLoc());
7855  else if (IDVal == ".fnend")
7856    return parseDirectiveFnEnd(DirectiveID.getLoc());
7857  else if (IDVal == ".cantunwind")
7858    return parseDirectiveCantUnwind(DirectiveID.getLoc());
7859  else if (IDVal == ".personality")
7860    return parseDirectivePersonality(DirectiveID.getLoc());
7861  else if (IDVal == ".handlerdata")
7862    return parseDirectiveHandlerData(DirectiveID.getLoc());
7863  else if (IDVal == ".setfp")
7864    return parseDirectiveSetFP(DirectiveID.getLoc());
7865  else if (IDVal == ".pad")
7866    return parseDirectivePad(DirectiveID.getLoc());
7867  else if (IDVal == ".save")
7868    return parseDirectiveRegSave(DirectiveID.getLoc(), false);
7869  else if (IDVal == ".vsave")
7870    return parseDirectiveRegSave(DirectiveID.getLoc(), true);
7871  return true;
7872}
7873
7874/// parseDirectiveWord
7875///  ::= .word [ expression (, expression)* ]
7876bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7877  if (getLexer().isNot(AsmToken::EndOfStatement)) {
7878    for (;;) {
7879      const MCExpr *Value;
7880      if (getParser().parseExpression(Value))
7881        return true;
7882
7883      getParser().getStreamer().EmitValue(Value, Size);
7884
7885      if (getLexer().is(AsmToken::EndOfStatement))
7886        break;
7887
7888      // FIXME: Improve diagnostic.
7889      if (getLexer().isNot(AsmToken::Comma))
7890        return Error(L, "unexpected token in directive");
7891      Parser.Lex();
7892    }
7893  }
7894
7895  Parser.Lex();
7896  return false;
7897}
7898
7899/// parseDirectiveThumb
7900///  ::= .thumb
7901bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7902  if (getLexer().isNot(AsmToken::EndOfStatement))
7903    return Error(L, "unexpected token in directive");
7904  Parser.Lex();
7905
7906  if (!hasThumb())
7907    return Error(L, "target does not support Thumb mode");
7908
7909  if (!isThumb())
7910    SwitchMode();
7911  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7912  return false;
7913}
7914
7915/// parseDirectiveARM
7916///  ::= .arm
7917bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7918  if (getLexer().isNot(AsmToken::EndOfStatement))
7919    return Error(L, "unexpected token in directive");
7920  Parser.Lex();
7921
7922  if (!hasARM())
7923    return Error(L, "target does not support ARM mode");
7924
7925  if (isThumb())
7926    SwitchMode();
7927  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7928  return false;
7929}
7930
7931/// parseDirectiveThumbFunc
7932///  ::= .thumbfunc symbol_name
7933bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7934  const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
7935  bool isMachO = MAI->hasSubsectionsViaSymbols();
7936  StringRef Name;
7937  bool needFuncName = true;
7938
7939  // Darwin asm has (optionally) function name after .thumb_func direction
7940  // ELF doesn't
7941  if (isMachO) {
7942    const AsmToken &Tok = Parser.getTok();
7943    if (Tok.isNot(AsmToken::EndOfStatement)) {
7944      if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7945        return Error(L, "unexpected token in .thumb_func directive");
7946      Name = Tok.getIdentifier();
7947      Parser.Lex(); // Consume the identifier token.
7948      needFuncName = false;
7949    }
7950  }
7951
7952  if (getLexer().isNot(AsmToken::EndOfStatement))
7953    return Error(L, "unexpected token in directive");
7954
7955  // Eat the end of statement and any blank lines that follow.
7956  while (getLexer().is(AsmToken::EndOfStatement))
7957    Parser.Lex();
7958
7959  // FIXME: assuming function name will be the line following .thumb_func
7960  // We really should be checking the next symbol definition even if there's
7961  // stuff in between.
7962  if (needFuncName) {
7963    Name = Parser.getTok().getIdentifier();
7964  }
7965
7966  // Mark symbol as a thumb symbol.
7967  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7968  getParser().getStreamer().EmitThumbFunc(Func);
7969  return false;
7970}
7971
7972/// parseDirectiveSyntax
7973///  ::= .syntax unified | divided
7974bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7975  const AsmToken &Tok = Parser.getTok();
7976  if (Tok.isNot(AsmToken::Identifier))
7977    return Error(L, "unexpected token in .syntax directive");
7978  StringRef Mode = Tok.getString();
7979  if (Mode == "unified" || Mode == "UNIFIED")
7980    Parser.Lex();
7981  else if (Mode == "divided" || Mode == "DIVIDED")
7982    return Error(L, "'.syntax divided' arm asssembly not supported");
7983  else
7984    return Error(L, "unrecognized syntax mode in .syntax directive");
7985
7986  if (getLexer().isNot(AsmToken::EndOfStatement))
7987    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7988  Parser.Lex();
7989
7990  // TODO tell the MC streamer the mode
7991  // getParser().getStreamer().Emit???();
7992  return false;
7993}
7994
7995/// parseDirectiveCode
7996///  ::= .code 16 | 32
7997bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7998  const AsmToken &Tok = Parser.getTok();
7999  if (Tok.isNot(AsmToken::Integer))
8000    return Error(L, "unexpected token in .code directive");
8001  int64_t Val = Parser.getTok().getIntVal();
8002  if (Val == 16)
8003    Parser.Lex();
8004  else if (Val == 32)
8005    Parser.Lex();
8006  else
8007    return Error(L, "invalid operand to .code directive");
8008
8009  if (getLexer().isNot(AsmToken::EndOfStatement))
8010    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
8011  Parser.Lex();
8012
8013  if (Val == 16) {
8014    if (!hasThumb())
8015      return Error(L, "target does not support Thumb mode");
8016
8017    if (!isThumb())
8018      SwitchMode();
8019    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8020  } else {
8021    if (!hasARM())
8022      return Error(L, "target does not support ARM mode");
8023
8024    if (isThumb())
8025      SwitchMode();
8026    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8027  }
8028
8029  return false;
8030}
8031
8032/// parseDirectiveReq
8033///  ::= name .req registername
8034bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8035  Parser.Lex(); // Eat the '.req' token.
8036  unsigned Reg;
8037  SMLoc SRegLoc, ERegLoc;
8038  if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8039    Parser.eatToEndOfStatement();
8040    return Error(SRegLoc, "register name expected");
8041  }
8042
8043  // Shouldn't be anything else.
8044  if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8045    Parser.eatToEndOfStatement();
8046    return Error(Parser.getTok().getLoc(),
8047                 "unexpected input in .req directive.");
8048  }
8049
8050  Parser.Lex(); // Consume the EndOfStatement
8051
8052  if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
8053    return Error(SRegLoc, "redefinition of '" + Name +
8054                          "' does not match original.");
8055
8056  return false;
8057}
8058
8059/// parseDirectiveUneq
8060///  ::= .unreq registername
8061bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8062  if (Parser.getTok().isNot(AsmToken::Identifier)) {
8063    Parser.eatToEndOfStatement();
8064    return Error(L, "unexpected input in .unreq directive.");
8065  }
8066  RegisterReqs.erase(Parser.getTok().getIdentifier());
8067  Parser.Lex(); // Eat the identifier.
8068  return false;
8069}
8070
8071/// parseDirectiveArch
8072///  ::= .arch token
8073bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8074  return true;
8075}
8076
8077/// parseDirectiveEabiAttr
8078///  ::= .eabi_attribute int, int
8079bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8080  return true;
8081}
8082
8083/// parseDirectiveFnStart
8084///  ::= .fnstart
8085bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8086  if (FnStartLoc.isValid()) {
8087    Error(L, ".fnstart starts before the end of previous one");
8088    Error(FnStartLoc, "previous .fnstart starts here");
8089    return true;
8090  }
8091
8092  FnStartLoc = L;
8093  getParser().getStreamer().EmitFnStart();
8094  return false;
8095}
8096
8097/// parseDirectiveFnEnd
8098///  ::= .fnend
8099bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8100  // Check the ordering of unwind directives
8101  if (!FnStartLoc.isValid())
8102    return Error(L, ".fnstart must precede .fnend directive");
8103
8104  // Reset the unwind directives parser state
8105  resetUnwindDirectiveParserState();
8106
8107  getParser().getStreamer().EmitFnEnd();
8108  return false;
8109}
8110
8111/// parseDirectiveCantUnwind
8112///  ::= .cantunwind
8113bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8114  // Check the ordering of unwind directives
8115  CantUnwindLoc = L;
8116  if (!FnStartLoc.isValid())
8117    return Error(L, ".fnstart must precede .cantunwind directive");
8118  if (HandlerDataLoc.isValid()) {
8119    Error(L, ".cantunwind can't be used with .handlerdata directive");
8120    Error(HandlerDataLoc, ".handlerdata was specified here");
8121    return true;
8122  }
8123  if (PersonalityLoc.isValid()) {
8124    Error(L, ".cantunwind can't be used with .personality directive");
8125    Error(PersonalityLoc, ".personality was specified here");
8126    return true;
8127  }
8128
8129  getParser().getStreamer().EmitCantUnwind();
8130  return false;
8131}
8132
8133/// parseDirectivePersonality
8134///  ::= .personality name
8135bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8136  // Check the ordering of unwind directives
8137  PersonalityLoc = L;
8138  if (!FnStartLoc.isValid())
8139    return Error(L, ".fnstart must precede .personality directive");
8140  if (CantUnwindLoc.isValid()) {
8141    Error(L, ".personality can't be used with .cantunwind directive");
8142    Error(CantUnwindLoc, ".cantunwind was specified here");
8143    return true;
8144  }
8145  if (HandlerDataLoc.isValid()) {
8146    Error(L, ".personality must precede .handlerdata directive");
8147    Error(HandlerDataLoc, ".handlerdata was specified here");
8148    return true;
8149  }
8150
8151  // Parse the name of the personality routine
8152  if (Parser.getTok().isNot(AsmToken::Identifier)) {
8153    Parser.eatToEndOfStatement();
8154    return Error(L, "unexpected input in .personality directive.");
8155  }
8156  StringRef Name(Parser.getTok().getIdentifier());
8157  Parser.Lex();
8158
8159  MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8160  getParser().getStreamer().EmitPersonality(PR);
8161  return false;
8162}
8163
8164/// parseDirectiveHandlerData
8165///  ::= .handlerdata
8166bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8167  // Check the ordering of unwind directives
8168  HandlerDataLoc = L;
8169  if (!FnStartLoc.isValid())
8170    return Error(L, ".fnstart must precede .personality directive");
8171  if (CantUnwindLoc.isValid()) {
8172    Error(L, ".handlerdata can't be used with .cantunwind directive");
8173    Error(CantUnwindLoc, ".cantunwind was specified here");
8174    return true;
8175  }
8176
8177  getParser().getStreamer().EmitHandlerData();
8178  return false;
8179}
8180
8181/// parseDirectiveSetFP
8182///  ::= .setfp fpreg, spreg [, offset]
8183bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8184  // Check the ordering of unwind directives
8185  if (!FnStartLoc.isValid())
8186    return Error(L, ".fnstart must precede .setfp directive");
8187  if (HandlerDataLoc.isValid())
8188    return Error(L, ".setfp must precede .handlerdata directive");
8189
8190  // Parse fpreg
8191  SMLoc NewFPRegLoc = Parser.getTok().getLoc();
8192  int NewFPReg = tryParseRegister();
8193  if (NewFPReg == -1)
8194    return Error(NewFPRegLoc, "frame pointer register expected");
8195
8196  // Consume comma
8197  if (!Parser.getTok().is(AsmToken::Comma))
8198    return Error(Parser.getTok().getLoc(), "comma expected");
8199  Parser.Lex(); // skip comma
8200
8201  // Parse spreg
8202  SMLoc NewSPRegLoc = Parser.getTok().getLoc();
8203  int NewSPReg = tryParseRegister();
8204  if (NewSPReg == -1)
8205    return Error(NewSPRegLoc, "stack pointer register expected");
8206
8207  if (NewSPReg != ARM::SP && NewSPReg != FPReg)
8208    return Error(NewSPRegLoc,
8209                 "register should be either $sp or the latest fp register");
8210
8211  // Update the frame pointer register
8212  FPReg = NewFPReg;
8213
8214  // Parse offset
8215  int64_t Offset = 0;
8216  if (Parser.getTok().is(AsmToken::Comma)) {
8217    Parser.Lex(); // skip comma
8218
8219    if (Parser.getTok().isNot(AsmToken::Hash) &&
8220        Parser.getTok().isNot(AsmToken::Dollar)) {
8221      return Error(Parser.getTok().getLoc(), "'#' expected");
8222    }
8223    Parser.Lex(); // skip hash token.
8224
8225    const MCExpr *OffsetExpr;
8226    SMLoc ExLoc = Parser.getTok().getLoc();
8227    SMLoc EndLoc;
8228    if (getParser().parseExpression(OffsetExpr, EndLoc))
8229      return Error(ExLoc, "malformed setfp offset");
8230    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8231    if (!CE)
8232      return Error(ExLoc, "setfp offset must be an immediate");
8233
8234    Offset = CE->getValue();
8235  }
8236
8237  getParser().getStreamer().EmitSetFP(static_cast<unsigned>(NewFPReg),
8238                                      static_cast<unsigned>(NewSPReg),
8239                                      Offset);
8240  return false;
8241}
8242
8243/// parseDirective
8244///  ::= .pad offset
8245bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8246  // Check the ordering of unwind directives
8247  if (!FnStartLoc.isValid())
8248    return Error(L, ".fnstart must precede .pad directive");
8249  if (HandlerDataLoc.isValid())
8250    return Error(L, ".pad must precede .handlerdata directive");
8251
8252  // Parse the offset
8253  if (Parser.getTok().isNot(AsmToken::Hash) &&
8254      Parser.getTok().isNot(AsmToken::Dollar)) {
8255    return Error(Parser.getTok().getLoc(), "'#' expected");
8256  }
8257  Parser.Lex(); // skip hash token.
8258
8259  const MCExpr *OffsetExpr;
8260  SMLoc ExLoc = Parser.getTok().getLoc();
8261  SMLoc EndLoc;
8262  if (getParser().parseExpression(OffsetExpr, EndLoc))
8263    return Error(ExLoc, "malformed pad offset");
8264  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8265  if (!CE)
8266    return Error(ExLoc, "pad offset must be an immediate");
8267
8268  getParser().getStreamer().EmitPad(CE->getValue());
8269  return false;
8270}
8271
8272/// parseDirectiveRegSave
8273///  ::= .save  { registers }
8274///  ::= .vsave { registers }
8275bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8276  // Check the ordering of unwind directives
8277  if (!FnStartLoc.isValid())
8278    return Error(L, ".fnstart must precede .save or .vsave directives");
8279  if (HandlerDataLoc.isValid())
8280    return Error(L, ".save or .vsave must precede .handlerdata directive");
8281
8282  // Parse the register list
8283  SmallVector<MCParsedAsmOperand*, 1> Operands;
8284  if (parseRegisterList(Operands))
8285    return true;
8286  ARMOperand *Op = (ARMOperand*)Operands[0];
8287  if (!IsVector && !Op->isRegList())
8288    return Error(L, ".save expects GPR registers");
8289  if (IsVector && !Op->isDPRRegList())
8290    return Error(L, ".vsave expects DPR registers");
8291
8292  getParser().getStreamer().EmitRegSave(Op->getRegList(), IsVector);
8293  return false;
8294}
8295
8296/// Force static initialization.
8297extern "C" void LLVMInitializeARMAsmParser() {
8298  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
8299  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
8300}
8301
8302#define GET_REGISTER_MATCHER
8303#define GET_SUBTARGET_FEATURE_NAME
8304#define GET_MATCHER_IMPLEMENTATION
8305#include "ARMGenAsmMatcher.inc"
8306
8307// Define this matcher function after the auto-generated include so we
8308// have the match class enum definitions.
8309unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
8310                                                  unsigned Kind) {
8311  ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
8312  // If the kind is a token for a literal immediate, check if our asm
8313  // operand matches. This is for InstAliases which have a fixed-value
8314  // immediate in the syntax.
8315  if (Kind == MCK__35_0 && Op->isImm()) {
8316    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
8317    if (!CE)
8318      return Match_InvalidOperand;
8319    if (CE->getValue() == 0)
8320      return Match_Success;
8321  }
8322  return Match_InvalidOperand;
8323}
8324